Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
69.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	18	31	63.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	17	18	51.43	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	54	1			T46	1		T6	1		T47	1
auto[OpGenId]	15	1			T156	1		T75	1		T65	1
auto[OpGenSwOut]	23	1			T56	1		T219	1		T220	1
auto[OpGenHwOut]	9	1			T6	1		T8	1		T48	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1648	1			T5	2		T12	90		T49	2
auto[StInit]	86	1			T17	1		T54	1		T26	1
auto[StCreatorRootKey]	51	1			T39	1		T55	1		T29	1
auto[StOwnerIntKey]	47	1			T49	1		T6	2		T112	2
auto[StOwnerKey]	43	1			T19	1		T63	1		T64	1
auto[StDisabled]	494	1			T5	5		T49	13		T6	5
auto[StInvalid]	50	1			T3	1		T15	1		T35	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3402

1

T1

1

T2

1

T3

2

auto[1]

101

1

T46

1

T6

2

T47

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1641	1			T5	2		T12	90		T49	2
auto[StReset]	auto[1]	7	1			T46	1		T52	1		T53	1
auto[StInit]	auto[0]	43	1			T17	1		T54	1		T26	1
auto[StInit]	auto[1]	43	1			T47	1		T56	1		T220	1
auto[StCreatorRootKey]	auto[0]	33	1			T39	1		T58	2		T59	1
auto[StCreatorRootKey]	auto[1]	18	1			T55	1		T29	1		T66	1
auto[StOwnerIntKey]	auto[0]	32	1			T49	1		T112	2		T62	1
auto[StOwnerIntKey]	auto[1]	15	1			T6	2		T219	1		T75	1
auto[StOwnerKey]	auto[0]	37	1			T19	1		T63	1		T64	1
auto[StOwnerKey]	auto[1]	6	1			T156	1		T65	1		T66	1
auto[StDisabled]	auto[0]	482	1			T5	5		T49	13		T6	5
auto[StDisabled]	auto[1]	12	1			T59	1		T69	1		T66	1
auto[StInvalid]	auto[0]	50	1			T3	1		T15	1		T35	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[StOwnerKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StDisabled]]	[auto[OpGenId]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	7	1			T46	1		T52	1		T53	1
auto[StInit]	auto[OpAdvance]	21	1			T47	1		T221	1		T222	1
auto[StInit]	auto[OpGenId]	8	1			T223	1		T224	2		T225	1
auto[StInit]	auto[OpGenSwOut]	12	1			T56	1		T220	1		T77	1
auto[StInit]	auto[OpGenHwOut]	2	1			T226	1		T227	1		-	-
auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T55	1		T29	1		T66	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T228	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T70	1		T229	1		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T8	1		T28	1		T230	1
auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T6	1		T157	1		T231	1
auto[StOwnerIntKey]	auto[OpGenId]	3	1			T75	1		T232	1		T233	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T219	1		T32	1		T27	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	1	1			T6	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenId]	3	1			T156	1		T65	1		T66	1
auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T234	1		T235	1		T236	1
auto[StDisabled]	auto[OpAdvance]	9	1			T59	1		T69	1		T66	1
auto[StDisabled]	auto[OpGenSwOut]	1	1			T237	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	2	1			T48	1		T238	1		-	-