Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.05	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	76	254	76.97

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	57	223	79.64	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4887

1

T1

1

T3

14

T5

24

auto[1]

610

1

T1

1

T5

2

T44

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4887

1

T1

1

T3

14

T5

24

auto[1]

610

1

T1

1

T5

2

T44

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4974

1

T1

2

T3

14

T5

23

auto[1]

523

1

T5

3

T16

1

T45

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4974

1

T1

2

T3

14

T5

23

auto[1]

523

1

T5

3

T16

1

T45

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	419	1			T3	1		T5	1		T16	1
auto[OpGenId]	1201	1			T3	5		T5	7		T15	2
auto[OpGenSwOut]	1236	1			T3	5		T5	11		T15	3
auto[OpGenHwOut]	2584	1			T1	2		T3	3		T5	6
auto[OpDisable]	57	1			T5	1		T71	1		T242	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	419	1			T3	1		T5	1		T16	1
auto[OpGenId]	1201	1			T3	5		T5	7		T15	2
auto[OpGenSwOut]	1236	1			T3	5		T5	11		T15	3
auto[OpGenHwOut]	2584	1			T1	2		T3	3		T5	6
auto[OpDisable]	57	1			T5	1		T71	1		T242	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4947

1

T1

2

T3

14

T5

24

auto[1]

550

1

T5

2

T42

1

T218

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4947

1

T1

2

T3

14

T5

24

auto[1]

550

1

T5

2

T42

1

T218

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5175

1

T1

2

T3

14

T5

26

auto[1]

322

1

T120

3

T121

3

T143

9

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1886	1			T1	1		T3	5		T5	10
auto[1]	691	1			T3	2		T5	1		T16	2
auto[2]	716	1			T3	1		T5	1		T15	2
auto[3]	732	1			T3	3		T5	4		T15	2
auto[4]	377	1			T1	1		T5	4		T16	2
auto[5]	351	1			T5	2		T16	1		T91	1
auto[6]	359	1			T3	1		T5	3		T16	1
auto[7]	385	1			T3	2		T5	1		T15	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1472	1			T1	1		T3	3		T5	10
clear_one[1]	691	1			T3	2		T5	1		T16	2
clear_one[2]	716	1			T3	1		T5	1		T15	2
clear_one[3]	732	1			T3	3		T5	4		T15	2
clear_none	1886	1			T1	1		T3	5		T5	10

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1039	1			T3	7		T5	8		T15	3
auto[StInit]	644	1			T5	2		T16	1		T18	4
auto[StCreatorRootKey]	591	1			T5	4		T91	1		T42	1
auto[StOwnerIntKey]	527	1			T1	1		T5	1		T16	1
auto[StOwnerKey]	501	1			T5	2		T16	1		T91	1
auto[StDisabled]	1941	1			T1	1		T5	9		T16	3
auto[StInvalid]	254	1			T3	7		T15	4		T35	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1039	1			T3	7		T5	8		T15	3
auto[StInit]	644	1			T5	2		T16	1		T18	4
auto[StCreatorRootKey]	591	1			T5	4		T91	1		T42	1
auto[StOwnerIntKey]	527	1			T1	1		T5	1		T16	1
auto[StOwnerKey]	501	1			T5	2		T16	1		T91	1
auto[StDisabled]	1941	1			T1	1		T5	9		T16	3
auto[StInvalid]	254	1			T3	7		T15	4		T35	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	57	223	79.64	57

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[5]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[7]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[7]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T147	1		T243	1		T244	1
auto[0]	auto[StReset]	auto[OpGenId]	152	1			T3	1		T15	1		T91	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	173	1			T5	1		T16	1		T18	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	277	1			T3	1		T5	2		T15	1
auto[0]	auto[StInit]	auto[OpAdvance]	44	1			T96	1		T203	1		T120	1
auto[0]	auto[StInit]	auto[OpGenId]	80	1			T92	1		T6	2		T112	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	92	1			T5	1		T91	1		T49	2
auto[0]	auto[StInit]	auto[OpGenHwOut]	185	1			T5	1		T34	1		T108	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	24	1			T49	1		T6	1		T62	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	63	1			T112	2		T144	1		T147	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	60	1			T213	1		T45	1		T49	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	80	1			T5	1		T42	1		T109	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T143	1		T245	1		T246	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	34	1			T63	1		T72	1		T120	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	30	1			T205	1		T211	1		T59	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	52	1			T1	1		T49	1		T207	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T5	1		T143	1		T94	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	30	1			T5	1		T143	1		T247	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	23	1			T110	1		T143	1		T95	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T49	2		T215	1		T145	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	28	1			T146	1		T57	1		T59	1
auto[0]	auto[StDisabled]	auto[OpGenId]	74	1			T49	1		T139	1		T6	2
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T5	2		T34	1		T213	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	164	1			T218	1		T45	1		T96	1
auto[0]	auto[StDisabled]	auto[OpDisable]	12	1			T59	1		T220	1		T248	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	13	1			T3	1		T249	1		T250	1
auto[0]	auto[StInvalid]	auto[OpGenId]	25	1			T3	1		T35	1		T51	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	25	1			T3	1		T50	1		T85	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T189	1		T192	1		T251	1
auto[1]	auto[StReset]	auto[OpGenId]	26	1			T5	1		T49	1		T198	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T3	1		T106	1		T102	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	44	1			T91	1		T218	1		T49	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T49	1		T252	1		T66	1
auto[1]	auto[StInit]	auto[OpGenId]	11	1			T18	1		T75	1		T253	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	14	1			T16	1		T254	1		T252	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	25	1			T255	1		T256	1		T257	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T258	1		T224	1		T259	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T210	1		T55	1		T260	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T91	1		T207	1		T209	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T218	1		T44	1		T49	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T261	1		T262	1		-	-
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T112	1		T59	2		T263	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T94	1		T69	1		T198	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	38	1			T218	1		T44	1		T133	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T139	1		T198	1		T77	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	15	1			T55	1		T264	1		T48	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T91	1		T59	1		T265	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T108	1		T200	1		T206	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	27	1			T145	2		T257	3		T75	1
auto[1]	auto[StDisabled]	auto[OpGenId]	44	1			T6	1		T266	1		T57	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	41	1			T34	1		T49	1		T6	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T16	1		T217	1		T45	1
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T71	1		T57	1		T75	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	6	1			T267	1		T194	1		T268	1
auto[1]	auto[StInvalid]	auto[OpGenId]	12	1			T249	1		T250	1		T269	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T3	1		T35	1		T50	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T50	1		T267	1		T193	1
auto[2]	auto[StReset]	auto[OpGenId]	19	1			T3	1		T15	1		T49	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	21	1			T5	1		T114	1		T189	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	39	1			T16	1		T200	1		T270	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T271	1		T272	1		T28	1
auto[2]	auto[StInit]	auto[OpGenId]	8	1			T18	1		T273	1		T66	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	6	1			T66	2		T274	1		T97	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	18	1			T217	1		T200	1		T201	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T262	1		T275	1		-	-
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T6	1		T57	1		T76	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T271	1		T225	1		T262	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	45	1			T111	1		T90	1		T256	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T49	1		T276	1		T195	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T6	1		T112	1		T77	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T96	1		T65	1		T231	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	48	1			T91	1		T110	1		T111	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T6	1		T58	1		T252	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	17	1			T42	1		T58	1		T277	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T16	1		T210	1		T266	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T201	1		T204	1		T112	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	35	1			T121	1		T55	1		T278	1
auto[2]	auto[StDisabled]	auto[OpGenId]	81	1			T110	1		T6	2		T214	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	71	1			T34	1		T49	1		T6	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	145	1			T218	1		T217	1		T49	3
auto[2]	auto[StDisabled]	auto[OpDisable]	7	1			T279	1		T199	1		T280	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	2	1			T281	1		T282	1		-	-
auto[2]	auto[StInvalid]	auto[OpGenId]	7	1			T193	1		T283	1		T284	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T15	1		T35	1		T51	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T196	1		T285	1		T286	1
auto[3]	auto[StReset]	auto[OpGenId]	18	1			T5	1		T214	1		T198	2
auto[3]	auto[StReset]	auto[OpGenSwOut]	21	1			T210	1		T197	1		T287	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	50	1			T3	2		T35	1		T212	1
auto[3]	auto[StInit]	auto[OpAdvance]	7	1			T287	1		T231	1		T288	1
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T25	1		T289	1		T58	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	14	1			T212	1		T110	1		T6	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	23	1			T44	1		T6	1		T133	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T274	1		T234	1		T290	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T5	1		T247	1		T58	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T289	1		T277	1		T291	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T110	1		T292	1		T289	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T287	1		T234	1		T293	4
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T210	1		T141	1		T55	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	22	1			T92	1		T212	1		T112	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T217	1		T49	1		T292	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T147	2		T225	1		T259	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	12	1			T121	3		T80	1		T48	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T49	1		T209	1		T59	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T44	1		T49	1		T112	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	18	1			T144	1		T59	1		T294	1
auto[3]	auto[StDisabled]	auto[OpGenId]	66	1			T5	1		T42	1		T49	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	70	1			T5	1		T213	1		T49	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	163	1			T92	1		T218	1		T44	1
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T242	1		T58	1		T253	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T295	1		T296	1		T297	1
auto[3]	auto[StInvalid]	auto[OpGenId]	6	1			T298	1		T299	1		T300	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T3	1		T15	1		T51	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T15	1		T50	1		T51	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T146	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	3	1			T242	1		T301	1		T302	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	15	1			T5	1		T209	1		T102	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	23	1			T218	1		T201	1		T84	1
auto[4]	auto[StInit]	auto[OpAdvance]	4	1			T146	1		T80	1		T303	2
auto[4]	auto[StInit]	auto[OpGenId]	6	1			T198	1		T304	1		T303	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T305	1		T234	1		T306	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T213	1		T146	1		T59	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T146	1		T29	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T6	1		T307	1		T308	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T55	1		T146	1		T69	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T108	1		T146	2		T67	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T6	2		T198	1		T77	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T49	1		T112	1		T309	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T42	1		T49	1		T77	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T108	1		T90	1		T146	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T198	1		T310	1		T245	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	5	1			T141	1		T48	1		T311	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T273	1		T77	1		T224	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T270	1		T90	1		T59	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	18	1			T209	1		T94	1		T273	1
auto[4]	auto[StDisabled]	auto[OpGenId]	36	1			T5	1		T16	1		T91	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T49	1		T214	1		T87	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	79	1			T1	1		T5	1		T16	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T5	1		T198	1		T312	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	4	1			T283	1		T285	1		T313	1
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T51	1		T102	1		T267	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T189	1		T314	2		T315	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T316	1		T267	1		T317	2
auto[5]	auto[StReset]	auto[OpGenId]	12	1			T318	1		T277	1		T199	2
auto[5]	auto[StReset]	auto[OpGenSwOut]	12	1			T59	1		T20	1		T312	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	19	1			T16	1		T91	1		T200	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T274	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T210	1		T49	1		T274	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T319	1		T320	1		T97	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	9	1			T321	1		T322	1		T323	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T120	1		T229	1		T324	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T279	1		T325	1		T326	2
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T198	1		T327	1		T328	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T5	1		T217	1		T200	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T62	1		-	-		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T226	1		T227	1		T275	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T5	1		T329	1		T80	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T49	1		T86	1		T330	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T252	2		T331	1		T332	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T55	1		T333	1		T227	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T213	1		T133	1		T198	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	15	1			T49	1		T120	2		T334	1
auto[5]	auto[StDisabled]	auto[OpGenId]	26	1			T92	1		T49	1		T209	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T335	1		T198	1		T336	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	89	1			T212	1		T217	1		T44	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T77	2		T337	1		T338	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T193	1		T284	1		T339	1
auto[5]	auto[StInvalid]	auto[OpGenId]	7	1			T269	1		T340	1		T341	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T106	1		T342	1		T343	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T203	1		T344	1		-	-
auto[6]	auto[StReset]	auto[OpGenId]	12	1			T3	1		T214	1		T198	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	10	1			T5	1		T91	1		T77	2
auto[6]	auto[StReset]	auto[OpGenHwOut]	21	1			T318	1		T58	1		T345	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T346	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T67	1		T347	1		T348	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	9	1			T18	1		T35	1		T76	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	10	1			T270	1		T349	1		T274	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T96	1		T98	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T350	1		T351	1		T352	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T5	1		T59	1		T77	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T84	1		T67	1		T353	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T16	1		T334	1		T351	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T48	1		T280	1		T354	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T49	1		T58	1		T355	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T49	1		T356	1		T58	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T88	1		T357	1		T358	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T198	1		T327	1		T359	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T59	1		T351	2		T360	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T217	1		T330	1		T361	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T45	1		T146	1		T258	1
auto[6]	auto[StDisabled]	auto[OpGenId]	36	1			T210	1		T202	1		T266	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	34	1			T5	1		T49	1		T198	2
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	67	1			T212	1		T44	1		T108	1
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T362	1		T363	1		T364	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T249	1		T85	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T269	1		T315	1		T365	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T340	1		T285	1		T366	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T193	1		T196	1		T367	1
auto[7]	auto[StReset]	auto[OpGenId]	14	1			T35	1		T49	2		T6	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	11	1			T57	1		T198	1		T272	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	26	1			T217	1		T44	1		T6	1
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T112	1		T129	1		T224	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	8	1			T18	1		T24	1		T198	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	13	1			T218	1		T24	1		T318	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T257	1		T368	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T276	1		T114	1		T75	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T369	1		T320	1		T230	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T204	1		T133	1		T72	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T6	1		T155	1		T369	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T49	1		T88	1		T129	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T202	1		T252	1		T262	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T200	1		T201	1		T84	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T370	1		T371	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	8	1			T257	2		T350	1		T346	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T6	1		T224	1		T274	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T218	1		T111	1		T155	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	13	1			T145	1		T75	1		T48	1
auto[7]	auto[StDisabled]	auto[OpGenId]	34	1			T5	1		T212	2		T112	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	43	1			T140	1		T155	1		T144	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T218	1		T111	1		T200	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T66	1		T280	1		T372	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T3	1		T102	1		T373	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T3	1		T15	1		T249	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T51	1		T203	1		T102	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1472

1

T1

1

T3

3

T5

10

clear_one[1]

auto[0]

auto[0]

auto[0]

402

1

T3

2

T5

1

T16

1

clear_one[1]

auto[0]

auto[0]

auto[1]

129

1

T218

2

T217

1

T45

1

clear_one[1]

auto[0]

auto[1]

auto[0]

124

1

T16

1

T200

1

T112

1

clear_one[1]

auto[0]

auto[1]

auto[1]

36

1

T139

1

T266

1

T25

1

clear_one[2]

auto[0]

auto[0]

auto[0]

388

1

T3

1

T5

1

T15

2

clear_one[2]

auto[0]

auto[0]

auto[1]

127

1

T218

1

T217

1

T49

2

clear_one[2]

auto[1]

auto[0]

auto[0]

164

1

T49

1

T111

2

T266

1

clear_one[2]

auto[1]

auto[0]

auto[1]

37

1

T49

1

T55

1

T94

1

clear_one[3]

auto[0]

auto[0]

auto[0]

422

1

T3

3

T5

3

T15

2

clear_one[3]

auto[0]

auto[1]

auto[0]

130

1

T49

1

T204

1

T121

1

clear_one[3]

auto[1]

auto[0]

auto[0]

137

1

T44

2

T108

3

T49

2

clear_one[3]

auto[1]

auto[1]

auto[0]

43

1

T5

1

T139

1

T55

1

clear_none

auto[0]

auto[0]

auto[0]

1362

1

T3

5

T5

7

T15

2

clear_none

auto[0]

auto[0]

auto[1]

160

1

T5

1

T42

1

T218

1

clear_none

auto[0]

auto[1]

auto[0]

122

1

T5

1

T49

1

T112

3

clear_none

auto[0]

auto[1]

auto[1]

13

1

T59

1

T374

1

T100

1

clear_none

auto[1]

auto[0]

auto[0]

141

1

T1

1

T96

1

T49

2

clear_none

auto[1]

auto[0]

auto[1]

33

1

T49

1

T63

1

T143

2

clear_none

auto[1]

auto[1]

auto[0]

40

1

T45

1

T49

1

T109

1

clear_none

auto[1]

auto[1]

auto[1]

15

1

T5

1

T57

2

T75

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1389	1			T1	1		T3	3		T5	10
clear_all	auto[1]	83	1			T120	3		T155	2		T146	10
clear_one[1]	auto[0]	654	1			T3	2		T5	1		T16	2
clear_one[1]	auto[1]	37	1			T145	3		T257	2		T252	3
clear_one[2]	auto[0]	657	1			T3	1		T5	1		T15	2
clear_one[2]	auto[1]	59	1			T144	1		T146	3		T147	6
clear_one[3]	auto[0]	676	1			T3	3		T5	4		T15	2
clear_one[3]	auto[1]	56	1			T121	2		T147	6		T289	4
clear_none	auto[0]	1799	1			T1	1		T3	5		T5	10
clear_none	auto[1]	87	1			T121	1		T143	9		T144	2