Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11804

1

T1

5

T2

5

T3

14

auto[Attestation]

7884

1

T1

8

T2

3

T3

12

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2917	1			T1	2		T2	1		T3	5
auto[Aes]	3573	1			T1	4		T3	4		T4	3
auto[Kmac]	3504	1			T1	4		T2	1		T3	2
auto[Otbn]	3534	1			T1	2		T3	5		T4	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8075	1			T1	3		T2	8		T3	1
auto[OpGenId]	6160	1			T1	1		T2	6		T3	10
auto[OpGenSwOut]	6291	1			T1	6		T2	2		T3	8
auto[OpGenHwOut]	7237	1			T1	6		T3	8		T5	39
auto[OpDisable]	126	1			T1	1		T5	1		T49	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11155

1

T1

12

T2

8

T3

1

auto[OpDoneFail]

16734

1

T1

5

T2

8

T3

26

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6706	1			T1	1		T2	1		T3	25
auto[StInit]	3875	1			T1	5		T2	2		T3	2
auto[StCreatorRootKey]	3312	1			T1	5		T2	2		T4	2
auto[StOwnerIntKey]	2959	1			T1	5		T2	2		T4	2
auto[StOwnerKey]	2611	1			T2	2		T4	2		T5	17
auto[StDisabled]	8426	1			T1	1		T2	7		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	319	1			T3	2		T4	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	112	1			T18	3		T49	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	82	1			T2	1		T5	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	75	1			T107	1		T6	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	62	1			T49	2		T112	1		T209	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	244	1			T5	2		T16	1		T91	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	364	1			T4	2		T5	2		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	98	1			T18	2		T24	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T1	1		T72	1		T121	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	78	1			T49	1		T112	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	59	1			T210	1		T209	1		T55	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	246	1			T4	1		T5	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	324	1			T4	2		T16	1		T35	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	128	1			T18	2		T35	1		T49	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T5	1		T49	2		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	78	1			T4	1		T42	1		T142	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	65	1			T5	1		T49	2		T55	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	236	1			T4	1		T5	2		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	381	1			T3	1		T4	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	105	1			T1	1		T5	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T5	1		T16	2		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T1	1		T112	1		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	68	1			T19	1		T91	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	239	1			T5	3		T34	1		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	58	1			T3	1		T5	2		T49	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	118	1			T1	1		T18	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	83	1			T5	2		T49	1		T139	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	80	1			T205	1		T209	1		T121	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	77	1			T4	1		T49	2		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	247	1			T5	1		T34	1		T213	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	54	1			T49	1		T112	1		T55	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	103	1			T3	1		T18	2		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	89	1			T16	1		T213	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	89	1			T5	2		T19	1		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	56	1			T96	1		T49	1		T112	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	226	1			T210	1		T49	5		T140	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	80	1			T3	1		T5	1		T49	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	108	1			T4	1		T5	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	87	1			T5	1		T91	1		T49	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	80	1			T1	2		T5	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	65	1			T49	1		T134	1		T214	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	233	1			T2	1		T4	1		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	72	1			T3	2		T5	1		T49	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	109	1			T18	1		T91	1		T49	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	79	1			T16	1		T49	2		T112	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	82	1			T5	1		T96	1		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	76	1			T5	2		T16	1		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	250	1			T5	1		T91	1		T93	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	306	1			T3	2		T15	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	88	1			T49	1		T106	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	94	1			T5	1		T212	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T1	1		T49	2		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	61	1			T91	1		T96	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	176	1			T5	1		T92	1		T49	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	493	1			T3	2		T5	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	126	1			T18	2		T44	1		T111	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	125	1			T5	1		T35	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	114	1			T44	1		T49	2		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	94	1			T44	1		T45	2		T49	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	295	1			T91	1		T42	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	546	1			T3	1		T5	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	117	1			T1	1		T18	1		T49	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	82	1			T5	2		T49	1		T109	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	97	1			T200	1		T134	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	80	1			T49	1		T200	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	306	1			T5	3		T16	3		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	482	1			T5	2		T16	4		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	123	1			T5	1		T18	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	117	1			T42	1		T217	1		T109	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T5	1		T218	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	92	1			T5	1		T218	1		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	292	1			T5	2		T218	3		T217	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	44	1			T5	3		T102	1		T198	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T5	1		T18	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	78	1			T92	1		T45	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T5	1		T213	1		T112	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	53	1			T5	1		T49	2		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	217	1			T5	5		T16	1		T91	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	52	1			T3	1		T5	1		T49	5
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	106	1			T18	3		T19	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	109	1			T1	2		T16	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	114	1			T5	1		T108	1		T49	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	100	1			T108	1		T49	3		T140	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	292	1			T1	1		T5	3		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T49	5		T55	2		T59	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	120	1			T1	1		T5	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T109	2		T200	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T91	1		T96	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	92	1			T92	1		T49	1		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	244	1			T92	1		T45	1		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	50	1			T3	1		T5	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	115	1			T3	1		T19	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	118	1			T19	1		T218	1		T109	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	88	1			T5	1		T49	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	87	1			T19	1		T212	1		T217	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	263	1			T5	2		T16	1		T91	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	204	1			T2	1		T5	1		T107	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	690	1			T3	2		T4	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	210	1			T1	1		T210	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	726	1			T4	3		T5	3		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	215	1			T4	1		T5	2		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	697	1			T4	3		T5	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	207	1			T1	1		T5	1		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	741	1			T1	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	222	1			T4	1		T5	2		T49	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	441	1			T1	1		T3	1		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	223	1			T5	2		T16	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	394	1			T3	1		T18	2		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	208	1			T1	2		T5	2		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	445	1			T2	1		T3	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	219	1			T5	3		T16	2		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	449	1			T3	2		T5	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	199	1			T1	1		T5	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	595	1			T3	2		T5	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	300	1			T5	1		T44	3		T45	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	947	1			T3	2		T5	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	241	1			T5	1		T49	2		T109	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	987	1			T1	1		T3	1		T5	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	285	1			T5	1		T42	1		T218	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	912	1			T5	6		T16	4		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	191	1			T5	1		T92	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	375	1			T5	10		T16	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	310	1			T1	2		T5	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	463	1			T1	1		T3	1		T5	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	280	1			T91	1		T92	1		T96	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	431	1			T1	1		T5	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	276	1			T5	1		T19	2		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	445	1			T3	2		T5	3		T16	1