Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34050

1

T1

19

T2

20

T3

57

auto[1]

292

1

T120

5

T121

7

T143

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	34062	1			T1	19		T2	20		T3	57
auto[134217728:268435455]	8	1			T245	1		T259	1		T351	2
auto[268435456:402653183]	6	1			T289	1		T271	2		T387	2
auto[402653184:536870911]	15	1			T120	1		T121	1		T143	1
auto[536870912:671088639]	8	1			T121	1		T146	1		T271	1
auto[671088640:805306367]	5	1			T145	1		T380	1		T388	1
auto[805306368:939524095]	10	1			T143	1		T146	1		T147	1
auto[939524096:1073741823]	11	1			T144	3		T245	1		T326	1
auto[1073741824:1207959551]	12	1			T144	1		T145	1		T294	1
auto[1207959552:1342177279]	5	1			T145	1		T289	1		T380	1
auto[1342177280:1476395007]	10	1			T289	1		T336	1		T287	1
auto[1476395008:1610612735]	8	1			T145	2		T326	1		T259	1
auto[1610612736:1744830463]	15	1			T145	1		T289	1		T294	1
auto[1744830464:1879048191]	8	1			T289	1		T294	1		T244	1
auto[1879048192:2013265919]	3	1			T351	1		T389	1		T324	1
auto[2013265920:2147483647]	11	1			T147	1		T289	2		T257	1
auto[2147483648:2281701375]	10	1			T289	1		T287	1		T380	1
auto[2281701376:2415919103]	9	1			T287	1		T380	1		T310	1
auto[2415919104:2550136831]	11	1			T143	1		T155	1		T294	1
auto[2550136832:2684354559]	8	1			T310	1		T245	1		T326	1
auto[2684354560:2818572287]	5	1			T121	1		T146	1		T289	1
auto[2818572288:2952790015]	12	1			T120	1		T143	1		T145	2
auto[2952790016:3087007743]	9	1			T121	2		T287	1		T381	1
auto[3087007744:3221225471]	6	1			T146	1		T289	1		T303	1
auto[3221225472:3355443199]	12	1			T121	1		T146	1		T147	1
auto[3355443200:3489660927]	7	1			T120	1		T257	1		T326	1
auto[3489660928:3623878655]	10	1			T120	1		T121	1		T143	1
auto[3623878656:3758096383]	13	1			T120	1		T147	1		T294	1
auto[3758096384:3892314111]	11	1			T289	1		T287	1		T252	1
auto[3892314112:4026531839]	5	1			T252	1		T245	1		T326	1
auto[4026531840:4160749567]	8	1			T144	1		T146	1		T252	1
auto[4160749568:4294967295]	9	1			T143	2		T145	1		T287	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	34050	1			T1	19		T2	20		T3	57
auto[0:134217727]	auto[1]	12	1			T147	1		T294	1		T252	2
auto[134217728:268435455]	auto[1]	8	1			T245	1		T259	1		T351	2
auto[268435456:402653183]	auto[1]	6	1			T289	1		T271	2		T387	2
auto[402653184:536870911]	auto[1]	15	1			T120	1		T121	1		T143	1
auto[536870912:671088639]	auto[1]	8	1			T121	1		T146	1		T271	1
auto[671088640:805306367]	auto[1]	5	1			T145	1		T380	1		T388	1
auto[805306368:939524095]	auto[1]	10	1			T143	1		T146	1		T147	1
auto[939524096:1073741823]	auto[1]	11	1			T144	3		T245	1		T326	1
auto[1073741824:1207959551]	auto[1]	12	1			T144	1		T145	1		T294	1
auto[1207959552:1342177279]	auto[1]	5	1			T145	1		T289	1		T380	1
auto[1342177280:1476395007]	auto[1]	10	1			T289	1		T336	1		T287	1
auto[1476395008:1610612735]	auto[1]	8	1			T145	2		T326	1		T259	1
auto[1610612736:1744830463]	auto[1]	15	1			T145	1		T289	1		T294	1
auto[1744830464:1879048191]	auto[1]	8	1			T289	1		T294	1		T244	1
auto[1879048192:2013265919]	auto[1]	3	1			T351	1		T389	1		T324	1
auto[2013265920:2147483647]	auto[1]	11	1			T147	1		T289	2		T257	1
auto[2147483648:2281701375]	auto[1]	10	1			T289	1		T287	1		T380	1
auto[2281701376:2415919103]	auto[1]	9	1			T287	1		T380	1		T310	1
auto[2415919104:2550136831]	auto[1]	11	1			T143	1		T155	1		T294	1
auto[2550136832:2684354559]	auto[1]	8	1			T310	1		T245	1		T326	1
auto[2684354560:2818572287]	auto[1]	5	1			T121	1		T146	1		T289	1
auto[2818572288:2952790015]	auto[1]	12	1			T120	1		T143	1		T145	2
auto[2952790016:3087007743]	auto[1]	9	1			T121	2		T287	1		T381	1
auto[3087007744:3221225471]	auto[1]	6	1			T146	1		T289	1		T303	1
auto[3221225472:3355443199]	auto[1]	12	1			T121	1		T146	1		T147	1
auto[3355443200:3489660927]	auto[1]	7	1			T120	1		T257	1		T326	1
auto[3489660928:3623878655]	auto[1]	10	1			T120	1		T121	1		T143	1
auto[3623878656:3758096383]	auto[1]	13	1			T120	1		T147	1		T294	1
auto[3758096384:3892314111]	auto[1]	11	1			T289	1		T287	1		T252	1
auto[3892314112:4026531839]	auto[1]	5	1			T252	1		T245	1		T326	1
auto[4026531840:4160749567]	auto[1]	8	1			T144	1		T146	1		T252	1
auto[4160749568:4294967295]	auto[1]	9	1			T143	2		T145	1		T287	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1602

1

T1

1

T3

6

T5

15

auto[1]

1825

1

T3

3

T5

14

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	131	1			T5	1		T91	1		T139	1
auto[134217728:268435455]	106	1			T5	2		T106	1		T112	1
auto[268435456:402653183]	99	1			T49	2		T6	2		T112	1
auto[402653184:536870911]	103	1			T3	1		T5	2		T15	2
auto[536870912:671088639]	104	1			T15	1		T96	1		T50	1
auto[671088640:805306367]	117	1			T3	1		T5	1		T35	1
auto[805306368:939524095]	100	1			T15	1		T18	1		T139	1
auto[939524096:1073741823]	97	1			T3	1		T15	1		T96	1
auto[1073741824:1207959551]	104	1			T96	1		T49	3		T51	1
auto[1207959552:1342177279]	97	1			T18	1		T96	1		T6	1
auto[1342177280:1476395007]	106	1			T3	1		T45	1		T49	2
auto[1476395008:1610612735]	94	1			T5	2		T16	1		T18	1
auto[1610612736:1744830463]	124	1			T210	1		T49	3		T24	1
auto[1744830464:1879048191]	97	1			T5	1		T91	1		T45	1
auto[1879048192:2013265919]	107	1			T1	1		T3	1		T15	1
auto[2013265920:2147483647]	135	1			T15	1		T35	1		T49	4
auto[2147483648:2281701375]	122	1			T5	1		T35	1		T50	1
auto[2281701376:2415919103]	104	1			T3	1		T5	1		T35	1
auto[2415919104:2550136831]	99	1			T5	1		T49	1		T209	1
auto[2550136832:2684354559]	109	1			T51	1		T47	1		T73	1
auto[2684354560:2818572287]	96	1			T5	2		T210	1		T49	1
auto[2818572288:2952790015]	109	1			T5	2		T24	1		T207	1
auto[2952790016:3087007743]	92	1			T3	1		T5	1		T16	1
auto[3087007744:3221225471]	122	1			T16	1		T96	1		T49	3
auto[3221225472:3355443199]	103	1			T5	3		T15	1		T35	1
auto[3355443200:3489660927]	103	1			T18	1		T91	1		T210	1
auto[3489660928:3623878655]	121	1			T5	2		T91	2		T50	1
auto[3623878656:3758096383]	106	1			T5	1		T16	1		T139	1
auto[3758096384:3892314111]	114	1			T3	1		T15	1		T18	1
auto[3892314112:4026531839]	99	1			T5	3		T15	1		T16	1
auto[4026531840:4160749567]	108	1			T3	1		T5	1		T45	1
auto[4160749568:4294967295]	99	1			T5	2		T18	1		T49	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T91	1		T47	1		T211	1
auto[0:134217727]	auto[1]	78	1			T5	1		T139	1		T62	1
auto[134217728:268435455]	auto[0]	38	1			T106	1		T120	1		T318	1
auto[134217728:268435455]	auto[1]	68	1			T5	2		T112	1		T47	1
auto[268435456:402653183]	auto[0]	43	1			T6	1		T340	1		T336	1
auto[268435456:402653183]	auto[1]	56	1			T49	2		T6	1		T112	1
auto[402653184:536870911]	auto[0]	49	1			T3	1		T5	1		T15	2
auto[402653184:536870911]	auto[1]	54	1			T5	1		T91	1		T210	1
auto[536870912:671088639]	auto[0]	43	1			T15	1		T50	1		T49	1
auto[536870912:671088639]	auto[1]	61	1			T96	1		T49	2		T6	1
auto[671088640:805306367]	auto[0]	58	1			T3	1		T5	1		T49	2
auto[671088640:805306367]	auto[1]	59	1			T35	1		T45	1		T210	1
auto[805306368:939524095]	auto[0]	46	1			T15	1		T18	1		T120	1
auto[805306368:939524095]	auto[1]	54	1			T139	1		T106	1		T6	1
auto[939524096:1073741823]	auto[0]	44	1			T51	1		T269	1		T57	2
auto[939524096:1073741823]	auto[1]	53	1			T3	1		T15	1		T96	1
auto[1073741824:1207959551]	auto[0]	53	1			T49	1		T106	2		T6	1
auto[1073741824:1207959551]	auto[1]	51	1			T96	1		T49	2		T51	1
auto[1207959552:1342177279]	auto[0]	51	1			T18	1		T96	1		T203	1
auto[1207959552:1342177279]	auto[1]	46	1			T6	1		T132	1		T55	1
auto[1342177280:1476395007]	auto[0]	52	1			T3	1		T49	1		T24	2
auto[1342177280:1476395007]	auto[1]	54	1			T45	1		T49	1		T207	1
auto[1476395008:1610612735]	auto[0]	48	1			T18	1		T102	1		T267	1
auto[1476395008:1610612735]	auto[1]	46	1			T5	2		T16	1		T49	2
auto[1610612736:1744830463]	auto[0]	58	1			T49	1		T24	1		T106	1
auto[1610612736:1744830463]	auto[1]	66	1			T210	1		T49	2		T139	1
auto[1744830464:1879048191]	auto[0]	45	1			T5	1		T91	1		T45	1
auto[1744830464:1879048191]	auto[1]	52	1			T49	1		T58	2		T198	1
auto[1879048192:2013265919]	auto[0]	61	1			T1	1		T3	1		T15	1
auto[1879048192:2013265919]	auto[1]	46	1			T210	1		T49	2		T143	1
auto[2013265920:2147483647]	auto[0]	69	1			T15	1		T35	1		T49	1
auto[2013265920:2147483647]	auto[1]	66	1			T49	3		T205	1		T86	1
auto[2147483648:2281701375]	auto[0]	52	1			T50	1		T139	1		T6	1
auto[2147483648:2281701375]	auto[1]	70	1			T5	1		T35	1		T49	1
auto[2281701376:2415919103]	auto[0]	51	1			T5	1		T50	1		T49	1
auto[2281701376:2415919103]	auto[1]	53	1			T3	1		T35	1		T55	1
auto[2415919104:2550136831]	auto[0]	45	1			T121	1		T55	1		T250	1
auto[2415919104:2550136831]	auto[1]	54	1			T5	1		T49	1		T209	1
auto[2550136832:2684354559]	auto[0]	50	1			T73	1		T85	1		T88	1
auto[2550136832:2684354559]	auto[1]	59	1			T51	1		T47	1		T209	2
auto[2684354560:2818572287]	auto[0]	48	1			T5	1		T24	1		T276	1
auto[2684354560:2818572287]	auto[1]	48	1			T5	1		T210	1		T49	1
auto[2818572288:2952790015]	auto[0]	54	1			T5	2		T55	1		T58	1
auto[2818572288:2952790015]	auto[1]	55	1			T24	1		T207	1		T209	1
auto[2952790016:3087007743]	auto[0]	39	1			T3	1		T16	1		T210	1
auto[2952790016:3087007743]	auto[1]	53	1			T5	1		T72	1		T318	1
auto[3087007744:3221225471]	auto[0]	60	1			T16	1		T96	1		T49	1
auto[3087007744:3221225471]	auto[1]	62	1			T49	2		T6	1		T112	1
auto[3221225472:3355443199]	auto[0]	40	1			T5	2		T15	1		T35	1
auto[3221225472:3355443199]	auto[1]	63	1			T5	1		T49	2		T46	1
auto[3355443200:3489660927]	auto[0]	43	1			T18	1		T210	1		T49	1
auto[3355443200:3489660927]	auto[1]	60	1			T91	1		T55	1		T94	1
auto[3489660928:3623878655]	auto[0]	62	1			T5	2		T91	1		T50	1
auto[3489660928:3623878655]	auto[1]	59	1			T91	1		T49	1		T207	1
auto[3623878656:3758096383]	auto[0]	49	1			T5	1		T6	1		T121	1
auto[3623878656:3758096383]	auto[1]	57	1			T16	1		T139	1		T6	1
auto[3758096384:3892314111]	auto[0]	53	1			T15	1		T35	1		T24	1
auto[3758096384:3892314111]	auto[1]	61	1			T3	1		T18	1		T207	1
auto[3892314112:4026531839]	auto[0]	43	1			T5	1		T15	1		T55	1
auto[3892314112:4026531839]	auto[1]	56	1			T5	2		T16	1		T50	1
auto[4026531840:4160749567]	auto[0]	51	1			T3	1		T106	1		T205	1
auto[4026531840:4160749567]	auto[1]	57	1			T5	1		T45	1		T96	1
auto[4160749568:4294967295]	auto[0]	51	1			T5	2		T18	1		T6	1
auto[4160749568:4294967295]	auto[1]	48	1			T49	1		T139	1		T6	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1568

1

T3

6

T5

16

T15

8

auto[1]

1859

1

T1

1

T3

3

T5

13

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T5	2		T16	1		T45	1
auto[134217728:268435455]	99	1			T3	1		T15	1		T16	1
auto[268435456:402653183]	104	1			T96	1		T210	1		T49	2
auto[402653184:536870911]	104	1			T5	1		T15	1		T91	1
auto[536870912:671088639]	114	1			T15	1		T106	1		T6	1
auto[671088640:805306367]	109	1			T35	1		T210	1		T24	1
auto[805306368:939524095]	113	1			T5	1		T15	1		T16	1
auto[939524096:1073741823]	93	1			T18	1		T49	1		T47	1
auto[1073741824:1207959551]	123	1			T5	2		T91	1		T210	1
auto[1207959552:1342177279]	113	1			T15	1		T210	1		T49	2
auto[1342177280:1476395007]	113	1			T5	2		T18	1		T210	1
auto[1476395008:1610612735]	82	1			T1	1		T15	1		T91	1
auto[1610612736:1744830463]	95	1			T3	1		T5	2		T15	1
auto[1744830464:1879048191]	94	1			T3	1		T91	1		T50	1
auto[1879048192:2013265919]	114	1			T5	1		T15	1		T91	1
auto[2013265920:2147483647]	88	1			T35	1		T49	3		T207	1
auto[2147483648:2281701375]	111	1			T3	1		T5	3		T49	1
auto[2281701376:2415919103]	120	1			T5	2		T16	1		T49	4
auto[2415919104:2550136831]	113	1			T3	1		T5	3		T35	1
auto[2550136832:2684354559]	109	1			T49	4		T203	1		T62	1
auto[2684354560:2818572287]	105	1			T5	2		T35	1		T6	1
auto[2818572288:2952790015]	102	1			T5	1		T15	1		T18	1
auto[2952790016:3087007743]	100	1			T5	1		T49	2		T106	2
auto[3087007744:3221225471]	109	1			T18	1		T45	1		T49	1
auto[3221225472:3355443199]	112	1			T3	1		T5	3		T96	1
auto[3355443200:3489660927]	120	1			T5	1		T50	1		T24	1
auto[3489660928:3623878655]	134	1			T3	1		T5	1		T35	2
auto[3623878656:3758096383]	98	1			T16	1		T49	2		T207	1
auto[3758096384:3892314111]	106	1			T3	1		T5	1		T18	1
auto[3892314112:4026531839]	99	1			T3	1		T91	2		T45	1
auto[4026531840:4160749567]	103	1			T18	1		T96	1		T50	1
auto[4160749568:4294967295]	120	1			T15	1		T49	1		T139	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T5	1		T16	1		T49	1
auto[0:134217727]	auto[1]	60	1			T5	1		T45	1		T49	1
auto[134217728:268435455]	auto[0]	48	1			T3	1		T15	1		T16	1
auto[134217728:268435455]	auto[1]	51	1			T59	1		T335	1		T349	1
auto[268435456:402653183]	auto[0]	43	1			T58	2		T254	2		T219	1
auto[268435456:402653183]	auto[1]	61	1			T96	1		T210	1		T49	2
auto[402653184:536870911]	auto[0]	40	1			T5	1		T91	1		T96	1
auto[402653184:536870911]	auto[1]	64	1			T15	1		T35	1		T49	3
auto[536870912:671088639]	auto[0]	55	1			T15	1		T106	1		T55	1
auto[536870912:671088639]	auto[1]	59	1			T6	1		T209	1		T55	1
auto[671088640:805306367]	auto[0]	54	1			T35	1		T24	1		T139	1
auto[671088640:805306367]	auto[1]	55	1			T210	1		T112	1		T55	1
auto[805306368:939524095]	auto[0]	57	1			T15	1		T24	1		T55	1
auto[805306368:939524095]	auto[1]	56	1			T5	1		T16	1		T96	1
auto[939524096:1073741823]	auto[0]	38	1			T18	1		T47	1		T25	1
auto[939524096:1073741823]	auto[1]	55	1			T49	1		T143	1		T145	1
auto[1073741824:1207959551]	auto[0]	53	1			T5	1		T91	1		T210	1
auto[1073741824:1207959551]	auto[1]	70	1			T5	1		T49	3		T46	1
auto[1207959552:1342177279]	auto[0]	50	1			T49	1		T24	1		T139	1
auto[1207959552:1342177279]	auto[1]	63	1			T15	1		T210	1		T49	1
auto[1342177280:1476395007]	auto[0]	46	1			T5	1		T18	1		T55	1
auto[1342177280:1476395007]	auto[1]	67	1			T5	1		T210	1		T49	1
auto[1476395008:1610612735]	auto[0]	41	1			T15	1		T50	1		T51	1
auto[1476395008:1610612735]	auto[1]	41	1			T1	1		T91	1		T47	1
auto[1610612736:1744830463]	auto[0]	46	1			T5	2		T15	1		T58	1
auto[1610612736:1744830463]	auto[1]	49	1			T3	1		T207	1		T6	3
auto[1744830464:1879048191]	auto[0]	41	1			T3	1		T50	1		T106	1
auto[1744830464:1879048191]	auto[1]	53	1			T91	1		T49	1		T139	1
auto[1879048192:2013265919]	auto[0]	44	1			T15	1		T91	1		T47	1
auto[1879048192:2013265919]	auto[1]	70	1			T5	1		T45	1		T96	1
auto[2013265920:2147483647]	auto[0]	40	1			T35	1		T49	2		T55	1
auto[2013265920:2147483647]	auto[1]	48	1			T49	1		T207	1		T112	1
auto[2147483648:2281701375]	auto[0]	56	1			T3	1		T5	2		T25	1
auto[2147483648:2281701375]	auto[1]	55	1			T5	1		T49	1		T112	1
auto[2281701376:2415919103]	auto[0]	51	1			T5	1		T49	3		T6	1
auto[2281701376:2415919103]	auto[1]	69	1			T5	1		T16	1		T49	1
auto[2415919104:2550136831]	auto[0]	55	1			T5	1		T210	1		T106	1
auto[2415919104:2550136831]	auto[1]	58	1			T3	1		T5	2		T35	1
auto[2550136832:2684354559]	auto[0]	49	1			T49	1		T203	1		T62	1
auto[2550136832:2684354559]	auto[1]	60	1			T49	3		T276	1		T57	1
auto[2684354560:2818572287]	auto[0]	52	1			T5	1		T73	1		T269	1
auto[2684354560:2818572287]	auto[1]	53	1			T5	1		T35	1		T6	1
auto[2818572288:2952790015]	auto[0]	41	1			T5	1		T15	1		T18	1
auto[2818572288:2952790015]	auto[1]	61	1			T49	1		T6	1		T205	1
auto[2952790016:3087007743]	auto[0]	51	1			T5	1		T106	2		T121	1
auto[2952790016:3087007743]	auto[1]	49	1			T49	2		T102	1		T155	1
auto[3087007744:3221225471]	auto[0]	45	1			T18	1		T63	1		T121	1
auto[3087007744:3221225471]	auto[1]	64	1			T45	1		T49	1		T6	1
auto[3221225472:3355443199]	auto[0]	50	1			T3	1		T49	1		T205	1
auto[3221225472:3355443199]	auto[1]	62	1			T5	3		T96	1		T47	1
auto[3355443200:3489660927]	auto[0]	59	1			T5	1		T24	1		T120	2
auto[3355443200:3489660927]	auto[1]	61	1			T50	1		T207	1		T51	1
auto[3489660928:3623878655]	auto[0]	62	1			T5	1		T35	1		T51	1
auto[3489660928:3623878655]	auto[1]	72	1			T3	1		T35	1		T49	2
auto[3623878656:3758096383]	auto[0]	46	1			T55	1		T86	1		T269	1
auto[3623878656:3758096383]	auto[1]	52	1			T16	1		T49	2		T207	1
auto[3758096384:3892314111]	auto[0]	53	1			T3	1		T5	1		T18	1
auto[3758096384:3892314111]	auto[1]	53	1			T35	1		T49	1		T112	1
auto[3892314112:4026531839]	auto[0]	44	1			T3	1		T91	2		T45	1
auto[3892314112:4026531839]	auto[1]	55	1			T51	1		T205	1		T55	1
auto[4026531840:4160749567]	auto[0]	49	1			T50	1		T49	1		T106	1
auto[4026531840:4160749567]	auto[1]	54	1			T18	1		T96	1		T6	2
auto[4160749568:4294967295]	auto[0]	61	1			T15	1		T207	1		T266	1
auto[4160749568:4294967295]	auto[1]	59	1			T49	1		T139	1		T121	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1628

1

T1

1

T3

7

T5

18

auto[1]

1799

1

T3

2

T5

11

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T5	1		T18	1		T91	1
auto[134217728:268435455]	120	1			T3	2		T5	1		T91	1
auto[268435456:402653183]	100	1			T15	2		T96	1		T139	1
auto[402653184:536870911]	113	1			T5	3		T49	1		T207	1
auto[536870912:671088639]	101	1			T5	1		T15	1		T16	1
auto[671088640:805306367]	88	1			T49	3		T106	2		T46	1
auto[805306368:939524095]	108	1			T5	1		T15	1		T210	1
auto[939524096:1073741823]	94	1			T3	1		T91	1		T139	1
auto[1073741824:1207959551]	117	1			T15	1		T18	1		T45	1
auto[1207959552:1342177279]	114	1			T15	1		T35	1		T50	1
auto[1342177280:1476395007]	91	1			T5	3		T15	1		T50	1
auto[1476395008:1610612735]	99	1			T5	3		T16	1		T45	1
auto[1610612736:1744830463]	100	1			T3	1		T18	1		T49	1
auto[1744830464:1879048191]	89	1			T5	1		T210	1		T49	1
auto[1879048192:2013265919]	97	1			T49	1		T24	1		T47	1
auto[2013265920:2147483647]	108	1			T3	1		T5	1		T35	1
auto[2147483648:2281701375]	108	1			T3	2		T5	1		T15	1
auto[2281701376:2415919103]	117	1			T5	1		T18	1		T35	1
auto[2415919104:2550136831]	117	1			T5	2		T18	1		T49	3
auto[2550136832:2684354559]	99	1			T50	1		T210	1		T49	1
auto[2684354560:2818572287]	86	1			T5	1		T49	1		T55	1
auto[2818572288:2952790015]	126	1			T3	1		T5	1		T49	1
auto[2952790016:3087007743]	105	1			T5	3		T16	1		T112	1
auto[3087007744:3221225471]	134	1			T3	1		T5	3		T210	2
auto[3221225472:3355443199]	123	1			T1	1		T49	3		T6	1
auto[3355443200:3489660927]	101	1			T91	1		T35	1		T45	1
auto[3489660928:3623878655]	114	1			T35	1		T49	2		T139	1
auto[3623878656:3758096383]	114	1			T16	1		T91	1		T96	1
auto[3758096384:3892314111]	102	1			T5	1		T16	1		T45	1
auto[3892314112:4026531839]	118	1			T96	1		T6	2		T132	1
auto[4026531840:4160749567]	117	1			T5	1		T15	1		T18	1
auto[4160749568:4294967295]	105	1			T15	1		T50	1		T49	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T5	1		T18	1		T207	1
auto[0:134217727]	auto[1]	47	1			T91	1		T49	1		T139	1
auto[134217728:268435455]	auto[0]	62	1			T3	1		T91	1		T35	1
auto[134217728:268435455]	auto[1]	58	1			T3	1		T5	1		T96	1
auto[268435456:402653183]	auto[0]	48	1			T15	1		T139	1		T59	1
auto[268435456:402653183]	auto[1]	52	1			T15	1		T96	1		T62	1
auto[402653184:536870911]	auto[0]	50	1			T5	2		T120	1		T209	1
auto[402653184:536870911]	auto[1]	63	1			T5	1		T49	1		T207	1
auto[536870912:671088639]	auto[0]	56	1			T5	1		T15	1		T16	1
auto[536870912:671088639]	auto[1]	45	1			T49	1		T209	1		T147	1
auto[671088640:805306367]	auto[0]	42	1			T49	1		T106	1		T6	1
auto[671088640:805306367]	auto[1]	46	1			T49	2		T106	1		T46	1
auto[805306368:939524095]	auto[0]	50	1			T15	1		T210	1		T106	1
auto[805306368:939524095]	auto[1]	58	1			T5	1		T49	1		T47	1
auto[939524096:1073741823]	auto[0]	53	1			T3	1		T91	1		T121	1
auto[939524096:1073741823]	auto[1]	41	1			T139	1		T6	2		T205	1
auto[1073741824:1207959551]	auto[0]	54	1			T15	1		T18	1		T45	1
auto[1073741824:1207959551]	auto[1]	63	1			T49	3		T209	1		T318	1
auto[1207959552:1342177279]	auto[0]	57	1			T15	1		T50	1		T72	1
auto[1207959552:1342177279]	auto[1]	57	1			T35	1		T49	1		T139	1
auto[1342177280:1476395007]	auto[0]	37	1			T5	2		T15	1		T50	1
auto[1342177280:1476395007]	auto[1]	54	1			T5	1		T6	1		T86	1
auto[1476395008:1610612735]	auto[0]	48	1			T5	2		T72	1		T144	1
auto[1476395008:1610612735]	auto[1]	51	1			T5	1		T16	1		T45	1
auto[1610612736:1744830463]	auto[0]	53	1			T3	1		T24	1		T55	1
auto[1610612736:1744830463]	auto[1]	47	1			T18	1		T49	1		T46	1
auto[1744830464:1879048191]	auto[0]	49	1			T5	1		T49	1		T144	1
auto[1744830464:1879048191]	auto[1]	40	1			T210	1		T6	2		T62	1
auto[1879048192:2013265919]	auto[0]	50	1			T49	1		T24	1		T47	1
auto[1879048192:2013265919]	auto[1]	47	1			T55	1		T242	1		T86	1
auto[2013265920:2147483647]	auto[0]	45	1			T3	1		T49	2		T25	1
auto[2013265920:2147483647]	auto[1]	63	1			T5	1		T35	1		T139	1
auto[2147483648:2281701375]	auto[0]	53	1			T3	2		T15	1		T91	2
auto[2147483648:2281701375]	auto[1]	55	1			T5	1		T6	1		T55	1
auto[2281701376:2415919103]	auto[0]	54	1			T5	1		T18	1		T35	1
auto[2281701376:2415919103]	auto[1]	63	1			T210	1		T49	4		T209	1
auto[2415919104:2550136831]	auto[0]	62	1			T5	2		T18	1		T49	1
auto[2415919104:2550136831]	auto[1]	55	1			T49	2		T47	1		T58	1
auto[2550136832:2684354559]	auto[0]	50	1			T50	1		T49	1		T106	1
auto[2550136832:2684354559]	auto[1]	49	1			T210	1		T207	1		T46	1
auto[2684354560:2818572287]	auto[0]	42	1			T25	1		T57	1		T294	1
auto[2684354560:2818572287]	auto[1]	44	1			T5	1		T49	1		T55	1
auto[2818572288:2952790015]	auto[0]	55	1			T3	1		T106	1		T47	1
auto[2818572288:2952790015]	auto[1]	71	1			T5	1		T49	1		T205	1
auto[2952790016:3087007743]	auto[0]	39	1			T5	2		T57	1		T59	1
auto[2952790016:3087007743]	auto[1]	66	1			T5	1		T16	1		T112	1
auto[3087007744:3221225471]	auto[0]	68	1			T5	2		T210	1		T47	1
auto[3087007744:3221225471]	auto[1]	66	1			T3	1		T5	1		T210	1
auto[3221225472:3355443199]	auto[0]	49	1			T1	1		T49	2		T211	1
auto[3221225472:3355443199]	auto[1]	74	1			T49	1		T6	1		T112	1
auto[3355443200:3489660927]	auto[0]	48	1			T91	1		T121	1		T269	1
auto[3355443200:3489660927]	auto[1]	53	1			T35	1		T45	1		T139	1
auto[3489660928:3623878655]	auto[0]	50	1			T35	1		T49	2		T139	1
auto[3489660928:3623878655]	auto[1]	64	1			T112	1		T249	2		T155	1
auto[3623878656:3758096383]	auto[0]	46	1			T24	1		T106	1		T6	1
auto[3623878656:3758096383]	auto[1]	68	1			T16	1		T91	1		T96	1
auto[3758096384:3892314111]	auto[0]	37	1			T5	1		T96	1		T278	1
auto[3758096384:3892314111]	auto[1]	65	1			T16	1		T45	1		T49	1
auto[3892314112:4026531839]	auto[0]	57	1			T6	2		T276	1		T198	2
auto[3892314112:4026531839]	auto[1]	61	1			T96	1		T132	1		T55	1
auto[4026531840:4160749567]	auto[0]	56	1			T5	1		T15	1		T18	1
auto[4026531840:4160749567]	auto[1]	61	1			T96	1		T49	3		T207	1
auto[4160749568:4294967295]	auto[0]	53	1			T15	1		T6	3		T94	1
auto[4160749568:4294967295]	auto[1]	52	1			T50	1		T49	2		T112	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1588

1

T3

6

T5

18

T15

9

auto[1]

1839

1

T1

1

T3

3

T5

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T5	1		T49	1		T106	1
auto[134217728:268435455]	114	1			T5	1		T49	2		T24	1
auto[268435456:402653183]	103	1			T5	1		T96	1		T49	1
auto[402653184:536870911]	126	1			T3	2		T5	1		T15	1
auto[536870912:671088639]	98	1			T5	4		T50	1		T49	3
auto[671088640:805306367]	105	1			T5	1		T16	1		T18	1
auto[805306368:939524095]	101	1			T35	2		T49	1		T207	1
auto[939524096:1073741823]	117	1			T5	2		T15	1		T16	1
auto[1073741824:1207959551]	117	1			T5	3		T91	1		T50	1
auto[1207959552:1342177279]	112	1			T210	2		T6	1		T120	1
auto[1342177280:1476395007]	100	1			T50	1		T49	2		T46	1
auto[1476395008:1610612735]	112	1			T5	1		T16	1		T18	1
auto[1610612736:1744830463]	91	1			T45	1		T210	1		T205	1
auto[1744830464:1879048191]	100	1			T1	1		T15	1		T91	1
auto[1879048192:2013265919]	111	1			T5	1		T15	1		T49	1
auto[2013265920:2147483647]	102	1			T3	2		T35	2		T50	1
auto[2147483648:2281701375]	99	1			T3	1		T5	1		T15	1
auto[2281701376:2415919103]	115	1			T5	1		T49	3		T24	1
auto[2415919104:2550136831]	116	1			T3	1		T5	2		T16	1
auto[2550136832:2684354559]	82	1			T106	1		T121	1		T318	1
auto[2684354560:2818572287]	112	1			T15	1		T91	1		T210	1
auto[2818572288:2952790015]	117	1			T3	2		T5	1		T35	1
auto[2952790016:3087007743]	113	1			T15	1		T210	1		T207	1
auto[3087007744:3221225471]	107	1			T5	1		T91	2		T35	1
auto[3221225472:3355443199]	112	1			T15	1		T49	2		T207	1
auto[3355443200:3489660927]	116	1			T5	1		T6	3		T318	2
auto[3489660928:3623878655]	102	1			T18	1		T45	1		T210	1
auto[3623878656:3758096383]	103	1			T5	2		T49	2		T139	1
auto[3758096384:3892314111]	122	1			T5	1		T49	2		T139	1
auto[3892314112:4026531839]	83	1			T15	2		T45	1		T49	1
auto[4026531840:4160749567]	121	1			T3	1		T5	2		T91	1
auto[4160749568:4294967295]	98	1			T5	1		T16	1		T72	1