Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3018

1

T1

1

T3

9

T5

29

auto[1]

281

1

T120

3

T121

3

T143

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T5	1		T15	1		T16	1
auto[134217728:268435455]	101	1			T3	2		T5	2		T91	1
auto[268435456:402653183]	119	1			T16	1		T18	1		T91	1
auto[402653184:536870911]	107	1			T5	1		T50	1		T139	1
auto[536870912:671088639]	103	1			T91	1		T210	1		T49	2
auto[671088640:805306367]	116	1			T3	1		T5	1		T91	1
auto[805306368:939524095]	87	1			T5	2		T210	1		T49	2
auto[939524096:1073741823]	114	1			T5	1		T49	4		T24	1
auto[1073741824:1207959551]	99	1			T16	1		T18	1		T6	1
auto[1207959552:1342177279]	108	1			T5	1		T15	1		T45	1
auto[1342177280:1476395007]	107	1			T50	1		T49	1		T139	1
auto[1476395008:1610612735]	106	1			T5	1		T15	1		T18	1
auto[1610612736:1744830463]	96	1			T1	1		T15	1		T91	1
auto[1744830464:1879048191]	107	1			T45	1		T51	1		T106	1
auto[1879048192:2013265919]	104	1			T5	1		T16	1		T49	1
auto[2013265920:2147483647]	101	1			T35	1		T49	2		T106	1
auto[2147483648:2281701375]	94	1			T91	1		T35	1		T45	1
auto[2281701376:2415919103]	89	1			T5	2		T24	1		T106	1
auto[2415919104:2550136831]	85	1			T5	1		T35	1		T49	1
auto[2550136832:2684354559]	98	1			T3	1		T5	4		T15	1
auto[2684354560:2818572287]	88	1			T3	1		T207	2		T6	1
auto[2818572288:2952790015]	101	1			T5	3		T16	1		T18	1
auto[2952790016:3087007743]	116	1			T3	3		T5	1		T49	2
auto[3087007744:3221225471]	100	1			T5	1		T15	1		T96	1
auto[3221225472:3355443199]	102	1			T5	2		T15	1		T18	1
auto[3355443200:3489660927]	129	1			T5	1		T96	1		T49	1
auto[3489660928:3623878655]	107	1			T35	1		T210	1		T49	1
auto[3623878656:3758096383]	120	1			T5	1		T15	1		T35	1
auto[3758096384:3892314111]	101	1			T5	1		T91	1		T96	1
auto[3892314112:4026531839]	92	1			T15	1		T35	2		T96	1
auto[4026531840:4160749567]	105	1			T50	1		T210	1		T49	1
auto[4160749568:4294967295]	94	1			T3	1		T5	1		T15	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	95	1			T5	1		T15	1		T16	1
auto[0:134217727]	auto[1]	8	1			T289	1		T257	1		T358	1
auto[134217728:268435455]	auto[0]	92	1			T3	2		T5	2		T91	1
auto[134217728:268435455]	auto[1]	9	1			T144	1		T334	1		T310	1
auto[268435456:402653183]	auto[0]	110	1			T16	1		T18	1		T91	1
auto[268435456:402653183]	auto[1]	9	1			T143	1		T147	1		T289	1
auto[402653184:536870911]	auto[0]	96	1			T5	1		T50	1		T139	1
auto[402653184:536870911]	auto[1]	11	1			T145	1		T252	1		T259	1
auto[536870912:671088639]	auto[0]	97	1			T91	1		T210	1		T49	2
auto[536870912:671088639]	auto[1]	6	1			T120	1		T145	1		T303	1
auto[671088640:805306367]	auto[0]	106	1			T3	1		T5	1		T91	1
auto[671088640:805306367]	auto[1]	10	1			T144	1		T145	1		T257	1
auto[805306368:939524095]	auto[0]	82	1			T5	2		T210	1		T49	2
auto[805306368:939524095]	auto[1]	5	1			T252	1		T259	1		T392	1
auto[939524096:1073741823]	auto[0]	102	1			T5	1		T49	4		T24	1
auto[939524096:1073741823]	auto[1]	12	1			T145	2		T146	1		T294	1
auto[1073741824:1207959551]	auto[0]	90	1			T16	1		T18	1		T6	1
auto[1073741824:1207959551]	auto[1]	9	1			T145	1		T336	1		T334	1
auto[1207959552:1342177279]	auto[0]	98	1			T5	1		T15	1		T45	1
auto[1207959552:1342177279]	auto[1]	10	1			T155	1		T257	1		T310	1
auto[1342177280:1476395007]	auto[0]	99	1			T50	1		T49	1		T139	1
auto[1342177280:1476395007]	auto[1]	8	1			T121	1		T334	1		T391	1
auto[1476395008:1610612735]	auto[0]	100	1			T5	1		T15	1		T18	1
auto[1476395008:1610612735]	auto[1]	6	1			T289	1		T294	1		T310	1
auto[1610612736:1744830463]	auto[0]	91	1			T1	1		T15	1		T91	1
auto[1610612736:1744830463]	auto[1]	5	1			T245	1		T388	1		T394	1
auto[1744830464:1879048191]	auto[0]	99	1			T45	1		T51	1		T106	1
auto[1744830464:1879048191]	auto[1]	8	1			T121	1		T380	1		T310	2
auto[1879048192:2013265919]	auto[0]	96	1			T5	1		T16	1		T49	1
auto[1879048192:2013265919]	auto[1]	8	1			T121	1		T145	1		T289	2
auto[2013265920:2147483647]	auto[0]	94	1			T35	1		T49	2		T106	1
auto[2013265920:2147483647]	auto[1]	7	1			T120	1		T245	1		T293	1
auto[2147483648:2281701375]	auto[0]	88	1			T91	1		T35	1		T45	1
auto[2147483648:2281701375]	auto[1]	6	1			T145	1		T334	1		T310	1
auto[2281701376:2415919103]	auto[0]	83	1			T5	2		T24	1		T106	1
auto[2281701376:2415919103]	auto[1]	6	1			T143	1		T245	1		T259	1
auto[2415919104:2550136831]	auto[0]	75	1			T5	1		T35	1		T49	1
auto[2415919104:2550136831]	auto[1]	10	1			T145	1		T146	1		T289	1
auto[2550136832:2684354559]	auto[0]	87	1			T3	1		T5	4		T15	1
auto[2550136832:2684354559]	auto[1]	11	1			T147	1		T310	1		T351	1
auto[2684354560:2818572287]	auto[0]	82	1			T3	1		T207	2		T6	1
auto[2684354560:2818572287]	auto[1]	6	1			T145	1		T146	1		T289	2
auto[2818572288:2952790015]	auto[0]	88	1			T5	3		T16	1		T18	1
auto[2818572288:2952790015]	auto[1]	13	1			T143	1		T146	1		T289	1
auto[2952790016:3087007743]	auto[0]	107	1			T3	3		T5	1		T49	2
auto[2952790016:3087007743]	auto[1]	9	1			T155	1		T289	1		T334	1
auto[3087007744:3221225471]	auto[0]	86	1			T5	1		T15	1		T96	1
auto[3087007744:3221225471]	auto[1]	14	1			T147	1		T252	1		T310	1
auto[3221225472:3355443199]	auto[0]	91	1			T5	2		T15	1		T18	1
auto[3221225472:3355443199]	auto[1]	11	1			T289	2		T271	1		T351	1
auto[3355443200:3489660927]	auto[0]	119	1			T5	1		T96	1		T49	1
auto[3355443200:3489660927]	auto[1]	10	1			T381	1		T245	1		T391	2
auto[3489660928:3623878655]	auto[0]	102	1			T35	1		T210	1		T49	1
auto[3489660928:3623878655]	auto[1]	5	1			T143	3		T380	1		T259	1
auto[3623878656:3758096383]	auto[0]	112	1			T5	1		T15	1		T35	1
auto[3623878656:3758096383]	auto[1]	8	1			T146	2		T147	1		T245	1
auto[3758096384:3892314111]	auto[0]	89	1			T5	1		T91	1		T96	1
auto[3758096384:3892314111]	auto[1]	12	1			T143	1		T155	1		T336	1
auto[3892314112:4026531839]	auto[0]	82	1			T15	1		T35	2		T96	1
auto[3892314112:4026531839]	auto[1]	10	1			T257	1		T310	2		T271	1
auto[4026531840:4160749567]	auto[0]	93	1			T50	1		T210	1		T49	1
auto[4026531840:4160749567]	auto[1]	12	1			T120	1		T334	2		T245	1
auto[4160749568:4294967295]	auto[0]	87	1			T3	1		T5	1		T15	1
auto[4160749568:4294967295]	auto[1]	7	1			T289	1		T294	1		T326	1