Unified Coverage Report :: Group Instance : attest_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1609

1

T1

1

T3

7

T5

15

auto[1]

1818

1

T3

2

T5

14

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T3	1		T15	1		T16	2
auto[134217728:268435455]	103	1			T88	1		T29	1		T58	3
auto[268435456:402653183]	117	1			T5	1		T15	2		T96	1
auto[402653184:536870911]	103	1			T5	1		T96	1		T210	1
auto[536870912:671088639]	109	1			T5	1		T15	1		T18	1
auto[671088640:805306367]	99	1			T5	1		T91	2		T49	1
auto[805306368:939524095]	106	1			T3	1		T49	2		T24	1
auto[939524096:1073741823]	128	1			T3	1		T5	4		T35	1
auto[1073741824:1207959551]	130	1			T5	2		T15	1		T91	1
auto[1207959552:1342177279]	91	1			T49	1		T71	1		T73	1
auto[1342177280:1476395007]	105	1			T5	2		T45	1		T49	1
auto[1476395008:1610612735]	97	1			T3	1		T18	1		T35	1
auto[1610612736:1744830463]	110	1			T3	1		T5	1		T210	1
auto[1744830464:1879048191]	110	1			T5	1		T15	2		T45	1
auto[1879048192:2013265919]	109	1			T15	1		T45	1		T49	2
auto[2013265920:2147483647]	126	1			T5	1		T35	1		T210	1
auto[2147483648:2281701375]	96	1			T49	1		T106	1		T6	3
auto[2281701376:2415919103]	100	1			T15	1		T91	1		T50	1
auto[2415919104:2550136831]	107	1			T5	1		T91	1		T51	1
auto[2550136832:2684354559]	121	1			T5	1		T49	4		T6	1
auto[2684354560:2818572287]	91	1			T5	1		T16	1		T18	1
auto[2818572288:2952790015]	112	1			T5	1		T35	1		T45	1
auto[2952790016:3087007743]	113	1			T5	2		T91	1		T96	1
auto[3087007744:3221225471]	105	1			T5	1		T16	1		T35	1
auto[3221225472:3355443199]	94	1			T3	1		T5	1		T50	1
auto[3355443200:3489660927]	100	1			T5	3		T18	1		T49	1
auto[3489660928:3623878655]	105	1			T1	1		T15	1		T210	1
auto[3623878656:3758096383]	98	1			T49	1		T6	2		T47	1
auto[3758096384:3892314111]	123	1			T18	1		T49	1		T6	2
auto[3892314112:4026531839]	93	1			T35	1		T49	2		T139	1
auto[4026531840:4160749567]	119	1			T3	1		T5	2		T16	1
auto[4160749568:4294967295]	100	1			T3	2		T5	1		T35	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T3	1		T15	1		T16	1
auto[0:134217727]	auto[1]	60	1			T16	1		T49	2		T55	1
auto[134217728:268435455]	auto[0]	51	1			T88	1		T58	2		T59	1
auto[134217728:268435455]	auto[1]	52	1			T29	1		T58	1		T59	1
auto[268435456:402653183]	auto[0]	50	1			T15	2		T62	1		T120	1
auto[268435456:402653183]	auto[1]	67	1			T5	1		T96	1		T6	1
auto[402653184:536870911]	auto[0]	55	1			T96	1		T49	1		T24	1
auto[402653184:536870911]	auto[1]	48	1			T5	1		T210	1		T49	1
auto[536870912:671088639]	auto[0]	60	1			T15	1		T18	1		T203	1
auto[536870912:671088639]	auto[1]	49	1			T5	1		T49	2		T106	1
auto[671088640:805306367]	auto[0]	49	1			T91	1		T55	1		T250	1
auto[671088640:805306367]	auto[1]	50	1			T5	1		T91	1		T49	1
auto[805306368:939524095]	auto[0]	54	1			T3	1		T49	1		T207	1
auto[805306368:939524095]	auto[1]	52	1			T49	1		T24	1		T6	1
auto[939524096:1073741823]	auto[0]	65	1			T3	1		T5	3		T35	1
auto[939524096:1073741823]	auto[1]	63	1			T5	1		T96	1		T49	1
auto[1073741824:1207959551]	auto[0]	68	1			T5	1		T15	1		T91	1
auto[1073741824:1207959551]	auto[1]	62	1			T5	1		T96	1		T210	1
auto[1207959552:1342177279]	auto[0]	41	1			T73	1		T269	1		T58	1
auto[1207959552:1342177279]	auto[1]	50	1			T49	1		T71	1		T266	1
auto[1342177280:1476395007]	auto[0]	52	1			T24	1		T6	2		T47	1
auto[1342177280:1476395007]	auto[1]	53	1			T5	2		T45	1		T49	1
auto[1476395008:1610612735]	auto[0]	45	1			T3	1		T18	1		T146	1
auto[1476395008:1610612735]	auto[1]	52	1			T35	1		T49	1		T102	1
auto[1610612736:1744830463]	auto[0]	56	1			T3	1		T5	1		T210	1
auto[1610612736:1744830463]	auto[1]	54	1			T49	1		T249	1		T55	2
auto[1744830464:1879048191]	auto[0]	48	1			T5	1		T15	1		T50	2
auto[1744830464:1879048191]	auto[1]	62	1			T15	1		T45	1		T49	1
auto[1879048192:2013265919]	auto[0]	47	1			T15	1		T49	1		T72	1
auto[1879048192:2013265919]	auto[1]	62	1			T45	1		T49	1		T139	2
auto[2013265920:2147483647]	auto[0]	56	1			T35	1		T210	1		T49	2
auto[2013265920:2147483647]	auto[1]	70	1			T5	1		T49	3		T207	1
auto[2147483648:2281701375]	auto[0]	50	1			T106	1		T6	1		T146	1
auto[2147483648:2281701375]	auto[1]	46	1			T49	1		T6	2		T47	1
auto[2281701376:2415919103]	auto[0]	44	1			T15	1		T91	1		T49	1
auto[2281701376:2415919103]	auto[1]	56	1			T50	1		T210	1		T6	1
auto[2415919104:2550136831]	auto[0]	56	1			T5	1		T55	1		T94	1
auto[2415919104:2550136831]	auto[1]	51	1			T91	1		T51	1		T46	1
auto[2550136832:2684354559]	auto[0]	50	1			T49	2		T6	1		T85	1
auto[2550136832:2684354559]	auto[1]	71	1			T5	1		T49	2		T112	1
auto[2684354560:2818572287]	auto[0]	36	1			T18	1		T139	1		T72	1
auto[2684354560:2818572287]	auto[1]	55	1			T5	1		T16	1		T139	1
auto[2818572288:2952790015]	auto[0]	56	1			T5	1		T45	1		T139	1
auto[2818572288:2952790015]	auto[1]	56	1			T35	1		T49	1		T207	1
auto[2952790016:3087007743]	auto[0]	55	1			T5	1		T91	1		T96	1
auto[2952790016:3087007743]	auto[1]	58	1			T5	1		T73	1		T120	1
auto[3087007744:3221225471]	auto[0]	48	1			T5	1		T35	1		T50	1
auto[3087007744:3221225471]	auto[1]	57	1			T16	1		T49	1		T112	1
auto[3221225472:3355443199]	auto[0]	46	1			T50	1		T49	1		T316	1
auto[3221225472:3355443199]	auto[1]	48	1			T3	1		T5	1		T49	1
auto[3355443200:3489660927]	auto[0]	49	1			T5	2		T18	1		T106	1
auto[3355443200:3489660927]	auto[1]	51	1			T5	1		T49	1		T207	1
auto[3489660928:3623878655]	auto[0]	39	1			T1	1		T15	1		T87	1
auto[3489660928:3623878655]	auto[1]	66	1			T210	1		T49	1		T207	1
auto[3623878656:3758096383]	auto[0]	39	1			T47	1		T95	1		T57	1
auto[3623878656:3758096383]	auto[1]	59	1			T49	1		T6	2		T55	1
auto[3758096384:3892314111]	auto[0]	54	1			T6	1		T121	1		T55	1
auto[3758096384:3892314111]	auto[1]	69	1			T18	1		T49	1		T6	1
auto[3892314112:4026531839]	auto[0]	47	1			T35	1		T139	1		T121	1
auto[3892314112:4026531839]	auto[1]	46	1			T49	2		T318	1		T145	1
auto[4026531840:4160749567]	auto[0]	48	1			T5	2		T18	1		T49	1
auto[4026531840:4160749567]	auto[1]	71	1			T3	1		T16	1		T6	1
auto[4160749568:4294967295]	auto[0]	48	1			T3	2		T5	1		T35	2
auto[4160749568:4294967295]	auto[1]	52	1			T96	1		T139	1		T6	2