Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.67 99.04 97.99 98.20 100.00 99.02 98.41 91.07


Total test records in report: 1084
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T1012 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.105222102 Aug 04 04:31:05 PM PDT 24 Aug 04 04:31:06 PM PDT 24 67057837 ps
T1013 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.495552761 Aug 04 04:31:01 PM PDT 24 Aug 04 04:31:06 PM PDT 24 185939126 ps
T1014 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1103007650 Aug 04 04:31:19 PM PDT 24 Aug 04 04:31:20 PM PDT 24 21075014 ps
T1015 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.65579279 Aug 04 04:31:12 PM PDT 24 Aug 04 04:31:13 PM PDT 24 131667821 ps
T1016 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1176661608 Aug 04 04:31:16 PM PDT 24 Aug 04 04:31:17 PM PDT 24 47370731 ps
T179 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1497529252 Aug 04 04:31:17 PM PDT 24 Aug 04 04:31:22 PM PDT 24 790101253 ps
T1017 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1121686471 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:12 PM PDT 24 9523465 ps
T177 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.911744134 Aug 04 04:31:21 PM PDT 24 Aug 04 04:31:25 PM PDT 24 339553960 ps
T1018 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3394308552 Aug 04 04:31:02 PM PDT 24 Aug 04 04:31:16 PM PDT 24 369156451 ps
T1019 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.144332831 Aug 04 04:31:15 PM PDT 24 Aug 04 04:31:18 PM PDT 24 191128179 ps
T1020 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2710498113 Aug 04 04:31:16 PM PDT 24 Aug 04 04:31:17 PM PDT 24 30141073 ps
T1021 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2612271445 Aug 04 04:30:58 PM PDT 24 Aug 04 04:31:01 PM PDT 24 412454442 ps
T1022 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2470947189 Aug 04 04:31:27 PM PDT 24 Aug 04 04:31:33 PM PDT 24 135777446 ps
T1023 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1772212921 Aug 04 04:31:13 PM PDT 24 Aug 04 04:31:26 PM PDT 24 1555873077 ps
T1024 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2086376832 Aug 04 04:31:19 PM PDT 24 Aug 04 04:31:22 PM PDT 24 72062018 ps
T1025 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3650584072 Aug 04 04:31:06 PM PDT 24 Aug 04 04:31:07 PM PDT 24 76177142 ps
T1026 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3192580034 Aug 04 04:31:12 PM PDT 24 Aug 04 04:31:14 PM PDT 24 41752734 ps
T1027 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.579312562 Aug 04 04:32:34 PM PDT 24 Aug 04 04:32:35 PM PDT 24 29948043 ps
T1028 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3384561170 Aug 04 04:31:08 PM PDT 24 Aug 04 04:31:09 PM PDT 24 23682868 ps
T1029 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1667839459 Aug 04 04:32:52 PM PDT 24 Aug 04 04:32:53 PM PDT 24 23494959 ps
T1030 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1409789552 Aug 04 04:31:20 PM PDT 24 Aug 04 04:31:23 PM PDT 24 322734343 ps
T1031 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2353006692 Aug 04 04:31:02 PM PDT 24 Aug 04 04:31:03 PM PDT 24 11496061 ps
T1032 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1929589080 Aug 04 04:31:01 PM PDT 24 Aug 04 04:31:02 PM PDT 24 50950997 ps
T171 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.397349320 Aug 04 04:31:09 PM PDT 24 Aug 04 04:31:13 PM PDT 24 250166698 ps
T1033 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1195245566 Aug 04 04:31:20 PM PDT 24 Aug 04 04:31:21 PM PDT 24 132729602 ps
T1034 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3048160098 Aug 04 04:31:06 PM PDT 24 Aug 04 04:31:07 PM PDT 24 49323701 ps
T174 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3605703990 Aug 04 04:32:35 PM PDT 24 Aug 04 04:32:41 PM PDT 24 854288107 ps
T164 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2932089895 Aug 04 04:31:05 PM PDT 24 Aug 04 04:31:09 PM PDT 24 133576863 ps
T1035 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2439776381 Aug 04 04:31:06 PM PDT 24 Aug 04 04:31:08 PM PDT 24 419134542 ps
T1036 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1270959914 Aug 04 04:31:06 PM PDT 24 Aug 04 04:31:15 PM PDT 24 3375765319 ps
T1037 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1945538320 Aug 04 04:31:20 PM PDT 24 Aug 04 04:31:26 PM PDT 24 239528026 ps
T1038 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.277773168 Aug 04 04:31:18 PM PDT 24 Aug 04 04:31:18 PM PDT 24 59215947 ps
T1039 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3380572436 Aug 04 04:31:17 PM PDT 24 Aug 04 04:31:19 PM PDT 24 52172372 ps
T1040 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.649577611 Aug 04 04:31:08 PM PDT 24 Aug 04 04:31:19 PM PDT 24 920251021 ps
T1041 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1448684914 Aug 04 04:31:11 PM PDT 24 Aug 04 04:31:13 PM PDT 24 293591006 ps
T170 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.505541854 Aug 04 04:30:57 PM PDT 24 Aug 04 04:31:06 PM PDT 24 924819998 ps
T1042 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1271061237 Aug 04 04:30:55 PM PDT 24 Aug 04 04:30:56 PM PDT 24 18387196 ps
T1043 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3373378149 Aug 04 04:31:19 PM PDT 24 Aug 04 04:31:20 PM PDT 24 11459388 ps
T176 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3060672141 Aug 04 04:31:07 PM PDT 24 Aug 04 04:31:12 PM PDT 24 382910353 ps
T1044 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1084991721 Aug 04 04:31:16 PM PDT 24 Aug 04 04:31:18 PM PDT 24 143277706 ps
T172 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.657887000 Aug 04 04:31:20 PM PDT 24 Aug 04 04:31:26 PM PDT 24 490142663 ps
T1045 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.738551887 Aug 04 04:31:23 PM PDT 24 Aug 04 04:31:24 PM PDT 24 44183716 ps
T1046 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2978875859 Aug 04 04:31:07 PM PDT 24 Aug 04 04:31:10 PM PDT 24 100106589 ps
T1047 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2926314132 Aug 04 04:31:04 PM PDT 24 Aug 04 04:31:05 PM PDT 24 12294996 ps
T1048 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1184223654 Aug 04 04:30:56 PM PDT 24 Aug 04 04:30:59 PM PDT 24 62539363 ps
T178 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.716829233 Aug 04 04:31:30 PM PDT 24 Aug 04 04:31:39 PM PDT 24 1273174935 ps
T1049 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1943501768 Aug 04 04:31:12 PM PDT 24 Aug 04 04:31:16 PM PDT 24 416674621 ps
T1050 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3334636380 Aug 04 04:30:59 PM PDT 24 Aug 04 04:31:16 PM PDT 24 4123196017 ps
T1051 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3295199515 Aug 04 04:31:20 PM PDT 24 Aug 04 04:31:23 PM PDT 24 164539189 ps
T1052 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.285196980 Aug 04 04:32:32 PM PDT 24 Aug 04 04:32:33 PM PDT 24 88337699 ps
T1053 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.677230223 Aug 04 04:31:21 PM PDT 24 Aug 04 04:31:22 PM PDT 24 77806759 ps
T1054 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.797512053 Aug 04 04:32:26 PM PDT 24 Aug 04 04:32:27 PM PDT 24 9707506 ps
T1055 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3440562304 Aug 04 04:31:11 PM PDT 24 Aug 04 04:31:14 PM PDT 24 657048352 ps
T1056 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3505456955 Aug 04 04:31:03 PM PDT 24 Aug 04 04:31:04 PM PDT 24 21378786 ps
T1057 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1607828782 Aug 04 04:31:19 PM PDT 24 Aug 04 04:31:26 PM PDT 24 986795811 ps
T1058 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.145845596 Aug 04 04:31:14 PM PDT 24 Aug 04 04:31:17 PM PDT 24 439940592 ps
T1059 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1276535879 Aug 04 04:31:18 PM PDT 24 Aug 04 04:31:23 PM PDT 24 233693202 ps
T1060 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3387345156 Aug 04 04:31:15 PM PDT 24 Aug 04 04:31:16 PM PDT 24 16740314 ps
T165 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4047215124 Aug 04 04:31:20 PM PDT 24 Aug 04 04:31:25 PM PDT 24 124364759 ps
T1061 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.467835394 Aug 04 04:31:15 PM PDT 24 Aug 04 04:31:19 PM PDT 24 172850353 ps
T1062 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1909360379 Aug 04 04:31:05 PM PDT 24 Aug 04 04:31:19 PM PDT 24 370587832 ps
T1063 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2231000840 Aug 04 04:31:12 PM PDT 24 Aug 04 04:31:14 PM PDT 24 105239666 ps
T1064 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.345018666 Aug 04 04:31:27 PM PDT 24 Aug 04 04:31:28 PM PDT 24 11791340 ps
T1065 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1974355814 Aug 04 04:31:13 PM PDT 24 Aug 04 04:31:16 PM PDT 24 210396498 ps
T1066 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.146833787 Aug 04 04:31:08 PM PDT 24 Aug 04 04:31:10 PM PDT 24 52595736 ps
T1067 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.172157413 Aug 04 04:31:17 PM PDT 24 Aug 04 04:31:33 PM PDT 24 906937435 ps
T1068 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3896359141 Aug 04 04:31:26 PM PDT 24 Aug 04 04:31:27 PM PDT 24 12104115 ps
T1069 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2864191590 Aug 04 04:31:13 PM PDT 24 Aug 04 04:31:14 PM PDT 24 199118316 ps
T1070 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3748509595 Aug 04 04:31:22 PM PDT 24 Aug 04 04:31:24 PM PDT 24 22482308 ps
T1071 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2325930704 Aug 04 04:31:13 PM PDT 24 Aug 04 04:31:16 PM PDT 24 82081036 ps
T1072 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2092890456 Aug 04 04:31:11 PM PDT 24 Aug 04 04:31:12 PM PDT 24 57224542 ps
T1073 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.146879290 Aug 04 04:31:19 PM PDT 24 Aug 04 04:31:21 PM PDT 24 64296236 ps
T1074 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2579099560 Aug 04 04:32:38 PM PDT 24 Aug 04 04:32:38 PM PDT 24 17216861 ps
T1075 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.4206718611 Aug 04 04:30:57 PM PDT 24 Aug 04 04:30:58 PM PDT 24 41548966 ps
T1076 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2485528112 Aug 04 04:31:00 PM PDT 24 Aug 04 04:31:14 PM PDT 24 394194192 ps
T1077 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1490832816 Aug 04 04:31:11 PM PDT 24 Aug 04 04:31:13 PM PDT 24 311013489 ps
T1078 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2742249242 Aug 04 04:31:16 PM PDT 24 Aug 04 04:31:18 PM PDT 24 101614858 ps
T1079 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2244699137 Aug 04 04:30:52 PM PDT 24 Aug 04 04:31:02 PM PDT 24 380068146 ps
T1080 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3371617002 Aug 04 04:31:13 PM PDT 24 Aug 04 04:31:15 PM PDT 24 77344675 ps
T1081 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1382628747 Aug 04 04:31:16 PM PDT 24 Aug 04 04:31:19 PM PDT 24 50807176 ps
T173 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.844207338 Aug 04 04:31:09 PM PDT 24 Aug 04 04:31:14 PM PDT 24 1808424288 ps
T1082 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1043451883 Aug 04 04:31:16 PM PDT 24 Aug 04 04:31:22 PM PDT 24 497940046 ps
T1083 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2462496708 Aug 04 04:31:04 PM PDT 24 Aug 04 04:31:04 PM PDT 24 54824658 ps
T1084 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3876028085 Aug 04 04:31:14 PM PDT 24 Aug 04 04:31:15 PM PDT 24 14990104 ps

Test location /workspace/coverage/default/17.keymgr_stress_all.1420950644
Short name T5
Test name
Test status
Simulation time 869655022 ps
CPU time 25.66 seconds
Started Aug 04 05:13:55 PM PDT 24
Finished Aug 04 05:14:20 PM PDT 24
Peak memory 220556 kb
Host smart-3c5d2c4c-1615-4112-9570-54b8b6e868fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420950644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1420950644
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2126374530
Short name T49
Test name
Test status
Simulation time 1795834921 ps
CPU time 25.42 seconds
Started Aug 04 05:13:59 PM PDT 24
Finished Aug 04 05:14:25 PM PDT 24
Peak memory 216844 kb
Host smart-9ab5ba41-9f48-41e5-aa0f-9c0ee7de7e65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126374530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2126374530
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2120652665
Short name T12
Test name
Test status
Simulation time 276841401 ps
CPU time 5.74 seconds
Started Aug 04 05:13:02 PM PDT 24
Finished Aug 04 05:13:08 PM PDT 24
Peak memory 229064 kb
Host smart-b76f1415-6e5c-4d48-9990-a97cd2322960
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120652665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2120652665
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.296521161
Short name T115
Test name
Test status
Simulation time 897965374 ps
CPU time 9.36 seconds
Started Aug 04 05:13:02 PM PDT 24
Finished Aug 04 05:13:12 PM PDT 24
Peak memory 221836 kb
Host smart-9a794999-f4d5-4b5d-a813-185a9442abdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296521161 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.296521161
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.553834093
Short name T3
Test name
Test status
Simulation time 598298797 ps
CPU time 6.55 seconds
Started Aug 04 05:13:27 PM PDT 24
Finished Aug 04 05:13:34 PM PDT 24
Peak memory 214164 kb
Host smart-5356f109-186f-489b-8c06-f0f75c1aeedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553834093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.553834093
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2401642463
Short name T59
Test name
Test status
Simulation time 5450259787 ps
CPU time 51.3 seconds
Started Aug 04 05:15:07 PM PDT 24
Finished Aug 04 05:15:58 PM PDT 24
Peak memory 216676 kb
Host smart-d51990c0-fa21-46eb-96c1-e68a325c1cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401642463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2401642463
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2152207439
Short name T6
Test name
Test status
Simulation time 633406941 ps
CPU time 22.97 seconds
Started Aug 04 05:14:38 PM PDT 24
Finished Aug 04 05:15:01 PM PDT 24
Peak memory 220952 kb
Host smart-a108df7f-79fc-492e-ad3f-06137bcab781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152207439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2152207439
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1480801099
Short name T289
Test name
Test status
Simulation time 1097195831 ps
CPU time 15.32 seconds
Started Aug 04 05:14:34 PM PDT 24
Finished Aug 04 05:14:49 PM PDT 24
Peak memory 215156 kb
Host smart-37e17f26-e162-446c-b8f1-716935cfad5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480801099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1480801099
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3924774882
Short name T80
Test name
Test status
Simulation time 8830742574 ps
CPU time 31.6 seconds
Started Aug 04 05:13:39 PM PDT 24
Finished Aug 04 05:14:11 PM PDT 24
Peak memory 223228 kb
Host smart-54a228ca-85f0-4179-a119-c980078c54c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924774882 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3924774882
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2686737346
Short name T15
Test name
Test status
Simulation time 44037093 ps
CPU time 2.53 seconds
Started Aug 04 05:14:53 PM PDT 24
Finished Aug 04 05:14:56 PM PDT 24
Peak memory 215084 kb
Host smart-7e33b358-f6de-4d2e-9a9a-2fa11bcb5891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686737346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2686737346
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1313974708
Short name T9
Test name
Test status
Simulation time 193313415 ps
CPU time 4.7 seconds
Started Aug 04 05:12:49 PM PDT 24
Finished Aug 04 05:12:54 PM PDT 24
Peak memory 222644 kb
Host smart-78d20922-eea8-4e92-bae4-9d03b51952a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313974708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1313974708
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2512662265
Short name T64
Test name
Test status
Simulation time 305042382 ps
CPU time 3.17 seconds
Started Aug 04 05:15:15 PM PDT 24
Finished Aug 04 05:15:18 PM PDT 24
Peak memory 209972 kb
Host smart-4b5bda71-7a64-4beb-a3db-2700823e3a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512662265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2512662265
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2612964956
Short name T117
Test name
Test status
Simulation time 1166839541 ps
CPU time 8.42 seconds
Started Aug 04 04:31:10 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 214620 kb
Host smart-239dc109-2833-428f-9573-c6955a04f9fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612964956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2612964956
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1289354346
Short name T303
Test name
Test status
Simulation time 385739513 ps
CPU time 7.18 seconds
Started Aug 04 05:12:53 PM PDT 24
Finished Aug 04 05:13:00 PM PDT 24
Peak memory 215492 kb
Host smart-80060a7f-c4e8-4a7b-961b-1f89eca7173d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289354346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1289354346
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.114752350
Short name T18
Test name
Test status
Simulation time 43894668 ps
CPU time 3.26 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:20 PM PDT 24
Peak memory 220772 kb
Host smart-162b9566-7a13-41a2-a117-7a13f3c1e3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114752350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.114752350
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.158895789
Short name T245
Test name
Test status
Simulation time 200940264 ps
CPU time 10.23 seconds
Started Aug 04 05:15:10 PM PDT 24
Finished Aug 04 05:15:20 PM PDT 24
Peak memory 215008 kb
Host smart-f795e3a5-1989-45a7-94dd-d2f6670be356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158895789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.158895789
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2966503392
Short name T147
Test name
Test status
Simulation time 246812759 ps
CPU time 7.05 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:24 PM PDT 24
Peak memory 214848 kb
Host smart-c5586f17-a757-4408-b26f-e5a990dd1781
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966503392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2966503392
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3265951868
Short name T58
Test name
Test status
Simulation time 1068656248 ps
CPU time 28.08 seconds
Started Aug 04 05:15:05 PM PDT 24
Finished Aug 04 05:15:33 PM PDT 24
Peak memory 220956 kb
Host smart-08b37770-ee14-43f6-b5f0-4a748277bcf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265951868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3265951868
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2559180671
Short name T126
Test name
Test status
Simulation time 1383547832 ps
CPU time 10.13 seconds
Started Aug 04 04:31:14 PM PDT 24
Finished Aug 04 04:31:24 PM PDT 24
Peak memory 214524 kb
Host smart-7f83dee0-aed3-440e-b59f-c9d2f92c54ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559180671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2559180671
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1153884200
Short name T708
Test name
Test status
Simulation time 795479982 ps
CPU time 20.38 seconds
Started Aug 04 05:13:49 PM PDT 24
Finished Aug 04 05:14:09 PM PDT 24
Peak memory 214384 kb
Host smart-085e84b0-3f7b-46a5-b783-7f41a0e06491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153884200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1153884200
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3974577873
Short name T198
Test name
Test status
Simulation time 1302239964 ps
CPU time 48.27 seconds
Started Aug 04 05:14:36 PM PDT 24
Finished Aug 04 05:15:24 PM PDT 24
Peak memory 222396 kb
Host smart-a845ad42-9956-4320-9a70-186a93cad870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974577873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3974577873
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.4091516771
Short name T112
Test name
Test status
Simulation time 179551364 ps
CPU time 11.85 seconds
Started Aug 04 05:14:18 PM PDT 24
Finished Aug 04 05:14:30 PM PDT 24
Peak memory 222460 kb
Host smart-04ead04a-7b9b-4fd8-a806-f982ece33c68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091516771 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.4091516771
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3528469135
Short name T257
Test name
Test status
Simulation time 461394634 ps
CPU time 12.5 seconds
Started Aug 04 05:13:06 PM PDT 24
Finished Aug 04 05:13:19 PM PDT 24
Peak memory 214216 kb
Host smart-09a288b0-f0b9-4e1d-9fbd-84fa5d2a3015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528469135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3528469135
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1939775437
Short name T561
Test name
Test status
Simulation time 311028470 ps
CPU time 6.32 seconds
Started Aug 04 05:14:34 PM PDT 24
Finished Aug 04 05:14:40 PM PDT 24
Peak memory 210468 kb
Host smart-da3a97d2-9608-4dc5-9061-b5403982783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939775437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1939775437
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3477499417
Short name T21
Test name
Test status
Simulation time 268656554 ps
CPU time 2.33 seconds
Started Aug 04 05:12:44 PM PDT 24
Finished Aug 04 05:12:47 PM PDT 24
Peak memory 208856 kb
Host smart-0b63bfee-2073-4f93-99d4-c5d9558e4eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477499417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3477499417
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3168790199
Short name T77
Test name
Test status
Simulation time 1171737529 ps
CPU time 44.42 seconds
Started Aug 04 05:14:28 PM PDT 24
Finished Aug 04 05:15:13 PM PDT 24
Peak memory 222524 kb
Host smart-8b5268a3-c721-4123-9727-87b90c06a338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168790199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3168790199
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.922987362
Short name T29
Test name
Test status
Simulation time 109880117 ps
CPU time 2.33 seconds
Started Aug 04 05:14:57 PM PDT 24
Finished Aug 04 05:15:00 PM PDT 24
Peak memory 209764 kb
Host smart-24add0be-7405-4ce1-ac06-b09a139aa44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922987362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.922987362
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.278226786
Short name T157
Test name
Test status
Simulation time 66459535 ps
CPU time 2.46 seconds
Started Aug 04 05:15:13 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 222532 kb
Host smart-5be54bac-568a-4267-b250-ba1f14f1797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278226786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.278226786
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3564592552
Short name T143
Test name
Test status
Simulation time 6939542543 ps
CPU time 21.75 seconds
Started Aug 04 05:13:13 PM PDT 24
Finished Aug 04 05:13:35 PM PDT 24
Peak memory 214404 kb
Host smart-b5dd80ed-aafe-4a67-b4f5-17e95a1065f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564592552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3564592552
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1416095498
Short name T387
Test name
Test status
Simulation time 1810967348 ps
CPU time 88.89 seconds
Started Aug 04 05:14:00 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 214928 kb
Host smart-c770d1f6-106a-4d72-9731-d71d1f9cc7ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416095498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1416095498
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3647305544
Short name T168
Test name
Test status
Simulation time 429308048 ps
CPU time 10.04 seconds
Started Aug 04 04:31:18 PM PDT 24
Finished Aug 04 04:31:28 PM PDT 24
Peak memory 214344 kb
Host smart-af632451-e1e4-4f8b-9a23-e6064f3b3b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647305544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3647305544
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2118323857
Short name T96
Test name
Test status
Simulation time 407617677 ps
CPU time 6.92 seconds
Started Aug 04 05:13:58 PM PDT 24
Finished Aug 04 05:14:05 PM PDT 24
Peak memory 214312 kb
Host smart-5ac2ae21-a976-4c3a-96a9-afef7d99c41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118323857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2118323857
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.443015759
Short name T66
Test name
Test status
Simulation time 4547186150 ps
CPU time 48.29 seconds
Started Aug 04 05:13:12 PM PDT 24
Finished Aug 04 05:14:00 PM PDT 24
Peak memory 222560 kb
Host smart-9d66df90-6064-499c-8888-bd3ff8a245d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443015759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.443015759
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2499273615
Short name T351
Test name
Test status
Simulation time 197281001 ps
CPU time 10.51 seconds
Started Aug 04 05:14:12 PM PDT 24
Finished Aug 04 05:14:23 PM PDT 24
Peak memory 222376 kb
Host smart-e2bf7e70-f17b-43c2-a635-d962f20f5a0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499273615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2499273615
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.4084089104
Short name T67
Test name
Test status
Simulation time 1538212627 ps
CPU time 21.84 seconds
Started Aug 04 05:13:14 PM PDT 24
Finished Aug 04 05:13:36 PM PDT 24
Peak memory 222508 kb
Host smart-2dad7885-03d3-4c02-a2f2-116049fe0eff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084089104 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.4084089104
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1728233152
Short name T28
Test name
Test status
Simulation time 247545586 ps
CPU time 6.26 seconds
Started Aug 04 05:14:46 PM PDT 24
Finished Aug 04 05:14:53 PM PDT 24
Peak memory 222240 kb
Host smart-179ff7f1-410a-49e1-80df-00f21b0a00cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728233152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1728233152
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.952829669
Short name T405
Test name
Test status
Simulation time 30823256 ps
CPU time 0.86 seconds
Started Aug 04 05:12:38 PM PDT 24
Finished Aug 04 05:12:39 PM PDT 24
Peak memory 205824 kb
Host smart-b7e4751f-3431-4890-be30-cc9d563ca189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952829669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.952829669
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2997160347
Short name T98
Test name
Test status
Simulation time 65675388 ps
CPU time 2.61 seconds
Started Aug 04 05:15:08 PM PDT 24
Finished Aug 04 05:15:11 PM PDT 24
Peak memory 214200 kb
Host smart-92ed78e4-cdd2-4bea-9c2d-8f66090c55da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997160347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2997160347
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2396334157
Short name T55
Test name
Test status
Simulation time 2669179333 ps
CPU time 33.96 seconds
Started Aug 04 05:15:14 PM PDT 24
Finished Aug 04 05:15:48 PM PDT 24
Peak memory 217076 kb
Host smart-b649e63d-f179-441a-bcf2-de63f783fd5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396334157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2396334157
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1697574218
Short name T163
Test name
Test status
Simulation time 331082057 ps
CPU time 11.17 seconds
Started Aug 04 04:31:08 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 214172 kb
Host smart-11164033-7e7c-4022-a086-a9c500c88d52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697574218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1697574218
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3688426089
Short name T287
Test name
Test status
Simulation time 67968672 ps
CPU time 4.8 seconds
Started Aug 04 05:13:52 PM PDT 24
Finished Aug 04 05:13:57 PM PDT 24
Peak memory 215952 kb
Host smart-dccbf484-c3f7-49b0-9412-5b4cd975a7b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3688426089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3688426089
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.783280306
Short name T229
Test name
Test status
Simulation time 2107628582 ps
CPU time 59.22 seconds
Started Aug 04 05:15:10 PM PDT 24
Finished Aug 04 05:16:09 PM PDT 24
Peak memory 222468 kb
Host smart-3bd6255a-3828-48da-a356-ef9fcfa517bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783280306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.783280306
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1583463707
Short name T19
Test name
Test status
Simulation time 2417907379 ps
CPU time 13.23 seconds
Started Aug 04 05:13:35 PM PDT 24
Finished Aug 04 05:13:48 PM PDT 24
Peak memory 211036 kb
Host smart-80e70a85-d13f-455e-af97-d77788ae8a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583463707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1583463707
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3303955756
Short name T267
Test name
Test status
Simulation time 1052749604 ps
CPU time 3.14 seconds
Started Aug 04 05:14:36 PM PDT 24
Finished Aug 04 05:14:39 PM PDT 24
Peak memory 222396 kb
Host smart-80880a84-609f-4884-a913-d35c4bfe735a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303955756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3303955756
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1591668806
Short name T310
Test name
Test status
Simulation time 264839848 ps
CPU time 3.64 seconds
Started Aug 04 05:14:24 PM PDT 24
Finished Aug 04 05:14:27 PM PDT 24
Peak memory 214236 kb
Host smart-d8a05482-1369-40c6-bd36-a0074130fee5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591668806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1591668806
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2793223809
Short name T224
Test name
Test status
Simulation time 14467636715 ps
CPU time 90.25 seconds
Started Aug 04 05:13:02 PM PDT 24
Finished Aug 04 05:14:33 PM PDT 24
Peak memory 217136 kb
Host smart-f24de4af-6eff-4830-aad4-b1a321eaac21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793223809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2793223809
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1363889715
Short name T13
Test name
Test status
Simulation time 1770030089 ps
CPU time 10.37 seconds
Started Aug 04 05:12:44 PM PDT 24
Finished Aug 04 05:12:55 PM PDT 24
Peak memory 230492 kb
Host smart-332772bd-3b7d-4f12-b624-8194538f14a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363889715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1363889715
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.381500310
Short name T46
Test name
Test status
Simulation time 808265289 ps
CPU time 3.24 seconds
Started Aug 04 05:12:52 PM PDT 24
Finished Aug 04 05:12:56 PM PDT 24
Peak memory 206124 kb
Host smart-6ae6b3b4-3a1d-4e8a-8d4e-291b8798c0e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381500310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.381500310
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2178781126
Short name T269
Test name
Test status
Simulation time 57124985 ps
CPU time 3.2 seconds
Started Aug 04 05:14:48 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 222420 kb
Host smart-33d0c207-5180-467d-bfb7-620c892a1af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178781126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2178781126
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3870377501
Short name T274
Test name
Test status
Simulation time 3586608494 ps
CPU time 67.76 seconds
Started Aug 04 05:15:17 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 222188 kb
Host smart-11ac2dd3-d6ad-4281-9b8d-60bb38049a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870377501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3870377501
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1425507967
Short name T24
Test name
Test status
Simulation time 954269748 ps
CPU time 13.57 seconds
Started Aug 04 05:12:40 PM PDT 24
Finished Aug 04 05:12:54 PM PDT 24
Peak memory 222108 kb
Host smart-fc90a108-d8de-4cb8-964a-ff682f35d9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425507967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1425507967
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1666386362
Short name T122
Test name
Test status
Simulation time 562560427 ps
CPU time 3.03 seconds
Started Aug 04 04:31:05 PM PDT 24
Finished Aug 04 04:31:09 PM PDT 24
Peak memory 214492 kb
Host smart-01bf4dcf-23f6-4a7d-a197-a6178038174b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666386362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1666386362
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2194370351
Short name T167
Test name
Test status
Simulation time 258122839 ps
CPU time 6.04 seconds
Started Aug 04 04:30:57 PM PDT 24
Finished Aug 04 04:31:03 PM PDT 24
Peak memory 205956 kb
Host smart-addda5e8-e0e6-4386-b1b9-a8f7ad44dc77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194370351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2194370351
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.657887000
Short name T172
Test name
Test status
Simulation time 490142663 ps
CPU time 6.32 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:26 PM PDT 24
Peak memory 214264 kb
Host smart-dd8d5802-584e-41e4-af7e-43603a6b3f78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657887000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.657887000
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3940515019
Short name T175
Test name
Test status
Simulation time 185236035 ps
CPU time 4.46 seconds
Started Aug 04 04:31:02 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 214188 kb
Host smart-e6b9b20e-ecf8-419e-8263-b4cc7d435111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940515019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3940515019
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2273871176
Short name T227
Test name
Test status
Simulation time 44605002519 ps
CPU time 540.7 seconds
Started Aug 04 05:15:28 PM PDT 24
Finished Aug 04 05:24:29 PM PDT 24
Peak memory 222704 kb
Host smart-9633d3fb-f0fb-49c4-bc66-2b9230596954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273871176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2273871176
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.4199859417
Short name T706
Test name
Test status
Simulation time 40164611 ps
CPU time 1.78 seconds
Started Aug 04 05:13:52 PM PDT 24
Finished Aug 04 05:13:54 PM PDT 24
Peak memory 214308 kb
Host smart-174f284f-860e-441d-a250-69000b1333fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199859417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.4199859417
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.108014168
Short name T252
Test name
Test status
Simulation time 503993253 ps
CPU time 26.56 seconds
Started Aug 04 05:14:35 PM PDT 24
Finished Aug 04 05:15:02 PM PDT 24
Peak memory 222396 kb
Host smart-9049e4e4-1e8a-4094-881f-344cb0dd4fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108014168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.108014168
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3296308420
Short name T204
Test name
Test status
Simulation time 94205485 ps
CPU time 3.85 seconds
Started Aug 04 05:15:00 PM PDT 24
Finished Aug 04 05:15:04 PM PDT 24
Peak memory 206996 kb
Host smart-57a0708a-0374-4e58-8ca4-a6cf5fc5a862
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296308420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3296308420
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1219448389
Short name T146
Test name
Test status
Simulation time 5475265666 ps
CPU time 71.42 seconds
Started Aug 04 05:15:22 PM PDT 24
Finished Aug 04 05:16:34 PM PDT 24
Peak memory 215272 kb
Host smart-03037837-a6f7-4ffc-96ae-0ee7f4e5188b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219448389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1219448389
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1385663860
Short name T285
Test name
Test status
Simulation time 121217721 ps
CPU time 2.52 seconds
Started Aug 04 05:15:22 PM PDT 24
Finished Aug 04 05:15:25 PM PDT 24
Peak memory 221964 kb
Host smart-70fc1c06-09c1-4191-a17e-68b885b474b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385663860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1385663860
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.385713877
Short name T160
Test name
Test status
Simulation time 24603378 ps
CPU time 1.87 seconds
Started Aug 04 05:14:35 PM PDT 24
Finished Aug 04 05:14:37 PM PDT 24
Peak memory 215720 kb
Host smart-bc646b54-41de-4adb-b039-82e652c91011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385713877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.385713877
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2388227977
Short name T158
Test name
Test status
Simulation time 71104352 ps
CPU time 1.9 seconds
Started Aug 04 05:14:52 PM PDT 24
Finished Aug 04 05:14:54 PM PDT 24
Peak memory 216572 kb
Host smart-2ab30e13-b88c-489d-ad69-0c85a7f6612b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388227977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2388227977
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1359467705
Short name T159
Test name
Test status
Simulation time 163004184 ps
CPU time 3.98 seconds
Started Aug 04 05:15:08 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 222548 kb
Host smart-bcdb6460-1da6-48a4-a1e4-6e975c3d53e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359467705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1359467705
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1801868018
Short name T75
Test name
Test status
Simulation time 393071909 ps
CPU time 19.33 seconds
Started Aug 04 05:13:48 PM PDT 24
Finished Aug 04 05:14:08 PM PDT 24
Peak memory 216884 kb
Host smart-c49d0042-3e92-4adc-9999-e051c981e33c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801868018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1801868018
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3031745727
Short name T217
Test name
Test status
Simulation time 154073577 ps
CPU time 3.67 seconds
Started Aug 04 05:13:48 PM PDT 24
Finished Aug 04 05:13:51 PM PDT 24
Peak memory 208676 kb
Host smart-7887642c-43d7-45ce-8d5b-596cee6e439f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031745727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3031745727
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.99099940
Short name T193
Test name
Test status
Simulation time 395093244 ps
CPU time 5.19 seconds
Started Aug 04 05:14:07 PM PDT 24
Finished Aug 04 05:14:12 PM PDT 24
Peak memory 222312 kb
Host smart-442f3faf-a13b-4527-b61d-ce108196e245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99099940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.99099940
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3801944032
Short name T48
Test name
Test status
Simulation time 648296462 ps
CPU time 30.32 seconds
Started Aug 04 05:14:20 PM PDT 24
Finished Aug 04 05:14:50 PM PDT 24
Peak memory 215332 kb
Host smart-6f5d30d9-1d34-4627-89b6-53ca561cfc74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801944032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3801944032
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.608937883
Short name T199
Test name
Test status
Simulation time 1947916755 ps
CPU time 37.65 seconds
Started Aug 04 05:14:21 PM PDT 24
Finished Aug 04 05:15:00 PM PDT 24
Peak memory 222508 kb
Host smart-e6c41b8a-fae3-446d-aba5-97629a5865dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608937883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.608937883
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2904310609
Short name T395
Test name
Test status
Simulation time 129357505 ps
CPU time 6.46 seconds
Started Aug 04 05:12:58 PM PDT 24
Finished Aug 04 05:13:05 PM PDT 24
Peak memory 215668 kb
Host smart-b815361a-e1bb-4f86-82f7-df79b0e58e3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904310609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2904310609
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4007260432
Short name T111
Test name
Test status
Simulation time 111935845 ps
CPU time 2.54 seconds
Started Aug 04 05:15:10 PM PDT 24
Finished Aug 04 05:15:13 PM PDT 24
Peak memory 207620 kb
Host smart-50f31354-8e6c-4d8c-918a-7e79308125c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007260432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4007260432
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3204335857
Short name T262
Test name
Test status
Simulation time 1348175375 ps
CPU time 42.39 seconds
Started Aug 04 05:15:11 PM PDT 24
Finished Aug 04 05:15:53 PM PDT 24
Peak memory 222480 kb
Host smart-b36e8e1d-3e1c-45cb-9acc-85e1dd811b75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204335857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3204335857
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.384807948
Short name T234
Test name
Test status
Simulation time 2061666525 ps
CPU time 27.27 seconds
Started Aug 04 05:13:25 PM PDT 24
Finished Aug 04 05:13:52 PM PDT 24
Peak memory 222412 kb
Host smart-513b43a4-9205-40e8-bc88-6d1f8e07cdc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384807948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.384807948
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.716829233
Short name T178
Test name
Test status
Simulation time 1273174935 ps
CPU time 8.84 seconds
Started Aug 04 04:31:30 PM PDT 24
Finished Aug 04 04:31:39 PM PDT 24
Peak memory 214312 kb
Host smart-8a414507-bc68-446e-bfd8-f19a75f48666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716829233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.716829233
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.397349320
Short name T171
Test name
Test status
Simulation time 250166698 ps
CPU time 3.81 seconds
Started Aug 04 04:31:09 PM PDT 24
Finished Aug 04 04:31:13 PM PDT 24
Peak memory 206168 kb
Host smart-3ced4271-8841-4f06-a7e1-d8302d466761
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397349320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
397349320
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.221767375
Short name T272
Test name
Test status
Simulation time 9189505616 ps
CPU time 261.99 seconds
Started Aug 04 05:14:46 PM PDT 24
Finished Aug 04 05:19:08 PM PDT 24
Peak memory 217752 kb
Host smart-97fd0023-d429-4b48-b757-dfb42ea93636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221767375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.221767375
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.472487360
Short name T156
Test name
Test status
Simulation time 207444669 ps
CPU time 3.27 seconds
Started Aug 04 05:12:33 PM PDT 24
Finished Aug 04 05:12:36 PM PDT 24
Peak memory 222544 kb
Host smart-df3d3346-b00d-46df-8c3c-26b434acb796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472487360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.472487360
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2304510155
Short name T841
Test name
Test status
Simulation time 38753493 ps
CPU time 2.36 seconds
Started Aug 04 05:13:29 PM PDT 24
Finished Aug 04 05:13:32 PM PDT 24
Peak memory 214212 kb
Host smart-94273e71-f5e7-493b-b7dd-a66933e8c3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304510155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2304510155
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.256038974
Short name T730
Test name
Test status
Simulation time 1006866353 ps
CPU time 18.85 seconds
Started Aug 04 05:13:33 PM PDT 24
Finished Aug 04 05:13:52 PM PDT 24
Peak memory 222452 kb
Host smart-253945be-3ed0-42b7-91f9-50b6794cf6ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256038974 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.256038974
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.762747106
Short name T709
Test name
Test status
Simulation time 721572715 ps
CPU time 4.12 seconds
Started Aug 04 05:13:35 PM PDT 24
Finished Aug 04 05:13:39 PM PDT 24
Peak memory 215528 kb
Host smart-88c02065-00bd-4f5e-b1ba-b6425dac1c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762747106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.762747106
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.476696946
Short name T62
Test name
Test status
Simulation time 117806130 ps
CPU time 4.43 seconds
Started Aug 04 05:13:35 PM PDT 24
Finished Aug 04 05:13:40 PM PDT 24
Peak memory 209844 kb
Host smart-2d2d9ace-00ce-4154-a6ea-efe748c21481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476696946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.476696946
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.431320932
Short name T346
Test name
Test status
Simulation time 648136383 ps
CPU time 14.61 seconds
Started Aug 04 05:13:39 PM PDT 24
Finished Aug 04 05:13:54 PM PDT 24
Peak memory 218972 kb
Host smart-2313ea56-d1f4-4c8b-ab40-0ad74629552d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431320932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.431320932
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1757388480
Short name T296
Test name
Test status
Simulation time 439603934 ps
CPU time 3.2 seconds
Started Aug 04 05:13:48 PM PDT 24
Finished Aug 04 05:13:51 PM PDT 24
Peak memory 222332 kb
Host smart-a6e60862-7ec4-4796-9823-8346400f9c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757388480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1757388480
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.4288646856
Short name T239
Test name
Test status
Simulation time 1286141144 ps
CPU time 11.29 seconds
Started Aug 04 05:13:47 PM PDT 24
Finished Aug 04 05:13:58 PM PDT 24
Peak memory 209072 kb
Host smart-8641a905-3088-435f-811f-7f560ca4889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288646856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.4288646856
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1990711702
Short name T237
Test name
Test status
Simulation time 379937471 ps
CPU time 18.55 seconds
Started Aug 04 05:13:53 PM PDT 24
Finished Aug 04 05:14:11 PM PDT 24
Peak memory 222556 kb
Host smart-0433575e-2bec-4802-876a-60a3e539e483
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990711702 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1990711702
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1736502928
Short name T532
Test name
Test status
Simulation time 51177764 ps
CPU time 1.72 seconds
Started Aug 04 05:13:52 PM PDT 24
Finished Aug 04 05:13:53 PM PDT 24
Peak memory 209648 kb
Host smart-76cc2938-65a7-444b-8035-00ce5b67a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736502928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1736502928
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2852674505
Short name T342
Test name
Test status
Simulation time 127670307 ps
CPU time 3.2 seconds
Started Aug 04 05:13:52 PM PDT 24
Finished Aug 04 05:13:55 PM PDT 24
Peak memory 221056 kb
Host smart-e58ae3d0-4e17-486e-98e5-ea8718b36de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852674505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2852674505
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4133865076
Short name T228
Test name
Test status
Simulation time 546034897 ps
CPU time 4.53 seconds
Started Aug 04 05:13:57 PM PDT 24
Finished Aug 04 05:14:02 PM PDT 24
Peak memory 220208 kb
Host smart-af137f36-e8da-43c0-9430-c230ed713078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133865076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4133865076
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.884505258
Short name T357
Test name
Test status
Simulation time 156115674 ps
CPU time 6.32 seconds
Started Aug 04 05:14:01 PM PDT 24
Finished Aug 04 05:14:07 PM PDT 24
Peak memory 208984 kb
Host smart-873741d0-55c7-477d-98c1-289d4ad39699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884505258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.884505258
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2297701729
Short name T85
Test name
Test status
Simulation time 272304369 ps
CPU time 3.75 seconds
Started Aug 04 05:12:48 PM PDT 24
Finished Aug 04 05:12:52 PM PDT 24
Peak memory 214216 kb
Host smart-94675c08-3202-4c70-9325-f4ebc53625da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297701729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2297701729
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.746556381
Short name T281
Test name
Test status
Simulation time 86314144 ps
CPU time 4.17 seconds
Started Aug 04 05:14:08 PM PDT 24
Finished Aug 04 05:14:13 PM PDT 24
Peak memory 214292 kb
Host smart-84c9f4f0-5eff-4bdd-8c5c-955ebf60ef9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746556381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.746556381
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.45814181
Short name T242
Test name
Test status
Simulation time 251294182 ps
CPU time 3 seconds
Started Aug 04 05:14:15 PM PDT 24
Finished Aug 04 05:14:18 PM PDT 24
Peak memory 209476 kb
Host smart-06ffea67-ed68-484c-8ebe-96ffc26be9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45814181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.45814181
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.378346443
Short name T145
Test name
Test status
Simulation time 773655243 ps
CPU time 37.73 seconds
Started Aug 04 05:14:23 PM PDT 24
Finished Aug 04 05:15:01 PM PDT 24
Peak memory 215740 kb
Host smart-fc03321e-9bd3-47a9-b020-08cca97c41bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378346443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.378346443
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3999777898
Short name T293
Test name
Test status
Simulation time 402753220 ps
CPU time 10.5 seconds
Started Aug 04 05:14:38 PM PDT 24
Finished Aug 04 05:14:48 PM PDT 24
Peak memory 215096 kb
Host smart-637173f0-e1db-4fe4-b501-9983b91d4a75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999777898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3999777898
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1414750483
Short name T334
Test name
Test status
Simulation time 187187249 ps
CPU time 3.59 seconds
Started Aug 04 05:14:42 PM PDT 24
Finished Aug 04 05:14:46 PM PDT 24
Peak memory 215376 kb
Host smart-856acaa5-e6f7-49d7-8459-747c0752e95d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1414750483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1414750483
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.595639464
Short name T370
Test name
Test status
Simulation time 50250645 ps
CPU time 3.56 seconds
Started Aug 04 05:15:01 PM PDT 24
Finished Aug 04 05:15:05 PM PDT 24
Peak memory 214736 kb
Host smart-24cf6d72-ad7c-4201-b949-841c30bfac2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=595639464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.595639464
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2757813942
Short name T203
Test name
Test status
Simulation time 99812497 ps
CPU time 3.41 seconds
Started Aug 04 05:15:12 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 214240 kb
Host smart-f9ed467f-8c88-4e84-b6b8-455919b51dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757813942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2757813942
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.904101515
Short name T161
Test name
Test status
Simulation time 425333481 ps
CPU time 3.44 seconds
Started Aug 04 05:13:29 PM PDT 24
Finished Aug 04 05:13:33 PM PDT 24
Peak memory 222520 kb
Host smart-054ff957-5cb8-46ee-982e-b7ed1d1295f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904101515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.904101515
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2244699137
Short name T1079
Test name
Test status
Simulation time 380068146 ps
CPU time 10.06 seconds
Started Aug 04 04:30:52 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 206016 kb
Host smart-e6d4a9ad-3ec4-474e-becd-5ee3f7b96574
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244699137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
244699137
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2740842571
Short name T921
Test name
Test status
Simulation time 308329607 ps
CPU time 5.93 seconds
Started Aug 04 04:31:08 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 206128 kb
Host smart-a523fb7a-841a-45e7-880f-39c57e7a37a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740842571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
740842571
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2569036748
Short name T919
Test name
Test status
Simulation time 68087661 ps
CPU time 1.11 seconds
Started Aug 04 04:31:07 PM PDT 24
Finished Aug 04 04:31:08 PM PDT 24
Peak memory 206020 kb
Host smart-5d23c549-5761-45d6-8909-3e8ee7af39bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569036748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
569036748
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1411602783
Short name T957
Test name
Test status
Simulation time 60070181 ps
CPU time 1.63 seconds
Started Aug 04 04:31:13 PM PDT 24
Finished Aug 04 04:31:15 PM PDT 24
Peak memory 214312 kb
Host smart-1ce3e0a6-294f-4189-9fd8-df6730afb88b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411602783 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1411602783
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2032806162
Short name T944
Test name
Test status
Simulation time 88216379 ps
CPU time 1.08 seconds
Started Aug 04 04:31:05 PM PDT 24
Finished Aug 04 04:31:06 PM PDT 24
Peak memory 206092 kb
Host smart-0dac2a87-60cb-4327-9ae9-0130c97cbde3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032806162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2032806162
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1128372722
Short name T918
Test name
Test status
Simulation time 22203591 ps
CPU time 0.69 seconds
Started Aug 04 04:30:46 PM PDT 24
Finished Aug 04 04:30:47 PM PDT 24
Peak memory 205744 kb
Host smart-2ba4e869-7d2d-437f-866e-d3f530cef654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128372722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1128372722
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.653023049
Short name T948
Test name
Test status
Simulation time 39103039 ps
CPU time 1.85 seconds
Started Aug 04 04:31:06 PM PDT 24
Finished Aug 04 04:31:08 PM PDT 24
Peak memory 206072 kb
Host smart-0d579745-d389-4cff-9fe1-60c832811fef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653023049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.653023049
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1270959914
Short name T1036
Test name
Test status
Simulation time 3375765319 ps
CPU time 9.09 seconds
Started Aug 04 04:31:06 PM PDT 24
Finished Aug 04 04:31:15 PM PDT 24
Peak memory 214648 kb
Host smart-e2db00ce-73ea-48fc-8b07-db3cc129563f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270959914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1270959914
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1222737607
Short name T936
Test name
Test status
Simulation time 39380127 ps
CPU time 1.47 seconds
Started Aug 04 04:31:11 PM PDT 24
Finished Aug 04 04:31:13 PM PDT 24
Peak memory 214276 kb
Host smart-9b149c4f-9419-4394-ae95-80c41371038d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222737607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1222737607
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3060672141
Short name T176
Test name
Test status
Simulation time 382910353 ps
CPU time 5.05 seconds
Started Aug 04 04:31:07 PM PDT 24
Finished Aug 04 04:31:12 PM PDT 24
Peak memory 215588 kb
Host smart-15094688-a43a-4af3-b9d7-0c0215938958
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060672141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3060672141
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.416907621
Short name T926
Test name
Test status
Simulation time 998458529 ps
CPU time 16.73 seconds
Started Aug 04 04:31:24 PM PDT 24
Finished Aug 04 04:31:41 PM PDT 24
Peak memory 206084 kb
Host smart-7e994db0-e2b9-407b-a36c-22d94d4f750d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416907621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.416907621
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3334636380
Short name T1050
Test name
Test status
Simulation time 4123196017 ps
CPU time 16.79 seconds
Started Aug 04 04:30:59 PM PDT 24
Finished Aug 04 04:31:16 PM PDT 24
Peak memory 206488 kb
Host smart-c53cb72c-61a3-4f84-9e4d-983766151c64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334636380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
334636380
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.958311368
Short name T985
Test name
Test status
Simulation time 75813693 ps
CPU time 1.19 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:03 PM PDT 24
Peak memory 205944 kb
Host smart-3eea6558-13bc-411a-97fe-3f6e02ef811e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958311368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.958311368
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.146833787
Short name T1066
Test name
Test status
Simulation time 52595736 ps
CPU time 1.39 seconds
Started Aug 04 04:31:08 PM PDT 24
Finished Aug 04 04:31:10 PM PDT 24
Peak memory 206092 kb
Host smart-cabe1d7c-14d2-40b2-adf6-d631fe6a141e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146833787 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.146833787
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2353006692
Short name T1031
Test name
Test status
Simulation time 11496061 ps
CPU time 0.95 seconds
Started Aug 04 04:31:02 PM PDT 24
Finished Aug 04 04:31:03 PM PDT 24
Peak memory 206036 kb
Host smart-68ee76e6-943c-4310-bb11-a229d68d6f93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353006692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2353006692
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2926314132
Short name T1047
Test name
Test status
Simulation time 12294996 ps
CPU time 0.72 seconds
Started Aug 04 04:31:04 PM PDT 24
Finished Aug 04 04:31:05 PM PDT 24
Peak memory 205848 kb
Host smart-5a49099d-2c79-4d4d-8bf1-86bba70613f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926314132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2926314132
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.808455867
Short name T150
Test name
Test status
Simulation time 722146426 ps
CPU time 1.82 seconds
Started Aug 04 04:31:05 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 205972 kb
Host smart-14b5aa03-182e-4c7e-b212-d5db0baed5af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808455867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.808455867
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2797425577
Short name T127
Test name
Test status
Simulation time 78714320 ps
CPU time 1.47 seconds
Started Aug 04 04:31:12 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 214660 kb
Host smart-30378e4c-1f04-4d80-a619-8417e8c56ccf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797425577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2797425577
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.495552761
Short name T1013
Test name
Test status
Simulation time 185939126 ps
CPU time 4.85 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:06 PM PDT 24
Peak memory 220660 kb
Host smart-263c0eb9-fa11-4dc3-81b2-66aeb7a635cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495552761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.495552761
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3295199515
Short name T1051
Test name
Test status
Simulation time 164539189 ps
CPU time 2.93 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:23 PM PDT 24
Peak memory 214292 kb
Host smart-7e70caca-4550-4e7d-a038-d45c896eaf24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295199515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3295199515
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3631232482
Short name T960
Test name
Test status
Simulation time 26179882 ps
CPU time 1.93 seconds
Started Aug 04 04:31:17 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 214244 kb
Host smart-a19c0318-c494-4f15-998e-ecfbb1b54f16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631232482 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3631232482
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3048160098
Short name T1034
Test name
Test status
Simulation time 49323701 ps
CPU time 1.2 seconds
Started Aug 04 04:31:06 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 206016 kb
Host smart-c1d22a57-b401-4eef-89d5-109e1d121c07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048160098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3048160098
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3896359141
Short name T1068
Test name
Test status
Simulation time 12104115 ps
CPU time 0.7 seconds
Started Aug 04 04:31:26 PM PDT 24
Finished Aug 04 04:31:27 PM PDT 24
Peak memory 205748 kb
Host smart-73554226-8f04-4559-8653-5653e6d12057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896359141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3896359141
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2978875859
Short name T1046
Test name
Test status
Simulation time 100106589 ps
CPU time 2.46 seconds
Started Aug 04 04:31:07 PM PDT 24
Finished Aug 04 04:31:10 PM PDT 24
Peak memory 206132 kb
Host smart-56ed6bbc-09f3-447a-a47d-f102ea9a105b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978875859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2978875859
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.32139802
Short name T125
Test name
Test status
Simulation time 192665193 ps
CPU time 3.28 seconds
Started Aug 04 04:31:15 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 214524 kb
Host smart-bf9e14bd-0e84-4a08-a959-b4fccbe7780e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32139802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow
_reg_errors.32139802
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1909360379
Short name T1062
Test name
Test status
Simulation time 370587832 ps
CPU time 13.35 seconds
Started Aug 04 04:31:05 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 214524 kb
Host smart-0dead965-f66a-4d8a-8f14-6b6b5b28edef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909360379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1909360379
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1851830049
Short name T940
Test name
Test status
Simulation time 284166492 ps
CPU time 1.66 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:18 PM PDT 24
Peak memory 214308 kb
Host smart-dd687382-f785-4697-8511-ad52380c080f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851830049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1851830049
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.844207338
Short name T173
Test name
Test status
Simulation time 1808424288 ps
CPU time 5.06 seconds
Started Aug 04 04:31:09 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 214176 kb
Host smart-cfd1ac3b-9198-4ad4-ac5f-bcd9fadeba40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844207338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.844207338
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3031224012
Short name T987
Test name
Test status
Simulation time 174175990 ps
CPU time 1.44 seconds
Started Aug 04 04:31:15 PM PDT 24
Finished Aug 04 04:31:16 PM PDT 24
Peak memory 214300 kb
Host smart-7c568e19-b4c8-4e79-888c-59f4fc63c1aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031224012 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3031224012
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.816086333
Short name T994
Test name
Test status
Simulation time 69867120 ps
CPU time 0.93 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:20 PM PDT 24
Peak memory 205816 kb
Host smart-e3d49ad2-6111-47c9-b2ed-df31c412b68a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816086333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.816086333
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.738551887
Short name T1045
Test name
Test status
Simulation time 44183716 ps
CPU time 0.71 seconds
Started Aug 04 04:31:23 PM PDT 24
Finished Aug 04 04:31:24 PM PDT 24
Peak memory 205848 kb
Host smart-e4b14ccb-9141-4496-8697-9bbf1e08256f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738551887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.738551887
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2864191590
Short name T1069
Test name
Test status
Simulation time 199118316 ps
CPU time 1.59 seconds
Started Aug 04 04:31:13 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 205980 kb
Host smart-07f4a964-0c72-4f7d-82aa-c7c21595d2b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864191590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2864191590
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2231000840
Short name T1063
Test name
Test status
Simulation time 105239666 ps
CPU time 1.63 seconds
Started Aug 04 04:31:12 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 214568 kb
Host smart-8dbfe6b9-cbe6-45f0-8bae-b2bd11f1c7f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231000840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2231000840
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1382628747
Short name T1081
Test name
Test status
Simulation time 50807176 ps
CPU time 3.29 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 216364 kb
Host smart-3d81496e-e779-43d5-9973-1497098d3fa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382628747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1382628747
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1070628417
Short name T942
Test name
Test status
Simulation time 48394947 ps
CPU time 1.88 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 214176 kb
Host smart-586a0ab9-9689-4e77-bf1a-3f451d3b4591
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070628417 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1070628417
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2710498113
Short name T1020
Test name
Test status
Simulation time 30141073 ps
CPU time 1.2 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:17 PM PDT 24
Peak memory 206076 kb
Host smart-2867a5ab-7570-4236-bb74-3c830e51c4a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710498113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2710498113
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2329165397
Short name T934
Test name
Test status
Simulation time 42773369 ps
CPU time 0.82 seconds
Started Aug 04 04:31:15 PM PDT 24
Finished Aug 04 04:31:16 PM PDT 24
Peak memory 205804 kb
Host smart-46f67be9-514d-4c2d-92be-3e3232ff0791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329165397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2329165397
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.145845596
Short name T1058
Test name
Test status
Simulation time 439940592 ps
CPU time 2.63 seconds
Started Aug 04 04:31:14 PM PDT 24
Finished Aug 04 04:31:17 PM PDT 24
Peak memory 206048 kb
Host smart-834f1e8c-9f64-4d0c-b4dd-63298d1b54ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145845596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.145845596
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2439776381
Short name T1035
Test name
Test status
Simulation time 419134542 ps
CPU time 1.97 seconds
Started Aug 04 04:31:06 PM PDT 24
Finished Aug 04 04:31:08 PM PDT 24
Peak memory 214528 kb
Host smart-3c1c2966-c1f0-429a-acb3-6417cafa8821
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439776381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2439776381
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1945538320
Short name T1037
Test name
Test status
Simulation time 239528026 ps
CPU time 5.44 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:26 PM PDT 24
Peak memory 214588 kb
Host smart-ec371a1d-4407-4121-bb2b-8fc0d3c4e412
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945538320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1945538320
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.146879290
Short name T1073
Test name
Test status
Simulation time 64296236 ps
CPU time 1.84 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:21 PM PDT 24
Peak memory 214240 kb
Host smart-5bec3c1d-09e3-4a1c-8392-75a95425dfcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146879290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.146879290
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.70602362
Short name T1006
Test name
Test status
Simulation time 641310915 ps
CPU time 4.07 seconds
Started Aug 04 04:31:25 PM PDT 24
Finished Aug 04 04:31:30 PM PDT 24
Peak memory 214244 kb
Host smart-a5f8386d-6641-4887-b865-3c800a54ac50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70602362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.70602362
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4020094517
Short name T988
Test name
Test status
Simulation time 31111046 ps
CPU time 2.14 seconds
Started Aug 04 04:31:18 PM PDT 24
Finished Aug 04 04:31:20 PM PDT 24
Peak memory 214256 kb
Host smart-897b2007-5551-4b1d-a7aa-a13ae764b682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020094517 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.4020094517
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.65579279
Short name T1015
Test name
Test status
Simulation time 131667821 ps
CPU time 0.95 seconds
Started Aug 04 04:31:12 PM PDT 24
Finished Aug 04 04:31:13 PM PDT 24
Peak memory 205784 kb
Host smart-35ecf351-a668-4873-b6b0-c71d9d9f8150
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65579279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.65579279
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.327512994
Short name T991
Test name
Test status
Simulation time 52640722 ps
CPU time 0.76 seconds
Started Aug 04 04:31:08 PM PDT 24
Finished Aug 04 04:31:09 PM PDT 24
Peak memory 205764 kb
Host smart-6b26f245-e3b5-418c-b2ae-e7f0519701e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327512994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.327512994
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2052031873
Short name T973
Test name
Test status
Simulation time 175812796 ps
CPU time 1.45 seconds
Started Aug 04 04:31:05 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 206144 kb
Host smart-60ab0596-7d75-4ddf-b903-83de5a45e6f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052031873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2052031873
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2174202465
Short name T1004
Test name
Test status
Simulation time 55421844 ps
CPU time 1.56 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:21 PM PDT 24
Peak memory 214652 kb
Host smart-8cfcfa7b-03f1-4586-98eb-5e1d74b74ca0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174202465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2174202465
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1607828782
Short name T1057
Test name
Test status
Simulation time 986795811 ps
CPU time 6.01 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:26 PM PDT 24
Peak memory 214524 kb
Host smart-5ea1a7f5-8287-49fb-bf12-d005e118b53b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607828782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1607828782
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.4114505992
Short name T932
Test name
Test status
Simulation time 37023032 ps
CPU time 1.5 seconds
Started Aug 04 04:31:15 PM PDT 24
Finished Aug 04 04:31:17 PM PDT 24
Peak memory 206148 kb
Host smart-807bda9d-48a6-407e-ab36-fefe2633189b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114505992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.4114505992
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.911744134
Short name T177
Test name
Test status
Simulation time 339553960 ps
CPU time 4.12 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:25 PM PDT 24
Peak memory 206444 kb
Host smart-2608bcc9-e5b9-46d3-942e-20d7cd8bfa59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911744134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.911744134
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.897392123
Short name T980
Test name
Test status
Simulation time 106902848 ps
CPU time 1.51 seconds
Started Aug 04 04:31:13 PM PDT 24
Finished Aug 04 04:31:15 PM PDT 24
Peak memory 214320 kb
Host smart-cbdcf446-7708-4552-a273-908d4204ca7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897392123 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.897392123
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1103007650
Short name T1014
Test name
Test status
Simulation time 21075014 ps
CPU time 0.91 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:20 PM PDT 24
Peak memory 205820 kb
Host smart-e56040ac-fe02-4864-90ac-349b58e41f85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103007650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1103007650
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.892736088
Short name T979
Test name
Test status
Simulation time 18768421 ps
CPU time 0.77 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:17 PM PDT 24
Peak memory 205852 kb
Host smart-89537a22-f184-4bf7-a767-e3eb9229d801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892736088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.892736088
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3986482005
Short name T153
Test name
Test status
Simulation time 105399252 ps
CPU time 1.8 seconds
Started Aug 04 04:31:15 PM PDT 24
Finished Aug 04 04:31:17 PM PDT 24
Peak memory 205976 kb
Host smart-fba25570-4f69-48de-903a-b57954ee8610
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986482005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3986482005
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2549454077
Short name T969
Test name
Test status
Simulation time 197496633 ps
CPU time 3.42 seconds
Started Aug 04 04:31:17 PM PDT 24
Finished Aug 04 04:31:20 PM PDT 24
Peak memory 214660 kb
Host smart-1208065a-1596-410e-9b67-a2e6510718cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549454077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2549454077
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1419577961
Short name T123
Test name
Test status
Simulation time 1030701249 ps
CPU time 5.6 seconds
Started Aug 04 04:31:12 PM PDT 24
Finished Aug 04 04:31:18 PM PDT 24
Peak memory 220332 kb
Host smart-f9d6f243-b0c2-4d99-8e9c-26ef09b15cf5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419577961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1419577961
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2325930704
Short name T1071
Test name
Test status
Simulation time 82081036 ps
CPU time 2.92 seconds
Started Aug 04 04:31:13 PM PDT 24
Finished Aug 04 04:31:16 PM PDT 24
Peak memory 214252 kb
Host smart-751d8943-dec5-47ea-9aa8-adcfaca4819a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325930704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2325930704
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3107962849
Short name T955
Test name
Test status
Simulation time 89350451 ps
CPU time 1.57 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:21 PM PDT 24
Peak memory 214348 kb
Host smart-e47f518a-e258-49b8-934e-005d0a8ad25f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107962849 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3107962849
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2742249242
Short name T1078
Test name
Test status
Simulation time 101614858 ps
CPU time 1.14 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:18 PM PDT 24
Peak memory 206044 kb
Host smart-c3c96baa-41ba-4503-90aa-a115fd5c9b2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742249242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2742249242
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1011732398
Short name T917
Test name
Test status
Simulation time 12147471 ps
CPU time 0.73 seconds
Started Aug 04 04:31:30 PM PDT 24
Finished Aug 04 04:31:31 PM PDT 24
Peak memory 205756 kb
Host smart-accea0ca-3052-4184-927b-baeaadac213c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011732398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1011732398
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3187249388
Short name T152
Test name
Test status
Simulation time 493664510 ps
CPU time 2.8 seconds
Started Aug 04 04:31:24 PM PDT 24
Finished Aug 04 04:31:27 PM PDT 24
Peak memory 205972 kb
Host smart-10789b03-bf83-4456-b0f6-183b28a6bbe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187249388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3187249388
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1448684914
Short name T1041
Test name
Test status
Simulation time 293591006 ps
CPU time 1.99 seconds
Started Aug 04 04:31:11 PM PDT 24
Finished Aug 04 04:31:13 PM PDT 24
Peak memory 214528 kb
Host smart-34727a7a-2fb7-4ffd-92a1-76e84f14bca2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448684914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1448684914
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3665723866
Short name T999
Test name
Test status
Simulation time 126736911 ps
CPU time 3.75 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 214608 kb
Host smart-c779b0d7-2e55-4dea-946f-68b5557d575f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665723866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3665723866
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.796072059
Short name T925
Test name
Test status
Simulation time 351227981 ps
CPU time 2.1 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 215424 kb
Host smart-564a2d1f-ae12-4d26-8c30-57a0c4647ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796072059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.796072059
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2677094922
Short name T376
Test name
Test status
Simulation time 222569692 ps
CPU time 4.11 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:23 PM PDT 24
Peak memory 214232 kb
Host smart-eb1ae700-135e-47c8-9872-77f7e31c05ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677094922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2677094922
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3380572436
Short name T1039
Test name
Test status
Simulation time 52172372 ps
CPU time 1.54 seconds
Started Aug 04 04:31:17 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 214212 kb
Host smart-f5cf646b-ea52-43b8-b4ad-c76752fba968
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380572436 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3380572436
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3192580034
Short name T1026
Test name
Test status
Simulation time 41752734 ps
CPU time 1.12 seconds
Started Aug 04 04:31:12 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 205964 kb
Host smart-f0a86664-09fe-4ff1-beaa-aee719a959f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192580034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3192580034
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2900627223
Short name T951
Test name
Test status
Simulation time 14427574 ps
CPU time 0.79 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 205848 kb
Host smart-14c85bda-a1d6-4078-a09d-8a6d6147a0fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900627223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2900627223
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2086376832
Short name T1024
Test name
Test status
Simulation time 72062018 ps
CPU time 2.29 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 206048 kb
Host smart-e527faa1-8a24-4415-9879-5dd59b626a3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086376832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2086376832
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3209738194
Short name T1001
Test name
Test status
Simulation time 187894562 ps
CPU time 4.36 seconds
Started Aug 04 04:31:23 PM PDT 24
Finished Aug 04 04:31:28 PM PDT 24
Peak memory 214484 kb
Host smart-7f317b30-e59b-4310-96c2-c40db3ba57ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209738194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3209738194
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2987709708
Short name T937
Test name
Test status
Simulation time 44374295 ps
CPU time 3.01 seconds
Started Aug 04 04:31:17 PM PDT 24
Finished Aug 04 04:31:21 PM PDT 24
Peak memory 214412 kb
Host smart-5bbfd078-78e2-4b76-bb5a-52313ba8cc79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987709708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2987709708
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3820553482
Short name T180
Test name
Test status
Simulation time 143268363 ps
CPU time 5.1 seconds
Started Aug 04 04:31:22 PM PDT 24
Finished Aug 04 04:31:28 PM PDT 24
Peak memory 213808 kb
Host smart-55566b34-6cb0-4837-83bd-e69f64c6adee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820553482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3820553482
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1191367649
Short name T947
Test name
Test status
Simulation time 105993355 ps
CPU time 1.17 seconds
Started Aug 04 04:31:10 PM PDT 24
Finished Aug 04 04:31:11 PM PDT 24
Peak memory 206012 kb
Host smart-0880a613-e23b-499d-9c07-7954dce291a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191367649 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1191367649
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.677230223
Short name T1053
Test name
Test status
Simulation time 77806759 ps
CPU time 1.16 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 206208 kb
Host smart-0d21db0c-2526-4fcc-ba9b-953391bd4e92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677230223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.677230223
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.256016653
Short name T972
Test name
Test status
Simulation time 10363167 ps
CPU time 0.78 seconds
Started Aug 04 04:31:08 PM PDT 24
Finished Aug 04 04:31:09 PM PDT 24
Peak memory 205828 kb
Host smart-2f0fbf00-6355-49dd-908c-128c99bfe331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256016653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.256016653
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2263989387
Short name T149
Test name
Test status
Simulation time 45024802 ps
CPU time 1.62 seconds
Started Aug 04 04:31:14 PM PDT 24
Finished Aug 04 04:31:16 PM PDT 24
Peak memory 206008 kb
Host smart-e3180ee6-ec04-4e0b-9f23-e2d0b4cd058e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263989387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2263989387
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.45421877
Short name T958
Test name
Test status
Simulation time 460717221 ps
CPU time 2.64 seconds
Started Aug 04 04:31:12 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 214588 kb
Host smart-6c7686e7-3a1d-488c-b791-1ed40ca2d432
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45421877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow
_reg_errors.45421877
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3363638982
Short name T1002
Test name
Test status
Simulation time 1493951074 ps
CPU time 8.55 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:30 PM PDT 24
Peak memory 214612 kb
Host smart-abb41fd4-cea5-4b3a-8f29-f3bea636a996
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363638982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3363638982
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3085926797
Short name T931
Test name
Test status
Simulation time 143360509 ps
CPU time 2.78 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:24 PM PDT 24
Peak memory 217432 kb
Host smart-a1cafa0d-3563-41a4-a22b-786f3f532561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085926797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3085926797
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2605727963
Short name T976
Test name
Test status
Simulation time 54448844 ps
CPU time 1.84 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:23 PM PDT 24
Peak memory 214404 kb
Host smart-6bd450d6-a765-411a-8851-3cb2912c699e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605727963 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2605727963
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.4081862707
Short name T162
Test name
Test status
Simulation time 77079534 ps
CPU time 0.95 seconds
Started Aug 04 04:31:17 PM PDT 24
Finished Aug 04 04:31:18 PM PDT 24
Peak memory 205884 kb
Host smart-124f7206-1b1f-4962-81b9-c094e48c0bd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081862707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.4081862707
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1213724150
Short name T1000
Test name
Test status
Simulation time 152961344 ps
CPU time 0.8 seconds
Started Aug 04 04:31:28 PM PDT 24
Finished Aug 04 04:31:29 PM PDT 24
Peak memory 205892 kb
Host smart-55ae2c18-1271-4f53-858a-4df5a35a9cb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213724150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1213724150
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2198129315
Short name T148
Test name
Test status
Simulation time 222428764 ps
CPU time 2.7 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 206100 kb
Host smart-77b69c7d-d474-4dc4-970f-571d22bb74c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198129315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2198129315
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4095363734
Short name T978
Test name
Test status
Simulation time 303833084 ps
CPU time 4.23 seconds
Started Aug 04 04:31:29 PM PDT 24
Finished Aug 04 04:31:33 PM PDT 24
Peak memory 214544 kb
Host smart-4393edaf-99f9-48ff-9e84-270522e5de83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095363734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.4095363734
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1772212921
Short name T1023
Test name
Test status
Simulation time 1555873077 ps
CPU time 13.01 seconds
Started Aug 04 04:31:13 PM PDT 24
Finished Aug 04 04:31:26 PM PDT 24
Peak memory 214520 kb
Host smart-7d00448d-9c98-4cfe-8a75-752211a856a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772212921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1772212921
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3700018703
Short name T943
Test name
Test status
Simulation time 51063893 ps
CPU time 1.98 seconds
Started Aug 04 04:31:31 PM PDT 24
Finished Aug 04 04:31:33 PM PDT 24
Peak memory 214344 kb
Host smart-a1e68f0a-bc83-4b8f-8178-6d9685ac9646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700018703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3700018703
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1497529252
Short name T179
Test name
Test status
Simulation time 790101253 ps
CPU time 4.74 seconds
Started Aug 04 04:31:17 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 214296 kb
Host smart-0eedc4c4-112c-42fe-a23a-29babf8b891f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497529252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1497529252
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3183954151
Short name T962
Test name
Test status
Simulation time 29460002 ps
CPU time 1.5 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 214272 kb
Host smart-c84d133e-3455-4699-998b-481393b77098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183954151 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3183954151
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2948014752
Short name T928
Test name
Test status
Simulation time 20585882 ps
CPU time 0.91 seconds
Started Aug 04 04:32:13 PM PDT 24
Finished Aug 04 04:32:14 PM PDT 24
Peak memory 204988 kb
Host smart-a8a601a2-baeb-43b3-a194-0137d40a2fb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948014752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2948014752
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1597560358
Short name T995
Test name
Test status
Simulation time 40726302 ps
CPU time 0.68 seconds
Started Aug 04 04:32:30 PM PDT 24
Finished Aug 04 04:32:30 PM PDT 24
Peak memory 205756 kb
Host smart-32714ebd-2513-4dd5-a1cd-06746d925222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597560358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1597560358
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.285196980
Short name T1052
Test name
Test status
Simulation time 88337699 ps
CPU time 1.47 seconds
Started Aug 04 04:32:32 PM PDT 24
Finished Aug 04 04:32:33 PM PDT 24
Peak memory 205996 kb
Host smart-e965cd80-0f79-4b48-ac2c-ee4376ec466f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285196980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.285196980
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3475018374
Short name T983
Test name
Test status
Simulation time 74297131 ps
CPU time 1.5 seconds
Started Aug 04 04:31:36 PM PDT 24
Finished Aug 04 04:31:38 PM PDT 24
Peak memory 214468 kb
Host smart-cf44b5c2-ed12-4d68-98e0-ab34f23c4394
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475018374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3475018374
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1294503421
Short name T997
Test name
Test status
Simulation time 858604889 ps
CPU time 14.63 seconds
Started Aug 04 04:31:14 PM PDT 24
Finished Aug 04 04:31:28 PM PDT 24
Peak memory 214556 kb
Host smart-26688ef0-f493-488c-9e5a-1fe14c85491a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294503421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1294503421
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3440562304
Short name T1055
Test name
Test status
Simulation time 657048352 ps
CPU time 3.33 seconds
Started Aug 04 04:31:11 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 217400 kb
Host smart-0657131c-f460-4984-9b1f-1955bbb6687c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440562304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3440562304
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3605703990
Short name T174
Test name
Test status
Simulation time 854288107 ps
CPU time 5.69 seconds
Started Aug 04 04:32:35 PM PDT 24
Finished Aug 04 04:32:41 PM PDT 24
Peak memory 216252 kb
Host smart-1ccc3362-5d95-467b-b5f5-ba08100b4d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605703990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3605703990
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3394308552
Short name T1018
Test name
Test status
Simulation time 369156451 ps
CPU time 14.21 seconds
Started Aug 04 04:31:02 PM PDT 24
Finished Aug 04 04:31:16 PM PDT 24
Peak memory 206064 kb
Host smart-bf4dd94d-7699-47ec-8962-b1215d9eb429
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394308552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
394308552
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.914548018
Short name T950
Test name
Test status
Simulation time 432333989 ps
CPU time 7.17 seconds
Started Aug 04 04:30:56 PM PDT 24
Finished Aug 04 04:31:03 PM PDT 24
Peak memory 206052 kb
Host smart-fa60ec50-c546-4d41-b802-5d72a5cca0ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914548018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.914548018
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1920996577
Short name T941
Test name
Test status
Simulation time 117911262 ps
CPU time 1.18 seconds
Started Aug 04 04:30:43 PM PDT 24
Finished Aug 04 04:30:49 PM PDT 24
Peak memory 206180 kb
Host smart-395c42f7-1990-4326-aa7f-1a0131e185af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920996577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
920996577
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1761957590
Short name T952
Test name
Test status
Simulation time 47968026 ps
CPU time 1.06 seconds
Started Aug 04 04:30:55 PM PDT 24
Finished Aug 04 04:30:56 PM PDT 24
Peak memory 206100 kb
Host smart-69aef60e-9b2d-444e-b273-58684063d792
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761957590 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1761957590
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3073223442
Short name T964
Test name
Test status
Simulation time 13465275 ps
CPU time 0.89 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 205916 kb
Host smart-5c2096e0-c81e-4c8f-aa03-1378495ad345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073223442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3073223442
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2462496708
Short name T1083
Test name
Test status
Simulation time 54824658 ps
CPU time 0.79 seconds
Started Aug 04 04:31:04 PM PDT 24
Finished Aug 04 04:31:04 PM PDT 24
Peak memory 205844 kb
Host smart-e4189561-46e9-4062-a753-1b2eae5f9c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462496708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2462496708
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.4093256097
Short name T961
Test name
Test status
Simulation time 308535093 ps
CPU time 2.44 seconds
Started Aug 04 04:30:55 PM PDT 24
Finished Aug 04 04:30:57 PM PDT 24
Peak memory 206068 kb
Host smart-04378235-cab6-47f1-9ebc-edb1e2914845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093256097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.4093256097
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3595380925
Short name T118
Test name
Test status
Simulation time 220764248 ps
CPU time 1.99 seconds
Started Aug 04 04:31:14 PM PDT 24
Finished Aug 04 04:31:16 PM PDT 24
Peak memory 214608 kb
Host smart-91d54a65-d4fb-489f-9d21-aee3cc1c9d77
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595380925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3595380925
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2397668630
Short name T151
Test name
Test status
Simulation time 215290604 ps
CPU time 6.13 seconds
Started Aug 04 04:31:08 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 220472 kb
Host smart-b2c293c8-3bc1-4c06-93c2-c3e9bdb4f8fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397668630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2397668630
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1184223654
Short name T1048
Test name
Test status
Simulation time 62539363 ps
CPU time 2.41 seconds
Started Aug 04 04:30:56 PM PDT 24
Finished Aug 04 04:30:59 PM PDT 24
Peak memory 216312 kb
Host smart-62b8dbf7-b643-432b-9096-30883ba9cdf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184223654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1184223654
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4047215124
Short name T165
Test name
Test status
Simulation time 124364759 ps
CPU time 2.77 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:25 PM PDT 24
Peak memory 206056 kb
Host smart-e6ba7dee-280d-4876-8576-c8cc4f4b76af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047215124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.4047215124
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1667839459
Short name T1029
Test name
Test status
Simulation time 23494959 ps
CPU time 0.76 seconds
Started Aug 04 04:32:52 PM PDT 24
Finished Aug 04 04:32:53 PM PDT 24
Peak memory 205712 kb
Host smart-1025318f-f66d-41c1-a2bd-0f2e725aec63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667839459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1667839459
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1121686471
Short name T1017
Test name
Test status
Simulation time 9523465 ps
CPU time 0.82 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:12 PM PDT 24
Peak memory 204924 kb
Host smart-b8f4d78c-8ccf-41fe-996b-b99929f676a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121686471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1121686471
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3463424844
Short name T922
Test name
Test status
Simulation time 40500411 ps
CPU time 0.75 seconds
Started Aug 04 04:31:25 PM PDT 24
Finished Aug 04 04:31:26 PM PDT 24
Peak memory 205848 kb
Host smart-47f4de28-822a-4ca5-bf85-e171063274bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463424844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3463424844
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.345018666
Short name T1064
Test name
Test status
Simulation time 11791340 ps
CPU time 0.86 seconds
Started Aug 04 04:31:27 PM PDT 24
Finished Aug 04 04:31:28 PM PDT 24
Peak memory 205724 kb
Host smart-e39f8021-20bc-4e32-92f7-42241de447bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345018666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.345018666
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1837299306
Short name T966
Test name
Test status
Simulation time 11587147 ps
CPU time 0.73 seconds
Started Aug 04 04:31:17 PM PDT 24
Finished Aug 04 04:31:18 PM PDT 24
Peak memory 205756 kb
Host smart-03fc62b5-3339-44a1-b983-4fe1cf975178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837299306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1837299306
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3086349295
Short name T916
Test name
Test status
Simulation time 129085409 ps
CPU time 0.7 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:21 PM PDT 24
Peak memory 205824 kb
Host smart-819e0f60-e6a5-4e13-a4e9-4cff2bf16396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086349295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3086349295
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1190923757
Short name T971
Test name
Test status
Simulation time 11368589 ps
CPU time 0.81 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:21 PM PDT 24
Peak memory 205820 kb
Host smart-dee38c20-e3e0-4637-8a85-a348e0d6e851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190923757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1190923757
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1256821183
Short name T938
Test name
Test status
Simulation time 34980274 ps
CPU time 0.82 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:23 PM PDT 24
Peak memory 205848 kb
Host smart-daba0db7-d752-4604-98fa-6716d5d4675f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256821183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1256821183
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1184091103
Short name T1003
Test name
Test status
Simulation time 43107364 ps
CPU time 0.82 seconds
Started Aug 04 04:31:53 PM PDT 24
Finished Aug 04 04:31:53 PM PDT 24
Peak memory 205820 kb
Host smart-f7e64b91-49e8-4be6-a283-0d4d53cea965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184091103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1184091103
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1195245566
Short name T1033
Test name
Test status
Simulation time 132729602 ps
CPU time 0.78 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:21 PM PDT 24
Peak memory 205848 kb
Host smart-3f882aac-f808-4967-bd53-131b6398fe18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195245566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1195245566
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1012137692
Short name T998
Test name
Test status
Simulation time 514800574 ps
CPU time 9.03 seconds
Started Aug 04 04:31:02 PM PDT 24
Finished Aug 04 04:31:11 PM PDT 24
Peak memory 206068 kb
Host smart-0c154d8d-e668-4fd8-8f71-2c26eef95e23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012137692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
012137692
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2470947189
Short name T1022
Test name
Test status
Simulation time 135777446 ps
CPU time 5.89 seconds
Started Aug 04 04:31:27 PM PDT 24
Finished Aug 04 04:31:33 PM PDT 24
Peak memory 205912 kb
Host smart-2d6d1b39-9065-4f6f-98e9-c6e168f0af8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470947189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
470947189
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3349688153
Short name T1011
Test name
Test status
Simulation time 33692075 ps
CPU time 1.07 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 205532 kb
Host smart-e8711f77-288d-4fdc-9a9b-3a562bfbc44d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349688153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
349688153
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2221005168
Short name T967
Test name
Test status
Simulation time 212487486 ps
CPU time 1.52 seconds
Started Aug 04 04:31:07 PM PDT 24
Finished Aug 04 04:31:08 PM PDT 24
Peak memory 214308 kb
Host smart-a5716bae-dc59-4a3f-9d36-a221a59e2717
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221005168 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2221005168
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3562722190
Short name T949
Test name
Test status
Simulation time 113715778 ps
CPU time 1.49 seconds
Started Aug 04 04:31:13 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 206032 kb
Host smart-5a05beff-cfa5-4f93-9a32-4159b8953e43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562722190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3562722190
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.440058871
Short name T956
Test name
Test status
Simulation time 14607811 ps
CPU time 0.82 seconds
Started Aug 04 04:30:59 PM PDT 24
Finished Aug 04 04:31:00 PM PDT 24
Peak memory 205784 kb
Host smart-c9a8271f-5d3b-4859-a1a1-76dd90717258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440058871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.440058871
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.947607921
Short name T1010
Test name
Test status
Simulation time 385176720 ps
CPU time 1.51 seconds
Started Aug 04 04:31:11 PM PDT 24
Finished Aug 04 04:31:12 PM PDT 24
Peak memory 206052 kb
Host smart-8e97f75f-e906-4ca8-ac6c-347fdb72b8b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947607921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.947607921
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2102391486
Short name T124
Test name
Test status
Simulation time 444915882 ps
CPU time 3.65 seconds
Started Aug 04 04:30:55 PM PDT 24
Finished Aug 04 04:30:59 PM PDT 24
Peak memory 214560 kb
Host smart-29e4ede1-c6c1-4a0b-980d-4b8d53a95373
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102391486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2102391486
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2485528112
Short name T1076
Test name
Test status
Simulation time 394194192 ps
CPU time 13.38 seconds
Started Aug 04 04:31:00 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 214492 kb
Host smart-bdfb4749-1ff6-43fb-870a-67b36f397b65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485528112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2485528112
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2612271445
Short name T1021
Test name
Test status
Simulation time 412454442 ps
CPU time 3 seconds
Started Aug 04 04:30:58 PM PDT 24
Finished Aug 04 04:31:01 PM PDT 24
Peak memory 214324 kb
Host smart-85828067-9c35-41a6-9a87-2ebcc024baf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612271445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2612271445
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1943501768
Short name T1049
Test name
Test status
Simulation time 416674621 ps
CPU time 3.64 seconds
Started Aug 04 04:31:12 PM PDT 24
Finished Aug 04 04:31:16 PM PDT 24
Peak memory 206172 kb
Host smart-d2daaf59-d2be-4945-b268-cc728cf10e59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943501768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1943501768
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3748509595
Short name T1070
Test name
Test status
Simulation time 22482308 ps
CPU time 0.68 seconds
Started Aug 04 04:31:22 PM PDT 24
Finished Aug 04 04:31:24 PM PDT 24
Peak memory 205852 kb
Host smart-07fe4a8d-f77d-4477-ac98-ee94e8b7247e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748509595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3748509595
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.579312562
Short name T1027
Test name
Test status
Simulation time 29948043 ps
CPU time 0.72 seconds
Started Aug 04 04:32:34 PM PDT 24
Finished Aug 04 04:32:35 PM PDT 24
Peak memory 205680 kb
Host smart-ebc156e6-a7ad-4ff1-a423-e70f8adbe095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579312562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.579312562
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.797512053
Short name T1054
Test name
Test status
Simulation time 9707506 ps
CPU time 0.78 seconds
Started Aug 04 04:32:26 PM PDT 24
Finished Aug 04 04:32:27 PM PDT 24
Peak memory 205680 kb
Host smart-3e279b41-be4c-4972-aadb-570fcc457914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797512053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.797512053
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1582002828
Short name T977
Test name
Test status
Simulation time 11230714 ps
CPU time 0.7 seconds
Started Aug 04 04:31:25 PM PDT 24
Finished Aug 04 04:31:26 PM PDT 24
Peak memory 205848 kb
Host smart-69966f1f-5cfa-4606-ab9a-06bbfdeb5c3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582002828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1582002828
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.657379589
Short name T924
Test name
Test status
Simulation time 8390433 ps
CPU time 0.77 seconds
Started Aug 04 04:31:22 PM PDT 24
Finished Aug 04 04:31:24 PM PDT 24
Peak memory 205740 kb
Host smart-36278942-35b2-4a8f-bcb5-cd1c2aed8c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657379589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.657379589
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.880845409
Short name T959
Test name
Test status
Simulation time 15595891 ps
CPU time 0.8 seconds
Started Aug 04 04:31:38 PM PDT 24
Finished Aug 04 04:31:39 PM PDT 24
Peak memory 205736 kb
Host smart-4e5e4721-aa66-469c-abbe-80a3be5f7c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880845409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.880845409
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1223060715
Short name T965
Test name
Test status
Simulation time 11379396 ps
CPU time 0.8 seconds
Started Aug 04 04:32:42 PM PDT 24
Finished Aug 04 04:32:43 PM PDT 24
Peak memory 205768 kb
Host smart-630b461f-0195-46d2-a576-78a29c3f772f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223060715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1223060715
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.925102247
Short name T939
Test name
Test status
Simulation time 11516492 ps
CPU time 0.67 seconds
Started Aug 04 04:32:26 PM PDT 24
Finished Aug 04 04:32:27 PM PDT 24
Peak memory 205756 kb
Host smart-24fc5728-de96-45f8-9e7a-042a0fe8c47f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925102247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.925102247
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.277773168
Short name T1038
Test name
Test status
Simulation time 59215947 ps
CPU time 0.73 seconds
Started Aug 04 04:31:18 PM PDT 24
Finished Aug 04 04:31:18 PM PDT 24
Peak memory 205800 kb
Host smart-c16276a4-d247-446f-b69b-33f47120a3e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277773168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.277773168
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3387345156
Short name T1060
Test name
Test status
Simulation time 16740314 ps
CPU time 0.7 seconds
Started Aug 04 04:31:15 PM PDT 24
Finished Aug 04 04:31:16 PM PDT 24
Peak memory 205860 kb
Host smart-56db359a-0d7b-48bc-bcf5-f35d1f360dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387345156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3387345156
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.649577611
Short name T1040
Test name
Test status
Simulation time 920251021 ps
CPU time 11.05 seconds
Started Aug 04 04:31:08 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 206016 kb
Host smart-915bcede-044f-470b-863d-b23aacc93978
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649577611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.649577611
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.369492577
Short name T975
Test name
Test status
Simulation time 2679668125 ps
CPU time 10.2 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:29 PM PDT 24
Peak memory 206076 kb
Host smart-72b06bb4-df92-4e70-bb56-5a5b01d07edf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369492577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.369492577
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1318957170
Short name T981
Test name
Test status
Simulation time 164862822 ps
CPU time 1.47 seconds
Started Aug 04 04:31:09 PM PDT 24
Finished Aug 04 04:31:10 PM PDT 24
Peak memory 206068 kb
Host smart-3d808e9b-b67f-4089-8ba9-a07636db6542
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318957170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
318957170
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1929589080
Short name T1032
Test name
Test status
Simulation time 50950997 ps
CPU time 1.62 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 214332 kb
Host smart-aa9f93e0-ecfc-45a1-9cc8-199d1f038671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929589080 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1929589080
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1830574155
Short name T1007
Test name
Test status
Simulation time 86658039 ps
CPU time 1.06 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 205980 kb
Host smart-900b5575-20ce-4dbf-9fb0-ac24c60462eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830574155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1830574155
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.55425292
Short name T929
Test name
Test status
Simulation time 21128889 ps
CPU time 0.66 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:17 PM PDT 24
Peak memory 205772 kb
Host smart-9cd0e6a6-a7e0-43a8-b70f-625d13f36720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55425292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.55425292
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.28380118
Short name T982
Test name
Test status
Simulation time 187981036 ps
CPU time 2.52 seconds
Started Aug 04 04:31:04 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 206160 kb
Host smart-b26b9443-3f10-4b8a-b8c8-7a3d11c2a00c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28380118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same
_csr_outstanding.28380118
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3322327543
Short name T989
Test name
Test status
Simulation time 52884863 ps
CPU time 1.47 seconds
Started Aug 04 04:31:04 PM PDT 24
Finished Aug 04 04:31:06 PM PDT 24
Peak memory 214528 kb
Host smart-5eea773d-ba0b-47b7-99fc-72a073e8deae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322327543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3322327543
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2832940761
Short name T116
Test name
Test status
Simulation time 653607723 ps
CPU time 4.48 seconds
Started Aug 04 04:31:17 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 214620 kb
Host smart-29db5756-2875-4eb9-9b35-b3f470953230
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832940761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2832940761
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2520609877
Short name T954
Test name
Test status
Simulation time 106289320 ps
CPU time 1.78 seconds
Started Aug 04 04:31:27 PM PDT 24
Finished Aug 04 04:31:28 PM PDT 24
Peak memory 214248 kb
Host smart-17ded9f7-2448-43b2-a461-37e60853454b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520609877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2520609877
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.505541854
Short name T170
Test name
Test status
Simulation time 924819998 ps
CPU time 8.76 seconds
Started Aug 04 04:30:57 PM PDT 24
Finished Aug 04 04:31:06 PM PDT 24
Peak memory 214152 kb
Host smart-0878090c-8d90-4857-ada9-4062f4e86b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505541854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
505541854
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2268973788
Short name T930
Test name
Test status
Simulation time 198839584 ps
CPU time 0.74 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 205748 kb
Host smart-293fee97-ea7b-48ca-bb4f-59b43a793763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268973788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2268973788
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.60332854
Short name T920
Test name
Test status
Simulation time 13692244 ps
CPU time 0.69 seconds
Started Aug 04 04:31:48 PM PDT 24
Finished Aug 04 04:31:49 PM PDT 24
Peak memory 205804 kb
Host smart-ae97b3e8-5e54-414b-82e2-ddadfc3ff6ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60332854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.60332854
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2315293014
Short name T927
Test name
Test status
Simulation time 14259861 ps
CPU time 0.73 seconds
Started Aug 04 04:31:18 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 205852 kb
Host smart-ff72ab41-69a7-4596-800b-8463c9f71cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315293014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2315293014
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2614035509
Short name T1008
Test name
Test status
Simulation time 12425236 ps
CPU time 0.77 seconds
Started Aug 04 04:32:29 PM PDT 24
Finished Aug 04 04:32:30 PM PDT 24
Peak memory 205680 kb
Host smart-d1c1ebca-6ed7-444f-8a61-bd6bfdf7b5f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614035509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2614035509
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.235025663
Short name T1009
Test name
Test status
Simulation time 40891839 ps
CPU time 0.68 seconds
Started Aug 04 04:32:39 PM PDT 24
Finished Aug 04 04:32:40 PM PDT 24
Peak memory 205680 kb
Host smart-01c71700-f3db-4820-90c9-4d918c2582dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235025663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.235025663
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3188581875
Short name T933
Test name
Test status
Simulation time 38937558 ps
CPU time 0.67 seconds
Started Aug 04 04:32:31 PM PDT 24
Finished Aug 04 04:32:31 PM PDT 24
Peak memory 205756 kb
Host smart-8d5dde0a-bc76-42ac-a7da-b81601ad8c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188581875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3188581875
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2579099560
Short name T1074
Test name
Test status
Simulation time 17216861 ps
CPU time 0.68 seconds
Started Aug 04 04:32:38 PM PDT 24
Finished Aug 04 04:32:38 PM PDT 24
Peak memory 205756 kb
Host smart-fb4c4151-7223-4168-853f-6f3576e22389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579099560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2579099560
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1400050546
Short name T974
Test name
Test status
Simulation time 12237337 ps
CPU time 0.73 seconds
Started Aug 04 04:31:22 PM PDT 24
Finished Aug 04 04:31:23 PM PDT 24
Peak memory 205932 kb
Host smart-7ccfc4ec-0a4c-406d-b55a-5df7727d5827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400050546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1400050546
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.440417532
Short name T996
Test name
Test status
Simulation time 17712391 ps
CPU time 0.75 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 205764 kb
Host smart-82d28213-c60c-4bd3-a7bb-0053e1c1aa93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440417532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.440417532
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3373378149
Short name T1043
Test name
Test status
Simulation time 11459388 ps
CPU time 0.83 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:20 PM PDT 24
Peak memory 205916 kb
Host smart-a1e55c78-9e99-47a2-b34e-63b29664693e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373378149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3373378149
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3232490393
Short name T992
Test name
Test status
Simulation time 26213768 ps
CPU time 1.36 seconds
Started Aug 04 04:31:06 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 206120 kb
Host smart-0ca745d3-9a9e-44f3-916c-0e078ae05828
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232490393 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3232490393
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3650584072
Short name T1025
Test name
Test status
Simulation time 76177142 ps
CPU time 1.1 seconds
Started Aug 04 04:31:06 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 205920 kb
Host smart-741fc715-dbfd-4f67-ab88-a6f84da3684a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650584072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3650584072
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3876028085
Short name T1084
Test name
Test status
Simulation time 14990104 ps
CPU time 0.69 seconds
Started Aug 04 04:31:14 PM PDT 24
Finished Aug 04 04:31:15 PM PDT 24
Peak memory 205772 kb
Host smart-3032e350-1cb9-4846-8a86-4db2c6af5534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876028085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3876028085
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1974355814
Short name T1065
Test name
Test status
Simulation time 210396498 ps
CPU time 2.88 seconds
Started Aug 04 04:31:13 PM PDT 24
Finished Aug 04 04:31:16 PM PDT 24
Peak memory 206112 kb
Host smart-83ec2090-78de-4828-aa6e-636f7faef43f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974355814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1974355814
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2265527410
Short name T945
Test name
Test status
Simulation time 98703144 ps
CPU time 2.66 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:03 PM PDT 24
Peak memory 214560 kb
Host smart-e2827082-1ff5-45d2-bde9-fd9fee9052e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265527410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2265527410
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.467835394
Short name T1061
Test name
Test status
Simulation time 172850353 ps
CPU time 4.29 seconds
Started Aug 04 04:31:15 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 214516 kb
Host smart-b6d9d1ad-1e84-4ade-b818-cc0808f201c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467835394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.467835394
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2674992936
Short name T923
Test name
Test status
Simulation time 92347637 ps
CPU time 1.72 seconds
Started Aug 04 04:31:18 PM PDT 24
Finished Aug 04 04:31:20 PM PDT 24
Peak memory 214216 kb
Host smart-33f76d9b-442b-4398-9a49-6a65194708b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674992936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2674992936
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.4206718611
Short name T1075
Test name
Test status
Simulation time 41548966 ps
CPU time 1.06 seconds
Started Aug 04 04:30:57 PM PDT 24
Finished Aug 04 04:30:58 PM PDT 24
Peak memory 206092 kb
Host smart-0e61fa9e-45c6-4753-8eaa-5bf5b3637b55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206718611 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.4206718611
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1271061237
Short name T1042
Test name
Test status
Simulation time 18387196 ps
CPU time 0.93 seconds
Started Aug 04 04:30:55 PM PDT 24
Finished Aug 04 04:30:56 PM PDT 24
Peak memory 205760 kb
Host smart-9ce3719c-9869-4c33-8011-d492ed4e570c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271061237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1271061237
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1591208636
Short name T915
Test name
Test status
Simulation time 12739160 ps
CPU time 0.72 seconds
Started Aug 04 04:31:23 PM PDT 24
Finished Aug 04 04:31:24 PM PDT 24
Peak memory 205736 kb
Host smart-675f06fc-0e2b-4744-b28c-caeabd4eaf65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591208636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1591208636
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3078301065
Short name T154
Test name
Test status
Simulation time 80434168 ps
CPU time 1.63 seconds
Started Aug 04 04:31:09 PM PDT 24
Finished Aug 04 04:31:10 PM PDT 24
Peak memory 206128 kb
Host smart-cbb47946-1ed7-40fb-8422-4c6538a876ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078301065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3078301065
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2063430060
Short name T119
Test name
Test status
Simulation time 798320705 ps
CPU time 3.47 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:20 PM PDT 24
Peak memory 214588 kb
Host smart-42ef9b2e-b481-4295-aee0-6af38ca61b3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063430060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2063430060
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.172157413
Short name T1067
Test name
Test status
Simulation time 906937435 ps
CPU time 15.62 seconds
Started Aug 04 04:31:17 PM PDT 24
Finished Aug 04 04:31:33 PM PDT 24
Peak memory 214576 kb
Host smart-0c5dca3c-2b33-4431-81b7-97d77aae2167
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172157413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.172157413
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1297480669
Short name T953
Test name
Test status
Simulation time 49257074 ps
CPU time 1.89 seconds
Started Aug 04 04:31:10 PM PDT 24
Finished Aug 04 04:31:12 PM PDT 24
Peak memory 214388 kb
Host smart-1c54691a-1ab6-456b-841a-fe4a402891a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297480669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1297480669
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3505190086
Short name T984
Test name
Test status
Simulation time 101804181 ps
CPU time 1.74 seconds
Started Aug 04 04:31:17 PM PDT 24
Finished Aug 04 04:31:18 PM PDT 24
Peak memory 214328 kb
Host smart-cd1c6738-d1ee-4685-87f9-5e6447518b66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505190086 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3505190086
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3384561170
Short name T1028
Test name
Test status
Simulation time 23682868 ps
CPU time 1.04 seconds
Started Aug 04 04:31:08 PM PDT 24
Finished Aug 04 04:31:09 PM PDT 24
Peak memory 205980 kb
Host smart-85c433b9-6839-4442-880d-650ce41fa86b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384561170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3384561170
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2054703366
Short name T1005
Test name
Test status
Simulation time 20059852 ps
CPU time 0.73 seconds
Started Aug 04 04:31:08 PM PDT 24
Finished Aug 04 04:31:08 PM PDT 24
Peak memory 205760 kb
Host smart-965f746a-b48c-4f02-8069-07eadb2eb053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054703366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2054703366
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1133047305
Short name T993
Test name
Test status
Simulation time 193115285 ps
CPU time 2.19 seconds
Started Aug 04 04:31:12 PM PDT 24
Finished Aug 04 04:31:15 PM PDT 24
Peak memory 206060 kb
Host smart-39ad71e8-c9ed-4773-b1d3-f6626ce664a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133047305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1133047305
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.144332831
Short name T1019
Test name
Test status
Simulation time 191128179 ps
CPU time 3.36 seconds
Started Aug 04 04:31:15 PM PDT 24
Finished Aug 04 04:31:18 PM PDT 24
Peak memory 214500 kb
Host smart-d346bbc1-c9eb-4de1-aaa1-c093968027e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144332831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.144332831
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1276535879
Short name T1059
Test name
Test status
Simulation time 233693202 ps
CPU time 3.45 seconds
Started Aug 04 04:31:18 PM PDT 24
Finished Aug 04 04:31:23 PM PDT 24
Peak memory 214568 kb
Host smart-67913728-4a52-448f-8e96-d4dee66beac1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276535879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1276535879
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1043451883
Short name T1082
Test name
Test status
Simulation time 497940046 ps
CPU time 5.13 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 222456 kb
Host smart-81bb2ff7-f4d6-4172-821f-5180022c3469
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043451883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1043451883
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2258376621
Short name T946
Test name
Test status
Simulation time 91032726 ps
CPU time 1.31 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:23 PM PDT 24
Peak memory 214248 kb
Host smart-d786bf83-7ef9-4add-9d6a-2909eda95445
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258376621 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2258376621
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.105222102
Short name T1012
Test name
Test status
Simulation time 67057837 ps
CPU time 0.93 seconds
Started Aug 04 04:31:05 PM PDT 24
Finished Aug 04 04:31:06 PM PDT 24
Peak memory 205768 kb
Host smart-4d9cf36b-a813-4fcf-9625-fe23b63853b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105222102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.105222102
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3505456955
Short name T1056
Test name
Test status
Simulation time 21378786 ps
CPU time 0.76 seconds
Started Aug 04 04:31:03 PM PDT 24
Finished Aug 04 04:31:04 PM PDT 24
Peak memory 205720 kb
Host smart-6a67f183-938b-4d46-878a-284691e1ebbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505456955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3505456955
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2092890456
Short name T1072
Test name
Test status
Simulation time 57224542 ps
CPU time 1.44 seconds
Started Aug 04 04:31:11 PM PDT 24
Finished Aug 04 04:31:12 PM PDT 24
Peak memory 206116 kb
Host smart-77ab1cf9-26e3-4414-8b7f-e6acc022e2f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092890456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2092890456
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2426895840
Short name T990
Test name
Test status
Simulation time 101771135 ps
CPU time 2.47 seconds
Started Aug 04 04:31:10 PM PDT 24
Finished Aug 04 04:31:13 PM PDT 24
Peak memory 214540 kb
Host smart-4047fffa-ab07-402c-8281-adf5525c3cbf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426895840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2426895840
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3037916057
Short name T968
Test name
Test status
Simulation time 78964141 ps
CPU time 3.61 seconds
Started Aug 04 04:31:18 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 214572 kb
Host smart-8e485c15-0ea3-44ae-9d38-8045fd142682
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037916057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3037916057
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1490832816
Short name T1077
Test name
Test status
Simulation time 311013489 ps
CPU time 2.31 seconds
Started Aug 04 04:31:11 PM PDT 24
Finished Aug 04 04:31:13 PM PDT 24
Peak memory 214256 kb
Host smart-23ed3eac-6467-4dbc-a6c4-c55e99436284
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490832816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1490832816
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2114583878
Short name T935
Test name
Test status
Simulation time 124637617 ps
CPU time 3.66 seconds
Started Aug 04 04:31:22 PM PDT 24
Finished Aug 04 04:31:27 PM PDT 24
Peak memory 213900 kb
Host smart-0eabb7ac-3a6e-4ef9-90af-f3987fac2a10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114583878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2114583878
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2935378549
Short name T986
Test name
Test status
Simulation time 15876035 ps
CPU time 1 seconds
Started Aug 04 04:31:13 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 205884 kb
Host smart-35084608-a978-4243-9df9-aa8cfdb76a4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935378549 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2935378549
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1582098137
Short name T963
Test name
Test status
Simulation time 133184710 ps
CPU time 0.98 seconds
Started Aug 04 04:31:10 PM PDT 24
Finished Aug 04 04:31:11 PM PDT 24
Peak memory 205896 kb
Host smart-8ae436f5-ed01-4504-a80c-b526507e01e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582098137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1582098137
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1176661608
Short name T1016
Test name
Test status
Simulation time 47370731 ps
CPU time 0.8 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:17 PM PDT 24
Peak memory 205756 kb
Host smart-f409a274-6cda-432c-b486-3e048058f474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176661608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1176661608
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1084991721
Short name T1044
Test name
Test status
Simulation time 143277706 ps
CPU time 2.03 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:18 PM PDT 24
Peak memory 206164 kb
Host smart-831150a3-a91c-465c-aac8-2bc45818cd7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084991721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1084991721
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3371617002
Short name T1080
Test name
Test status
Simulation time 77344675 ps
CPU time 1.62 seconds
Started Aug 04 04:31:13 PM PDT 24
Finished Aug 04 04:31:15 PM PDT 24
Peak memory 214484 kb
Host smart-b23e8298-3c92-4a51-a3c6-0d58ed560e74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371617002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3371617002
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2785859536
Short name T970
Test name
Test status
Simulation time 711927165 ps
CPU time 6.94 seconds
Started Aug 04 04:31:07 PM PDT 24
Finished Aug 04 04:31:15 PM PDT 24
Peak memory 220584 kb
Host smart-674a2939-9d41-437b-a798-ed2317da8b7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785859536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2785859536
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1409789552
Short name T1030
Test name
Test status
Simulation time 322734343 ps
CPU time 2.3 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:23 PM PDT 24
Peak memory 214492 kb
Host smart-beaee64a-8122-4ec3-9dfe-e37e76a6be70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409789552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1409789552
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2932089895
Short name T164
Test name
Test status
Simulation time 133576863 ps
CPU time 3.68 seconds
Started Aug 04 04:31:05 PM PDT 24
Finished Aug 04 04:31:09 PM PDT 24
Peak memory 214176 kb
Host smart-fac2810e-1707-4742-abf0-e0ed795ec984
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932089895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2932089895
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1717451352
Short name T121
Test name
Test status
Simulation time 58267046 ps
CPU time 3.92 seconds
Started Aug 04 05:12:33 PM PDT 24
Finished Aug 04 05:12:37 PM PDT 24
Peak memory 214292 kb
Host smart-306a8dc1-b625-4216-9eb8-fb013463446e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1717451352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1717451352
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1396531805
Short name T652
Test name
Test status
Simulation time 249693730 ps
CPU time 3.7 seconds
Started Aug 04 05:12:33 PM PDT 24
Finished Aug 04 05:12:37 PM PDT 24
Peak memory 208580 kb
Host smart-57ad47c3-977e-40f7-bd3d-0528651a375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396531805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1396531805
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.184456739
Short name T264
Test name
Test status
Simulation time 117028996 ps
CPU time 2.62 seconds
Started Aug 04 05:12:33 PM PDT 24
Finished Aug 04 05:12:35 PM PDT 24
Peak memory 209732 kb
Host smart-3d13e1e4-c13b-481c-b8c2-826f561b6ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184456739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.184456739
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2371930700
Short name T899
Test name
Test status
Simulation time 403576373 ps
CPU time 4.7 seconds
Started Aug 04 05:12:33 PM PDT 24
Finished Aug 04 05:12:38 PM PDT 24
Peak memory 213464 kb
Host smart-a29820f0-27f1-4d22-9c55-d2e25596dfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371930700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2371930700
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.637490633
Short name T47
Test name
Test status
Simulation time 165348296 ps
CPU time 2.78 seconds
Started Aug 04 05:12:32 PM PDT 24
Finished Aug 04 05:12:35 PM PDT 24
Peak memory 222500 kb
Host smart-db116afe-7ded-410b-99d4-f7db89b56e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637490633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.637490633
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3826677316
Short name T453
Test name
Test status
Simulation time 90272352 ps
CPU time 4.07 seconds
Started Aug 04 05:12:34 PM PDT 24
Finished Aug 04 05:12:38 PM PDT 24
Peak memory 209340 kb
Host smart-90c1a001-8662-4126-8346-f8813183b28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826677316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3826677316
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2151886878
Short name T43
Test name
Test status
Simulation time 1885381336 ps
CPU time 11.13 seconds
Started Aug 04 05:12:37 PM PDT 24
Finished Aug 04 05:12:48 PM PDT 24
Peak memory 238572 kb
Host smart-0c60656a-5d3f-41ca-bd93-86f9d9ea7b44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151886878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2151886878
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.4063334675
Short name T460
Test name
Test status
Simulation time 228309794 ps
CPU time 5.95 seconds
Started Aug 04 05:12:32 PM PDT 24
Finished Aug 04 05:12:38 PM PDT 24
Peak memory 208356 kb
Host smart-37a24d29-72f8-46ed-b744-f5b01e4d2471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063334675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.4063334675
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1607282056
Short name T749
Test name
Test status
Simulation time 248415536 ps
CPU time 3.32 seconds
Started Aug 04 05:12:32 PM PDT 24
Finished Aug 04 05:12:36 PM PDT 24
Peak memory 206904 kb
Host smart-6a7ff7db-a5fe-46b2-b5b4-97593f3dcb8c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607282056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1607282056
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1941210626
Short name T905
Test name
Test status
Simulation time 121624791 ps
CPU time 2.29 seconds
Started Aug 04 05:12:33 PM PDT 24
Finished Aug 04 05:12:35 PM PDT 24
Peak memory 207308 kb
Host smart-c8707a6f-e47b-4eed-9f76-2e4ea806c62d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941210626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1941210626
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1132335745
Short name T426
Test name
Test status
Simulation time 26055419 ps
CPU time 2.21 seconds
Started Aug 04 05:12:33 PM PDT 24
Finished Aug 04 05:12:35 PM PDT 24
Peak memory 208952 kb
Host smart-d22015ae-0a8a-42d4-b5e4-5c02d86b6818
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132335745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1132335745
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.665159131
Short name T331
Test name
Test status
Simulation time 661422685 ps
CPU time 7.08 seconds
Started Aug 04 05:12:32 PM PDT 24
Finished Aug 04 05:12:40 PM PDT 24
Peak memory 215892 kb
Host smart-6890e9c9-f53e-436a-b994-bac8f8cb1ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665159131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.665159131
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3531160059
Short name T869
Test name
Test status
Simulation time 106456711 ps
CPU time 3.32 seconds
Started Aug 04 05:12:31 PM PDT 24
Finished Aug 04 05:12:35 PM PDT 24
Peak memory 206876 kb
Host smart-19cb7e6e-4d1f-41a8-ac2a-24ef67291a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531160059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3531160059
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3706299525
Short name T904
Test name
Test status
Simulation time 2013230607 ps
CPU time 11.53 seconds
Started Aug 04 05:12:32 PM PDT 24
Finished Aug 04 05:12:44 PM PDT 24
Peak memory 216188 kb
Host smart-be2f85e4-526c-433f-acfc-97af486887f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706299525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3706299525
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3181698002
Short name T129
Test name
Test status
Simulation time 682661752 ps
CPU time 12.39 seconds
Started Aug 04 05:12:38 PM PDT 24
Finished Aug 04 05:12:51 PM PDT 24
Peak memory 217736 kb
Host smart-9816efed-2173-45dd-adf8-9af6cde1aacf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181698002 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3181698002
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1510343898
Short name T871
Test name
Test status
Simulation time 123873334 ps
CPU time 4.37 seconds
Started Aug 04 05:12:34 PM PDT 24
Finished Aug 04 05:12:39 PM PDT 24
Peak memory 209464 kb
Host smart-2f385509-89f7-4435-b9cf-3c9ba7244911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510343898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1510343898
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3882015077
Short name T61
Test name
Test status
Simulation time 14105289448 ps
CPU time 16.5 seconds
Started Aug 04 05:12:32 PM PDT 24
Finished Aug 04 05:12:49 PM PDT 24
Peak memory 211488 kb
Host smart-a2c49399-7bc4-45ce-945a-94e9630c5ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882015077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3882015077
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.4173184619
Short name T469
Test name
Test status
Simulation time 13978737 ps
CPU time 0.87 seconds
Started Aug 04 05:12:44 PM PDT 24
Finished Aug 04 05:12:45 PM PDT 24
Peak memory 205900 kb
Host smart-a8c2f82a-b5d5-4c23-8908-a9f2bcaba0ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173184619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4173184619
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.670316308
Short name T656
Test name
Test status
Simulation time 32863310 ps
CPU time 2.6 seconds
Started Aug 04 05:12:41 PM PDT 24
Finished Aug 04 05:12:44 PM PDT 24
Peak memory 214240 kb
Host smart-2115edbe-7ee3-4054-b6b0-d87eb270c72e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670316308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.670316308
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3255152648
Short name T737
Test name
Test status
Simulation time 29953176 ps
CPU time 2.02 seconds
Started Aug 04 05:12:43 PM PDT 24
Finished Aug 04 05:12:45 PM PDT 24
Peak memory 207848 kb
Host smart-058a899c-3079-4f22-9f88-25ec4e6b0f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255152648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3255152648
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2423933663
Short name T647
Test name
Test status
Simulation time 564187684 ps
CPU time 4.11 seconds
Started Aug 04 05:12:40 PM PDT 24
Finished Aug 04 05:12:44 PM PDT 24
Peak memory 222416 kb
Host smart-7d3da7fc-678f-4818-a3e1-1a2d82e9f599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423933663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2423933663
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.291870763
Short name T528
Test name
Test status
Simulation time 581586847 ps
CPU time 4.28 seconds
Started Aug 04 05:12:40 PM PDT 24
Finished Aug 04 05:12:45 PM PDT 24
Peak memory 209540 kb
Host smart-658ad7ab-3bb5-48e0-8331-924df437bfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291870763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.291870763
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.613327473
Short name T434
Test name
Test status
Simulation time 388158032 ps
CPU time 5.71 seconds
Started Aug 04 05:12:42 PM PDT 24
Finished Aug 04 05:12:48 PM PDT 24
Peak memory 214232 kb
Host smart-eee2bfb5-68b1-42c0-8439-4bf07cd643e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613327473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.613327473
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4057361413
Short name T521
Test name
Test status
Simulation time 575151405 ps
CPU time 12.29 seconds
Started Aug 04 05:12:41 PM PDT 24
Finished Aug 04 05:12:54 PM PDT 24
Peak memory 207896 kb
Host smart-27809ec3-5cc3-463c-927b-6ca48f840ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057361413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4057361413
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1765196699
Short name T270
Test name
Test status
Simulation time 261077480 ps
CPU time 5.77 seconds
Started Aug 04 05:12:42 PM PDT 24
Finished Aug 04 05:12:48 PM PDT 24
Peak memory 208796 kb
Host smart-6c1d5f66-ab41-4b8c-b656-aebc07594bf1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765196699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1765196699
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1110197347
Short name T773
Test name
Test status
Simulation time 26382547 ps
CPU time 1.99 seconds
Started Aug 04 05:12:42 PM PDT 24
Finished Aug 04 05:12:44 PM PDT 24
Peak memory 208640 kb
Host smart-86609108-5336-40a0-ba4f-d27272ad74bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110197347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1110197347
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.52232204
Short name T712
Test name
Test status
Simulation time 230741037 ps
CPU time 4.85 seconds
Started Aug 04 05:12:41 PM PDT 24
Finished Aug 04 05:12:46 PM PDT 24
Peak memory 207960 kb
Host smart-4be2772b-da7f-4bf5-b2d4-ad1efe088081
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52232204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.52232204
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.491730896
Short name T360
Test name
Test status
Simulation time 169278467 ps
CPU time 6.53 seconds
Started Aug 04 05:12:44 PM PDT 24
Finished Aug 04 05:12:51 PM PDT 24
Peak memory 208792 kb
Host smart-777bcf58-7458-4f30-8df8-c523bf29ba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491730896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.491730896
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1695030952
Short name T400
Test name
Test status
Simulation time 494077478 ps
CPU time 3.22 seconds
Started Aug 04 05:12:38 PM PDT 24
Finished Aug 04 05:12:41 PM PDT 24
Peak memory 206796 kb
Host smart-ff693fc8-81be-4475-8431-abf9a2b90e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695030952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1695030952
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3727684
Short name T230
Test name
Test status
Simulation time 3788454711 ps
CPU time 87.84 seconds
Started Aug 04 05:12:44 PM PDT 24
Finished Aug 04 05:14:12 PM PDT 24
Peak memory 222560 kb
Host smart-e89501d4-e8f4-4489-b48b-26ccc605922f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3727684
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.999974166
Short name T488
Test name
Test status
Simulation time 153402283 ps
CPU time 5.6 seconds
Started Aug 04 05:12:40 PM PDT 24
Finished Aug 04 05:12:46 PM PDT 24
Peak memory 207936 kb
Host smart-de528abe-1684-49c0-aae3-fe6c345909ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999974166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.999974166
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2083397046
Short name T432
Test name
Test status
Simulation time 74983109 ps
CPU time 2.64 seconds
Started Aug 04 05:12:46 PM PDT 24
Finished Aug 04 05:12:49 PM PDT 24
Peak memory 210452 kb
Host smart-d90a384c-b360-4aa2-bffd-7aefd5dd3c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083397046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2083397046
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.789190789
Short name T105
Test name
Test status
Simulation time 41979337 ps
CPU time 0.73 seconds
Started Aug 04 05:13:31 PM PDT 24
Finished Aug 04 05:13:32 PM PDT 24
Peak memory 205956 kb
Host smart-5a845ec2-c3dc-489e-83a8-7a4c75146cf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789190789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.789190789
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1722103097
Short name T120
Test name
Test status
Simulation time 91380537 ps
CPU time 3.56 seconds
Started Aug 04 05:13:31 PM PDT 24
Finished Aug 04 05:13:35 PM PDT 24
Peak memory 215248 kb
Host smart-8323719d-9a03-4de9-82a2-d3ac91ec9a70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722103097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1722103097
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2223853273
Short name T27
Test name
Test status
Simulation time 139382377 ps
CPU time 5.95 seconds
Started Aug 04 05:13:32 PM PDT 24
Finished Aug 04 05:13:38 PM PDT 24
Peak memory 222560 kb
Host smart-0ff7deff-2729-42a2-8387-9b803b92008b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223853273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2223853273
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3110400831
Short name T341
Test name
Test status
Simulation time 82797419 ps
CPU time 2.76 seconds
Started Aug 04 05:13:32 PM PDT 24
Finished Aug 04 05:13:35 PM PDT 24
Peak memory 214252 kb
Host smart-18b56eb8-f9a7-4809-88d9-b2c31a54f85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110400831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3110400831
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3902257760
Short name T339
Test name
Test status
Simulation time 182996868 ps
CPU time 4.25 seconds
Started Aug 04 05:13:33 PM PDT 24
Finished Aug 04 05:13:37 PM PDT 24
Peak memory 214988 kb
Host smart-c0e49431-fb88-4b7f-86d0-d48c42f8ecf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902257760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3902257760
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.726724181
Short name T555
Test name
Test status
Simulation time 172500824 ps
CPU time 4.95 seconds
Started Aug 04 05:13:34 PM PDT 24
Finished Aug 04 05:13:39 PM PDT 24
Peak memory 209756 kb
Host smart-97a8fd2f-319e-4ef4-a91d-45cc4b9fbe69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726724181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.726724181
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2956096756
Short name T720
Test name
Test status
Simulation time 1607438718 ps
CPU time 20.98 seconds
Started Aug 04 05:13:31 PM PDT 24
Finished Aug 04 05:13:52 PM PDT 24
Peak memory 208064 kb
Host smart-709ab47b-121f-466a-ba4a-86af4e6d7e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956096756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2956096756
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3325423895
Short name T202
Test name
Test status
Simulation time 406464562 ps
CPU time 3.55 seconds
Started Aug 04 05:13:30 PM PDT 24
Finished Aug 04 05:13:34 PM PDT 24
Peak memory 206716 kb
Host smart-743439d6-4f8c-484e-beec-6b6cdc10394e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325423895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3325423895
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2880990052
Short name T590
Test name
Test status
Simulation time 124393832 ps
CPU time 3.15 seconds
Started Aug 04 05:13:33 PM PDT 24
Finished Aug 04 05:13:37 PM PDT 24
Peak memory 208736 kb
Host smart-697e9f6c-42f9-4069-bc53-8f3c7f24812d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880990052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2880990052
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.855648267
Short name T430
Test name
Test status
Simulation time 110286891 ps
CPU time 3.81 seconds
Started Aug 04 05:13:34 PM PDT 24
Finished Aug 04 05:13:38 PM PDT 24
Peak memory 208652 kb
Host smart-cd6185d0-e65f-48f5-8be8-9b5f984ae8f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855648267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.855648267
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.721071803
Short name T256
Test name
Test status
Simulation time 74837016 ps
CPU time 3.03 seconds
Started Aug 04 05:13:32 PM PDT 24
Finished Aug 04 05:13:36 PM PDT 24
Peak memory 208452 kb
Host smart-d9dbed7f-3db7-4417-a119-aa892d45f468
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721071803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.721071803
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2078042640
Short name T495
Test name
Test status
Simulation time 40886074 ps
CPU time 1.76 seconds
Started Aug 04 05:13:34 PM PDT 24
Finished Aug 04 05:13:36 PM PDT 24
Peak memory 214940 kb
Host smart-32b87f1f-9d2b-4507-8d91-d85517a2ea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078042640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2078042640
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3438038825
Short name T645
Test name
Test status
Simulation time 807072041 ps
CPU time 19.56 seconds
Started Aug 04 05:13:35 PM PDT 24
Finished Aug 04 05:13:54 PM PDT 24
Peak memory 208264 kb
Host smart-a4286a14-d4ae-4f91-8ba1-73245ea5f62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438038825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3438038825
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2142774988
Short name T220
Test name
Test status
Simulation time 326140571 ps
CPU time 9.93 seconds
Started Aug 04 05:13:30 PM PDT 24
Finished Aug 04 05:13:40 PM PDT 24
Peak memory 214804 kb
Host smart-6cfc9855-7ccb-4a3c-8754-95ebaca5d67e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142774988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2142774988
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.469196866
Short name T413
Test name
Test status
Simulation time 195558586 ps
CPU time 6.73 seconds
Started Aug 04 05:13:31 PM PDT 24
Finished Aug 04 05:13:38 PM PDT 24
Peak memory 206960 kb
Host smart-90141359-821f-49fd-8e19-8b2e6bdc451d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469196866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.469196866
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2040394012
Short name T569
Test name
Test status
Simulation time 74565377 ps
CPU time 2.98 seconds
Started Aug 04 05:13:31 PM PDT 24
Finished Aug 04 05:13:34 PM PDT 24
Peak memory 210564 kb
Host smart-b42ae7df-bc95-44d8-841b-08906248506b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040394012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2040394012
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.405682351
Short name T623
Test name
Test status
Simulation time 20675468 ps
CPU time 0.76 seconds
Started Aug 04 05:13:37 PM PDT 24
Finished Aug 04 05:13:38 PM PDT 24
Peak memory 205872 kb
Host smart-3d4a1e26-fe49-4f91-a111-90a0a51682a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405682351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.405682351
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.775939992
Short name T243
Test name
Test status
Simulation time 89257132 ps
CPU time 5.14 seconds
Started Aug 04 05:13:35 PM PDT 24
Finished Aug 04 05:13:40 PM PDT 24
Peak memory 214196 kb
Host smart-a6083182-29e8-4155-8ee6-9c6738edb638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775939992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.775939992
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2196180173
Short name T693
Test name
Test status
Simulation time 109681764 ps
CPU time 2.97 seconds
Started Aug 04 05:13:36 PM PDT 24
Finished Aug 04 05:13:39 PM PDT 24
Peak memory 208028 kb
Host smart-e9d9f221-779f-498a-8fc9-38d32f54eda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196180173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2196180173
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.293448507
Short name T572
Test name
Test status
Simulation time 148898601 ps
CPU time 2.05 seconds
Started Aug 04 05:13:37 PM PDT 24
Finished Aug 04 05:13:39 PM PDT 24
Peak memory 207668 kb
Host smart-df3a83cf-272c-4075-b69d-a1803918d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293448507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.293448507
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1093378413
Short name T50
Test name
Test status
Simulation time 73165844 ps
CPU time 3.59 seconds
Started Aug 04 05:13:37 PM PDT 24
Finished Aug 04 05:13:40 PM PDT 24
Peak memory 222456 kb
Host smart-a099ca2d-6a97-4616-83b7-66bf0cc44fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093378413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1093378413
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1602739732
Short name T914
Test name
Test status
Simulation time 49562075 ps
CPU time 3.53 seconds
Started Aug 04 05:13:40 PM PDT 24
Finished Aug 04 05:13:43 PM PDT 24
Peak memory 222332 kb
Host smart-cceca2da-5ece-40cc-930b-152dafefe514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602739732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1602739732
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3141964580
Short name T309
Test name
Test status
Simulation time 183383970 ps
CPU time 3.7 seconds
Started Aug 04 05:13:35 PM PDT 24
Finished Aug 04 05:13:39 PM PDT 24
Peak memory 214396 kb
Host smart-eeaefcbe-7b19-48b2-ade0-8ae7516ec4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141964580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3141964580
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.913053637
Short name T586
Test name
Test status
Simulation time 66567779 ps
CPU time 3.82 seconds
Started Aug 04 05:13:35 PM PDT 24
Finished Aug 04 05:13:39 PM PDT 24
Peak memory 208500 kb
Host smart-752c5743-9611-4e18-bc2b-2d9e264430c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913053637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.913053637
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.716422348
Short name T213
Test name
Test status
Simulation time 3590802876 ps
CPU time 42.66 seconds
Started Aug 04 05:13:31 PM PDT 24
Finished Aug 04 05:14:14 PM PDT 24
Peak memory 208484 kb
Host smart-355b83c3-94b0-46b0-867e-cce3b2beea3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716422348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.716422348
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2500492371
Short name T588
Test name
Test status
Simulation time 88896224 ps
CPU time 1.99 seconds
Started Aug 04 05:13:30 PM PDT 24
Finished Aug 04 05:13:33 PM PDT 24
Peak memory 208576 kb
Host smart-2bce489e-97f6-4e6c-8497-8d28d344c248
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500492371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2500492371
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2439217485
Short name T796
Test name
Test status
Simulation time 459023296 ps
CPU time 5.49 seconds
Started Aug 04 05:13:33 PM PDT 24
Finished Aug 04 05:13:39 PM PDT 24
Peak memory 208428 kb
Host smart-e988abda-8d51-4652-89b7-159d6b646b15
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439217485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2439217485
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2079389042
Short name T465
Test name
Test status
Simulation time 838562478 ps
CPU time 12.53 seconds
Started Aug 04 05:13:34 PM PDT 24
Finished Aug 04 05:13:47 PM PDT 24
Peak memory 207812 kb
Host smart-aa24c9b5-b6f4-4216-aaa6-eea0b33a393f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079389042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2079389042
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3597818046
Short name T627
Test name
Test status
Simulation time 32100206 ps
CPU time 2.51 seconds
Started Aug 04 05:13:37 PM PDT 24
Finished Aug 04 05:13:40 PM PDT 24
Peak memory 214364 kb
Host smart-a57dca5e-8d93-4bb2-9fa5-44f2a1ff8d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597818046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3597818046
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.751125187
Short name T490
Test name
Test status
Simulation time 1367806734 ps
CPU time 21.95 seconds
Started Aug 04 05:13:35 PM PDT 24
Finished Aug 04 05:13:57 PM PDT 24
Peak memory 208452 kb
Host smart-0e2b8e0d-b34c-48cc-b086-f007dbbabc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751125187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.751125187
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2202059933
Short name T306
Test name
Test status
Simulation time 386948835 ps
CPU time 20.33 seconds
Started Aug 04 05:13:36 PM PDT 24
Finished Aug 04 05:13:56 PM PDT 24
Peak memory 215704 kb
Host smart-7b407fb6-aeaf-41d1-9d77-2d06eca09a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202059933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2202059933
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2125388135
Short name T509
Test name
Test status
Simulation time 87500379 ps
CPU time 4.29 seconds
Started Aug 04 05:13:36 PM PDT 24
Finished Aug 04 05:13:40 PM PDT 24
Peak memory 214420 kb
Host smart-ac9b72dc-8ec7-4aee-a53e-5598a91bdbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125388135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2125388135
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1392920512
Short name T524
Test name
Test status
Simulation time 12661387 ps
CPU time 0.79 seconds
Started Aug 04 05:13:38 PM PDT 24
Finished Aug 04 05:13:39 PM PDT 24
Peak memory 205964 kb
Host smart-edd0187e-4862-434c-803e-48a647dcfd20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392920512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1392920512
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1301813649
Short name T890
Test name
Test status
Simulation time 170582741 ps
CPU time 9.26 seconds
Started Aug 04 05:13:36 PM PDT 24
Finished Aug 04 05:13:45 PM PDT 24
Peak memory 214336 kb
Host smart-d72d831c-6dc0-455d-8273-5786241deaaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301813649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1301813649
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1354682109
Short name T848
Test name
Test status
Simulation time 726610738 ps
CPU time 4.06 seconds
Started Aug 04 05:13:39 PM PDT 24
Finished Aug 04 05:13:44 PM PDT 24
Peak memory 218880 kb
Host smart-7b4d3085-24bb-477c-b3a6-fbf4d8e0b9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354682109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1354682109
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.830177998
Short name T448
Test name
Test status
Simulation time 1233348690 ps
CPU time 10.04 seconds
Started Aug 04 05:13:36 PM PDT 24
Finished Aug 04 05:13:46 PM PDT 24
Peak memory 214236 kb
Host smart-cea8afad-d8fc-4527-98a9-bbd4253e6a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830177998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.830177998
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.17396174
Short name T855
Test name
Test status
Simulation time 139017258 ps
CPU time 4.04 seconds
Started Aug 04 05:13:39 PM PDT 24
Finished Aug 04 05:13:43 PM PDT 24
Peak memory 215128 kb
Host smart-3cf2e19b-be98-4605-9bc5-ca473c7862fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17396174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.17396174
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.2533490298
Short name T550
Test name
Test status
Simulation time 119442098 ps
CPU time 5.37 seconds
Started Aug 04 05:13:37 PM PDT 24
Finished Aug 04 05:13:43 PM PDT 24
Peak memory 209608 kb
Host smart-e539bb78-409b-47c5-9411-b40d90a8fc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533490298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2533490298
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.720224291
Short name T140
Test name
Test status
Simulation time 134412968 ps
CPU time 5.34 seconds
Started Aug 04 05:13:35 PM PDT 24
Finished Aug 04 05:13:41 PM PDT 24
Peak memory 207848 kb
Host smart-21d2c695-0f67-486b-bf1a-c39e6e4d27d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720224291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.720224291
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1248927974
Short name T667
Test name
Test status
Simulation time 173451636 ps
CPU time 4.33 seconds
Started Aug 04 05:13:36 PM PDT 24
Finished Aug 04 05:13:41 PM PDT 24
Peak memory 208500 kb
Host smart-59d04123-1445-41fe-9d01-0c874bff5cac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248927974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1248927974
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.4165136156
Short name T672
Test name
Test status
Simulation time 754282239 ps
CPU time 25.93 seconds
Started Aug 04 05:13:34 PM PDT 24
Finished Aug 04 05:14:00 PM PDT 24
Peak memory 208688 kb
Host smart-3258a420-7052-493c-88c2-3bc7d0833701
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165136156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.4165136156
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.4159199398
Short name T625
Test name
Test status
Simulation time 50726611 ps
CPU time 2.63 seconds
Started Aug 04 05:13:36 PM PDT 24
Finished Aug 04 05:13:39 PM PDT 24
Peak memory 208568 kb
Host smart-2f68acb6-d6f5-49af-a607-1880d3ed6177
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159199398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4159199398
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.575964249
Short name T686
Test name
Test status
Simulation time 382688175 ps
CPU time 4.11 seconds
Started Aug 04 05:13:40 PM PDT 24
Finished Aug 04 05:13:44 PM PDT 24
Peak memory 208076 kb
Host smart-a2d4fada-4638-45db-9f9f-12e51db35355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575964249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.575964249
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3761994511
Short name T651
Test name
Test status
Simulation time 293681136 ps
CPU time 3.84 seconds
Started Aug 04 05:14:13 PM PDT 24
Finished Aug 04 05:14:16 PM PDT 24
Peak memory 207904 kb
Host smart-5b6c72c9-c80c-40b4-bf93-f816aa93579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761994511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3761994511
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.734521897
Short name T86
Test name
Test status
Simulation time 228251889 ps
CPU time 4.03 seconds
Started Aug 04 05:13:40 PM PDT 24
Finished Aug 04 05:13:44 PM PDT 24
Peak memory 209472 kb
Host smart-cbf53c1b-86dc-4c64-a1c9-12e8619caf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734521897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.734521897
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2275638852
Short name T554
Test name
Test status
Simulation time 123690233 ps
CPU time 2.01 seconds
Started Aug 04 05:13:39 PM PDT 24
Finished Aug 04 05:13:41 PM PDT 24
Peak memory 209880 kb
Host smart-e89fee52-6948-4cb4-9324-a39d250dd3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275638852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2275638852
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2974325911
Short name T891
Test name
Test status
Simulation time 30162600 ps
CPU time 0.8 seconds
Started Aug 04 05:13:43 PM PDT 24
Finished Aug 04 05:13:44 PM PDT 24
Peak memory 205956 kb
Host smart-d85897e0-8168-46fe-810d-22df70459fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974325911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2974325911
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.481364320
Short name T275
Test name
Test status
Simulation time 46730358 ps
CPU time 3.08 seconds
Started Aug 04 05:13:43 PM PDT 24
Finished Aug 04 05:13:47 PM PDT 24
Peak memory 222372 kb
Host smart-4e391f80-6f2d-4f16-8481-23e13efdce54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=481364320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.481364320
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2439553832
Short name T575
Test name
Test status
Simulation time 450890414 ps
CPU time 5.04 seconds
Started Aug 04 05:13:43 PM PDT 24
Finished Aug 04 05:13:48 PM PDT 24
Peak memory 210544 kb
Host smart-09676033-9234-4814-a870-3e46c12d3d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439553832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2439553832
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1830966056
Short name T74
Test name
Test status
Simulation time 152002663 ps
CPU time 3.17 seconds
Started Aug 04 05:13:42 PM PDT 24
Finished Aug 04 05:13:45 PM PDT 24
Peak memory 208788 kb
Host smart-95a0f98b-bd6d-4592-9384-af2b5af4a15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830966056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1830966056
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.4070074965
Short name T814
Test name
Test status
Simulation time 180955060 ps
CPU time 6.29 seconds
Started Aug 04 05:13:45 PM PDT 24
Finished Aug 04 05:13:51 PM PDT 24
Peak memory 218416 kb
Host smart-6ffa8f27-0345-4517-9ab5-fb45ec58495d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070074965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.4070074965
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3981605483
Short name T541
Test name
Test status
Simulation time 366296614 ps
CPU time 2.49 seconds
Started Aug 04 05:13:43 PM PDT 24
Finished Aug 04 05:13:46 PM PDT 24
Peak memory 214240 kb
Host smart-0e62759a-9935-4fbe-b33a-f6e5d61c048d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981605483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3981605483
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.960729129
Short name T908
Test name
Test status
Simulation time 312738402 ps
CPU time 4.34 seconds
Started Aug 04 05:13:42 PM PDT 24
Finished Aug 04 05:13:47 PM PDT 24
Peak memory 210036 kb
Host smart-ce7da914-d136-41d8-881e-1af6a76e19cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960729129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.960729129
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2575918409
Short name T599
Test name
Test status
Simulation time 144254062 ps
CPU time 4.02 seconds
Started Aug 04 05:13:39 PM PDT 24
Finished Aug 04 05:13:43 PM PDT 24
Peak memory 206804 kb
Host smart-b8ec7b20-0c34-4cc5-8fca-e984b968191c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575918409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2575918409
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2971872423
Short name T832
Test name
Test status
Simulation time 372909979 ps
CPU time 3.19 seconds
Started Aug 04 05:13:45 PM PDT 24
Finished Aug 04 05:13:49 PM PDT 24
Peak memory 208296 kb
Host smart-36f755cd-6c18-49e2-8a3b-80e9db07ba88
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971872423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2971872423
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2358164209
Short name T739
Test name
Test status
Simulation time 38699284 ps
CPU time 1.83 seconds
Started Aug 04 05:13:39 PM PDT 24
Finished Aug 04 05:13:41 PM PDT 24
Peak memory 206832 kb
Host smart-82e080ab-5e10-417e-855a-03d3afe25f3a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358164209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2358164209
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.920686534
Short name T323
Test name
Test status
Simulation time 38477902 ps
CPU time 2.63 seconds
Started Aug 04 05:13:42 PM PDT 24
Finished Aug 04 05:13:45 PM PDT 24
Peak memory 208844 kb
Host smart-ace087fe-bdf4-4491-890d-e922a8e8ea69
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920686534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.920686534
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3053098459
Short name T533
Test name
Test status
Simulation time 102179643 ps
CPU time 4.37 seconds
Started Aug 04 05:13:42 PM PDT 24
Finished Aug 04 05:13:46 PM PDT 24
Peak memory 210080 kb
Host smart-8c58070a-c49c-4813-a06a-87aa35c3e512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053098459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3053098459
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.153822104
Short name T107
Test name
Test status
Simulation time 35528663 ps
CPU time 2.07 seconds
Started Aug 04 05:13:40 PM PDT 24
Finished Aug 04 05:13:43 PM PDT 24
Peak memory 206888 kb
Host smart-dbef5365-69e2-48e5-8f68-37f989b50066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153822104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.153822104
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1718513134
Short name T185
Test name
Test status
Simulation time 1370216970 ps
CPU time 26.71 seconds
Started Aug 04 05:13:43 PM PDT 24
Finished Aug 04 05:14:09 PM PDT 24
Peak memory 222492 kb
Host smart-dad11b21-b6c4-47f3-8829-2ea78f7a0ce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718513134 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1718513134
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3768073009
Short name T277
Test name
Test status
Simulation time 132994581 ps
CPU time 5.67 seconds
Started Aug 04 05:13:45 PM PDT 24
Finished Aug 04 05:13:51 PM PDT 24
Peak memory 214336 kb
Host smart-7dc1bae5-ed1b-4004-ab82-a5b9080e5586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768073009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3768073009
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2584106739
Short name T511
Test name
Test status
Simulation time 147502558 ps
CPU time 2.08 seconds
Started Aug 04 05:13:42 PM PDT 24
Finished Aug 04 05:13:44 PM PDT 24
Peak memory 209780 kb
Host smart-8c839ab0-6596-4588-8dd8-1b0e2488c462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584106739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2584106739
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1294997091
Short name T478
Test name
Test status
Simulation time 15679650 ps
CPU time 0.77 seconds
Started Aug 04 05:13:47 PM PDT 24
Finished Aug 04 05:13:48 PM PDT 24
Peak memory 206104 kb
Host smart-3b068e63-3a15-4968-9b2f-8a9a26d809e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294997091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1294997091
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2650486291
Short name T336
Test name
Test status
Simulation time 118880302 ps
CPU time 2.6 seconds
Started Aug 04 05:13:46 PM PDT 24
Finished Aug 04 05:13:49 PM PDT 24
Peak memory 214340 kb
Host smart-5472f759-e8a0-4863-a582-eab48de528f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2650486291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2650486291
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.760461444
Short name T68
Test name
Test status
Simulation time 352029684 ps
CPU time 7.13 seconds
Started Aug 04 05:13:49 PM PDT 24
Finished Aug 04 05:13:56 PM PDT 24
Peak memory 209844 kb
Host smart-8808b40a-4feb-4528-a980-71f7307671ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760461444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.760461444
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3940709583
Short name T87
Test name
Test status
Simulation time 142894962 ps
CPU time 2.36 seconds
Started Aug 04 05:13:47 PM PDT 24
Finished Aug 04 05:13:49 PM PDT 24
Peak memory 214320 kb
Host smart-f4b2a1b2-539b-4b20-8ee5-122e14420a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940709583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3940709583
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2404126191
Short name T101
Test name
Test status
Simulation time 1115791646 ps
CPU time 5.41 seconds
Started Aug 04 05:13:46 PM PDT 24
Finished Aug 04 05:13:52 PM PDT 24
Peak memory 214324 kb
Host smart-d5ce298e-3322-4fe2-889a-8e68311c93f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404126191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2404126191
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.706743012
Short name T189
Test name
Test status
Simulation time 726290243 ps
CPU time 4.57 seconds
Started Aug 04 05:13:50 PM PDT 24
Finished Aug 04 05:13:55 PM PDT 24
Peak memory 222408 kb
Host smart-93f2e0b1-82aa-4c21-b5ff-a46771e7fbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706743012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.706743012
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4074784468
Short name T53
Test name
Test status
Simulation time 27755735 ps
CPU time 1.52 seconds
Started Aug 04 05:13:49 PM PDT 24
Finished Aug 04 05:13:50 PM PDT 24
Peak memory 214760 kb
Host smart-a9102090-c76a-4755-a300-7e467eac9623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074784468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4074784468
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1250581422
Short name T889
Test name
Test status
Simulation time 7970488135 ps
CPU time 78.04 seconds
Started Aug 04 05:13:55 PM PDT 24
Finished Aug 04 05:15:14 PM PDT 24
Peak memory 209660 kb
Host smart-9e89e551-14f9-4078-9f1c-c13f02173db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250581422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1250581422
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2800919377
Short name T727
Test name
Test status
Simulation time 307309318 ps
CPU time 5.71 seconds
Started Aug 04 05:13:42 PM PDT 24
Finished Aug 04 05:13:48 PM PDT 24
Peak memory 208484 kb
Host smart-a5fc1cc0-656a-4459-950d-bf2fad47c397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800919377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2800919377
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1872540617
Short name T552
Test name
Test status
Simulation time 174755415 ps
CPU time 4.86 seconds
Started Aug 04 05:13:46 PM PDT 24
Finished Aug 04 05:13:51 PM PDT 24
Peak memory 208660 kb
Host smart-c1644515-fcd7-41e2-8872-7a0f4e2b1856
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872540617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1872540617
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.407170757
Short name T523
Test name
Test status
Simulation time 2621329371 ps
CPU time 35.76 seconds
Started Aug 04 05:13:42 PM PDT 24
Finished Aug 04 05:14:18 PM PDT 24
Peak memory 208552 kb
Host smart-d702e702-5b74-45c0-bc89-99097b29ab1d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407170757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.407170757
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1183426494
Short name T721
Test name
Test status
Simulation time 565133455 ps
CPU time 17.91 seconds
Started Aug 04 05:13:49 PM PDT 24
Finished Aug 04 05:14:07 PM PDT 24
Peak memory 208228 kb
Host smart-587fce57-11a3-41cd-8cae-90f1132ecde8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183426494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1183426494
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3404319361
Short name T479
Test name
Test status
Simulation time 106404443 ps
CPU time 1.54 seconds
Started Aug 04 05:13:50 PM PDT 24
Finished Aug 04 05:13:51 PM PDT 24
Peak memory 214296 kb
Host smart-99e16030-abfa-4d7c-b815-4e1bedcb9d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404319361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3404319361
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.565594692
Short name T419
Test name
Test status
Simulation time 175899917 ps
CPU time 3.76 seconds
Started Aug 04 05:13:42 PM PDT 24
Finished Aug 04 05:13:46 PM PDT 24
Peak memory 207068 kb
Host smart-04349c2c-6408-4844-abf4-957512df2242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565594692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.565594692
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2598701365
Short name T350
Test name
Test status
Simulation time 5665569180 ps
CPU time 130.91 seconds
Started Aug 04 05:13:49 PM PDT 24
Finished Aug 04 05:16:00 PM PDT 24
Peak memory 222472 kb
Host smart-1e878b71-3862-4d7d-a4bd-b8db883cdc4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598701365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2598701365
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2557931544
Short name T567
Test name
Test status
Simulation time 140031067 ps
CPU time 9.07 seconds
Started Aug 04 05:13:48 PM PDT 24
Finished Aug 04 05:13:57 PM PDT 24
Peak memory 222476 kb
Host smart-6b5eefb4-3cf3-4dde-881e-4b1e91c73d05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557931544 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2557931544
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1837086244
Short name T354
Test name
Test status
Simulation time 758692869 ps
CPU time 9.04 seconds
Started Aug 04 05:13:46 PM PDT 24
Finished Aug 04 05:13:55 PM PDT 24
Peak memory 208856 kb
Host smart-599077ad-f95c-41c1-80fb-7c45dadc543f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837086244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1837086244
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1107029608
Short name T674
Test name
Test status
Simulation time 527079528 ps
CPU time 4.42 seconds
Started Aug 04 05:13:46 PM PDT 24
Finished Aug 04 05:13:51 PM PDT 24
Peak memory 209788 kb
Host smart-3cc7c19c-bf85-4794-a508-8f97ab3985ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107029608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1107029608
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.995096297
Short name T769
Test name
Test status
Simulation time 30039238 ps
CPU time 0.94 seconds
Started Aug 04 05:13:51 PM PDT 24
Finished Aug 04 05:13:52 PM PDT 24
Peak memory 205988 kb
Host smart-be8f4ff3-e0b8-43d8-baaa-34e339ba9d9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995096297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.995096297
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.4011994579
Short name T26
Test name
Test status
Simulation time 531506320 ps
CPU time 2.74 seconds
Started Aug 04 05:13:51 PM PDT 24
Finished Aug 04 05:13:54 PM PDT 24
Peak memory 216832 kb
Host smart-9ee43338-42b1-4df3-b561-584f15443fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011994579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.4011994579
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.781131738
Short name T79
Test name
Test status
Simulation time 175756663 ps
CPU time 2.83 seconds
Started Aug 04 05:13:55 PM PDT 24
Finished Aug 04 05:13:58 PM PDT 24
Peak memory 209252 kb
Host smart-64ce215f-ee14-4251-b3f3-85c5e75eb6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781131738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.781131738
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1564491843
Short name T299
Test name
Test status
Simulation time 62883029 ps
CPU time 1.97 seconds
Started Aug 04 05:13:50 PM PDT 24
Finished Aug 04 05:13:52 PM PDT 24
Peak memory 214240 kb
Host smart-bc375f03-a57f-4978-abf9-1652cc0601e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564491843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1564491843
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3323633447
Short name T646
Test name
Test status
Simulation time 243515322 ps
CPU time 3.62 seconds
Started Aug 04 05:13:55 PM PDT 24
Finished Aug 04 05:13:59 PM PDT 24
Peak memory 214564 kb
Host smart-d925f554-0ea1-4362-b123-9621de2efac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323633447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3323633447
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1479577675
Short name T534
Test name
Test status
Simulation time 1680941703 ps
CPU time 14.29 seconds
Started Aug 04 05:13:55 PM PDT 24
Finished Aug 04 05:14:10 PM PDT 24
Peak memory 220408 kb
Host smart-034bebc5-5395-4934-93fd-564e1b34f45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479577675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1479577675
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.441577503
Short name T403
Test name
Test status
Simulation time 265006324 ps
CPU time 1.91 seconds
Started Aug 04 05:13:47 PM PDT 24
Finished Aug 04 05:13:49 PM PDT 24
Peak memory 206056 kb
Host smart-4d050093-3c46-472c-a50a-af3205c91adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441577503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.441577503
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.963026907
Short name T868
Test name
Test status
Simulation time 219646865 ps
CPU time 4.37 seconds
Started Aug 04 05:13:49 PM PDT 24
Finished Aug 04 05:13:53 PM PDT 24
Peak memory 206888 kb
Host smart-31fd4a07-1cd0-4c10-be18-649c42ad7bd0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963026907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.963026907
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2638214664
Short name T546
Test name
Test status
Simulation time 1519549931 ps
CPU time 15.4 seconds
Started Aug 04 05:13:47 PM PDT 24
Finished Aug 04 05:14:03 PM PDT 24
Peak memory 208524 kb
Host smart-9868e645-fb26-4e93-84c4-f8e520b341f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638214664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2638214664
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.881398340
Short name T513
Test name
Test status
Simulation time 59328759 ps
CPU time 2.99 seconds
Started Aug 04 05:13:52 PM PDT 24
Finished Aug 04 05:13:55 PM PDT 24
Peak memory 209408 kb
Host smart-d4542c59-25e1-4fb2-b3a5-52a299479bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881398340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.881398340
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3048767454
Short name T504
Test name
Test status
Simulation time 371803557 ps
CPU time 2.38 seconds
Started Aug 04 05:13:46 PM PDT 24
Finished Aug 04 05:13:49 PM PDT 24
Peak memory 206952 kb
Host smart-4f04e013-46f4-4235-8c67-31a65b76dab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048767454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3048767454
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3354872604
Short name T665
Test name
Test status
Simulation time 31419209354 ps
CPU time 184.84 seconds
Started Aug 04 05:13:53 PM PDT 24
Finished Aug 04 05:16:58 PM PDT 24
Peak memory 216736 kb
Host smart-bb369866-b5b9-4062-907e-6bee142d6423
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354872604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3354872604
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2282336448
Short name T785
Test name
Test status
Simulation time 1164457707 ps
CPU time 27.78 seconds
Started Aug 04 05:13:48 PM PDT 24
Finished Aug 04 05:14:16 PM PDT 24
Peak memory 214224 kb
Host smart-55782542-7f9b-4c87-b70a-c85893915123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282336448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2282336448
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2558043537
Short name T563
Test name
Test status
Simulation time 26593482 ps
CPU time 1.02 seconds
Started Aug 04 05:13:54 PM PDT 24
Finished Aug 04 05:13:56 PM PDT 24
Peak memory 205992 kb
Host smart-5e087d31-3c13-48c3-b184-41287623aed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558043537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2558043537
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.772352456
Short name T823
Test name
Test status
Simulation time 83698651 ps
CPU time 3.27 seconds
Started Aug 04 05:13:53 PM PDT 24
Finished Aug 04 05:13:56 PM PDT 24
Peak memory 214528 kb
Host smart-aae14cd3-0b1a-42bb-9ee7-015d386b1aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772352456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.772352456
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.524993034
Short name T684
Test name
Test status
Simulation time 196335251 ps
CPU time 2.43 seconds
Started Aug 04 05:13:52 PM PDT 24
Finished Aug 04 05:13:55 PM PDT 24
Peak memory 207836 kb
Host smart-dbaa2879-6255-472a-baba-6c4977938a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524993034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.524993034
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.300248781
Short name T359
Test name
Test status
Simulation time 67189296 ps
CPU time 4.36 seconds
Started Aug 04 05:13:54 PM PDT 24
Finished Aug 04 05:13:59 PM PDT 24
Peak memory 209944 kb
Host smart-121b5708-5225-4b35-96b1-507e54109564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300248781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.300248781
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2063792109
Short name T333
Test name
Test status
Simulation time 233896909 ps
CPU time 4.17 seconds
Started Aug 04 05:13:51 PM PDT 24
Finished Aug 04 05:13:56 PM PDT 24
Peak memory 214320 kb
Host smart-95831780-af4a-4a35-9806-478f289b0fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063792109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2063792109
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1730039924
Short name T34
Test name
Test status
Simulation time 80715975 ps
CPU time 2.26 seconds
Started Aug 04 05:13:52 PM PDT 24
Finished Aug 04 05:13:55 PM PDT 24
Peak memory 206812 kb
Host smart-52ca43d9-b07c-489a-96b8-3579c905210b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730039924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1730039924
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.191390419
Short name T821
Test name
Test status
Simulation time 55319039 ps
CPU time 1.97 seconds
Started Aug 04 05:13:50 PM PDT 24
Finished Aug 04 05:13:52 PM PDT 24
Peak memory 208592 kb
Host smart-47d11d8a-a568-4974-b044-8ee018e47154
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191390419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.191390419
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1246870871
Short name T470
Test name
Test status
Simulation time 116824695 ps
CPU time 4.05 seconds
Started Aug 04 05:13:53 PM PDT 24
Finished Aug 04 05:13:57 PM PDT 24
Peak memory 208740 kb
Host smart-35f521df-bd5d-404f-8cfe-e10935a640a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246870871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1246870871
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2935133282
Short name T542
Test name
Test status
Simulation time 157928177 ps
CPU time 4.44 seconds
Started Aug 04 05:13:51 PM PDT 24
Finished Aug 04 05:13:56 PM PDT 24
Peak memory 208440 kb
Host smart-6f0e090d-614c-49c2-ad14-f3f810fa01ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935133282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2935133282
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1204205643
Short name T475
Test name
Test status
Simulation time 44979486 ps
CPU time 1.72 seconds
Started Aug 04 05:13:52 PM PDT 24
Finished Aug 04 05:13:54 PM PDT 24
Peak memory 215848 kb
Host smart-b5296d02-7665-411e-a1cc-b0f1b2289b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204205643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1204205643
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.374606565
Short name T464
Test name
Test status
Simulation time 435703314 ps
CPU time 7.87 seconds
Started Aug 04 05:13:51 PM PDT 24
Finished Aug 04 05:13:59 PM PDT 24
Peak memory 207824 kb
Host smart-db04f60d-12be-4b2b-be9f-7190a70585f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374606565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.374606565
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2761654923
Short name T385
Test name
Test status
Simulation time 268776371 ps
CPU time 9.78 seconds
Started Aug 04 05:13:52 PM PDT 24
Finished Aug 04 05:14:02 PM PDT 24
Peak memory 219908 kb
Host smart-89cee0c8-e425-4652-898e-77a45dff509f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761654923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2761654923
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.483581409
Short name T130
Test name
Test status
Simulation time 176898443 ps
CPU time 11 seconds
Started Aug 04 05:13:52 PM PDT 24
Finished Aug 04 05:14:03 PM PDT 24
Peak memory 222448 kb
Host smart-0e488300-c7f7-49bb-9fc7-31f0b4f7e7ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483581409 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.483581409
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1562909706
Short name T852
Test name
Test status
Simulation time 3899158499 ps
CPU time 7.96 seconds
Started Aug 04 05:13:52 PM PDT 24
Finished Aug 04 05:14:00 PM PDT 24
Peak memory 214408 kb
Host smart-9a6aeb87-1dcb-446c-9274-db7b81eabc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562909706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1562909706
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.4263053022
Short name T680
Test name
Test status
Simulation time 163731788 ps
CPU time 3.53 seconds
Started Aug 04 05:13:51 PM PDT 24
Finished Aug 04 05:13:54 PM PDT 24
Peak memory 210336 kb
Host smart-c244418d-ba05-407e-a546-ce3c59d0d741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263053022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.4263053022
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2344399958
Short name T752
Test name
Test status
Simulation time 23702573 ps
CPU time 0.86 seconds
Started Aug 04 05:13:57 PM PDT 24
Finished Aug 04 05:13:58 PM PDT 24
Peak memory 205940 kb
Host smart-c603ccae-3d41-4baf-8786-33fc207b1067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344399958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2344399958
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1230673868
Short name T391
Test name
Test status
Simulation time 12147391469 ps
CPU time 34.26 seconds
Started Aug 04 05:13:57 PM PDT 24
Finished Aug 04 05:14:31 PM PDT 24
Peak memory 214640 kb
Host smart-dcd4fec8-24fa-4281-bd75-cf23aa7b6efc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230673868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1230673868
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1953779508
Short name T31
Test name
Test status
Simulation time 175482230 ps
CPU time 4.29 seconds
Started Aug 04 05:13:58 PM PDT 24
Finished Aug 04 05:14:03 PM PDT 24
Peak memory 220184 kb
Host smart-5fe61160-9867-4156-8e03-4f88b69b6415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953779508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1953779508
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.955690199
Short name T608
Test name
Test status
Simulation time 614824027 ps
CPU time 3.58 seconds
Started Aug 04 05:13:58 PM PDT 24
Finished Aug 04 05:14:02 PM PDT 24
Peak memory 214204 kb
Host smart-032b7971-5f2e-4793-9e62-5a62903d522e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955690199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.955690199
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1923762208
Short name T767
Test name
Test status
Simulation time 100005805 ps
CPU time 5.08 seconds
Started Aug 04 05:13:56 PM PDT 24
Finished Aug 04 05:14:02 PM PDT 24
Peak memory 209268 kb
Host smart-5e74efd6-4f66-4057-bb3e-b11c5cd4a8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923762208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1923762208
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.4211343711
Short name T906
Test name
Test status
Simulation time 34222469 ps
CPU time 2.12 seconds
Started Aug 04 05:13:56 PM PDT 24
Finished Aug 04 05:13:58 PM PDT 24
Peak memory 214160 kb
Host smart-0047d99e-28f0-45cc-bfdf-1d838eb11e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211343711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.4211343711
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.4043063319
Short name T771
Test name
Test status
Simulation time 68656700 ps
CPU time 2.05 seconds
Started Aug 04 05:13:58 PM PDT 24
Finished Aug 04 05:14:00 PM PDT 24
Peak memory 214392 kb
Host smart-a8c0f94b-e7d3-4027-a3be-763b958a79ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043063319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.4043063319
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2356658503
Short name T799
Test name
Test status
Simulation time 85788595 ps
CPU time 2.76 seconds
Started Aug 04 05:13:56 PM PDT 24
Finished Aug 04 05:13:58 PM PDT 24
Peak memory 208368 kb
Host smart-101a0ca9-c16d-4abb-9520-d6d62376c180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356658503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2356658503
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1619512789
Short name T617
Test name
Test status
Simulation time 353660377 ps
CPU time 6.74 seconds
Started Aug 04 05:13:53 PM PDT 24
Finished Aug 04 05:14:00 PM PDT 24
Peak memory 208592 kb
Host smart-73c16f0e-f34d-4dd9-ad60-228114bd8e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619512789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1619512789
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.6646335
Short name T215
Test name
Test status
Simulation time 52883049 ps
CPU time 2.56 seconds
Started Aug 04 05:13:53 PM PDT 24
Finished Aug 04 05:13:55 PM PDT 24
Peak memory 207020 kb
Host smart-7bca9b25-1e35-49ad-97a7-adef00b81ae8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6646335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.6646335
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2459358438
Short name T506
Test name
Test status
Simulation time 216712088 ps
CPU time 3.15 seconds
Started Aug 04 05:13:53 PM PDT 24
Finished Aug 04 05:13:57 PM PDT 24
Peak memory 209048 kb
Host smart-b3a8fa16-05ff-4470-ae41-144e56baa31d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459358438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2459358438
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1147485212
Short name T551
Test name
Test status
Simulation time 29560706 ps
CPU time 2.35 seconds
Started Aug 04 05:13:52 PM PDT 24
Finished Aug 04 05:13:54 PM PDT 24
Peak memory 208896 kb
Host smart-1c5a278e-eb26-42a8-b613-eb22bf28ced6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147485212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1147485212
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3306589091
Short name T132
Test name
Test status
Simulation time 78041653 ps
CPU time 2.02 seconds
Started Aug 04 05:13:56 PM PDT 24
Finished Aug 04 05:13:58 PM PDT 24
Peak memory 209548 kb
Host smart-3415cabb-0622-4995-a4e2-494471683c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306589091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3306589091
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.154909768
Short name T142
Test name
Test status
Simulation time 57756299 ps
CPU time 2.24 seconds
Started Aug 04 05:13:50 PM PDT 24
Finished Aug 04 05:13:52 PM PDT 24
Peak memory 206724 kb
Host smart-5d706197-f4cc-44f1-83b4-26cf3fed1745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154909768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.154909768
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2974604265
Short name T581
Test name
Test status
Simulation time 137900424 ps
CPU time 6.76 seconds
Started Aug 04 05:13:57 PM PDT 24
Finished Aug 04 05:14:04 PM PDT 24
Peak memory 208568 kb
Host smart-0333fedd-6fdd-4f8a-bbdb-996f6e6ac0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974604265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2974604265
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3185502885
Short name T113
Test name
Test status
Simulation time 437804011 ps
CPU time 2.4 seconds
Started Aug 04 05:13:56 PM PDT 24
Finished Aug 04 05:13:59 PM PDT 24
Peak memory 209716 kb
Host smart-3b32f801-a986-4662-acc2-65dc05e84e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185502885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3185502885
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3364885342
Short name T804
Test name
Test status
Simulation time 74651487 ps
CPU time 0.81 seconds
Started Aug 04 05:13:58 PM PDT 24
Finished Aug 04 05:13:59 PM PDT 24
Peak memory 205976 kb
Host smart-c5d5f070-20d4-45e2-8324-62a0f4c22a5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364885342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3364885342
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3186185277
Short name T379
Test name
Test status
Simulation time 187211225 ps
CPU time 3.63 seconds
Started Aug 04 05:13:54 PM PDT 24
Finished Aug 04 05:13:58 PM PDT 24
Peak memory 222532 kb
Host smart-09b088cc-7871-4acd-b8b2-81fb4b1259ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186185277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3186185277
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1860682009
Short name T23
Test name
Test status
Simulation time 273069271 ps
CPU time 5.41 seconds
Started Aug 04 05:13:56 PM PDT 24
Finished Aug 04 05:14:02 PM PDT 24
Peak memory 219352 kb
Host smart-88b99f90-94d5-464a-bc3c-3b0c38cc9651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860682009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1860682009
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2105267378
Short name T71
Test name
Test status
Simulation time 81907309 ps
CPU time 2.49 seconds
Started Aug 04 05:13:57 PM PDT 24
Finished Aug 04 05:14:00 PM PDT 24
Peak memory 208528 kb
Host smart-5f7b06da-b505-450e-8ecd-7f7304142e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105267378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2105267378
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3283777871
Short name T844
Test name
Test status
Simulation time 861563726 ps
CPU time 3 seconds
Started Aug 04 05:13:59 PM PDT 24
Finished Aug 04 05:14:02 PM PDT 24
Peak memory 214324 kb
Host smart-33654871-d981-4c6e-8693-8c252393f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283777871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3283777871
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2798936901
Short name T268
Test name
Test status
Simulation time 357654536 ps
CPU time 3.63 seconds
Started Aug 04 05:13:54 PM PDT 24
Finished Aug 04 05:13:58 PM PDT 24
Peak memory 214252 kb
Host smart-da562275-86c6-4e12-ad33-4586cc7b2930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798936901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2798936901
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_random.2057305136
Short name T369
Test name
Test status
Simulation time 138945767 ps
CPU time 5.99 seconds
Started Aug 04 05:13:58 PM PDT 24
Finished Aug 04 05:14:04 PM PDT 24
Peak memory 218080 kb
Host smart-f42fa882-d127-432c-9df2-afbde29ba4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057305136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2057305136
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1961234488
Short name T751
Test name
Test status
Simulation time 310989896 ps
CPU time 2.47 seconds
Started Aug 04 05:13:55 PM PDT 24
Finished Aug 04 05:13:57 PM PDT 24
Peak memory 206952 kb
Host smart-a9c8abe9-7d89-4ecb-b143-c006cd15e68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961234488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1961234488
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.373229768
Short name T558
Test name
Test status
Simulation time 193125651 ps
CPU time 7.58 seconds
Started Aug 04 05:13:55 PM PDT 24
Finished Aug 04 05:14:03 PM PDT 24
Peak memory 208944 kb
Host smart-b14e8613-80be-4a85-b3d0-ff38377140de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373229768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.373229768
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3379257520
Short name T632
Test name
Test status
Simulation time 361561006 ps
CPU time 8.94 seconds
Started Aug 04 05:13:55 PM PDT 24
Finished Aug 04 05:14:04 PM PDT 24
Peak memory 207980 kb
Host smart-777c623e-0a6f-4cd7-be67-fb6d7af8d98c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379257520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3379257520
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.646827996
Short name T688
Test name
Test status
Simulation time 2502013755 ps
CPU time 17.52 seconds
Started Aug 04 05:13:57 PM PDT 24
Finished Aug 04 05:14:15 PM PDT 24
Peak memory 208912 kb
Host smart-61138fc0-3bb6-4e7e-a7d9-f1ea05e6eee3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646827996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.646827996
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2210541007
Short name T507
Test name
Test status
Simulation time 94973646 ps
CPU time 3.3 seconds
Started Aug 04 05:14:00 PM PDT 24
Finished Aug 04 05:14:04 PM PDT 24
Peak memory 214300 kb
Host smart-01bec277-d881-4d48-9b10-2dff1a2e85fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210541007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2210541007
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.799848222
Short name T514
Test name
Test status
Simulation time 1389420842 ps
CPU time 14.17 seconds
Started Aug 04 05:13:57 PM PDT 24
Finished Aug 04 05:14:11 PM PDT 24
Peak memory 206992 kb
Host smart-e04e04ad-aa5f-4ec9-8e5d-044c83034ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799848222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.799848222
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.4024322662
Short name T182
Test name
Test status
Simulation time 463272543 ps
CPU time 16.32 seconds
Started Aug 04 05:14:00 PM PDT 24
Finished Aug 04 05:14:16 PM PDT 24
Peak memory 220564 kb
Host smart-6ca96cda-8577-470b-b386-47fe07dd2416
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024322662 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.4024322662
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3921441738
Short name T825
Test name
Test status
Simulation time 91583860 ps
CPU time 3.8 seconds
Started Aug 04 05:13:55 PM PDT 24
Finished Aug 04 05:13:59 PM PDT 24
Peak memory 214208 kb
Host smart-d94f926f-cca5-45ad-bc8a-b35fd968ae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921441738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3921441738
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2441475231
Short name T452
Test name
Test status
Simulation time 43844771 ps
CPU time 1.97 seconds
Started Aug 04 05:14:00 PM PDT 24
Finished Aug 04 05:14:02 PM PDT 24
Peak memory 210064 kb
Host smart-7f4f06d6-49c2-4b9c-bd23-a57a5f80d5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441475231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2441475231
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3845767493
Short name T560
Test name
Test status
Simulation time 11739249 ps
CPU time 0.82 seconds
Started Aug 04 05:14:06 PM PDT 24
Finished Aug 04 05:14:07 PM PDT 24
Peak memory 205980 kb
Host smart-cf284272-e786-4326-934e-c187d9d49073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845767493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3845767493
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1051334851
Short name T631
Test name
Test status
Simulation time 322254513 ps
CPU time 3.06 seconds
Started Aug 04 05:14:07 PM PDT 24
Finished Aug 04 05:14:10 PM PDT 24
Peak memory 222632 kb
Host smart-8fc2fc89-8258-4b11-ad63-0123ed2e5e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051334851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1051334851
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.982291361
Short name T675
Test name
Test status
Simulation time 304734654 ps
CPU time 4.72 seconds
Started Aug 04 05:13:58 PM PDT 24
Finished Aug 04 05:14:03 PM PDT 24
Peak memory 209096 kb
Host smart-fab5bf4d-2d16-4850-8964-a1cb1f6d7828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982291361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.982291361
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3419792140
Short name T878
Test name
Test status
Simulation time 61609890 ps
CPU time 3.41 seconds
Started Aug 04 05:14:03 PM PDT 24
Finished Aug 04 05:14:06 PM PDT 24
Peak memory 220592 kb
Host smart-b7a82c74-049f-4f6d-bfca-23291f5025b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419792140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3419792140
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1983289628
Short name T222
Test name
Test status
Simulation time 259958886 ps
CPU time 3.41 seconds
Started Aug 04 05:14:00 PM PDT 24
Finished Aug 04 05:14:03 PM PDT 24
Peak memory 220128 kb
Host smart-6730d5bd-7feb-4f5c-940e-e25154c908a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983289628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1983289628
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3446437610
Short name T42
Test name
Test status
Simulation time 42201980 ps
CPU time 2.36 seconds
Started Aug 04 05:14:01 PM PDT 24
Finished Aug 04 05:14:03 PM PDT 24
Peak memory 206876 kb
Host smart-d8b20248-8e43-4750-bc6c-c6747277a5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446437610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3446437610
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1507527461
Short name T912
Test name
Test status
Simulation time 37719955 ps
CPU time 2.46 seconds
Started Aug 04 05:14:01 PM PDT 24
Finished Aug 04 05:14:03 PM PDT 24
Peak memory 208488 kb
Host smart-6171f76c-f39f-40dc-8ce7-f16560a41d72
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507527461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1507527461
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3293366527
Short name T456
Test name
Test status
Simulation time 112361521 ps
CPU time 2.86 seconds
Started Aug 04 05:13:59 PM PDT 24
Finished Aug 04 05:14:02 PM PDT 24
Peak memory 206808 kb
Host smart-786cfbd2-f322-4f1c-941c-edd7e53c2933
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293366527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3293366527
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.818548307
Short name T84
Test name
Test status
Simulation time 111828104 ps
CPU time 3.95 seconds
Started Aug 04 05:14:00 PM PDT 24
Finished Aug 04 05:14:04 PM PDT 24
Peak memory 209084 kb
Host smart-8d0aa71a-a038-4869-8c7c-47cca030e80e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818548307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.818548307
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.543128195
Short name T476
Test name
Test status
Simulation time 87526417 ps
CPU time 2.39 seconds
Started Aug 04 05:14:04 PM PDT 24
Finished Aug 04 05:14:06 PM PDT 24
Peak memory 214268 kb
Host smart-0422c630-b861-4c5d-96c2-40593144abba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543128195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.543128195
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1096789843
Short name T538
Test name
Test status
Simulation time 20884683 ps
CPU time 1.67 seconds
Started Aug 04 05:14:00 PM PDT 24
Finished Aug 04 05:14:02 PM PDT 24
Peak memory 206776 kb
Host smart-c166736b-f387-4c78-b638-1da27b79ec92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096789843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1096789843
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3169457453
Short name T335
Test name
Test status
Simulation time 364960616 ps
CPU time 9.62 seconds
Started Aug 04 05:14:03 PM PDT 24
Finished Aug 04 05:14:13 PM PDT 24
Peak memory 216920 kb
Host smart-95b7345d-4a37-42f0-872e-cfa507fe7cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169457453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3169457453
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.920403588
Short name T910
Test name
Test status
Simulation time 47272594 ps
CPU time 3.04 seconds
Started Aug 04 05:14:01 PM PDT 24
Finished Aug 04 05:14:04 PM PDT 24
Peak memory 207536 kb
Host smart-19e63058-1429-4885-b4fd-66a1be765c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920403588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.920403588
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3129492295
Short name T375
Test name
Test status
Simulation time 214216540 ps
CPU time 3.37 seconds
Started Aug 04 05:14:04 PM PDT 24
Finished Aug 04 05:14:07 PM PDT 24
Peak memory 210296 kb
Host smart-77f5ef56-300b-4d3c-945f-157cc8402e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129492295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3129492295
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.4233011513
Short name T664
Test name
Test status
Simulation time 33039012 ps
CPU time 0.84 seconds
Started Aug 04 05:12:54 PM PDT 24
Finished Aug 04 05:12:55 PM PDT 24
Peak memory 205948 kb
Host smart-b4234644-a3e3-4e4a-b4b6-55e4e6c22879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233011513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.4233011513
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2504766293
Short name T82
Test name
Test status
Simulation time 40114353 ps
CPU time 2.58 seconds
Started Aug 04 05:12:49 PM PDT 24
Finished Aug 04 05:12:52 PM PDT 24
Peak memory 219880 kb
Host smart-8366f92f-abe3-43af-ba8c-f8141570892d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504766293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2504766293
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3626171671
Short name T831
Test name
Test status
Simulation time 59729121 ps
CPU time 2.41 seconds
Started Aug 04 05:12:53 PM PDT 24
Finished Aug 04 05:12:56 PM PDT 24
Peak memory 214148 kb
Host smart-fb54a1f2-b945-46c2-8219-9a6b3d0a69c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626171671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3626171671
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2687670450
Short name T63
Test name
Test status
Simulation time 588425085 ps
CPU time 8.51 seconds
Started Aug 04 05:12:49 PM PDT 24
Finished Aug 04 05:12:58 PM PDT 24
Peak memory 209688 kb
Host smart-41d20bcd-9f66-4fec-b691-f16fbe4c377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687670450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2687670450
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3141449949
Short name T276
Test name
Test status
Simulation time 89412531 ps
CPU time 4.22 seconds
Started Aug 04 05:12:48 PM PDT 24
Finished Aug 04 05:12:53 PM PDT 24
Peak memory 219080 kb
Host smart-b34800ba-1af5-483b-a025-ccd7441f4616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141449949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3141449949
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.838681843
Short name T14
Test name
Test status
Simulation time 401151001 ps
CPU time 10.15 seconds
Started Aug 04 05:12:52 PM PDT 24
Finished Aug 04 05:13:03 PM PDT 24
Peak memory 229520 kb
Host smart-b589fdee-812e-4035-8d2a-2a7142795a54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838681843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.838681843
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3400179904
Short name T659
Test name
Test status
Simulation time 2474670663 ps
CPU time 13.3 seconds
Started Aug 04 05:12:48 PM PDT 24
Finished Aug 04 05:13:02 PM PDT 24
Peak memory 208344 kb
Host smart-bd32f6df-4896-49f6-a184-3becf4791596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400179904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3400179904
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2883023595
Short name T44
Test name
Test status
Simulation time 104438201 ps
CPU time 4.49 seconds
Started Aug 04 05:12:48 PM PDT 24
Finished Aug 04 05:12:53 PM PDT 24
Peak memory 208644 kb
Host smart-05838ca6-a08b-48e7-af16-24d165897cf8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883023595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2883023595
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.755907081
Short name T722
Test name
Test status
Simulation time 177538482 ps
CPU time 5.3 seconds
Started Aug 04 05:12:49 PM PDT 24
Finished Aug 04 05:12:55 PM PDT 24
Peak memory 207688 kb
Host smart-2738d1df-9d85-4655-921a-cff2023878a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755907081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.755907081
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2282543599
Short name T557
Test name
Test status
Simulation time 488376401 ps
CPU time 16 seconds
Started Aug 04 05:12:50 PM PDT 24
Finished Aug 04 05:13:06 PM PDT 24
Peak memory 208044 kb
Host smart-f81883bf-af15-41ff-997e-9f75ede82656
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282543599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2282543599
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.164817966
Short name T761
Test name
Test status
Simulation time 326163256 ps
CPU time 4.23 seconds
Started Aug 04 05:12:49 PM PDT 24
Finished Aug 04 05:12:53 PM PDT 24
Peak memory 208980 kb
Host smart-6a01155c-df34-422d-9209-776cbc620c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164817966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.164817966
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.777109501
Short name T827
Test name
Test status
Simulation time 639312960 ps
CPU time 5.86 seconds
Started Aug 04 05:12:50 PM PDT 24
Finished Aug 04 05:12:56 PM PDT 24
Peak memory 207960 kb
Host smart-731eac46-5545-4ab2-b371-db64674df867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777109501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.777109501
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.679768727
Short name T81
Test name
Test status
Simulation time 1206314723 ps
CPU time 22.77 seconds
Started Aug 04 05:12:52 PM PDT 24
Finished Aug 04 05:13:15 PM PDT 24
Peak memory 222352 kb
Host smart-925a4e67-0c85-4131-b4f7-a427998d5257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679768727 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.679768727
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2291627612
Short name T209
Test name
Test status
Simulation time 121592886 ps
CPU time 5.31 seconds
Started Aug 04 05:12:49 PM PDT 24
Finished Aug 04 05:12:55 PM PDT 24
Peak memory 209900 kb
Host smart-c1e72d5d-e175-4001-b216-ed9babaa7c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291627612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2291627612
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.4206928866
Short name T166
Test name
Test status
Simulation time 66127104 ps
CPU time 1.44 seconds
Started Aug 04 05:12:49 PM PDT 24
Finished Aug 04 05:12:51 PM PDT 24
Peak memory 209720 kb
Host smart-ca91d1e3-069e-4ae3-b978-5c86ee6fd49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206928866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.4206928866
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3425393370
Short name T839
Test name
Test status
Simulation time 14116069 ps
CPU time 0.79 seconds
Started Aug 04 05:14:09 PM PDT 24
Finished Aug 04 05:14:10 PM PDT 24
Peak memory 205808 kb
Host smart-95b4b3f8-b2c8-4d88-ad13-3021f74c37ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425393370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3425393370
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3167734122
Short name T540
Test name
Test status
Simulation time 92624267 ps
CPU time 2.42 seconds
Started Aug 04 05:14:11 PM PDT 24
Finished Aug 04 05:14:14 PM PDT 24
Peak memory 222780 kb
Host smart-ba721dfd-e91c-44c7-b9e0-0f77a4323656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167734122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3167734122
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3071333044
Short name T73
Test name
Test status
Simulation time 337962011 ps
CPU time 8.4 seconds
Started Aug 04 05:14:02 PM PDT 24
Finished Aug 04 05:14:11 PM PDT 24
Peak memory 210272 kb
Host smart-697e3e27-1cb7-48f2-8a73-710ef336e052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071333044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3071333044
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2438303851
Short name T700
Test name
Test status
Simulation time 218152090 ps
CPU time 2.25 seconds
Started Aug 04 05:14:10 PM PDT 24
Finished Aug 04 05:14:12 PM PDT 24
Peak memory 214292 kb
Host smart-937a8d2f-75ce-49a5-8394-b0b76e82efe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438303851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2438303851
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3940558277
Short name T52
Test name
Test status
Simulation time 264778554 ps
CPU time 2.89 seconds
Started Aug 04 05:14:05 PM PDT 24
Finished Aug 04 05:14:08 PM PDT 24
Peak memory 219828 kb
Host smart-2cb43deb-5a1d-4d50-bca8-f6469734cb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940558277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3940558277
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1204279020
Short name T497
Test name
Test status
Simulation time 440171250 ps
CPU time 5.46 seconds
Started Aug 04 05:14:04 PM PDT 24
Finished Aug 04 05:14:10 PM PDT 24
Peak memory 207744 kb
Host smart-00061bc3-0b63-4e08-a517-69dd9310277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204279020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1204279020
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1847002477
Short name T214
Test name
Test status
Simulation time 59576652 ps
CPU time 2.98 seconds
Started Aug 04 05:14:04 PM PDT 24
Finished Aug 04 05:14:08 PM PDT 24
Peak memory 208492 kb
Host smart-c9962edc-6cd6-491b-8b3c-e2ded3463b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847002477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1847002477
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.4086395287
Short name T510
Test name
Test status
Simulation time 201187485 ps
CPU time 2.68 seconds
Started Aug 04 05:14:04 PM PDT 24
Finished Aug 04 05:14:07 PM PDT 24
Peak memory 207100 kb
Host smart-319bec96-6976-42a8-81d1-738d58095847
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086395287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.4086395287
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1350908952
Short name T480
Test name
Test status
Simulation time 212132876 ps
CPU time 5.65 seconds
Started Aug 04 05:14:04 PM PDT 24
Finished Aug 04 05:14:10 PM PDT 24
Peak memory 208864 kb
Host smart-67badc48-66e9-4de4-ad69-16e5d7bb9e9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350908952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1350908952
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2919929695
Short name T255
Test name
Test status
Simulation time 429883662 ps
CPU time 7.43 seconds
Started Aug 04 05:14:04 PM PDT 24
Finished Aug 04 05:14:11 PM PDT 24
Peak memory 208936 kb
Host smart-a23e2967-33ad-4222-ab20-4969b6173556
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919929695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2919929695
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1245986270
Short name T246
Test name
Test status
Simulation time 96187655 ps
CPU time 2.57 seconds
Started Aug 04 05:14:12 PM PDT 24
Finished Aug 04 05:14:15 PM PDT 24
Peak memory 208704 kb
Host smart-41cc906a-fc48-40da-a105-3497227c0909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245986270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1245986270
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2035169124
Short name T668
Test name
Test status
Simulation time 75216234 ps
CPU time 2.16 seconds
Started Aug 04 05:14:06 PM PDT 24
Finished Aug 04 05:14:08 PM PDT 24
Peak memory 208200 kb
Host smart-1fdb5955-cc9f-418d-8a1a-4cd32bc02a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035169124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2035169124
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1742510663
Short name T280
Test name
Test status
Simulation time 4368119715 ps
CPU time 41.98 seconds
Started Aug 04 05:14:12 PM PDT 24
Finished Aug 04 05:14:55 PM PDT 24
Peak memory 222424 kb
Host smart-ed1dc3f4-db00-4f6f-acea-0e0b68937b89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742510663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1742510663
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2537171200
Short name T559
Test name
Test status
Simulation time 459008362 ps
CPU time 4.22 seconds
Started Aug 04 05:14:06 PM PDT 24
Finished Aug 04 05:14:11 PM PDT 24
Peak memory 207304 kb
Host smart-818b2774-7f51-4907-a057-3550397b8525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537171200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2537171200
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2972927293
Short name T39
Test name
Test status
Simulation time 97792315 ps
CPU time 2.22 seconds
Started Aug 04 05:14:08 PM PDT 24
Finished Aug 04 05:14:11 PM PDT 24
Peak memory 210004 kb
Host smart-d5644636-3691-4f82-b84e-d420b55b4569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972927293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2972927293
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3162319166
Short name T780
Test name
Test status
Simulation time 24491677 ps
CPU time 0.72 seconds
Started Aug 04 05:14:14 PM PDT 24
Finished Aug 04 05:14:15 PM PDT 24
Peak memory 205980 kb
Host smart-bbdd33c4-e493-4073-84e9-12dc54cf2b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162319166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3162319166
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3125275176
Short name T394
Test name
Test status
Simulation time 176926541 ps
CPU time 5.02 seconds
Started Aug 04 05:14:07 PM PDT 24
Finished Aug 04 05:14:12 PM PDT 24
Peak memory 214216 kb
Host smart-bb54e913-f405-4c7f-9a59-4446d254badc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125275176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3125275176
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1701787849
Short name T382
Test name
Test status
Simulation time 35231627 ps
CPU time 1.88 seconds
Started Aug 04 05:14:12 PM PDT 24
Finished Aug 04 05:14:14 PM PDT 24
Peak memory 209076 kb
Host smart-d1026a2c-8a9f-4783-8632-bfe919095501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701787849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1701787849
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.900562323
Short name T545
Test name
Test status
Simulation time 54386637 ps
CPU time 2.06 seconds
Started Aug 04 05:14:16 PM PDT 24
Finished Aug 04 05:14:18 PM PDT 24
Peak memory 209244 kb
Host smart-087a3cfc-48fc-406e-b90e-138f7f4c3875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900562323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.900562323
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1375669425
Short name T826
Test name
Test status
Simulation time 183773490 ps
CPU time 5.85 seconds
Started Aug 04 05:14:08 PM PDT 24
Finished Aug 04 05:14:14 PM PDT 24
Peak memory 214300 kb
Host smart-0cda476c-8fec-48fc-967e-24adfa35e02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375669425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1375669425
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1288250516
Short name T724
Test name
Test status
Simulation time 142482914 ps
CPU time 4.36 seconds
Started Aug 04 05:14:15 PM PDT 24
Finished Aug 04 05:14:20 PM PDT 24
Peak memory 220084 kb
Host smart-02ef5f13-b58d-46a8-98bf-f28befd8d109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288250516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1288250516
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.55399124
Short name T600
Test name
Test status
Simulation time 360010488 ps
CPU time 4.88 seconds
Started Aug 04 05:14:07 PM PDT 24
Finished Aug 04 05:14:12 PM PDT 24
Peak memory 209644 kb
Host smart-4eb7ffd3-6302-4833-b12c-37e8dc8b1d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55399124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.55399124
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3634136446
Short name T438
Test name
Test status
Simulation time 166434291 ps
CPU time 4.86 seconds
Started Aug 04 05:14:13 PM PDT 24
Finished Aug 04 05:14:18 PM PDT 24
Peak memory 207804 kb
Host smart-46f4c07d-76db-4d1b-a247-06cbdc644cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634136446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3634136446
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2347270574
Short name T861
Test name
Test status
Simulation time 126358136 ps
CPU time 3.28 seconds
Started Aug 04 05:14:14 PM PDT 24
Finished Aug 04 05:14:17 PM PDT 24
Peak memory 206872 kb
Host smart-398a8260-11c0-45df-985b-c093c0ad707e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347270574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2347270574
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2952084118
Short name T607
Test name
Test status
Simulation time 1618631931 ps
CPU time 18.63 seconds
Started Aug 04 05:14:13 PM PDT 24
Finished Aug 04 05:14:31 PM PDT 24
Peak memory 209024 kb
Host smart-3ac24020-03be-44f1-8bfc-32b3b536d8be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952084118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2952084118
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3910324044
Short name T574
Test name
Test status
Simulation time 103549525 ps
CPU time 3.53 seconds
Started Aug 04 05:14:09 PM PDT 24
Finished Aug 04 05:14:13 PM PDT 24
Peak memory 206704 kb
Host smart-7add7766-2c57-40e9-a920-7a2bc58c4172
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910324044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3910324044
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2686596512
Short name T308
Test name
Test status
Simulation time 49410335 ps
CPU time 1.79 seconds
Started Aug 04 05:14:13 PM PDT 24
Finished Aug 04 05:14:15 PM PDT 24
Peak memory 207000 kb
Host smart-a6860281-6a77-470c-bb7f-14f9902283c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686596512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2686596512
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.220414945
Short name T658
Test name
Test status
Simulation time 127067855 ps
CPU time 3.5 seconds
Started Aug 04 05:14:09 PM PDT 24
Finished Aug 04 05:14:12 PM PDT 24
Peak memory 208520 kb
Host smart-afb6876f-77c2-4357-a805-33b6bb6133b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220414945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.220414945
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1834198976
Short name T278
Test name
Test status
Simulation time 62596054 ps
CPU time 2.26 seconds
Started Aug 04 05:14:15 PM PDT 24
Finished Aug 04 05:14:17 PM PDT 24
Peak memory 207596 kb
Host smart-129511e0-8a58-428d-9573-d0f4f78ba754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834198976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1834198976
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2962720576
Short name T743
Test name
Test status
Simulation time 129516560 ps
CPU time 4.3 seconds
Started Aug 04 05:14:12 PM PDT 24
Finished Aug 04 05:14:16 PM PDT 24
Peak memory 207980 kb
Host smart-7858b170-accb-4643-aaed-f01f5ca9a2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962720576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2962720576
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2465918763
Short name T443
Test name
Test status
Simulation time 2855324062 ps
CPU time 16.22 seconds
Started Aug 04 05:14:12 PM PDT 24
Finished Aug 04 05:14:29 PM PDT 24
Peak memory 211040 kb
Host smart-c98849a8-fd13-4bd6-849a-e8a09b22deee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465918763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2465918763
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3192686818
Short name T409
Test name
Test status
Simulation time 58532354 ps
CPU time 0.78 seconds
Started Aug 04 05:14:11 PM PDT 24
Finished Aug 04 05:14:12 PM PDT 24
Peak memory 205852 kb
Host smart-43d02e79-742d-4225-9ec0-f17013e98398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192686818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3192686818
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2276820837
Short name T828
Test name
Test status
Simulation time 34441468 ps
CPU time 2.43 seconds
Started Aug 04 05:14:13 PM PDT 24
Finished Aug 04 05:14:15 PM PDT 24
Peak memory 214768 kb
Host smart-df5271a2-2c3c-498e-985e-b3542500fc50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2276820837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2276820837
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2098691192
Short name T854
Test name
Test status
Simulation time 2037566342 ps
CPU time 11.59 seconds
Started Aug 04 05:14:15 PM PDT 24
Finished Aug 04 05:14:26 PM PDT 24
Peak memory 210120 kb
Host smart-2fa23ff0-2dc4-47d0-843d-f0c33cedb2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098691192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2098691192
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3602169538
Short name T573
Test name
Test status
Simulation time 25901220 ps
CPU time 1.97 seconds
Started Aug 04 05:14:15 PM PDT 24
Finished Aug 04 05:14:17 PM PDT 24
Peak memory 218336 kb
Host smart-d30882c5-5359-4962-83ee-a55136f92def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602169538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3602169538
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.4001693183
Short name T367
Test name
Test status
Simulation time 143971331 ps
CPU time 3.21 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:20 PM PDT 24
Peak memory 219692 kb
Host smart-1569eb1b-3736-4943-936b-3d28325610c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001693183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.4001693183
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1155657725
Short name T502
Test name
Test status
Simulation time 34960539 ps
CPU time 2.4 seconds
Started Aug 04 05:14:16 PM PDT 24
Finished Aug 04 05:14:18 PM PDT 24
Peak memory 218656 kb
Host smart-6546f92a-5217-43b5-9b45-405cf491d315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155657725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1155657725
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2850768363
Short name T881
Test name
Test status
Simulation time 1441477069 ps
CPU time 27.38 seconds
Started Aug 04 05:14:16 PM PDT 24
Finished Aug 04 05:14:44 PM PDT 24
Peak memory 214384 kb
Host smart-5fc1ee7d-5d94-44d9-a3b4-3cda2c08a0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850768363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2850768363
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.287000450
Short name T677
Test name
Test status
Simulation time 385382028 ps
CPU time 11.84 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:29 PM PDT 24
Peak memory 208152 kb
Host smart-12f590b0-c1d8-4663-b947-5d0d4183f09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287000450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.287000450
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1997152970
Short name T292
Test name
Test status
Simulation time 2759378049 ps
CPU time 17.19 seconds
Started Aug 04 05:14:14 PM PDT 24
Finished Aug 04 05:14:31 PM PDT 24
Peak memory 208444 kb
Host smart-2bf06ff3-bf58-48ae-8bde-ecdc118fa710
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997152970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1997152970
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3411485153
Short name T770
Test name
Test status
Simulation time 63346829 ps
CPU time 3.17 seconds
Started Aug 04 05:14:13 PM PDT 24
Finished Aug 04 05:14:16 PM PDT 24
Peak memory 208716 kb
Host smart-909c6809-1cd7-4e95-a897-2f8867add43b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411485153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3411485153
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2221588230
Short name T717
Test name
Test status
Simulation time 543950495 ps
CPU time 4.33 seconds
Started Aug 04 05:14:16 PM PDT 24
Finished Aug 04 05:14:21 PM PDT 24
Peak memory 207876 kb
Host smart-fde56c93-f01d-4d2c-b827-794aa2c9d3fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221588230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2221588230
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.216059049
Short name T263
Test name
Test status
Simulation time 27187070 ps
CPU time 1.6 seconds
Started Aug 04 05:14:15 PM PDT 24
Finished Aug 04 05:14:17 PM PDT 24
Peak memory 208132 kb
Host smart-631bad19-a73b-41e0-95d8-a2ba388b5343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216059049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.216059049
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.224255827
Short name T472
Test name
Test status
Simulation time 1392248308 ps
CPU time 7.2 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:24 PM PDT 24
Peak memory 208780 kb
Host smart-a0a55860-fa9c-4f68-89c6-ae777ec5f230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224255827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.224255827
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3044636504
Short name T595
Test name
Test status
Simulation time 1351792767 ps
CPU time 53.62 seconds
Started Aug 04 05:14:18 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 220908 kb
Host smart-b243ded1-2b45-49fd-9c7c-054646615759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044636504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3044636504
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1228103392
Short name T139
Test name
Test status
Simulation time 70912570 ps
CPU time 3.85 seconds
Started Aug 04 05:14:16 PM PDT 24
Finished Aug 04 05:14:20 PM PDT 24
Peak memory 209916 kb
Host smart-cf236ffe-b9c7-4999-9f1a-0e996f74f953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228103392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1228103392
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4124794564
Short name T880
Test name
Test status
Simulation time 142275910 ps
CPU time 1.99 seconds
Started Aug 04 05:14:15 PM PDT 24
Finished Aug 04 05:14:17 PM PDT 24
Peak memory 210116 kb
Host smart-41d29eff-139e-410c-b1b4-3f54ec467965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124794564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4124794564
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3992194912
Short name T766
Test name
Test status
Simulation time 13262135 ps
CPU time 0.85 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:18 PM PDT 24
Peak memory 205920 kb
Host smart-6dcdbaf2-78a1-4033-9708-d2314f1a7a46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992194912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3992194912
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2859363532
Short name T7
Test name
Test status
Simulation time 51716694 ps
CPU time 2.45 seconds
Started Aug 04 05:14:14 PM PDT 24
Finished Aug 04 05:14:16 PM PDT 24
Peak memory 208928 kb
Host smart-94932873-00b5-492c-8aaf-bbd3a670befc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859363532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2859363532
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3394057032
Short name T94
Test name
Test status
Simulation time 208217884 ps
CPU time 7.73 seconds
Started Aug 04 05:14:16 PM PDT 24
Finished Aug 04 05:14:23 PM PDT 24
Peak memory 214324 kb
Host smart-ec38b396-3428-4097-a049-ce6ea8598e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394057032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3394057032
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1520530911
Short name T316
Test name
Test status
Simulation time 258204840 ps
CPU time 3.39 seconds
Started Aug 04 05:14:12 PM PDT 24
Finished Aug 04 05:14:15 PM PDT 24
Peak memory 214172 kb
Host smart-85f3ea69-fea4-4ce9-a7f1-aaf8440b273a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520530911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1520530911
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2274029998
Short name T553
Test name
Test status
Simulation time 373071619 ps
CPU time 4.84 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:21 PM PDT 24
Peak memory 210584 kb
Host smart-2341cd94-dca8-4439-942e-f922112950e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274029998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2274029998
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3959517340
Short name T273
Test name
Test status
Simulation time 1277780588 ps
CPU time 9.84 seconds
Started Aug 04 05:14:10 PM PDT 24
Finished Aug 04 05:14:20 PM PDT 24
Peak memory 214328 kb
Host smart-bb8d45f2-3cb5-4d63-9406-510c8f376b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959517340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3959517340
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1393749952
Short name T670
Test name
Test status
Simulation time 285631389 ps
CPU time 3.3 seconds
Started Aug 04 05:14:16 PM PDT 24
Finished Aug 04 05:14:19 PM PDT 24
Peak memory 208556 kb
Host smart-542ac5f1-6d1f-4bd9-b821-90a94d066764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393749952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1393749952
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2935352622
Short name T433
Test name
Test status
Simulation time 595945096 ps
CPU time 14.41 seconds
Started Aug 04 05:14:12 PM PDT 24
Finished Aug 04 05:14:27 PM PDT 24
Peak memory 208048 kb
Host smart-f82e96c0-caa6-46db-b596-549bd86b2d79
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935352622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2935352622
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2152750016
Short name T216
Test name
Test status
Simulation time 701640055 ps
CPU time 18.93 seconds
Started Aug 04 05:14:18 PM PDT 24
Finished Aug 04 05:14:37 PM PDT 24
Peak memory 208204 kb
Host smart-38d39520-614b-4d1a-b664-f45b034f4dfc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152750016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2152750016
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3261769162
Short name T620
Test name
Test status
Simulation time 5856709467 ps
CPU time 62.31 seconds
Started Aug 04 05:14:13 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 208576 kb
Host smart-4106396f-8813-4b3e-a4ac-949180b86390
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261769162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3261769162
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.946394706
Short name T529
Test name
Test status
Simulation time 1071803469 ps
CPU time 6.07 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:23 PM PDT 24
Peak memory 209380 kb
Host smart-741ba421-5724-4e4a-b35c-2eab030d5c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946394706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.946394706
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3314823746
Short name T481
Test name
Test status
Simulation time 203121813 ps
CPU time 2.01 seconds
Started Aug 04 05:14:15 PM PDT 24
Finished Aug 04 05:14:17 PM PDT 24
Peak memory 206760 kb
Host smart-f6929623-535a-4aab-a05a-5d90f3473d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314823746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3314823746
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1338450727
Short name T188
Test name
Test status
Simulation time 755849267 ps
CPU time 6.94 seconds
Started Aug 04 05:14:15 PM PDT 24
Finished Aug 04 05:14:22 PM PDT 24
Peak memory 218540 kb
Host smart-bf9f2059-2973-4851-b654-ddec8512d513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338450727 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1338450727
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.661777021
Short name T741
Test name
Test status
Simulation time 116522610 ps
CPU time 5.03 seconds
Started Aug 04 05:14:18 PM PDT 24
Finished Aug 04 05:14:23 PM PDT 24
Peak memory 207160 kb
Host smart-6d05c232-f5e6-40a0-b184-874f2f900e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661777021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.661777021
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3375121624
Short name T641
Test name
Test status
Simulation time 162376900 ps
CPU time 2.24 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:20 PM PDT 24
Peak memory 209964 kb
Host smart-454d5964-22d4-4beb-b29a-3d1150f5c415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375121624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3375121624
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.853341448
Short name T764
Test name
Test status
Simulation time 11576417 ps
CPU time 0.87 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:18 PM PDT 24
Peak memory 205860 kb
Host smart-46ae5a80-7f07-47f2-9766-a4976322fcea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853341448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.853341448
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.143729854
Short name T11
Test name
Test status
Simulation time 96902059 ps
CPU time 4.46 seconds
Started Aug 04 05:14:21 PM PDT 24
Finished Aug 04 05:14:25 PM PDT 24
Peak memory 216092 kb
Host smart-6790ffde-a5b3-49b2-9b0b-8e8dd936b362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143729854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.143729854
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1053126254
Short name T1
Test name
Test status
Simulation time 447391013 ps
CPU time 9.91 seconds
Started Aug 04 05:14:16 PM PDT 24
Finished Aug 04 05:14:26 PM PDT 24
Peak memory 208392 kb
Host smart-efbb5408-473f-412f-91c6-fc9101a1e0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053126254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1053126254
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3855753670
Short name T547
Test name
Test status
Simulation time 354577204 ps
CPU time 4.06 seconds
Started Aug 04 05:14:18 PM PDT 24
Finished Aug 04 05:14:22 PM PDT 24
Peak memory 214312 kb
Host smart-40bfb454-d2cc-4db8-b409-376333e7f6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855753670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3855753670
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1097669336
Short name T373
Test name
Test status
Simulation time 389153266 ps
CPU time 3.65 seconds
Started Aug 04 05:14:16 PM PDT 24
Finished Aug 04 05:14:20 PM PDT 24
Peak memory 214288 kb
Host smart-1986dc33-a6eb-4a59-9ac0-7a0d5a2adf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097669336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1097669336
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1580929220
Short name T711
Test name
Test status
Simulation time 236021996 ps
CPU time 4.94 seconds
Started Aug 04 05:14:15 PM PDT 24
Finished Aug 04 05:14:20 PM PDT 24
Peak memory 220564 kb
Host smart-0edf587e-0186-4e10-ad77-f47bc9121954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580929220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1580929220
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1572698246
Short name T320
Test name
Test status
Simulation time 175787511 ps
CPU time 6.4 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:23 PM PDT 24
Peak memory 214216 kb
Host smart-4fbb399d-af5c-4fc3-a7bc-b4fe090a188d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572698246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1572698246
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.315237360
Short name T703
Test name
Test status
Simulation time 357385900 ps
CPU time 5.08 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:22 PM PDT 24
Peak memory 207876 kb
Host smart-f510f832-3a30-4558-8fed-1bfd5204cb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315237360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.315237360
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2945822444
Short name T653
Test name
Test status
Simulation time 64292579 ps
CPU time 3.26 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:21 PM PDT 24
Peak memory 208656 kb
Host smart-8456cb63-adb9-4796-9910-ecd4775e65d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945822444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2945822444
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.792342480
Short name T671
Test name
Test status
Simulation time 54148159 ps
CPU time 2.22 seconds
Started Aug 04 05:14:18 PM PDT 24
Finished Aug 04 05:14:20 PM PDT 24
Peak memory 208792 kb
Host smart-2c0187f3-955f-41be-9353-094a957b338c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792342480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.792342480
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2268957761
Short name T330
Test name
Test status
Simulation time 104097704 ps
CPU time 3.22 seconds
Started Aug 04 05:14:19 PM PDT 24
Finished Aug 04 05:14:22 PM PDT 24
Peak memory 207120 kb
Host smart-8c7c826e-9556-4840-b7d7-a16cea0aecfb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268957761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2268957761
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1074215561
Short name T702
Test name
Test status
Simulation time 56497971 ps
CPU time 1.96 seconds
Started Aug 04 05:14:20 PM PDT 24
Finished Aug 04 05:14:22 PM PDT 24
Peak memory 208032 kb
Host smart-1163607b-6dc2-4ebf-a883-d673c97276e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074215561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1074215561
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2734160520
Short name T698
Test name
Test status
Simulation time 53366928 ps
CPU time 2.22 seconds
Started Aug 04 05:14:16 PM PDT 24
Finished Aug 04 05:14:18 PM PDT 24
Peak memory 206924 kb
Host smart-aec52d2b-60c1-42a6-8250-7ff236360f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734160520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2734160520
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2059650961
Short name T76
Test name
Test status
Simulation time 171602158 ps
CPU time 11.99 seconds
Started Aug 04 05:14:16 PM PDT 24
Finished Aug 04 05:14:28 PM PDT 24
Peak memory 222680 kb
Host smart-3ea1af71-5a8e-4f7a-b6f1-0efa63e7bd59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059650961 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2059650961
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2678052888
Short name T603
Test name
Test status
Simulation time 1055030960 ps
CPU time 28.35 seconds
Started Aug 04 05:14:15 PM PDT 24
Finished Aug 04 05:14:44 PM PDT 24
Peak memory 208612 kb
Host smart-6b031ff0-0e53-44cb-aa3a-3892821af802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678052888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2678052888
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.821073265
Short name T628
Test name
Test status
Simulation time 84896609 ps
CPU time 2.23 seconds
Started Aug 04 05:14:16 PM PDT 24
Finished Aug 04 05:14:19 PM PDT 24
Peak memory 209848 kb
Host smart-c4765ecc-16eb-43cf-aa02-5baae1999d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821073265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.821073265
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3011719062
Short name T637
Test name
Test status
Simulation time 52449694 ps
CPU time 0.82 seconds
Started Aug 04 05:14:19 PM PDT 24
Finished Aug 04 05:14:20 PM PDT 24
Peak memory 205808 kb
Host smart-30f8a94a-e517-4b51-8326-729dc04591a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011719062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3011719062
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3235165602
Short name T390
Test name
Test status
Simulation time 305947054 ps
CPU time 4.83 seconds
Started Aug 04 05:14:22 PM PDT 24
Finished Aug 04 05:14:27 PM PDT 24
Peak memory 215116 kb
Host smart-7f0a2f12-65cb-4081-88ee-49fc1f44094d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235165602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3235165602
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.329665368
Short name T20
Test name
Test status
Simulation time 88995130 ps
CPU time 3.25 seconds
Started Aug 04 05:14:20 PM PDT 24
Finished Aug 04 05:14:24 PM PDT 24
Peak memory 222668 kb
Host smart-882dde6e-eb65-4905-b027-66ac9f71b2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329665368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.329665368
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2283219397
Short name T907
Test name
Test status
Simulation time 73391714 ps
CPU time 2.82 seconds
Started Aug 04 05:14:20 PM PDT 24
Finished Aug 04 05:14:23 PM PDT 24
Peak memory 207564 kb
Host smart-05954f16-28e5-4161-af05-a9db2e1c56de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283219397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2283219397
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2600246449
Short name T195
Test name
Test status
Simulation time 240807284 ps
CPU time 3.84 seconds
Started Aug 04 05:14:22 PM PDT 24
Finished Aug 04 05:14:26 PM PDT 24
Peak memory 209268 kb
Host smart-be990cbc-381b-43b5-9199-7a5f9b767907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600246449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2600246449
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.217921073
Short name T194
Test name
Test status
Simulation time 54953238 ps
CPU time 3.03 seconds
Started Aug 04 05:14:21 PM PDT 24
Finished Aug 04 05:14:25 PM PDT 24
Peak memory 222480 kb
Host smart-5b95351f-d1bc-48a4-a0c2-a86f272b5f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217921073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.217921073
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.279737646
Short name T849
Test name
Test status
Simulation time 83484295 ps
CPU time 2.67 seconds
Started Aug 04 05:14:21 PM PDT 24
Finished Aug 04 05:14:24 PM PDT 24
Peak memory 214236 kb
Host smart-5dab5244-0142-41ba-9206-325212a53580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279737646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.279737646
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2271638293
Short name T772
Test name
Test status
Simulation time 273261273 ps
CPU time 3.23 seconds
Started Aug 04 05:14:21 PM PDT 24
Finished Aug 04 05:14:24 PM PDT 24
Peak memory 208860 kb
Host smart-38e5072e-579f-4f9b-957d-4d59053c03f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271638293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2271638293
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2457859838
Short name T327
Test name
Test status
Simulation time 124970696 ps
CPU time 3.87 seconds
Started Aug 04 05:14:17 PM PDT 24
Finished Aug 04 05:14:21 PM PDT 24
Peak memory 206992 kb
Host smart-f5edc971-4bf8-4062-8ce2-b6cec935d552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457859838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2457859838
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2012498968
Short name T705
Test name
Test status
Simulation time 345986425 ps
CPU time 3.42 seconds
Started Aug 04 05:14:22 PM PDT 24
Finished Aug 04 05:14:26 PM PDT 24
Peak memory 206920 kb
Host smart-fb612864-a0e0-408c-b4bf-9de20477b7cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012498968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2012498968
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3820335223
Short name T622
Test name
Test status
Simulation time 1413219710 ps
CPU time 5.47 seconds
Started Aug 04 05:14:20 PM PDT 24
Finished Aug 04 05:14:26 PM PDT 24
Peak memory 207064 kb
Host smart-91a858e1-bcab-4ec6-beb2-79b5b5e30dad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820335223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3820335223
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2590960028
Short name T466
Test name
Test status
Simulation time 758859355 ps
CPU time 8.48 seconds
Started Aug 04 05:14:22 PM PDT 24
Finished Aug 04 05:14:30 PM PDT 24
Peak memory 208700 kb
Host smart-fa7aa2c6-b4d8-4f56-b4f0-e93d816c2af8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590960028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2590960028
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1341193490
Short name T775
Test name
Test status
Simulation time 129711514 ps
CPU time 2.74 seconds
Started Aug 04 05:14:20 PM PDT 24
Finished Aug 04 05:14:23 PM PDT 24
Peak memory 214456 kb
Host smart-9965ecb1-7110-45de-b62b-37f6ecc2f069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341193490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1341193490
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.877710920
Short name T792
Test name
Test status
Simulation time 35644681 ps
CPU time 2.15 seconds
Started Aug 04 05:14:18 PM PDT 24
Finished Aug 04 05:14:20 PM PDT 24
Peak memory 206764 kb
Host smart-e0f102b2-a6b5-4479-b217-a63cfde5bd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877710920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.877710920
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1433030494
Short name T236
Test name
Test status
Simulation time 1536811724 ps
CPU time 28 seconds
Started Aug 04 05:14:20 PM PDT 24
Finished Aug 04 05:14:48 PM PDT 24
Peak memory 222444 kb
Host smart-e345d932-700a-49b4-854c-55bdcdeaa0fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433030494 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1433030494
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2272309503
Short name T748
Test name
Test status
Simulation time 478195225 ps
CPU time 6.02 seconds
Started Aug 04 05:14:20 PM PDT 24
Finished Aug 04 05:14:26 PM PDT 24
Peak memory 209984 kb
Host smart-5e33825c-2c80-4b3e-bff9-f617125e3cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272309503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2272309503
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1205316019
Short name T377
Test name
Test status
Simulation time 150607003 ps
CPU time 3.15 seconds
Started Aug 04 05:14:20 PM PDT 24
Finished Aug 04 05:14:24 PM PDT 24
Peak memory 209768 kb
Host smart-33a5546e-7ffb-4438-adef-5aeb88b20879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205316019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1205316019
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.810928038
Short name T415
Test name
Test status
Simulation time 13057864 ps
CPU time 0.77 seconds
Started Aug 04 05:14:26 PM PDT 24
Finished Aug 04 05:14:27 PM PDT 24
Peak memory 205868 kb
Host smart-34de96f1-3bf7-4334-8565-79f0c0259f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810928038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.810928038
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1592467986
Short name T685
Test name
Test status
Simulation time 508015193 ps
CPU time 5.8 seconds
Started Aug 04 05:14:26 PM PDT 24
Finished Aug 04 05:14:32 PM PDT 24
Peak memory 210200 kb
Host smart-ea6a5fa2-e8b8-435d-b353-2c27605e121a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592467986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1592467986
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2936519827
Short name T801
Test name
Test status
Simulation time 689043739 ps
CPU time 4.33 seconds
Started Aug 04 05:14:24 PM PDT 24
Finished Aug 04 05:14:29 PM PDT 24
Peak memory 214416 kb
Host smart-a4a64554-6b64-400c-ae6d-d42f6c0efdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936519827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2936519827
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3456405526
Short name T492
Test name
Test status
Simulation time 553530323 ps
CPU time 17.5 seconds
Started Aug 04 05:14:25 PM PDT 24
Finished Aug 04 05:14:43 PM PDT 24
Peak memory 221696 kb
Host smart-1d4a6277-22d4-4de5-8f1f-0384e6453b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456405526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3456405526
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3180930485
Short name T283
Test name
Test status
Simulation time 84513057 ps
CPU time 3.67 seconds
Started Aug 04 05:14:24 PM PDT 24
Finished Aug 04 05:14:28 PM PDT 24
Peak memory 221580 kb
Host smart-b10738fb-1187-4d41-9c8d-a3417d97a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180930485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3180930485
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.560520571
Short name T805
Test name
Test status
Simulation time 693397418 ps
CPU time 2.93 seconds
Started Aug 04 05:14:24 PM PDT 24
Finished Aug 04 05:14:28 PM PDT 24
Peak memory 219592 kb
Host smart-a090a325-dd3d-4e64-a1e7-aaa9a2078a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560520571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.560520571
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.4106509928
Short name T797
Test name
Test status
Simulation time 2115178221 ps
CPU time 49.78 seconds
Started Aug 04 05:14:26 PM PDT 24
Finished Aug 04 05:15:16 PM PDT 24
Peak memory 218628 kb
Host smart-0ccdbbb5-ae73-4736-8810-b5431d8bdcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106509928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.4106509928
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1424802429
Short name T837
Test name
Test status
Simulation time 2404288559 ps
CPU time 30.58 seconds
Started Aug 04 05:14:23 PM PDT 24
Finished Aug 04 05:14:54 PM PDT 24
Peak memory 208980 kb
Host smart-37fe9258-f039-45cf-b4f1-a41cae109bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424802429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1424802429
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.743974081
Short name T876
Test name
Test status
Simulation time 922758124 ps
CPU time 17.16 seconds
Started Aug 04 05:14:28 PM PDT 24
Finished Aug 04 05:14:45 PM PDT 24
Peak memory 208176 kb
Host smart-f32929ea-4bc8-4c3e-96b4-7e5d89e42879
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743974081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.743974081
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2633823832
Short name T669
Test name
Test status
Simulation time 230555088 ps
CPU time 2.85 seconds
Started Aug 04 05:14:24 PM PDT 24
Finished Aug 04 05:14:27 PM PDT 24
Peak memory 208524 kb
Host smart-218910b1-6d84-40f7-848b-8defe4349a72
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633823832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2633823832
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1596763486
Short name T503
Test name
Test status
Simulation time 86224982 ps
CPU time 1.77 seconds
Started Aug 04 05:14:23 PM PDT 24
Finished Aug 04 05:14:25 PM PDT 24
Peak memory 206776 kb
Host smart-cc84fd87-6969-4514-804c-8b59679de70e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596763486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1596763486
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1175621566
Short name T318
Test name
Test status
Simulation time 174725306 ps
CPU time 3.06 seconds
Started Aug 04 05:14:28 PM PDT 24
Finished Aug 04 05:14:31 PM PDT 24
Peak memory 214292 kb
Host smart-66737c26-b26c-446b-9de2-a51d7c2b2693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175621566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1175621566
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.845649263
Short name T412
Test name
Test status
Simulation time 540175597 ps
CPU time 3.94 seconds
Started Aug 04 05:14:26 PM PDT 24
Finished Aug 04 05:14:30 PM PDT 24
Peak memory 208804 kb
Host smart-a4d91414-1379-4bb8-b8a6-7c8d8fa2207e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845649263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.845649263
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2886663852
Short name T57
Test name
Test status
Simulation time 3157392132 ps
CPU time 30.25 seconds
Started Aug 04 05:14:24 PM PDT 24
Finished Aug 04 05:14:55 PM PDT 24
Peak memory 221184 kb
Host smart-3066919d-b374-47f4-82ce-6b91cd8f6da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886663852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2886663852
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3728353503
Short name T704
Test name
Test status
Simulation time 478852668 ps
CPU time 19.1 seconds
Started Aug 04 05:14:24 PM PDT 24
Finished Aug 04 05:14:44 PM PDT 24
Peak memory 219504 kb
Host smart-7579c848-8376-444d-b2d8-ecf8723fd71d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728353503 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3728353503
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3168090645
Short name T348
Test name
Test status
Simulation time 1299659154 ps
CPU time 9.81 seconds
Started Aug 04 05:14:25 PM PDT 24
Finished Aug 04 05:14:35 PM PDT 24
Peak memory 214212 kb
Host smart-4f046527-4488-42b3-8a8a-27f81f4e71d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168090645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3168090645
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1178682281
Short name T137
Test name
Test status
Simulation time 93696592 ps
CPU time 1.51 seconds
Started Aug 04 05:14:24 PM PDT 24
Finished Aug 04 05:14:26 PM PDT 24
Peak memory 209720 kb
Host smart-f88c7fdf-f74a-445b-a2ad-b778f6f441f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178682281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1178682281
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1919617606
Short name T842
Test name
Test status
Simulation time 11051473 ps
CPU time 0.87 seconds
Started Aug 04 05:14:30 PM PDT 24
Finished Aug 04 05:14:31 PM PDT 24
Peak memory 205940 kb
Host smart-35bf9681-440a-42ba-8de4-3039bbd1df08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919617606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1919617606
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.444221713
Short name T33
Test name
Test status
Simulation time 88166700 ps
CPU time 3.22 seconds
Started Aug 04 05:14:31 PM PDT 24
Finished Aug 04 05:14:34 PM PDT 24
Peak memory 222684 kb
Host smart-2ef6187e-87b5-434d-a1be-058427ea17d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444221713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.444221713
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.419739279
Short name T755
Test name
Test status
Simulation time 21589287 ps
CPU time 1.77 seconds
Started Aug 04 05:14:28 PM PDT 24
Finished Aug 04 05:14:30 PM PDT 24
Peak memory 214320 kb
Host smart-4b3d7b55-5136-4bf1-b38a-45d1ceae9647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419739279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.419739279
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.707974550
Short name T250
Test name
Test status
Simulation time 782522477 ps
CPU time 2.63 seconds
Started Aug 04 05:14:29 PM PDT 24
Finished Aug 04 05:14:31 PM PDT 24
Peak memory 214568 kb
Host smart-1419a9f9-91dc-433b-9b61-975104471ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707974550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.707974550
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.960525290
Short name T106
Test name
Test status
Simulation time 503385884 ps
CPU time 6.08 seconds
Started Aug 04 05:14:29 PM PDT 24
Finished Aug 04 05:14:35 PM PDT 24
Peak memory 215100 kb
Host smart-5a3e1d59-0984-4cbc-ade7-91e2201d86a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960525290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.960525290
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1827662001
Short name T290
Test name
Test status
Simulation time 2178357659 ps
CPU time 4.23 seconds
Started Aug 04 05:14:29 PM PDT 24
Finished Aug 04 05:14:34 PM PDT 24
Peak memory 210516 kb
Host smart-5e94e2e4-c493-4d3c-a266-bc7cefa08811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827662001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1827662001
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1267500117
Short name T738
Test name
Test status
Simulation time 37999655 ps
CPU time 2.49 seconds
Started Aug 04 05:14:26 PM PDT 24
Finished Aug 04 05:14:29 PM PDT 24
Peak memory 208620 kb
Host smart-ced298cf-ab96-4983-a3ec-1b14974e597b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267500117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1267500117
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3885496979
Short name T643
Test name
Test status
Simulation time 84469633 ps
CPU time 3.05 seconds
Started Aug 04 05:14:24 PM PDT 24
Finished Aug 04 05:14:27 PM PDT 24
Peak memory 208712 kb
Host smart-7ceeebe2-e771-4523-8500-b4f558cfb22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885496979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3885496979
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1683617688
Short name T440
Test name
Test status
Simulation time 149117861 ps
CPU time 5.03 seconds
Started Aug 04 05:14:28 PM PDT 24
Finished Aug 04 05:14:33 PM PDT 24
Peak memory 208724 kb
Host smart-7c25e597-7cb7-4e35-81a9-1003ede9d6c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683617688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1683617688
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2826078866
Short name T410
Test name
Test status
Simulation time 237230946 ps
CPU time 6.12 seconds
Started Aug 04 05:14:27 PM PDT 24
Finished Aug 04 05:14:33 PM PDT 24
Peak memory 208660 kb
Host smart-cd58b240-b583-4ac4-b5fe-3fd5557f876b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826078866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2826078866
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3870610327
Short name T718
Test name
Test status
Simulation time 157147178 ps
CPU time 3.37 seconds
Started Aug 04 05:14:23 PM PDT 24
Finished Aug 04 05:14:27 PM PDT 24
Peak memory 206840 kb
Host smart-db79f863-cac0-468e-b7d3-a27c82fe969e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870610327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3870610327
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2120276354
Short name T109
Test name
Test status
Simulation time 121765330 ps
CPU time 2.21 seconds
Started Aug 04 05:14:31 PM PDT 24
Finished Aug 04 05:14:34 PM PDT 24
Peak memory 207160 kb
Host smart-387b25e5-9988-4298-99d5-3717bc5524f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120276354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2120276354
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2823408230
Short name T597
Test name
Test status
Simulation time 127636477 ps
CPU time 3.4 seconds
Started Aug 04 05:14:27 PM PDT 24
Finished Aug 04 05:14:30 PM PDT 24
Peak memory 208176 kb
Host smart-fe3c9019-27bc-41b4-8f98-256ab837f944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823408230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2823408230
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2060740610
Short name T311
Test name
Test status
Simulation time 116075045 ps
CPU time 3.88 seconds
Started Aug 04 05:14:29 PM PDT 24
Finished Aug 04 05:14:33 PM PDT 24
Peak memory 214276 kb
Host smart-f6ce70da-1979-49f0-99fd-4dc742144732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060740610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2060740610
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3622508404
Short name T378
Test name
Test status
Simulation time 152273017 ps
CPU time 2.71 seconds
Started Aug 04 05:14:28 PM PDT 24
Finished Aug 04 05:14:31 PM PDT 24
Peak memory 209608 kb
Host smart-c189fec0-10c5-4ea5-b44e-29ecf2bb96b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622508404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3622508404
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1845711615
Short name T487
Test name
Test status
Simulation time 68686853 ps
CPU time 0.72 seconds
Started Aug 04 05:14:38 PM PDT 24
Finished Aug 04 05:14:39 PM PDT 24
Peak memory 205860 kb
Host smart-96500e0d-7d48-4b6a-aa32-ad42f2355d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845711615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1845711615
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3170904853
Short name T352
Test name
Test status
Simulation time 561289671 ps
CPU time 3.92 seconds
Started Aug 04 05:14:30 PM PDT 24
Finished Aug 04 05:14:34 PM PDT 24
Peak memory 214264 kb
Host smart-6b1c4085-9c57-4cb1-8031-e4e9c09ec157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170904853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3170904853
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.4258790605
Short name T72
Test name
Test status
Simulation time 1294619922 ps
CPU time 22.71 seconds
Started Aug 04 05:14:28 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 209012 kb
Host smart-2383f6d6-68b0-48dc-abf3-fd783ec1451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258790605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4258790605
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3628425355
Short name T365
Test name
Test status
Simulation time 143992263 ps
CPU time 2.17 seconds
Started Aug 04 05:14:28 PM PDT 24
Finished Aug 04 05:14:30 PM PDT 24
Peak memory 214188 kb
Host smart-0caa8764-da6a-46bf-ad92-34db0a9e16bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628425355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3628425355
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3536617482
Short name T598
Test name
Test status
Simulation time 444466772 ps
CPU time 4.66 seconds
Started Aug 04 05:14:26 PM PDT 24
Finished Aug 04 05:14:31 PM PDT 24
Peak memory 221108 kb
Host smart-b5ec05a6-03be-4906-988a-309d6214bb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536617482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3536617482
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1998488681
Short name T69
Test name
Test status
Simulation time 39893751 ps
CPU time 2.9 seconds
Started Aug 04 05:14:27 PM PDT 24
Finished Aug 04 05:14:30 PM PDT 24
Peak memory 208532 kb
Host smart-bcc6d3b6-bc46-4e64-80f5-0186b9b06471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998488681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1998488681
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1436065261
Short name T660
Test name
Test status
Simulation time 6619400986 ps
CPU time 23.45 seconds
Started Aug 04 05:14:28 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 214444 kb
Host smart-02f76f93-d6b6-4d61-94d9-da353e17186c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436065261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1436065261
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1746717661
Short name T322
Test name
Test status
Simulation time 139586731 ps
CPU time 3.12 seconds
Started Aug 04 05:14:37 PM PDT 24
Finished Aug 04 05:14:41 PM PDT 24
Peak memory 208708 kb
Host smart-6ab59de1-204f-4714-be69-63e38c547873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746717661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1746717661
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1688958315
Short name T356
Test name
Test status
Simulation time 154482972 ps
CPU time 4.4 seconds
Started Aug 04 05:14:35 PM PDT 24
Finished Aug 04 05:14:40 PM PDT 24
Peak memory 207752 kb
Host smart-51e95f40-fde4-462c-91d3-469ed679315a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688958315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1688958315
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3750098450
Short name T735
Test name
Test status
Simulation time 643552969 ps
CPU time 22.05 seconds
Started Aug 04 05:14:27 PM PDT 24
Finished Aug 04 05:14:49 PM PDT 24
Peak memory 208468 kb
Host smart-d8bb00e3-6f77-469d-96bb-011f65e8f054
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750098450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3750098450
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.360802400
Short name T859
Test name
Test status
Simulation time 205305861 ps
CPU time 5.41 seconds
Started Aug 04 05:14:28 PM PDT 24
Finished Aug 04 05:14:33 PM PDT 24
Peak memory 207968 kb
Host smart-7abe8142-e61c-49bf-9323-192fa321baf2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360802400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.360802400
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.750913140
Short name T614
Test name
Test status
Simulation time 126714497 ps
CPU time 3.34 seconds
Started Aug 04 05:14:27 PM PDT 24
Finished Aug 04 05:14:31 PM PDT 24
Peak memory 210028 kb
Host smart-9a46a787-2b4a-4d73-8a69-d977522d754a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750913140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.750913140
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3738421495
Short name T418
Test name
Test status
Simulation time 72968899 ps
CPU time 2.05 seconds
Started Aug 04 05:14:30 PM PDT 24
Finished Aug 04 05:14:32 PM PDT 24
Peak memory 206016 kb
Host smart-d4e23a95-0534-48ed-aec8-dee184903b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738421495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3738421495
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2704445613
Short name T886
Test name
Test status
Simulation time 1638837265 ps
CPU time 52.04 seconds
Started Aug 04 05:14:29 PM PDT 24
Finished Aug 04 05:15:21 PM PDT 24
Peak memory 222468 kb
Host smart-b0608f96-61a2-4c77-8b5f-55751ed5e4f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704445613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2704445613
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1821383081
Short name T307
Test name
Test status
Simulation time 222879001 ps
CPU time 11.64 seconds
Started Aug 04 05:14:34 PM PDT 24
Finished Aug 04 05:14:46 PM PDT 24
Peak memory 222532 kb
Host smart-9561eb0b-9d2b-4dce-b22b-c220812d8c32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821383081 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1821383081
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2413762345
Short name T422
Test name
Test status
Simulation time 403163075 ps
CPU time 5 seconds
Started Aug 04 05:14:29 PM PDT 24
Finished Aug 04 05:14:34 PM PDT 24
Peak memory 208112 kb
Host smart-4c4c00dd-ed6a-4fb6-9af6-56afd26f0fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413762345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2413762345
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1642113264
Short name T83
Test name
Test status
Simulation time 92628029 ps
CPU time 1.98 seconds
Started Aug 04 05:14:28 PM PDT 24
Finished Aug 04 05:14:30 PM PDT 24
Peak memory 209764 kb
Host smart-657c2e6f-e3cb-4c32-9ee4-804dad085ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642113264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1642113264
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1050020419
Short name T759
Test name
Test status
Simulation time 18945360 ps
CPU time 0.98 seconds
Started Aug 04 05:14:37 PM PDT 24
Finished Aug 04 05:14:38 PM PDT 24
Peak memory 206000 kb
Host smart-3c241d4a-7e9d-4b77-aff2-63f7fd45974f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050020419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1050020419
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.379204007
Short name T723
Test name
Test status
Simulation time 37363521 ps
CPU time 1.76 seconds
Started Aug 04 05:14:38 PM PDT 24
Finished Aug 04 05:14:40 PM PDT 24
Peak memory 222276 kb
Host smart-2edfa05a-9946-4882-a621-b0428d1ffef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379204007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.379204007
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.309831461
Short name T78
Test name
Test status
Simulation time 156174391 ps
CPU time 3.43 seconds
Started Aug 04 05:14:31 PM PDT 24
Finished Aug 04 05:14:35 PM PDT 24
Peak memory 207424 kb
Host smart-364876a2-ec0b-494d-a474-3490bf6b664f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309831461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.309831461
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3470842202
Short name T728
Test name
Test status
Simulation time 361475727 ps
CPU time 3.6 seconds
Started Aug 04 05:14:34 PM PDT 24
Finished Aug 04 05:14:38 PM PDT 24
Peak memory 208724 kb
Host smart-a05f78a7-ce4a-4cf7-8ce6-f194b99d43c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470842202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3470842202
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1942845983
Short name T678
Test name
Test status
Simulation time 44305888 ps
CPU time 2.43 seconds
Started Aug 04 05:14:38 PM PDT 24
Finished Aug 04 05:14:41 PM PDT 24
Peak memory 222284 kb
Host smart-b9b2f2ad-312b-4e81-881b-03beb1043fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942845983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1942845983
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3995209112
Short name T835
Test name
Test status
Simulation time 298892978 ps
CPU time 2.56 seconds
Started Aug 04 05:14:31 PM PDT 24
Finished Aug 04 05:14:34 PM PDT 24
Peak memory 214324 kb
Host smart-e49d0d71-34c3-4531-8aa0-3dd5565a5c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995209112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3995209112
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.586413237
Short name T91
Test name
Test status
Simulation time 431331074 ps
CPU time 6.97 seconds
Started Aug 04 05:14:30 PM PDT 24
Finished Aug 04 05:14:37 PM PDT 24
Peak memory 214352 kb
Host smart-8602a9ab-f823-4fae-8201-03a6bbfbe5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586413237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.586413237
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.683999742
Short name T589
Test name
Test status
Simulation time 618593276 ps
CPU time 14.76 seconds
Started Aug 04 05:14:30 PM PDT 24
Finished Aug 04 05:14:45 PM PDT 24
Peak memory 208588 kb
Host smart-7616aec3-3e51-44bd-a1f7-8bcb1a6be2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683999742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.683999742
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2244716936
Short name T531
Test name
Test status
Simulation time 816105486 ps
CPU time 6.89 seconds
Started Aug 04 05:14:35 PM PDT 24
Finished Aug 04 05:14:42 PM PDT 24
Peak memory 208688 kb
Host smart-bd7164ac-830c-4d79-b5e9-99db45550195
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244716936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2244716936
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2795133115
Short name T406
Test name
Test status
Simulation time 49235457 ps
CPU time 2.63 seconds
Started Aug 04 05:14:32 PM PDT 24
Finished Aug 04 05:14:34 PM PDT 24
Peak memory 206776 kb
Host smart-d7845e20-153b-44ad-93d4-5fe39259ebfb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795133115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2795133115
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4214435745
Short name T733
Test name
Test status
Simulation time 84269574 ps
CPU time 3.56 seconds
Started Aug 04 05:14:34 PM PDT 24
Finished Aug 04 05:14:38 PM PDT 24
Peak memory 206948 kb
Host smart-d7ab0448-f201-4dfe-94e8-b16ccbf57dc5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214435745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4214435745
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1897265843
Short name T302
Test name
Test status
Simulation time 228704499 ps
CPU time 2.95 seconds
Started Aug 04 05:14:38 PM PDT 24
Finished Aug 04 05:14:41 PM PDT 24
Peak memory 214292 kb
Host smart-3b958e57-ec6b-44ac-9748-1cc22237af60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897265843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1897265843
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1122711972
Short name T2
Test name
Test status
Simulation time 406105699 ps
CPU time 4.39 seconds
Started Aug 04 05:14:32 PM PDT 24
Finished Aug 04 05:14:36 PM PDT 24
Peak memory 206832 kb
Host smart-bcadd356-e24a-4039-b778-05bd8294fa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122711972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1122711972
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2767618701
Short name T798
Test name
Test status
Simulation time 1628497899 ps
CPU time 36.29 seconds
Started Aug 04 05:14:30 PM PDT 24
Finished Aug 04 05:15:07 PM PDT 24
Peak memory 216124 kb
Host smart-ee2532ac-3519-4416-aa31-d48f30469172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767618701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2767618701
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2971549694
Short name T467
Test name
Test status
Simulation time 359553872 ps
CPU time 4.16 seconds
Started Aug 04 05:14:33 PM PDT 24
Finished Aug 04 05:14:37 PM PDT 24
Peak memory 209372 kb
Host smart-25212e97-80cd-40dd-a853-b3553b52e6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971549694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2971549694
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3609227329
Short name T60
Test name
Test status
Simulation time 639547894 ps
CPU time 3.73 seconds
Started Aug 04 05:14:32 PM PDT 24
Finished Aug 04 05:14:36 PM PDT 24
Peak memory 209992 kb
Host smart-193e72b5-ce94-4f34-b125-2b5866180bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609227329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3609227329
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3277568510
Short name T692
Test name
Test status
Simulation time 30056290 ps
CPU time 0.7 seconds
Started Aug 04 05:13:00 PM PDT 24
Finished Aug 04 05:13:00 PM PDT 24
Peak memory 205936 kb
Host smart-af986d1d-a1c6-466e-b3db-3007e684cdab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277568510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3277568510
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1210689517
Short name T896
Test name
Test status
Simulation time 802743748 ps
CPU time 10.87 seconds
Started Aug 04 05:12:59 PM PDT 24
Finished Aug 04 05:13:10 PM PDT 24
Peak memory 208816 kb
Host smart-09fb69b7-83a8-488c-9001-0d7b3fba280b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210689517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1210689517
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.791560935
Short name T248
Test name
Test status
Simulation time 761804401 ps
CPU time 13.66 seconds
Started Aug 04 05:12:58 PM PDT 24
Finished Aug 04 05:13:12 PM PDT 24
Peak memory 214320 kb
Host smart-01ba7241-8f94-46d8-b776-22bf161c06ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791560935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.791560935
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1469793052
Short name T25
Test name
Test status
Simulation time 460936321 ps
CPU time 5.48 seconds
Started Aug 04 05:12:58 PM PDT 24
Finished Aug 04 05:13:03 PM PDT 24
Peak memory 209348 kb
Host smart-26ca01cb-bfa4-4f3b-9d3f-ce3e1b451751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469793052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1469793052
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1638471371
Short name T638
Test name
Test status
Simulation time 110500494 ps
CPU time 3.61 seconds
Started Aug 04 05:12:58 PM PDT 24
Finished Aug 04 05:13:01 PM PDT 24
Peak memory 222240 kb
Host smart-2ff9a5dc-f6fb-44d3-aa7e-62eca0d67999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638471371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1638471371
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2336388293
Short name T436
Test name
Test status
Simulation time 90292969 ps
CPU time 3.2 seconds
Started Aug 04 05:12:59 PM PDT 24
Finished Aug 04 05:13:03 PM PDT 24
Peak memory 214696 kb
Host smart-a7f5e12e-e19a-49bc-a0fe-c7b69cff1f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336388293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2336388293
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2676448905
Short name T516
Test name
Test status
Simulation time 276112989 ps
CPU time 8.16 seconds
Started Aug 04 05:13:00 PM PDT 24
Finished Aug 04 05:13:09 PM PDT 24
Peak memory 208180 kb
Host smart-ad67e71c-793a-4737-978a-5dfc97fdc4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676448905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2676448905
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3747849244
Short name T696
Test name
Test status
Simulation time 92645061 ps
CPU time 3.13 seconds
Started Aug 04 05:12:57 PM PDT 24
Finished Aug 04 05:13:00 PM PDT 24
Peak memory 208588 kb
Host smart-2ac98d1a-45d7-4fa3-9f3f-94306c67d7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747849244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3747849244
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1001671497
Short name T811
Test name
Test status
Simulation time 79526498 ps
CPU time 3.5 seconds
Started Aug 04 05:12:58 PM PDT 24
Finished Aug 04 05:13:02 PM PDT 24
Peak memory 209044 kb
Host smart-be83bf0f-7cb1-43b3-8f88-6ec6f36626c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001671497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1001671497
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3950535804
Short name T584
Test name
Test status
Simulation time 126275024 ps
CPU time 4.09 seconds
Started Aug 04 05:12:58 PM PDT 24
Finished Aug 04 05:13:02 PM PDT 24
Peak memory 208820 kb
Host smart-b8358899-4507-4aac-9b19-7007c1a73320
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950535804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3950535804
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1581151340
Short name T439
Test name
Test status
Simulation time 338201093 ps
CPU time 2.96 seconds
Started Aug 04 05:12:57 PM PDT 24
Finished Aug 04 05:13:00 PM PDT 24
Peak memory 206996 kb
Host smart-222ffdc4-7809-48b3-b821-baa10ef8fee3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581151340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1581151340
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1029999153
Short name T803
Test name
Test status
Simulation time 160348322 ps
CPU time 2.07 seconds
Started Aug 04 05:12:59 PM PDT 24
Finished Aug 04 05:13:01 PM PDT 24
Peak memory 215576 kb
Host smart-07e808f1-a610-4b45-af4e-adfee6d27fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029999153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1029999153
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.4047198863
Short name T190
Test name
Test status
Simulation time 1921827688 ps
CPU time 4.94 seconds
Started Aug 04 05:12:53 PM PDT 24
Finished Aug 04 05:12:58 PM PDT 24
Peak memory 206864 kb
Host smart-de17f273-4a4b-46f7-9312-c74554f24c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047198863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4047198863
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1004125649
Short name T265
Test name
Test status
Simulation time 277592286 ps
CPU time 8.34 seconds
Started Aug 04 05:12:59 PM PDT 24
Finished Aug 04 05:13:07 PM PDT 24
Peak memory 210216 kb
Host smart-5277611d-35ff-4605-9a26-ee5a3fa73aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004125649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1004125649
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2954249027
Short name T442
Test name
Test status
Simulation time 107233629 ps
CPU time 1.86 seconds
Started Aug 04 05:13:00 PM PDT 24
Finished Aug 04 05:13:02 PM PDT 24
Peak memory 209832 kb
Host smart-bb660a2d-56e4-41f9-b416-0df0a7eaa443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954249027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2954249027
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.156146108
Short name T716
Test name
Test status
Simulation time 27677216 ps
CPU time 0.7 seconds
Started Aug 04 05:14:35 PM PDT 24
Finished Aug 04 05:14:36 PM PDT 24
Peak memory 205864 kb
Host smart-9ab3bd29-d03e-4d10-bddb-5d4be379efb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156146108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.156146108
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3560365600
Short name T397
Test name
Test status
Simulation time 74517051 ps
CPU time 3.39 seconds
Started Aug 04 05:14:38 PM PDT 24
Finished Aug 04 05:14:41 PM PDT 24
Peak memory 214224 kb
Host smart-18ff1d9d-efbf-421c-ac00-ebad2b066ab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3560365600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3560365600
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.708256620
Short name T38
Test name
Test status
Simulation time 195962724 ps
CPU time 5.32 seconds
Started Aug 04 05:14:38 PM PDT 24
Finished Aug 04 05:14:43 PM PDT 24
Peak memory 218448 kb
Host smart-9141d0e7-6890-4874-ba7f-c091d7034126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708256620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.708256620
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2837029867
Short name T715
Test name
Test status
Simulation time 61271107 ps
CPU time 2.97 seconds
Started Aug 04 05:14:31 PM PDT 24
Finished Aug 04 05:14:34 PM PDT 24
Peak memory 208084 kb
Host smart-cac522fb-a3bf-47b8-8d65-3479525e8d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837029867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2837029867
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2380622574
Short name T840
Test name
Test status
Simulation time 1463620804 ps
CPU time 4.73 seconds
Started Aug 04 05:14:34 PM PDT 24
Finished Aug 04 05:14:38 PM PDT 24
Peak memory 221688 kb
Host smart-75017865-03c3-433d-8f7a-9a8d1bfc57d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380622574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2380622574
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2919059596
Short name T284
Test name
Test status
Simulation time 185276798 ps
CPU time 4.11 seconds
Started Aug 04 05:14:37 PM PDT 24
Finished Aug 04 05:14:41 PM PDT 24
Peak memory 214260 kb
Host smart-c840aebc-089d-42cf-8580-09fb10d46e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919059596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2919059596
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2360819558
Short name T219
Test name
Test status
Simulation time 295159455 ps
CPU time 3.34 seconds
Started Aug 04 05:14:35 PM PDT 24
Finished Aug 04 05:14:39 PM PDT 24
Peak memory 214224 kb
Host smart-881a5301-2b20-48a9-92a8-5cb798cf31ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360819558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2360819558
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2411124404
Short name T210
Test name
Test status
Simulation time 206803774 ps
CPU time 4.96 seconds
Started Aug 04 05:14:38 PM PDT 24
Finished Aug 04 05:14:43 PM PDT 24
Peak memory 218444 kb
Host smart-29754fc6-a152-4563-b6e2-7d68bd240f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411124404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2411124404
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.459262011
Short name T568
Test name
Test status
Simulation time 129021837 ps
CPU time 1.76 seconds
Started Aug 04 05:14:34 PM PDT 24
Finished Aug 04 05:14:36 PM PDT 24
Peak memory 206788 kb
Host smart-38c59606-57fd-404c-93c9-ab001bf65e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459262011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.459262011
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.186303889
Short name T602
Test name
Test status
Simulation time 298036639 ps
CPU time 2.82 seconds
Started Aug 04 05:14:36 PM PDT 24
Finished Aug 04 05:14:39 PM PDT 24
Peak memory 206876 kb
Host smart-e0f8366e-6abf-42c8-9cca-f13f70412042
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186303889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.186303889
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3487495091
Short name T644
Test name
Test status
Simulation time 56242737 ps
CPU time 3.03 seconds
Started Aug 04 05:14:34 PM PDT 24
Finished Aug 04 05:14:38 PM PDT 24
Peak memory 207660 kb
Host smart-4e624e6f-4556-461d-b12e-d7d2b6fc226a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487495091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3487495091
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3039186519
Short name T345
Test name
Test status
Simulation time 89448267 ps
CPU time 4.16 seconds
Started Aug 04 05:14:38 PM PDT 24
Finished Aug 04 05:14:42 PM PDT 24
Peak memory 208736 kb
Host smart-a8f20963-5f40-422d-a167-e949e876a51e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039186519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3039186519
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3709116619
Short name T777
Test name
Test status
Simulation time 68470916 ps
CPU time 2.65 seconds
Started Aug 04 05:14:36 PM PDT 24
Finished Aug 04 05:14:39 PM PDT 24
Peak memory 218364 kb
Host smart-2e435693-98d9-40a3-9431-76f9c9418f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709116619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3709116619
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3435377854
Short name T830
Test name
Test status
Simulation time 49612679 ps
CPU time 2.69 seconds
Started Aug 04 05:14:33 PM PDT 24
Finished Aug 04 05:14:35 PM PDT 24
Peak memory 206644 kb
Host smart-fc4684a8-b164-42dc-848d-a42463e1871c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435377854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3435377854
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.675182404
Short name T483
Test name
Test status
Simulation time 322416511 ps
CPU time 3.75 seconds
Started Aug 04 05:14:38 PM PDT 24
Finished Aug 04 05:14:42 PM PDT 24
Peak memory 208248 kb
Host smart-f554d6e1-dc8b-4d98-b73b-3d6a29c21223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675182404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.675182404
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3640982855
Short name T411
Test name
Test status
Simulation time 254423835 ps
CPU time 2.62 seconds
Started Aug 04 05:14:35 PM PDT 24
Finished Aug 04 05:14:38 PM PDT 24
Peak memory 209924 kb
Host smart-fe587d57-c3cf-4ad8-a75d-e0c1ffde6a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640982855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3640982855
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.398334431
Short name T650
Test name
Test status
Simulation time 61752833 ps
CPU time 0.79 seconds
Started Aug 04 05:14:39 PM PDT 24
Finished Aug 04 05:14:40 PM PDT 24
Peak memory 205948 kb
Host smart-0bd94bb2-3cd7-446a-82bf-671cc5138773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398334431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.398334431
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3461732118
Short name T253
Test name
Test status
Simulation time 355221268 ps
CPU time 5.5 seconds
Started Aug 04 05:14:35 PM PDT 24
Finished Aug 04 05:14:40 PM PDT 24
Peak memory 214232 kb
Host smart-7b124bb0-c3c0-4e19-b744-530ed0c2f1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461732118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3461732118
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2598031636
Short name T196
Test name
Test status
Simulation time 354334479 ps
CPU time 2.17 seconds
Started Aug 04 05:14:35 PM PDT 24
Finished Aug 04 05:14:38 PM PDT 24
Peak memory 222032 kb
Host smart-2f7a1d61-81d1-48a1-b4fc-4847d8e077c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598031636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2598031636
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.612700905
Short name T850
Test name
Test status
Simulation time 339316930 ps
CPU time 3.45 seconds
Started Aug 04 05:14:34 PM PDT 24
Finished Aug 04 05:14:38 PM PDT 24
Peak memory 208404 kb
Host smart-2efb405d-9b3e-40a2-a629-3a4bc06f7d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612700905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.612700905
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.721436000
Short name T446
Test name
Test status
Simulation time 6157472435 ps
CPU time 53.67 seconds
Started Aug 04 05:14:34 PM PDT 24
Finished Aug 04 05:15:28 PM PDT 24
Peak memory 214356 kb
Host smart-32f89154-816e-46f0-a0d4-cba5d2183d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721436000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.721436000
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2084257450
Short name T329
Test name
Test status
Simulation time 167773404 ps
CPU time 4.03 seconds
Started Aug 04 05:14:36 PM PDT 24
Finished Aug 04 05:14:40 PM PDT 24
Peak memory 208960 kb
Host smart-f68d4e00-b23e-4145-aafa-8e00b53f0c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084257450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2084257450
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.495076429
Short name T474
Test name
Test status
Simulation time 44520568 ps
CPU time 1.87 seconds
Started Aug 04 05:14:34 PM PDT 24
Finished Aug 04 05:14:36 PM PDT 24
Peak memory 206836 kb
Host smart-e6a3cf9a-46fb-4481-8702-6d456ed1d166
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495076429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.495076429
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3201796173
Short name T605
Test name
Test status
Simulation time 736671381 ps
CPU time 4.72 seconds
Started Aug 04 05:14:38 PM PDT 24
Finished Aug 04 05:14:43 PM PDT 24
Peak memory 208640 kb
Host smart-404432c1-87c8-4c41-baaf-853ded8fc1c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201796173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3201796173
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3794132550
Short name T206
Test name
Test status
Simulation time 12152167830 ps
CPU time 52.97 seconds
Started Aug 04 05:14:32 PM PDT 24
Finished Aug 04 05:15:25 PM PDT 24
Peak memory 208268 kb
Host smart-4d6e33de-16ad-4cee-8bc2-3113edf71e98
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794132550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3794132550
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1140498901
Short name T463
Test name
Test status
Simulation time 55105232 ps
CPU time 2.62 seconds
Started Aug 04 05:14:37 PM PDT 24
Finished Aug 04 05:14:40 PM PDT 24
Peak memory 210112 kb
Host smart-3311c79b-2a34-4132-a37f-a082b89a36df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140498901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1140498901
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3456971586
Short name T93
Test name
Test status
Simulation time 45571665 ps
CPU time 2.48 seconds
Started Aug 04 05:14:39 PM PDT 24
Finished Aug 04 05:14:41 PM PDT 24
Peak memory 206680 kb
Host smart-53a1d851-0f29-4f60-8104-ca31dcbd4403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456971586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3456971586
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.606212029
Short name T879
Test name
Test status
Simulation time 681796239 ps
CPU time 5.89 seconds
Started Aug 04 05:14:57 PM PDT 24
Finished Aug 04 05:15:03 PM PDT 24
Peak memory 214272 kb
Host smart-59ff8e76-2a9e-4190-8389-bfe662f5f568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606212029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.606212029
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.992340369
Short name T697
Test name
Test status
Simulation time 204641572 ps
CPU time 2.55 seconds
Started Aug 04 05:14:35 PM PDT 24
Finished Aug 04 05:14:38 PM PDT 24
Peak memory 209920 kb
Host smart-79212227-db76-44fc-b235-ceb0a3e69fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992340369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.992340369
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1675286930
Short name T642
Test name
Test status
Simulation time 13016093 ps
CPU time 0.73 seconds
Started Aug 04 05:14:42 PM PDT 24
Finished Aug 04 05:14:43 PM PDT 24
Peak memory 205944 kb
Host smart-e63fa254-df2b-4abb-89c2-93dddb9e849a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675286930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1675286930
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3605119505
Short name T363
Test name
Test status
Simulation time 760104231 ps
CPU time 6.24 seconds
Started Aug 04 05:14:37 PM PDT 24
Finished Aug 04 05:14:44 PM PDT 24
Peak memory 217980 kb
Host smart-6c5788cb-7a3a-4186-b2e9-0542e125cb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605119505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3605119505
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.522224031
Short name T97
Test name
Test status
Simulation time 92908482 ps
CPU time 4.12 seconds
Started Aug 04 05:14:43 PM PDT 24
Finished Aug 04 05:14:48 PM PDT 24
Peak memory 220252 kb
Host smart-7632aaf9-bfcf-47f9-948a-c8f17ed44987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522224031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.522224031
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.350855467
Short name T249
Test name
Test status
Simulation time 30138786 ps
CPU time 2.16 seconds
Started Aug 04 05:14:43 PM PDT 24
Finished Aug 04 05:14:46 PM PDT 24
Peak memory 214240 kb
Host smart-23f2b471-aa8b-4e33-b4fb-808b3d45fb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350855467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.350855467
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1288766842
Short name T834
Test name
Test status
Simulation time 1028965649 ps
CPU time 8.51 seconds
Started Aug 04 05:14:37 PM PDT 24
Finished Aug 04 05:14:45 PM PDT 24
Peak memory 220768 kb
Host smart-fad5467d-e4fd-4ec9-9faa-667f9072185e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288766842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1288766842
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3176715774
Short name T349
Test name
Test status
Simulation time 113624602 ps
CPU time 4.27 seconds
Started Aug 04 05:14:39 PM PDT 24
Finished Aug 04 05:14:44 PM PDT 24
Peak memory 210204 kb
Host smart-576d3959-fadf-466d-86f5-f36f5b4ec118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176715774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3176715774
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3124080030
Short name T305
Test name
Test status
Simulation time 123607723 ps
CPU time 5.07 seconds
Started Aug 04 05:14:40 PM PDT 24
Finished Aug 04 05:14:45 PM PDT 24
Peak memory 208692 kb
Host smart-57061dbd-1334-4c69-b4b0-775ede9dbeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124080030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3124080030
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2423867900
Short name T537
Test name
Test status
Simulation time 53129748 ps
CPU time 2.8 seconds
Started Aug 04 05:14:39 PM PDT 24
Finished Aug 04 05:14:42 PM PDT 24
Peak memory 206964 kb
Host smart-c75e9e9a-3b09-49a1-a390-a59d53555fd5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423867900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2423867900
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3549145992
Short name T200
Test name
Test status
Simulation time 67705326 ps
CPU time 2.35 seconds
Started Aug 04 05:14:39 PM PDT 24
Finished Aug 04 05:14:41 PM PDT 24
Peak memory 208296 kb
Host smart-35a55926-4d5d-47fe-9575-9ca963277e5a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549145992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3549145992
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.607342232
Short name T820
Test name
Test status
Simulation time 433666111 ps
CPU time 2.94 seconds
Started Aug 04 05:14:37 PM PDT 24
Finished Aug 04 05:14:40 PM PDT 24
Peak memory 206992 kb
Host smart-b9e26105-2f5f-4698-bedc-e5bf87be0ecf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607342232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.607342232
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.336701031
Short name T543
Test name
Test status
Simulation time 542478580 ps
CPU time 2.36 seconds
Started Aug 04 05:14:41 PM PDT 24
Finished Aug 04 05:14:43 PM PDT 24
Peak memory 215524 kb
Host smart-c63fe118-a3ff-4b7b-8b18-f36007f00317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336701031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.336701031
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.825066356
Short name T895
Test name
Test status
Simulation time 1082025941 ps
CPU time 9.69 seconds
Started Aug 04 05:14:39 PM PDT 24
Finished Aug 04 05:14:48 PM PDT 24
Peak memory 208416 kb
Host smart-1fc727c1-ccc3-4d4b-9696-0f07cb179e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825066356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.825066356
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.171137723
Short name T364
Test name
Test status
Simulation time 327096923 ps
CPU time 16.04 seconds
Started Aug 04 05:14:42 PM PDT 24
Finished Aug 04 05:14:59 PM PDT 24
Peak memory 216044 kb
Host smart-bc56f182-1be8-45a4-beb6-149e480c8571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171137723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.171137723
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1858060398
Short name T131
Test name
Test status
Simulation time 337894630 ps
CPU time 12.02 seconds
Started Aug 04 05:14:53 PM PDT 24
Finished Aug 04 05:15:05 PM PDT 24
Peak memory 222372 kb
Host smart-8207b034-b6de-43ea-81e1-5684fde470ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858060398 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1858060398
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3057898686
Short name T812
Test name
Test status
Simulation time 101765655 ps
CPU time 2.41 seconds
Started Aug 04 05:14:43 PM PDT 24
Finished Aug 04 05:14:46 PM PDT 24
Peak memory 207428 kb
Host smart-66587030-8bb8-40d0-ab1d-d5d1b7297cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057898686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3057898686
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1462448262
Short name T17
Test name
Test status
Simulation time 26452327 ps
CPU time 1.63 seconds
Started Aug 04 05:14:45 PM PDT 24
Finished Aug 04 05:14:46 PM PDT 24
Peak memory 208472 kb
Host smart-5de7ab31-d4e9-461f-ae49-72ac876d6a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462448262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1462448262
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3785193988
Short name T135
Test name
Test status
Simulation time 41637566 ps
CPU time 0.75 seconds
Started Aug 04 05:14:47 PM PDT 24
Finished Aug 04 05:14:48 PM PDT 24
Peak memory 206104 kb
Host smart-22b0c544-2eaf-4251-9bf2-c038d731bea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785193988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3785193988
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.998055861
Short name T36
Test name
Test status
Simulation time 530641565 ps
CPU time 3.02 seconds
Started Aug 04 05:14:47 PM PDT 24
Finished Aug 04 05:14:50 PM PDT 24
Peak memory 209924 kb
Host smart-7d67c128-324f-42d1-af03-3d32028678d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998055861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.998055861
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3992245234
Short name T338
Test name
Test status
Simulation time 129006771 ps
CPU time 2.1 seconds
Started Aug 04 05:14:44 PM PDT 24
Finished Aug 04 05:14:46 PM PDT 24
Peak memory 209104 kb
Host smart-1acd6c99-a9f1-4c39-bf28-28e8980c9720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992245234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3992245234
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.718007066
Short name T282
Test name
Test status
Simulation time 106013730 ps
CPU time 4.54 seconds
Started Aug 04 05:14:46 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 215060 kb
Host smart-5740bba9-c773-4ee1-920b-80fb619ad85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718007066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.718007066
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1954814660
Short name T836
Test name
Test status
Simulation time 168226283 ps
CPU time 3.08 seconds
Started Aug 04 05:14:44 PM PDT 24
Finished Aug 04 05:14:47 PM PDT 24
Peak memory 219732 kb
Host smart-a6ce2417-c966-4b89-a34e-a257e5c3a110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954814660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1954814660
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1430051969
Short name T304
Test name
Test status
Simulation time 991887089 ps
CPU time 7.42 seconds
Started Aug 04 05:14:41 PM PDT 24
Finished Aug 04 05:14:48 PM PDT 24
Peak memory 218396 kb
Host smart-d5179c8d-c18d-4c65-829d-5f6cf61b84fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430051969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1430051969
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.543872840
Short name T212
Test name
Test status
Simulation time 1927910620 ps
CPU time 38.74 seconds
Started Aug 04 05:14:46 PM PDT 24
Finished Aug 04 05:15:25 PM PDT 24
Peak memory 208260 kb
Host smart-14661375-4d5a-463a-b2f2-241dc8d723de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543872840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.543872840
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2623838121
Short name T882
Test name
Test status
Simulation time 214115480 ps
CPU time 3.61 seconds
Started Aug 04 05:14:44 PM PDT 24
Finished Aug 04 05:14:48 PM PDT 24
Peak memory 208876 kb
Host smart-a2418f87-270e-419b-9662-9248e3abb858
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623838121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2623838121
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.972415786
Short name T681
Test name
Test status
Simulation time 85016549 ps
CPU time 1.98 seconds
Started Aug 04 05:14:42 PM PDT 24
Finished Aug 04 05:14:44 PM PDT 24
Peak memory 208608 kb
Host smart-ada44f3f-1ab8-4619-a091-73dc3ea78728
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972415786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.972415786
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1370890196
Short name T90
Test name
Test status
Simulation time 40469864 ps
CPU time 2.33 seconds
Started Aug 04 05:14:43 PM PDT 24
Finished Aug 04 05:14:45 PM PDT 24
Peak memory 207264 kb
Host smart-0883c5f1-8e50-4d37-a8f0-1cbf5767efa1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370890196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1370890196
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3449901866
Short name T288
Test name
Test status
Simulation time 342920724 ps
CPU time 2.61 seconds
Started Aug 04 05:14:48 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 210368 kb
Host smart-3a5d487d-a98f-4c9f-8d57-3398b07bf89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449901866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3449901866
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3835562911
Short name T649
Test name
Test status
Simulation time 238900911 ps
CPU time 2.63 seconds
Started Aug 04 05:14:44 PM PDT 24
Finished Aug 04 05:14:46 PM PDT 24
Peak memory 208476 kb
Host smart-4947eb70-cf38-4128-83b2-bc15180590f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835562911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3835562911
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.337899933
Short name T238
Test name
Test status
Simulation time 1236101007 ps
CPU time 18.74 seconds
Started Aug 04 05:14:45 PM PDT 24
Finished Aug 04 05:15:04 PM PDT 24
Peak memory 215180 kb
Host smart-7f81ff10-1eed-47c9-9257-28756d841c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337899933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.337899933
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3012567413
Short name T866
Test name
Test status
Simulation time 293453190 ps
CPU time 4.46 seconds
Started Aug 04 05:14:41 PM PDT 24
Finished Aug 04 05:14:45 PM PDT 24
Peak memory 207736 kb
Host smart-850eee57-891f-4480-9cce-c88b3b90070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012567413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3012567413
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3151414007
Short name T556
Test name
Test status
Simulation time 54466018 ps
CPU time 1.69 seconds
Started Aug 04 05:14:47 PM PDT 24
Finished Aug 04 05:14:49 PM PDT 24
Peak memory 209984 kb
Host smart-02cfd1d1-4d4d-4742-a908-6ff1427e5317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151414007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3151414007
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.4097903884
Short name T104
Test name
Test status
Simulation time 39126030 ps
CPU time 0.83 seconds
Started Aug 04 05:14:50 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 205856 kb
Host smart-b16ea51f-b16e-4a0b-a3c0-36b9a2cf103a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097903884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.4097903884
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1192558070
Short name T259
Test name
Test status
Simulation time 422674597 ps
CPU time 9.28 seconds
Started Aug 04 05:14:46 PM PDT 24
Finished Aug 04 05:14:55 PM PDT 24
Peak memory 222724 kb
Host smart-68e0c845-0498-47bc-980a-6fd46839d3ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192558070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1192558070
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2805437658
Short name T639
Test name
Test status
Simulation time 411914098 ps
CPU time 4.49 seconds
Started Aug 04 05:14:46 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 218752 kb
Host smart-01bc9f85-1b1c-4d45-9e98-73273e0ffc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805437658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2805437658
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.4234122
Short name T421
Test name
Test status
Simulation time 218022382 ps
CPU time 1.92 seconds
Started Aug 04 05:14:47 PM PDT 24
Finished Aug 04 05:14:49 PM PDT 24
Peak memory 207860 kb
Host smart-efc7671a-12e0-4598-9390-9c2f3aff4961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.4234122
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3747015062
Short name T689
Test name
Test status
Simulation time 614776883 ps
CPU time 2.12 seconds
Started Aug 04 05:14:48 PM PDT 24
Finished Aug 04 05:14:50 PM PDT 24
Peak memory 214248 kb
Host smart-f4c43522-a274-482a-942e-47824be00e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747015062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3747015062
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2854573851
Short name T591
Test name
Test status
Simulation time 517112171 ps
CPU time 11.23 seconds
Started Aug 04 05:14:50 PM PDT 24
Finished Aug 04 05:15:01 PM PDT 24
Peak memory 214572 kb
Host smart-dff4c9a8-5a5f-4f6b-8821-c2cf86a70751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854573851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2854573851
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1598783572
Short name T699
Test name
Test status
Simulation time 307335205 ps
CPU time 3.05 seconds
Started Aug 04 05:14:46 PM PDT 24
Finished Aug 04 05:14:49 PM PDT 24
Peak memory 214208 kb
Host smart-cdbf007b-9574-469c-8716-b49711ad5b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598783572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1598783572
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1487078522
Short name T508
Test name
Test status
Simulation time 253052219 ps
CPU time 3.24 seconds
Started Aug 04 05:14:48 PM PDT 24
Finished Aug 04 05:14:52 PM PDT 24
Peak memory 206844 kb
Host smart-fbca54cc-ecd6-414e-9483-84daf2a15b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487078522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1487078522
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2313706487
Short name T134
Test name
Test status
Simulation time 261679166 ps
CPU time 2.57 seconds
Started Aug 04 05:14:48 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 206580 kb
Host smart-a9b794ee-8fb4-4855-bfc3-73b4f12e21ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313706487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2313706487
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2663256446
Short name T544
Test name
Test status
Simulation time 383317113 ps
CPU time 4.54 seconds
Started Aug 04 05:14:45 PM PDT 24
Finished Aug 04 05:14:50 PM PDT 24
Peak memory 206992 kb
Host smart-85bab666-5006-4b2b-82f1-85cd37513aee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663256446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2663256446
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.482978381
Short name T856
Test name
Test status
Simulation time 235829965 ps
CPU time 3.19 seconds
Started Aug 04 05:14:48 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 207428 kb
Host smart-d71c416b-529e-40b1-83a4-47daf2334a89
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482978381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.482978381
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.968283018
Short name T782
Test name
Test status
Simulation time 295081100 ps
CPU time 3.32 seconds
Started Aug 04 05:14:50 PM PDT 24
Finished Aug 04 05:14:53 PM PDT 24
Peak memory 206772 kb
Host smart-3f72be93-e1ac-451b-b23f-eaf12f9d8bbe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968283018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.968283018
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4073069739
Short name T853
Test name
Test status
Simulation time 785491756 ps
CPU time 8.55 seconds
Started Aug 04 05:14:46 PM PDT 24
Finished Aug 04 05:14:54 PM PDT 24
Peak memory 208108 kb
Host smart-723db267-c56c-4acb-9081-ec1f94e4e764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073069739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4073069739
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3696454321
Short name T902
Test name
Test status
Simulation time 788325687 ps
CPU time 5.61 seconds
Started Aug 04 05:14:48 PM PDT 24
Finished Aug 04 05:14:54 PM PDT 24
Peak memory 206684 kb
Host smart-e94d87f9-fd18-4893-929b-8d05a07c3d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696454321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3696454321
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.988019833
Short name T793
Test name
Test status
Simulation time 2408396495 ps
CPU time 16.83 seconds
Started Aug 04 05:14:45 PM PDT 24
Finished Aug 04 05:15:02 PM PDT 24
Peak memory 218444 kb
Host smart-5981219b-e060-4f09-bff8-19ae93eabb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988019833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.988019833
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.104902258
Short name T40
Test name
Test status
Simulation time 102748272 ps
CPU time 1.83 seconds
Started Aug 04 05:14:45 PM PDT 24
Finished Aug 04 05:14:47 PM PDT 24
Peak memory 209844 kb
Host smart-5100c7ff-f594-46f9-8a0f-42a2a883899a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104902258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.104902258
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.852181387
Short name T763
Test name
Test status
Simulation time 25869107 ps
CPU time 0.91 seconds
Started Aug 04 05:14:50 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 206024 kb
Host smart-ca92e44b-ff9a-44cb-b356-9c9cf97533fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852181387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.852181387
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2513454979
Short name T388
Test name
Test status
Simulation time 910461317 ps
CPU time 30.23 seconds
Started Aug 04 05:14:50 PM PDT 24
Finished Aug 04 05:15:21 PM PDT 24
Peak memory 214340 kb
Host smart-286407e4-0d17-4ad8-9152-efe14f077787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513454979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2513454979
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3486454333
Short name T30
Test name
Test status
Simulation time 204173338 ps
CPU time 2.31 seconds
Started Aug 04 05:14:49 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 209360 kb
Host smart-2b9bba24-f5e2-4cc5-904b-abeb0a9599cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486454333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3486454333
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.941314463
Short name T679
Test name
Test status
Simulation time 487656834 ps
CPU time 3.53 seconds
Started Aug 04 05:14:50 PM PDT 24
Finished Aug 04 05:14:54 PM PDT 24
Peak memory 207384 kb
Host smart-f627c5a2-ae23-4500-9ab8-eaf4788cfa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941314463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.941314463
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.4108156735
Short name T592
Test name
Test status
Simulation time 230807938 ps
CPU time 5.48 seconds
Started Aug 04 05:15:04 PM PDT 24
Finished Aug 04 05:15:10 PM PDT 24
Peak memory 209424 kb
Host smart-39a2da31-12af-4aef-bea8-217554fcd725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108156735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.4108156735
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2496446007
Short name T315
Test name
Test status
Simulation time 99796153 ps
CPU time 3.4 seconds
Started Aug 04 05:14:50 PM PDT 24
Finished Aug 04 05:14:53 PM PDT 24
Peak memory 214460 kb
Host smart-3486fb88-12a8-44e3-9e30-c29dfdd23a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496446007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2496446007
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3201300337
Short name T744
Test name
Test status
Simulation time 79554168 ps
CPU time 2.97 seconds
Started Aug 04 05:15:04 PM PDT 24
Finished Aug 04 05:15:07 PM PDT 24
Peak memory 214312 kb
Host smart-c1abb4d4-1428-4f9e-96b1-9e50ec941c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201300337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3201300337
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.365085136
Short name T765
Test name
Test status
Simulation time 197807229 ps
CPU time 7.8 seconds
Started Aug 04 05:15:03 PM PDT 24
Finished Aug 04 05:15:11 PM PDT 24
Peak memory 208884 kb
Host smart-131405c2-0298-406d-ae83-19c930e21e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365085136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.365085136
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1186150622
Short name T527
Test name
Test status
Simulation time 16550736360 ps
CPU time 36.56 seconds
Started Aug 04 05:14:47 PM PDT 24
Finished Aug 04 05:15:24 PM PDT 24
Peak memory 208416 kb
Host smart-418e61da-5d66-46df-83fb-63d24ead391f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186150622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1186150622
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1807935551
Short name T579
Test name
Test status
Simulation time 451466831 ps
CPU time 9.03 seconds
Started Aug 04 05:14:50 PM PDT 24
Finished Aug 04 05:14:59 PM PDT 24
Peak memory 207248 kb
Host smart-18315ca3-55db-49fc-a0eb-93b7a01e7911
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807935551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1807935551
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.503328547
Short name T386
Test name
Test status
Simulation time 1251893652 ps
CPU time 31.3 seconds
Started Aug 04 05:14:51 PM PDT 24
Finished Aug 04 05:15:23 PM PDT 24
Peak memory 208808 kb
Host smart-063762cb-97c5-4dc4-8ad2-594e02d6ba35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503328547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.503328547
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1143366019
Short name T445
Test name
Test status
Simulation time 105531546 ps
CPU time 3 seconds
Started Aug 04 05:14:52 PM PDT 24
Finished Aug 04 05:14:55 PM PDT 24
Peak memory 206972 kb
Host smart-4e634a30-fe89-44c6-91ec-0e392b918002
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143366019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1143366019
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3058919289
Short name T500
Test name
Test status
Simulation time 485550878 ps
CPU time 4.23 seconds
Started Aug 04 05:14:50 PM PDT 24
Finished Aug 04 05:14:54 PM PDT 24
Peak memory 222316 kb
Host smart-282b8855-f6b3-4103-8444-d23fb4c9c449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058919289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3058919289
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1107718774
Short name T471
Test name
Test status
Simulation time 108902594 ps
CPU time 2.46 seconds
Started Aug 04 05:14:52 PM PDT 24
Finished Aug 04 05:14:55 PM PDT 24
Peak memory 206904 kb
Host smart-312f16d0-8b59-4d77-94e4-ed51ee457608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107718774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1107718774
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.6910973
Short name T624
Test name
Test status
Simulation time 3751465363 ps
CPU time 55.41 seconds
Started Aug 04 05:15:02 PM PDT 24
Finished Aug 04 05:15:58 PM PDT 24
Peak memory 222372 kb
Host smart-f535e638-0e7d-4427-aa40-ace9b61b1acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6910973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.6910973
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2233738266
Short name T794
Test name
Test status
Simulation time 233223922 ps
CPU time 3.91 seconds
Started Aug 04 05:15:04 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 207324 kb
Host smart-0bf99ef6-600c-44b0-8abc-9204fb2ad83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233738266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2233738266
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2095259194
Short name T783
Test name
Test status
Simulation time 121626515 ps
CPU time 2.29 seconds
Started Aug 04 05:15:03 PM PDT 24
Finished Aug 04 05:15:05 PM PDT 24
Peak memory 210072 kb
Host smart-2b8bde12-8296-4d04-b800-de400e731bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095259194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2095259194
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1085137969
Short name T519
Test name
Test status
Simulation time 12651941 ps
CPU time 0.78 seconds
Started Aug 04 05:14:54 PM PDT 24
Finished Aug 04 05:14:55 PM PDT 24
Peak memory 205956 kb
Host smart-df5464ff-d62a-4f69-b7d4-9c92664ec4af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085137969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1085137969
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2896422764
Short name T399
Test name
Test status
Simulation time 1143282723 ps
CPU time 54.94 seconds
Started Aug 04 05:14:53 PM PDT 24
Finished Aug 04 05:15:48 PM PDT 24
Peak memory 215052 kb
Host smart-ae79f9ca-9477-4116-a3a2-194f88cc599a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2896422764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2896422764
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3594147898
Short name T539
Test name
Test status
Simulation time 261964576 ps
CPU time 4.03 seconds
Started Aug 04 05:14:54 PM PDT 24
Finished Aug 04 05:14:58 PM PDT 24
Peak memory 218120 kb
Host smart-bdc990bd-2de7-4245-a591-30690dc4f65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594147898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3594147898
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3370584614
Short name T95
Test name
Test status
Simulation time 916393688 ps
CPU time 4.19 seconds
Started Aug 04 05:14:54 PM PDT 24
Finished Aug 04 05:14:58 PM PDT 24
Peak memory 209616 kb
Host smart-f91369a7-36f7-44b3-a05b-6bc9f34a4818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370584614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3370584614
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2958420103
Short name T893
Test name
Test status
Simulation time 63250511 ps
CPU time 3.02 seconds
Started Aug 04 05:14:55 PM PDT 24
Finished Aug 04 05:14:58 PM PDT 24
Peak memory 214224 kb
Host smart-03bdda03-1505-4d47-bc67-29fb97167f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958420103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2958420103
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3570924580
Short name T261
Test name
Test status
Simulation time 1951312241 ps
CPU time 6.53 seconds
Started Aug 04 05:14:54 PM PDT 24
Finished Aug 04 05:15:01 PM PDT 24
Peak memory 218484 kb
Host smart-a612e13a-2dae-44a4-9d60-25c64ffde0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570924580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3570924580
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2132103784
Short name T897
Test name
Test status
Simulation time 28106491 ps
CPU time 2.15 seconds
Started Aug 04 05:15:04 PM PDT 24
Finished Aug 04 05:15:06 PM PDT 24
Peak memory 208324 kb
Host smart-d846799d-17a0-49a1-937c-2ad2c820acbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132103784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2132103784
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.331443385
Short name T477
Test name
Test status
Simulation time 426903430 ps
CPU time 3.16 seconds
Started Aug 04 05:14:50 PM PDT 24
Finished Aug 04 05:14:53 PM PDT 24
Peak memory 206776 kb
Host smart-26794ae4-070a-489a-a99e-02051b23c662
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331443385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.331443385
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.295778122
Short name T444
Test name
Test status
Simulation time 74169045 ps
CPU time 2.83 seconds
Started Aug 04 05:14:53 PM PDT 24
Finished Aug 04 05:14:56 PM PDT 24
Peak memory 208676 kb
Host smart-f555eff5-a8d5-4dbf-ae10-eb81769ea0cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295778122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.295778122
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.528139383
Short name T429
Test name
Test status
Simulation time 7222751071 ps
CPU time 24.1 seconds
Started Aug 04 05:14:51 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 208816 kb
Host smart-5526e595-83a3-4375-8976-f38743dcb995
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528139383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.528139383
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3177051509
Short name T655
Test name
Test status
Simulation time 48284669 ps
CPU time 2.02 seconds
Started Aug 04 05:14:54 PM PDT 24
Finished Aug 04 05:14:56 PM PDT 24
Peak memory 214304 kb
Host smart-454fdeb9-1f50-4e88-a694-063868769f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177051509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3177051509
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.391029483
Short name T732
Test name
Test status
Simulation time 624702171 ps
CPU time 4.41 seconds
Started Aug 04 05:15:04 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 208540 kb
Host smart-0a8ecf0e-4a46-4736-b60f-8209a4ff9c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391029483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.391029483
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4278848058
Short name T795
Test name
Test status
Simulation time 315218263 ps
CPU time 8.74 seconds
Started Aug 04 05:14:52 PM PDT 24
Finished Aug 04 05:15:01 PM PDT 24
Peak memory 220968 kb
Host smart-beb29152-839e-4632-a31b-ee36b54590b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278848058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4278848058
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3225450119
Short name T291
Test name
Test status
Simulation time 235534154 ps
CPU time 4.9 seconds
Started Aug 04 05:14:54 PM PDT 24
Finished Aug 04 05:14:59 PM PDT 24
Peak memory 214208 kb
Host smart-f9848ea9-b242-4ced-a01a-a5e53aea389d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225450119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3225450119
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3073147034
Short name T169
Test name
Test status
Simulation time 1210467768 ps
CPU time 5.21 seconds
Started Aug 04 05:14:55 PM PDT 24
Finished Aug 04 05:15:01 PM PDT 24
Peak memory 210432 kb
Host smart-0dc8586d-9fc1-484c-ba26-555c270c44b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073147034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3073147034
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3962261491
Short name T745
Test name
Test status
Simulation time 18159810 ps
CPU time 0.9 seconds
Started Aug 04 05:15:00 PM PDT 24
Finished Aug 04 05:15:01 PM PDT 24
Peak memory 206148 kb
Host smart-1e183c9f-650e-461c-9bb5-f9707e324125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962261491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3962261491
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3124237119
Short name T271
Test name
Test status
Simulation time 139772440 ps
CPU time 8.44 seconds
Started Aug 04 05:14:56 PM PDT 24
Finished Aug 04 05:15:05 PM PDT 24
Peak memory 215448 kb
Host smart-343ce456-9f19-443f-8b30-4a75049c7b06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124237119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3124237119
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2026753633
Short name T807
Test name
Test status
Simulation time 63137164 ps
CPU time 2.85 seconds
Started Aug 04 05:14:53 PM PDT 24
Finished Aug 04 05:14:55 PM PDT 24
Peak memory 209640 kb
Host smart-876a36c6-142b-4b61-b8fa-497993b8ea7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026753633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2026753633
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1091899346
Short name T366
Test name
Test status
Simulation time 119755392 ps
CPU time 2.75 seconds
Started Aug 04 05:14:53 PM PDT 24
Finished Aug 04 05:14:56 PM PDT 24
Peak memory 214424 kb
Host smart-afde8ee8-5d25-45f5-b32e-b21394479cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091899346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1091899346
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1504829118
Short name T317
Test name
Test status
Simulation time 49667243 ps
CPU time 3.16 seconds
Started Aug 04 05:15:04 PM PDT 24
Finished Aug 04 05:15:07 PM PDT 24
Peak memory 214444 kb
Host smart-cdebd4e0-151f-4802-a5b8-5dac245b338f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504829118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1504829118
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.320759776
Short name T8
Test name
Test status
Simulation time 133181551 ps
CPU time 1.91 seconds
Started Aug 04 05:14:55 PM PDT 24
Finished Aug 04 05:14:57 PM PDT 24
Peak memory 214288 kb
Host smart-2f9142d7-e56a-43ca-baf3-902d843219bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320759776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.320759776
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2925984753
Short name T695
Test name
Test status
Simulation time 84237785 ps
CPU time 4.21 seconds
Started Aug 04 05:14:55 PM PDT 24
Finished Aug 04 05:15:00 PM PDT 24
Peak memory 207532 kb
Host smart-21ea043b-8fa3-47c9-8e9d-0a00b79b929b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925984753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2925984753
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1658061549
Short name T496
Test name
Test status
Simulation time 44414343 ps
CPU time 2.47 seconds
Started Aug 04 05:14:54 PM PDT 24
Finished Aug 04 05:14:57 PM PDT 24
Peak memory 208472 kb
Host smart-8702e6ea-5f34-45d5-8b68-87ac3b14737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658061549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1658061549
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1397725449
Short name T548
Test name
Test status
Simulation time 512074564 ps
CPU time 18.49 seconds
Started Aug 04 05:14:53 PM PDT 24
Finished Aug 04 05:15:11 PM PDT 24
Peak memory 208300 kb
Host smart-0694516b-049c-410c-88a2-a8d4714f2510
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397725449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1397725449
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3355231982
Short name T416
Test name
Test status
Simulation time 147362388 ps
CPU time 3.69 seconds
Started Aug 04 05:14:52 PM PDT 24
Finished Aug 04 05:14:56 PM PDT 24
Peak memory 208828 kb
Host smart-fe59440a-6360-459f-b06d-2ee3ca1b0345
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355231982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3355231982
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3707893719
Short name T536
Test name
Test status
Simulation time 564935664 ps
CPU time 4.47 seconds
Started Aug 04 05:14:56 PM PDT 24
Finished Aug 04 05:15:01 PM PDT 24
Peak memory 208484 kb
Host smart-e9a6ed54-3549-4672-857c-73cc6a88db84
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707893719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3707893719
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2046657301
Short name T368
Test name
Test status
Simulation time 64403505 ps
CPU time 3.07 seconds
Started Aug 04 05:14:52 PM PDT 24
Finished Aug 04 05:14:56 PM PDT 24
Peak memory 214324 kb
Host smart-4a9beb1d-3f77-43b4-8216-f004c10aab9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046657301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2046657301
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3984022179
Short name T383
Test name
Test status
Simulation time 4319892109 ps
CPU time 25.89 seconds
Started Aug 04 05:14:54 PM PDT 24
Finished Aug 04 05:15:20 PM PDT 24
Peak memory 208124 kb
Host smart-5b690eaa-639d-4ecf-91ef-96f0c893531d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984022179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3984022179
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.394343531
Short name T328
Test name
Test status
Simulation time 389031049 ps
CPU time 10.85 seconds
Started Aug 04 05:14:57 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 214720 kb
Host smart-7a6b57e1-6793-4640-b1cb-588a3c2ab2b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394343531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.394343531
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3875217534
Short name T184
Test name
Test status
Simulation time 541452616 ps
CPU time 15.36 seconds
Started Aug 04 05:14:57 PM PDT 24
Finished Aug 04 05:15:13 PM PDT 24
Peak memory 222580 kb
Host smart-6b12d4da-6390-416d-990d-fa2bb0466b69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875217534 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3875217534
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2538048291
Short name T858
Test name
Test status
Simulation time 74750814 ps
CPU time 4.18 seconds
Started Aug 04 05:14:55 PM PDT 24
Finished Aug 04 05:14:59 PM PDT 24
Peak memory 208940 kb
Host smart-c3290276-3ec4-4a45-929b-9dbce4aba114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538048291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2538048291
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1101585476
Short name T778
Test name
Test status
Simulation time 170287300 ps
CPU time 2.4 seconds
Started Aug 04 05:14:53 PM PDT 24
Finished Aug 04 05:14:56 PM PDT 24
Peak memory 209748 kb
Host smart-b743f44c-f31a-4ed0-bb9e-b7e65cf0149b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101585476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1101585476
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.4216953180
Short name T473
Test name
Test status
Simulation time 89188571 ps
CPU time 0.99 seconds
Started Aug 04 05:15:01 PM PDT 24
Finished Aug 04 05:15:02 PM PDT 24
Peak memory 206112 kb
Host smart-76e21926-cb20-4cb4-8249-04649f6b8a04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216953180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.4216953180
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2047732274
Short name T380
Test name
Test status
Simulation time 92804793 ps
CPU time 3.39 seconds
Started Aug 04 05:15:00 PM PDT 24
Finished Aug 04 05:15:03 PM PDT 24
Peak memory 214220 kb
Host smart-589fd61f-027a-4a05-827c-ec9875681d8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2047732274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2047732274
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.4007159253
Short name T810
Test name
Test status
Simulation time 84699135 ps
CPU time 2.09 seconds
Started Aug 04 05:14:57 PM PDT 24
Finished Aug 04 05:14:59 PM PDT 24
Peak memory 209348 kb
Host smart-9dbe8aaa-eb6c-4e41-9281-2ac8c5b44ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007159253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.4007159253
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1357827290
Short name T362
Test name
Test status
Simulation time 79875217 ps
CPU time 1.74 seconds
Started Aug 04 05:14:59 PM PDT 24
Finished Aug 04 05:15:01 PM PDT 24
Peak memory 208092 kb
Host smart-a7223f91-2a9b-492a-92e4-e0e696882f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357827290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1357827290
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1366561944
Short name T297
Test name
Test status
Simulation time 87102942 ps
CPU time 2.87 seconds
Started Aug 04 05:14:57 PM PDT 24
Finished Aug 04 05:15:00 PM PDT 24
Peak memory 214224 kb
Host smart-9cf0dcd9-5abb-4b18-bbf7-97d2f829f376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366561944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1366561944
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1492644427
Short name T286
Test name
Test status
Simulation time 144516118 ps
CPU time 2.3 seconds
Started Aug 04 05:14:58 PM PDT 24
Finished Aug 04 05:15:01 PM PDT 24
Peak memory 221540 kb
Host smart-3e1ccfc8-c094-4c45-9e7a-be64a7c4451f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492644427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1492644427
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2211538982
Short name T776
Test name
Test status
Simulation time 268303601 ps
CPU time 3.23 seconds
Started Aug 04 05:14:59 PM PDT 24
Finished Aug 04 05:15:02 PM PDT 24
Peak memory 209788 kb
Host smart-f62be30c-682b-472a-8b26-7e66f1fcb1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211538982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2211538982
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3526168452
Short name T626
Test name
Test status
Simulation time 445822387 ps
CPU time 4.76 seconds
Started Aug 04 05:14:57 PM PDT 24
Finished Aug 04 05:15:02 PM PDT 24
Peak memory 208824 kb
Host smart-cb7a029e-4f45-473c-ad77-e610ddd23d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526168452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3526168452
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1650091646
Short name T687
Test name
Test status
Simulation time 740873337 ps
CPU time 5.37 seconds
Started Aug 04 05:15:00 PM PDT 24
Finished Aug 04 05:15:06 PM PDT 24
Peak memory 208056 kb
Host smart-8c3b2992-2517-4726-b574-8f5336c9129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650091646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1650091646
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2912994808
Short name T486
Test name
Test status
Simulation time 82370804 ps
CPU time 3.74 seconds
Started Aug 04 05:15:01 PM PDT 24
Finished Aug 04 05:15:04 PM PDT 24
Peak memory 208928 kb
Host smart-8aade361-95e8-404c-a2de-eb123272afd9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912994808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2912994808
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3902175318
Short name T845
Test name
Test status
Simulation time 104536455 ps
CPU time 4.7 seconds
Started Aug 04 05:15:00 PM PDT 24
Finished Aug 04 05:15:05 PM PDT 24
Peak memory 208584 kb
Host smart-7fd89405-0d67-4a5a-ab05-63602f4aa67f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902175318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3902175318
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2468011640
Short name T468
Test name
Test status
Simulation time 365421029 ps
CPU time 3.74 seconds
Started Aug 04 05:15:00 PM PDT 24
Finished Aug 04 05:15:04 PM PDT 24
Peak memory 214248 kb
Host smart-62a27028-bde2-43bd-9ee7-5ca3ac01dc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468011640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2468011640
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2078101104
Short name T447
Test name
Test status
Simulation time 3427137600 ps
CPU time 4.49 seconds
Started Aug 04 05:14:59 PM PDT 24
Finished Aug 04 05:15:04 PM PDT 24
Peak memory 207900 kb
Host smart-38a046f2-cc18-4d6c-abad-c7ea76efab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078101104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2078101104
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.931304872
Short name T225
Test name
Test status
Simulation time 10884048924 ps
CPU time 206.32 seconds
Started Aug 04 05:14:58 PM PDT 24
Finished Aug 04 05:18:24 PM PDT 24
Peak memory 218520 kb
Host smart-355ed944-7852-4437-9e79-f67b3a79fdcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931304872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.931304872
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3998480395
Short name T822
Test name
Test status
Simulation time 561360662 ps
CPU time 5.3 seconds
Started Aug 04 05:14:59 PM PDT 24
Finished Aug 04 05:15:05 PM PDT 24
Peak memory 209900 kb
Host smart-cbf71b50-25eb-4a4b-9698-3038bedcc40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998480395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3998480395
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2072785587
Short name T423
Test name
Test status
Simulation time 49183523 ps
CPU time 1.36 seconds
Started Aug 04 05:14:58 PM PDT 24
Finished Aug 04 05:14:59 PM PDT 24
Peak memory 208852 kb
Host smart-7e5334c5-19ca-4125-9238-9107f94c6ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072785587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2072785587
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.822815190
Short name T489
Test name
Test status
Simulation time 10458703 ps
CPU time 0.84 seconds
Started Aug 04 05:15:03 PM PDT 24
Finished Aug 04 05:15:04 PM PDT 24
Peak memory 205836 kb
Host smart-197e8626-b7a4-4e3c-a8e2-4b0f3c15ffb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822815190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.822815190
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2709700348
Short name T381
Test name
Test status
Simulation time 117144472 ps
CPU time 2.72 seconds
Started Aug 04 05:14:59 PM PDT 24
Finished Aug 04 05:15:01 PM PDT 24
Peak memory 214272 kb
Host smart-2278638a-e872-49b1-8645-7aba55460e39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2709700348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2709700348
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.959382318
Short name T663
Test name
Test status
Simulation time 37488196 ps
CPU time 2.18 seconds
Started Aug 04 05:15:03 PM PDT 24
Finished Aug 04 05:15:06 PM PDT 24
Peak memory 214284 kb
Host smart-820218bc-11b5-4f34-bb36-10fbe79781b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959382318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.959382318
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2651091149
Short name T99
Test name
Test status
Simulation time 109067039 ps
CPU time 2.32 seconds
Started Aug 04 05:14:59 PM PDT 24
Finished Aug 04 05:15:02 PM PDT 24
Peak memory 208776 kb
Host smart-f22ed1cf-08de-4acb-8edd-8ca06d87cbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651091149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2651091149
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1286567812
Short name T343
Test name
Test status
Simulation time 238377369 ps
CPU time 4.75 seconds
Started Aug 04 05:15:03 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 222548 kb
Host smart-e0ed52d1-1816-44ad-ac0a-efddff625297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286567812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1286567812
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2048657451
Short name T65
Test name
Test status
Simulation time 106910256 ps
CPU time 3.77 seconds
Started Aug 04 05:15:03 PM PDT 24
Finished Aug 04 05:15:07 PM PDT 24
Peak memory 218344 kb
Host smart-40418c24-7cb2-4bbf-9593-70bfb2656af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048657451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2048657451
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.934177001
Short name T691
Test name
Test status
Simulation time 109296966 ps
CPU time 2.31 seconds
Started Aug 04 05:14:58 PM PDT 24
Finished Aug 04 05:15:00 PM PDT 24
Peak memory 207020 kb
Host smart-69ae659a-74ba-4cb3-a719-8b060463d151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934177001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.934177001
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.4859643
Short name T355
Test name
Test status
Simulation time 35073609 ps
CPU time 2.29 seconds
Started Aug 04 05:14:57 PM PDT 24
Finished Aug 04 05:14:59 PM PDT 24
Peak memory 206752 kb
Host smart-2f1a4b6b-7ff5-4ebb-94a0-2e47ed4dd9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4859643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4859643
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3183281841
Short name T424
Test name
Test status
Simulation time 1373576019 ps
CPU time 4.77 seconds
Started Aug 04 05:14:57 PM PDT 24
Finished Aug 04 05:15:02 PM PDT 24
Peak memory 207964 kb
Host smart-e681be00-e513-4c0d-b1f9-a3deb154a7e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183281841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3183281841
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3017057620
Short name T612
Test name
Test status
Simulation time 1311794410 ps
CPU time 3.5 seconds
Started Aug 04 05:15:00 PM PDT 24
Finished Aug 04 05:15:03 PM PDT 24
Peak memory 208764 kb
Host smart-5686b6e8-a73f-4b44-be44-1537c074d31a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017057620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3017057620
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.989663924
Short name T218
Test name
Test status
Simulation time 357985726 ps
CPU time 3.63 seconds
Started Aug 04 05:15:04 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 208580 kb
Host smart-8ab50336-ab1b-4eca-9a0f-d8f4cb289c05
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989663924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.989663924
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3657351221
Short name T903
Test name
Test status
Simulation time 826052208 ps
CPU time 3.93 seconds
Started Aug 04 05:15:03 PM PDT 24
Finished Aug 04 05:15:07 PM PDT 24
Peak memory 208060 kb
Host smart-4c382238-01a5-4a46-99bc-5e8b99b8a2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657351221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3657351221
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2117357263
Short name T491
Test name
Test status
Simulation time 5861579348 ps
CPU time 15.76 seconds
Started Aug 04 05:15:00 PM PDT 24
Finished Aug 04 05:15:16 PM PDT 24
Peak memory 208344 kb
Host smart-a7ea7da7-e965-4768-8104-edd86b449f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117357263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2117357263
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1985143941
Short name T235
Test name
Test status
Simulation time 1285779867 ps
CPU time 49.46 seconds
Started Aug 04 05:15:01 PM PDT 24
Finished Aug 04 05:15:50 PM PDT 24
Peak memory 222524 kb
Host smart-0a9782d8-a266-47bc-aeaa-e4f2f3eff3a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985143941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1985143941
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.883809378
Short name T181
Test name
Test status
Simulation time 1338472071 ps
CPU time 12.18 seconds
Started Aug 04 05:15:02 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 222444 kb
Host smart-3ea68868-ac86-4840-949f-4cce7038a655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883809378 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.883809378
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.387658169
Short name T457
Test name
Test status
Simulation time 130262144 ps
CPU time 4.76 seconds
Started Aug 04 05:15:04 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 207644 kb
Host smart-8fcd6810-5743-4f85-ba13-31e3ee06cf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387658169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.387658169
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1982884206
Short name T629
Test name
Test status
Simulation time 35347643 ps
CPU time 2.22 seconds
Started Aug 04 05:15:01 PM PDT 24
Finished Aug 04 05:15:03 PM PDT 24
Peak memory 209856 kb
Host smart-15f3daf9-4be6-40fb-83c0-ce2717366626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982884206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1982884206
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1713930455
Short name T606
Test name
Test status
Simulation time 54711504 ps
CPU time 0.79 seconds
Started Aug 04 05:13:10 PM PDT 24
Finished Aug 04 05:13:11 PM PDT 24
Peak memory 205932 kb
Host smart-e5ec2648-4761-4146-8eb1-0d6b7ef6310e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713930455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1713930455
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2343189716
Short name T32
Test name
Test status
Simulation time 142819193 ps
CPU time 2.74 seconds
Started Aug 04 05:13:11 PM PDT 24
Finished Aug 04 05:13:14 PM PDT 24
Peak memory 221460 kb
Host smart-0365fe58-07fd-4777-a9b9-641ddc0bf7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343189716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2343189716
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2499621303
Short name T913
Test name
Test status
Simulation time 98062359 ps
CPU time 2.12 seconds
Started Aug 04 05:13:07 PM PDT 24
Finished Aug 04 05:13:09 PM PDT 24
Peak memory 208672 kb
Host smart-3e5274ee-45d3-4c22-bd23-35a451401422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499621303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2499621303
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1365616877
Short name T596
Test name
Test status
Simulation time 1938195717 ps
CPU time 7.97 seconds
Started Aug 04 05:13:10 PM PDT 24
Finished Aug 04 05:13:19 PM PDT 24
Peak memory 214220 kb
Host smart-15a7898b-0d6f-4210-8101-8a932e7249ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365616877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1365616877
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.4128536510
Short name T300
Test name
Test status
Simulation time 72528613 ps
CPU time 2.23 seconds
Started Aug 04 05:13:10 PM PDT 24
Finished Aug 04 05:13:12 PM PDT 24
Peak memory 214160 kb
Host smart-6734bd10-2750-4b98-8cf4-3f884f0a43f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128536510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.4128536510
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2707415366
Short name T393
Test name
Test status
Simulation time 493849575 ps
CPU time 2.46 seconds
Started Aug 04 05:13:08 PM PDT 24
Finished Aug 04 05:13:11 PM PDT 24
Peak memory 206736 kb
Host smart-cb5c8083-2bde-43f9-913a-79f3a4aa0d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707415366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2707415366
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.860543880
Short name T518
Test name
Test status
Simulation time 124360490 ps
CPU time 6 seconds
Started Aug 04 05:13:06 PM PDT 24
Finished Aug 04 05:13:12 PM PDT 24
Peak memory 214264 kb
Host smart-37636c26-bee0-4efc-959c-f5a7d6c70abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860543880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.860543880
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.948018450
Short name T41
Test name
Test status
Simulation time 973613068 ps
CPU time 9.21 seconds
Started Aug 04 05:13:10 PM PDT 24
Finished Aug 04 05:13:20 PM PDT 24
Peak memory 237296 kb
Host smart-cb5fde1f-a051-4207-9a69-cafea4708f58
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948018450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.948018450
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2284859264
Short name T325
Test name
Test status
Simulation time 506974858 ps
CPU time 4.41 seconds
Started Aug 04 05:13:06 PM PDT 24
Finished Aug 04 05:13:11 PM PDT 24
Peak memory 208520 kb
Host smart-16969555-1476-483e-b5c2-c41c2a9ff9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284859264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2284859264
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.968075755
Short name T437
Test name
Test status
Simulation time 199550427 ps
CPU time 4.26 seconds
Started Aug 04 05:13:06 PM PDT 24
Finished Aug 04 05:13:10 PM PDT 24
Peak memory 206856 kb
Host smart-7e709839-a216-48da-a85c-51f18514ee22
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968075755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.968075755
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4197069158
Short name T874
Test name
Test status
Simulation time 260169390 ps
CPU time 2.51 seconds
Started Aug 04 05:13:06 PM PDT 24
Finished Aug 04 05:13:09 PM PDT 24
Peak memory 206824 kb
Host smart-f7aaefb5-ade2-448d-9885-69ba7a8a37e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197069158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4197069158
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.867367964
Short name T690
Test name
Test status
Simulation time 878491052 ps
CPU time 4.59 seconds
Started Aug 04 05:13:06 PM PDT 24
Finished Aug 04 05:13:11 PM PDT 24
Peak memory 208128 kb
Host smart-5febb88f-de01-4e67-b402-953fa21f7b8d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867367964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.867367964
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3541383438
Short name T613
Test name
Test status
Simulation time 3313399826 ps
CPU time 16.41 seconds
Started Aug 04 05:13:08 PM PDT 24
Finished Aug 04 05:13:25 PM PDT 24
Peak memory 209112 kb
Host smart-5b684187-38a3-4123-95d4-f326da11d5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541383438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3541383438
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3539596963
Short name T462
Test name
Test status
Simulation time 703536509 ps
CPU time 4.52 seconds
Started Aug 04 05:13:06 PM PDT 24
Finished Aug 04 05:13:11 PM PDT 24
Peak memory 207676 kb
Host smart-7a3584f2-8bc6-4b67-92a1-706378c00b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539596963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3539596963
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.972680325
Short name T873
Test name
Test status
Simulation time 413207321 ps
CPU time 4.28 seconds
Started Aug 04 05:13:11 PM PDT 24
Finished Aug 04 05:13:16 PM PDT 24
Peak memory 207876 kb
Host smart-f88940f8-438b-48e6-8a92-dced7f0b3960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972680325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.972680325
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.35819153
Short name T673
Test name
Test status
Simulation time 370560299 ps
CPU time 4.54 seconds
Started Aug 04 05:13:07 PM PDT 24
Finished Aug 04 05:13:12 PM PDT 24
Peak memory 207312 kb
Host smart-f47ce302-357f-4597-9d4d-71c67875c057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35819153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.35819153
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.259305946
Short name T138
Test name
Test status
Simulation time 272392718 ps
CPU time 2.79 seconds
Started Aug 04 05:13:09 PM PDT 24
Finished Aug 04 05:13:12 PM PDT 24
Peak memory 210032 kb
Host smart-9f08644d-7543-4437-967b-8d7d698e7c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259305946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.259305946
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.969686475
Short name T829
Test name
Test status
Simulation time 44982476 ps
CPU time 0.9 seconds
Started Aug 04 05:15:06 PM PDT 24
Finished Aug 04 05:15:07 PM PDT 24
Peak memory 205860 kb
Host smart-5d503cb2-b324-4175-8676-aed936db99a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969686475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.969686475
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3429806937
Short name T22
Test name
Test status
Simulation time 83593350 ps
CPU time 2.3 seconds
Started Aug 04 05:15:03 PM PDT 24
Finished Aug 04 05:15:05 PM PDT 24
Peak memory 221020 kb
Host smart-a5c5294b-5f00-439a-a4f4-db1ff229d633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429806937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3429806937
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1115009773
Short name T846
Test name
Test status
Simulation time 645972123 ps
CPU time 4.73 seconds
Started Aug 04 05:15:00 PM PDT 24
Finished Aug 04 05:15:05 PM PDT 24
Peak memory 214316 kb
Host smart-e3abd710-bde4-41ea-b899-e905f1224b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115009773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1115009773
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.29085558
Short name T314
Test name
Test status
Simulation time 87134588 ps
CPU time 3.03 seconds
Started Aug 04 05:15:00 PM PDT 24
Finished Aug 04 05:15:03 PM PDT 24
Peak memory 214200 kb
Host smart-930ac105-bf3b-4a7e-a01f-6984abd21982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29085558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.29085558
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.4204924716
Short name T35
Test name
Test status
Simulation time 550007444 ps
CPU time 4.94 seconds
Started Aug 04 05:15:01 PM PDT 24
Finished Aug 04 05:15:06 PM PDT 24
Peak memory 222412 kb
Host smart-1bef47bf-2342-4ca7-9f5c-8d05042d8aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204924716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.4204924716
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3524954652
Short name T838
Test name
Test status
Simulation time 282052500 ps
CPU time 3.35 seconds
Started Aug 04 05:15:01 PM PDT 24
Finished Aug 04 05:15:05 PM PDT 24
Peak memory 207000 kb
Host smart-0d1c85fc-f71c-4328-b068-a35be0f3c036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524954652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3524954652
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1603970239
Short name T266
Test name
Test status
Simulation time 372465316 ps
CPU time 5.93 seconds
Started Aug 04 05:15:00 PM PDT 24
Finished Aug 04 05:15:07 PM PDT 24
Peak memory 209880 kb
Host smart-6af69b07-d933-4e85-a426-3636c83d9df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603970239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1603970239
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1605950635
Short name T813
Test name
Test status
Simulation time 178238404 ps
CPU time 4.16 seconds
Started Aug 04 05:15:03 PM PDT 24
Finished Aug 04 05:15:07 PM PDT 24
Peak memory 206876 kb
Host smart-b9c3905e-9c27-42f7-afb1-052c89fbf3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605950635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1605950635
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3695007094
Short name T108
Test name
Test status
Simulation time 636663807 ps
CPU time 20.25 seconds
Started Aug 04 05:15:04 PM PDT 24
Finished Aug 04 05:15:24 PM PDT 24
Peak memory 208004 kb
Host smart-554645bb-6535-4984-b5e8-3a0cdf509862
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695007094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3695007094
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.52794138
Short name T877
Test name
Test status
Simulation time 60885369 ps
CPU time 2.41 seconds
Started Aug 04 05:15:01 PM PDT 24
Finished Aug 04 05:15:03 PM PDT 24
Peak memory 206824 kb
Host smart-965ecc1d-6fc2-4a37-835e-b111fef7a227
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52794138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.52794138
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3527389223
Short name T449
Test name
Test status
Simulation time 429758092 ps
CPU time 5.1 seconds
Started Aug 04 05:15:03 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 207060 kb
Host smart-8db68467-4651-450b-9d7a-dbf947a97c03
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527389223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3527389223
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3124467218
Short name T525
Test name
Test status
Simulation time 219005048 ps
CPU time 5.97 seconds
Started Aug 04 05:15:02 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 215884 kb
Host smart-6ec729e8-faca-4a46-b4c7-ab6ae26b03c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124467218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3124467218
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2209521216
Short name T788
Test name
Test status
Simulation time 157602089 ps
CPU time 3.53 seconds
Started Aug 04 05:15:03 PM PDT 24
Finished Aug 04 05:15:06 PM PDT 24
Peak memory 208468 kb
Host smart-7748b182-b0fb-4f95-90db-9d9bf7d35c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209521216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2209521216
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.4096638595
Short name T640
Test name
Test status
Simulation time 422584507 ps
CPU time 4.29 seconds
Started Aug 04 05:15:01 PM PDT 24
Finished Aug 04 05:15:05 PM PDT 24
Peak memory 207508 kb
Host smart-cc7d3d91-1169-4fb6-902f-2bd05b9d4a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096638595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.4096638595
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.380812334
Short name T808
Test name
Test status
Simulation time 72634010 ps
CPU time 2.69 seconds
Started Aug 04 05:15:01 PM PDT 24
Finished Aug 04 05:15:04 PM PDT 24
Peak memory 210312 kb
Host smart-a5078139-4f35-4fe4-a23e-95e2d62aa032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380812334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.380812334
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2122797176
Short name T654
Test name
Test status
Simulation time 18711261 ps
CPU time 0.81 seconds
Started Aug 04 05:15:09 PM PDT 24
Finished Aug 04 05:15:10 PM PDT 24
Peak memory 205936 kb
Host smart-23f97c69-09c5-45e3-9ea9-9bb0c26cdea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122797176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2122797176
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.161065458
Short name T398
Test name
Test status
Simulation time 149194864 ps
CPU time 5.09 seconds
Started Aug 04 05:15:07 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 214228 kb
Host smart-75ca34a7-ad6d-4f9f-80a2-e685f086d847
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161065458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.161065458
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1463260982
Short name T710
Test name
Test status
Simulation time 94828840 ps
CPU time 4.41 seconds
Started Aug 04 05:15:07 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 210316 kb
Host smart-1d30c992-bbae-41eb-a846-8e2f666de2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463260982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1463260982
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2568064550
Short name T719
Test name
Test status
Simulation time 531059264 ps
CPU time 2.5 seconds
Started Aug 04 05:15:05 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 207452 kb
Host smart-4ad3dbbd-857f-462b-a261-81c5b2c0d17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568064550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2568064550
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1327647988
Short name T102
Test name
Test status
Simulation time 79594535 ps
CPU time 3.03 seconds
Started Aug 04 05:15:05 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 222504 kb
Host smart-0283aab2-2d8c-4ec3-b450-6f866191fd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327647988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1327647988
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.724382654
Short name T427
Test name
Test status
Simulation time 119448424 ps
CPU time 2.32 seconds
Started Aug 04 05:15:08 PM PDT 24
Finished Aug 04 05:15:10 PM PDT 24
Peak memory 208552 kb
Host smart-ef6aea6d-32d5-4ecd-999f-c9c1aa7a983f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724382654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.724382654
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1246679901
Short name T824
Test name
Test status
Simulation time 200408230 ps
CPU time 3.48 seconds
Started Aug 04 05:15:08 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 207628 kb
Host smart-3d9944c9-a999-4805-a5d8-4d7584c2d1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246679901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1246679901
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2310481216
Short name T301
Test name
Test status
Simulation time 176469371 ps
CPU time 3.34 seconds
Started Aug 04 05:15:05 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 208844 kb
Host smart-3ef60086-415a-4242-b606-4964e5be844f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310481216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2310481216
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2863275608
Short name T562
Test name
Test status
Simulation time 3440207630 ps
CPU time 23.28 seconds
Started Aug 04 05:15:06 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 206748 kb
Host smart-5a9c1a34-4c18-457d-b47d-9a8403d0840f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863275608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2863275608
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.417954383
Short name T494
Test name
Test status
Simulation time 67607415 ps
CPU time 2.46 seconds
Started Aug 04 05:15:04 PM PDT 24
Finished Aug 04 05:15:07 PM PDT 24
Peak memory 208676 kb
Host smart-f522a136-5acc-4f67-a373-47c3c5edba6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417954383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.417954383
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1888624730
Short name T451
Test name
Test status
Simulation time 33216033 ps
CPU time 2.44 seconds
Started Aug 04 05:15:12 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 208676 kb
Host smart-93b37070-5f67-465f-ab09-5398f13ba8db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888624730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1888624730
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1432439036
Short name T747
Test name
Test status
Simulation time 59023331 ps
CPU time 1.99 seconds
Started Aug 04 05:15:06 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 207448 kb
Host smart-c5462b50-6c20-41ff-b9d2-17566fed493e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432439036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1432439036
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.621005051
Short name T501
Test name
Test status
Simulation time 538614912 ps
CPU time 5.3 seconds
Started Aug 04 05:15:04 PM PDT 24
Finished Aug 04 05:15:09 PM PDT 24
Peak memory 206796 kb
Host smart-4cc78c55-6822-4e38-b4af-973157530fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621005051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.621005051
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3364870998
Short name T226
Test name
Test status
Simulation time 619471276 ps
CPU time 26.68 seconds
Started Aug 04 05:15:08 PM PDT 24
Finished Aug 04 05:15:35 PM PDT 24
Peak memory 222608 kb
Host smart-be573ab8-4b75-4348-ab21-6c4c6bbad607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364870998 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3364870998
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.641381268
Short name T260
Test name
Test status
Simulation time 11984310116 ps
CPU time 56.85 seconds
Started Aug 04 05:15:07 PM PDT 24
Finished Aug 04 05:16:04 PM PDT 24
Peak memory 209308 kb
Host smart-03a6cfdb-0f77-450b-8ed8-f640c0be7697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641381268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.641381268
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2318169769
Short name T781
Test name
Test status
Simulation time 88181667 ps
CPU time 1.81 seconds
Started Aug 04 05:15:06 PM PDT 24
Finished Aug 04 05:15:08 PM PDT 24
Peak memory 209960 kb
Host smart-8ff4bbdf-17d0-46e8-af6e-8654bb125206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318169769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2318169769
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2817238025
Short name T402
Test name
Test status
Simulation time 37954392 ps
CPU time 0.71 seconds
Started Aug 04 05:15:08 PM PDT 24
Finished Aug 04 05:15:09 PM PDT 24
Peak memory 205976 kb
Host smart-e3352e94-f728-4a0c-ae87-3c4960b76250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817238025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2817238025
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3301658525
Short name T746
Test name
Test status
Simulation time 265553275 ps
CPU time 3.49 seconds
Started Aug 04 05:15:10 PM PDT 24
Finished Aug 04 05:15:13 PM PDT 24
Peak memory 216932 kb
Host smart-09d084b3-6d95-4fa3-a339-40c57b5e68ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301658525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3301658525
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3203119174
Short name T601
Test name
Test status
Simulation time 302209323 ps
CPU time 2.78 seconds
Started Aug 04 05:15:07 PM PDT 24
Finished Aug 04 05:15:10 PM PDT 24
Peak memory 207856 kb
Host smart-2d9a45eb-69d7-4af7-a70b-ed7ff90119d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203119174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3203119174
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.287139938
Short name T898
Test name
Test status
Simulation time 29758744 ps
CPU time 2.26 seconds
Started Aug 04 05:15:07 PM PDT 24
Finished Aug 04 05:15:09 PM PDT 24
Peak memory 214320 kb
Host smart-1e05b1b9-8798-4035-a7c8-f1976372bcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287139938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.287139938
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1441886666
Short name T223
Test name
Test status
Simulation time 65996492 ps
CPU time 2.54 seconds
Started Aug 04 05:15:12 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 214392 kb
Host smart-0522f599-6f02-460f-bc3e-b1649aa0d5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441886666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1441886666
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3193215148
Short name T520
Test name
Test status
Simulation time 127670064 ps
CPU time 5.5 seconds
Started Aug 04 05:15:12 PM PDT 24
Finished Aug 04 05:15:18 PM PDT 24
Peak memory 218388 kb
Host smart-5091d9cb-2a31-40d4-82b3-19ae7f9fb977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193215148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3193215148
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.236854676
Short name T867
Test name
Test status
Simulation time 108184557 ps
CPU time 2.63 seconds
Started Aug 04 05:15:08 PM PDT 24
Finished Aug 04 05:15:10 PM PDT 24
Peak memory 207536 kb
Host smart-f5ec751c-680c-4bc6-ada3-0298ca0f09ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236854676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.236854676
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2848113370
Short name T634
Test name
Test status
Simulation time 162259545 ps
CPU time 4.81 seconds
Started Aug 04 05:15:10 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 208844 kb
Host smart-2a08e76d-56a5-47c5-a4a3-6dce0d51f6aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848113370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2848113370
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2399559248
Short name T201
Test name
Test status
Simulation time 134524996 ps
CPU time 3.02 seconds
Started Aug 04 05:15:10 PM PDT 24
Finished Aug 04 05:15:13 PM PDT 24
Peak memory 208812 kb
Host smart-96f5751f-c2a2-410e-8ba5-f8c6ceab99d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399559248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2399559248
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1728432580
Short name T666
Test name
Test status
Simulation time 68709089 ps
CPU time 2.46 seconds
Started Aug 04 05:15:10 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 209272 kb
Host smart-747b072f-864c-4e5e-a956-9e456d5c5e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728432580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1728432580
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4186783710
Short name T549
Test name
Test status
Simulation time 135500879 ps
CPU time 2.5 seconds
Started Aug 04 05:15:06 PM PDT 24
Finished Aug 04 05:15:09 PM PDT 24
Peak memory 205968 kb
Host smart-fb127257-e3a1-4d82-ae6a-9ab665dfd2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186783710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4186783710
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.4023720079
Short name T114
Test name
Test status
Simulation time 185502921 ps
CPU time 10.42 seconds
Started Aug 04 05:15:08 PM PDT 24
Finished Aug 04 05:15:18 PM PDT 24
Peak memory 222432 kb
Host smart-8a80426f-5216-4211-a657-1f0dc5b5333a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023720079 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.4023720079
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3541098471
Short name T587
Test name
Test status
Simulation time 116653468 ps
CPU time 5.47 seconds
Started Aug 04 05:15:06 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 208648 kb
Host smart-6351c7bf-7f41-44ca-b4fa-90a810e3d7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541098471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3541098471
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3862985582
Short name T583
Test name
Test status
Simulation time 5598405483 ps
CPU time 23.14 seconds
Started Aug 04 05:15:09 PM PDT 24
Finished Aug 04 05:15:32 PM PDT 24
Peak memory 211368 kb
Host smart-9d87e565-080b-42e0-8c77-c9b27d54f180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862985582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3862985582
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2372609823
Short name T633
Test name
Test status
Simulation time 38436869 ps
CPU time 0.79 seconds
Started Aug 04 05:15:13 PM PDT 24
Finished Aug 04 05:15:14 PM PDT 24
Peak memory 205868 kb
Host smart-f3e34540-f258-434d-9e6e-813c6ee232b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372609823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2372609823
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.551598590
Short name T324
Test name
Test status
Simulation time 198890085 ps
CPU time 3.69 seconds
Started Aug 04 05:15:10 PM PDT 24
Finished Aug 04 05:15:14 PM PDT 24
Peak memory 214316 kb
Host smart-360ed0f2-6e25-4fe6-9ef2-83f321122aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=551598590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.551598590
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.533199104
Short name T312
Test name
Test status
Simulation time 564452474 ps
CPU time 15.81 seconds
Started Aug 04 05:15:11 PM PDT 24
Finished Aug 04 05:15:27 PM PDT 24
Peak memory 214212 kb
Host smart-2a014158-0d02-4e89-9695-154b9f8fb634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533199104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.533199104
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3093424433
Short name T45
Test name
Test status
Simulation time 935732985 ps
CPU time 9.8 seconds
Started Aug 04 05:15:09 PM PDT 24
Finished Aug 04 05:15:19 PM PDT 24
Peak memory 214224 kb
Host smart-e5a9d87f-383e-4736-bbed-3d1cce446bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093424433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3093424433
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3397156194
Short name T313
Test name
Test status
Simulation time 735607283 ps
CPU time 2.58 seconds
Started Aug 04 05:15:11 PM PDT 24
Finished Aug 04 05:15:14 PM PDT 24
Peak memory 214164 kb
Host smart-1d2b8809-9bd3-49e8-9ca9-99d9bf9f34d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397156194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3397156194
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3271759729
Short name T580
Test name
Test status
Simulation time 186408749 ps
CPU time 3.99 seconds
Started Aug 04 05:15:08 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 209000 kb
Host smart-dc318c46-d16d-4fc9-83f8-86fc7831fc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271759729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3271759729
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1141086870
Short name T16
Test name
Test status
Simulation time 860857288 ps
CPU time 21.07 seconds
Started Aug 04 05:15:09 PM PDT 24
Finished Aug 04 05:15:30 PM PDT 24
Peak memory 218240 kb
Host smart-897b5345-0091-4734-8b55-ff2519bc18ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141086870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1141086870
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1696060698
Short name T648
Test name
Test status
Simulation time 99244230 ps
CPU time 2.53 seconds
Started Aug 04 05:15:09 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 206796 kb
Host smart-128627f7-611f-4769-96d9-3fe98961939b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696060698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1696060698
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3014369496
Short name T815
Test name
Test status
Simulation time 297772161 ps
CPU time 4.8 seconds
Started Aug 04 05:15:11 PM PDT 24
Finished Aug 04 05:15:16 PM PDT 24
Peak memory 207904 kb
Host smart-1bc1d74a-65f8-4414-9f23-754502f7b639
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014369496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3014369496
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1127189226
Short name T571
Test name
Test status
Simulation time 24724473 ps
CPU time 2.06 seconds
Started Aug 04 05:15:10 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 208572 kb
Host smart-1eeb47bc-d271-4c71-ba67-02d6e6223a5c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127189226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1127189226
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.364906605
Short name T566
Test name
Test status
Simulation time 50563086 ps
CPU time 2.71 seconds
Started Aug 04 05:15:10 PM PDT 24
Finished Aug 04 05:15:13 PM PDT 24
Peak memory 206700 kb
Host smart-8d36c6b6-4cea-4c17-a1e3-69ed13d5e940
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364906605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.364906605
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.800511893
Short name T726
Test name
Test status
Simulation time 221032369 ps
CPU time 2.74 seconds
Started Aug 04 05:15:09 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 215828 kb
Host smart-9ab515ae-76d8-457a-b478-0103577157f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800511893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.800511893
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1378746412
Short name T809
Test name
Test status
Simulation time 23802807 ps
CPU time 1.68 seconds
Started Aug 04 05:15:09 PM PDT 24
Finished Aug 04 05:15:11 PM PDT 24
Peak memory 206976 kb
Host smart-6d5052be-f625-4ed1-b6a0-9ebe0bdf1b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378746412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1378746412
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3197540500
Short name T186
Test name
Test status
Simulation time 963790016 ps
CPU time 10.24 seconds
Started Aug 04 05:15:12 PM PDT 24
Finished Aug 04 05:15:22 PM PDT 24
Peak memory 222512 kb
Host smart-bc87d939-d51d-49f5-9c5f-42325576cc32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197540500 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3197540500
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.140375173
Short name T784
Test name
Test status
Simulation time 94576454 ps
CPU time 4.64 seconds
Started Aug 04 05:15:07 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 207324 kb
Host smart-b962abec-436f-43cd-803c-273d5b4bcd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140375173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.140375173
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2075003010
Short name T505
Test name
Test status
Simulation time 89876281 ps
CPU time 2.68 seconds
Started Aug 04 05:15:09 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 210332 kb
Host smart-2c6fefc6-89ab-46bd-8dbc-400c5de835c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075003010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2075003010
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3725753846
Short name T900
Test name
Test status
Simulation time 45100519 ps
CPU time 0.9 seconds
Started Aug 04 05:15:15 PM PDT 24
Finished Aug 04 05:15:16 PM PDT 24
Peak memory 205860 kb
Host smart-62e531dc-04ed-42f9-9769-e713d25e91f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725753846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3725753846
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1335099270
Short name T358
Test name
Test status
Simulation time 34721954 ps
CPU time 2.67 seconds
Started Aug 04 05:15:14 PM PDT 24
Finished Aug 04 05:15:17 PM PDT 24
Peak memory 214876 kb
Host smart-f50f9bff-ec31-4e55-ade2-c7fc1bc01b3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1335099270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1335099270
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1843219100
Short name T774
Test name
Test status
Simulation time 261333509 ps
CPU time 4.02 seconds
Started Aug 04 05:15:12 PM PDT 24
Finished Aug 04 05:15:16 PM PDT 24
Peak memory 208712 kb
Host smart-d294938e-e9a9-4976-b27e-ff18ddc1ec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843219100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1843219100
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.725379684
Short name T884
Test name
Test status
Simulation time 201662724 ps
CPU time 2.25 seconds
Started Aug 04 05:15:14 PM PDT 24
Finished Aug 04 05:15:16 PM PDT 24
Peak memory 208592 kb
Host smart-4b5b1307-9908-4c18-b88e-147353a9d97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725379684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.725379684
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3146169430
Short name T662
Test name
Test status
Simulation time 32134146 ps
CPU time 1.82 seconds
Started Aug 04 05:15:13 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 214188 kb
Host smart-a0ee4a0c-f2f9-4e20-9204-49d360ee3e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146169430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3146169430
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1945745629
Short name T787
Test name
Test status
Simulation time 235371035 ps
CPU time 4.05 seconds
Started Aug 04 05:15:15 PM PDT 24
Finished Aug 04 05:15:20 PM PDT 24
Peak memory 209472 kb
Host smart-13066a9a-afba-4613-a53c-e24a3d6dc52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945745629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1945745629
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.854016217
Short name T577
Test name
Test status
Simulation time 278576313 ps
CPU time 3.73 seconds
Started Aug 04 05:15:12 PM PDT 24
Finished Aug 04 05:15:16 PM PDT 24
Peak memory 207188 kb
Host smart-47508497-cbbb-4217-91aa-a125880726f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854016217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.854016217
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.789183772
Short name T883
Test name
Test status
Simulation time 5225745092 ps
CPU time 22.55 seconds
Started Aug 04 05:15:14 PM PDT 24
Finished Aug 04 05:15:36 PM PDT 24
Peak memory 208804 kb
Host smart-df480c4c-e298-4b44-9c4b-4207d160fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789183772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.789183772
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2127897119
Short name T800
Test name
Test status
Simulation time 511724244 ps
CPU time 4.59 seconds
Started Aug 04 05:15:11 PM PDT 24
Finished Aug 04 05:15:16 PM PDT 24
Peak memory 207920 kb
Host smart-8da4315b-4790-4090-acb4-da4fe9a8bbc8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127897119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2127897119
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1497165559
Short name T618
Test name
Test status
Simulation time 393468943 ps
CPU time 3.48 seconds
Started Aug 04 05:15:14 PM PDT 24
Finished Aug 04 05:15:17 PM PDT 24
Peak memory 208892 kb
Host smart-13326651-b67d-4476-889a-916cb9e03bd5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497165559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1497165559
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.79562806
Short name T458
Test name
Test status
Simulation time 209451235 ps
CPU time 3.82 seconds
Started Aug 04 05:15:13 PM PDT 24
Finished Aug 04 05:15:17 PM PDT 24
Peak memory 208696 kb
Host smart-60ae6ce8-9f2f-4ee2-8b6a-6fc4b37d71f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79562806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.79562806
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3014184917
Short name T205
Test name
Test status
Simulation time 64354211 ps
CPU time 2.24 seconds
Started Aug 04 05:15:13 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 214432 kb
Host smart-d0a98f92-cd29-49ec-abfb-7982d67d9124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014184917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3014184917
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2802436413
Short name T4
Test name
Test status
Simulation time 126251519 ps
CPU time 2.98 seconds
Started Aug 04 05:15:12 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 208280 kb
Host smart-7894b29f-fd84-40d4-aea7-e73bfd98f8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802436413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2802436413
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.3141178750
Short name T128
Test name
Test status
Simulation time 1491240099 ps
CPU time 16.34 seconds
Started Aug 04 05:15:14 PM PDT 24
Finished Aug 04 05:15:30 PM PDT 24
Peak memory 222420 kb
Host smart-1c23ad00-005a-467d-b523-9afd13a2fcf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141178750 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.3141178750
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3150939533
Short name T818
Test name
Test status
Simulation time 188246501 ps
CPU time 6.09 seconds
Started Aug 04 05:15:11 PM PDT 24
Finished Aug 04 05:15:17 PM PDT 24
Peak memory 218136 kb
Host smart-b4e01f24-1f1b-49a2-82bc-751e5bbd0f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150939533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3150939533
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2288837424
Short name T657
Test name
Test status
Simulation time 45356117 ps
CPU time 0.91 seconds
Started Aug 04 05:15:28 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 205852 kb
Host smart-333d5a8b-4742-49b6-aa5a-34fddb8066bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288837424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2288837424
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3179680438
Short name T294
Test name
Test status
Simulation time 718409465 ps
CPU time 9.97 seconds
Started Aug 04 05:15:16 PM PDT 24
Finished Aug 04 05:15:26 PM PDT 24
Peak memory 214232 kb
Host smart-09c08b65-1970-4bfe-854e-41f3132e866b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179680438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3179680438
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4266135729
Short name T864
Test name
Test status
Simulation time 239371220 ps
CPU time 3.35 seconds
Started Aug 04 05:15:19 PM PDT 24
Finished Aug 04 05:15:23 PM PDT 24
Peak memory 221588 kb
Host smart-028ca96a-0b14-4e83-85ef-6b42d51fcdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266135729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4266135729
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3449548220
Short name T441
Test name
Test status
Simulation time 119249049 ps
CPU time 3.34 seconds
Started Aug 04 05:15:16 PM PDT 24
Finished Aug 04 05:15:19 PM PDT 24
Peak memory 208432 kb
Host smart-41faea51-16d3-4020-b095-b219b05de226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449548220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3449548220
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.209413601
Short name T100
Test name
Test status
Simulation time 110815487 ps
CPU time 3.52 seconds
Started Aug 04 05:15:18 PM PDT 24
Finished Aug 04 05:15:22 PM PDT 24
Peak memory 208592 kb
Host smart-a5d1ab16-8c3d-4ee4-89bb-01bc7696f889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209413601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.209413601
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1320576618
Short name T51
Test name
Test status
Simulation time 139741002 ps
CPU time 3.77 seconds
Started Aug 04 05:15:18 PM PDT 24
Finished Aug 04 05:15:22 PM PDT 24
Peak memory 214240 kb
Host smart-10d62cdb-6c71-4b36-82e3-4bb971454513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320576618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1320576618
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2131866406
Short name T221
Test name
Test status
Simulation time 204859623 ps
CPU time 2.99 seconds
Started Aug 04 05:15:20 PM PDT 24
Finished Aug 04 05:15:23 PM PDT 24
Peak memory 218564 kb
Host smart-9e091a49-b544-41dc-a697-56c8c7ba942f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131866406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2131866406
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1940651669
Short name T247
Test name
Test status
Simulation time 115990532 ps
CPU time 4.51 seconds
Started Aug 04 05:15:15 PM PDT 24
Finished Aug 04 05:15:19 PM PDT 24
Peak memory 209716 kb
Host smart-eb26b8d6-62a7-42a3-8242-8b5415e19259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940651669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1940651669
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3365966791
Short name T141
Test name
Test status
Simulation time 536209338 ps
CPU time 7.72 seconds
Started Aug 04 05:15:13 PM PDT 24
Finished Aug 04 05:15:21 PM PDT 24
Peak memory 208028 kb
Host smart-72e4dec2-b95b-4b1e-9678-8bab2faa2fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365966791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3365966791
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2480312717
Short name T862
Test name
Test status
Simulation time 46015273 ps
CPU time 2.52 seconds
Started Aug 04 05:15:13 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 208440 kb
Host smart-43d7e0ee-a6f5-401e-89d1-750dbf6fd8cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480312717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2480312717
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1373529827
Short name T404
Test name
Test status
Simulation time 82203413 ps
CPU time 3.39 seconds
Started Aug 04 05:15:14 PM PDT 24
Finished Aug 04 05:15:18 PM PDT 24
Peak memory 208548 kb
Host smart-fe4b60b5-fb74-4e56-8076-3349e1325e27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373529827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1373529827
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.924872512
Short name T817
Test name
Test status
Simulation time 191775774 ps
CPU time 3.06 seconds
Started Aug 04 05:15:12 PM PDT 24
Finished Aug 04 05:15:15 PM PDT 24
Peak memory 208532 kb
Host smart-689665de-4662-4ec3-bd1d-e25b4ee00061
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924872512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.924872512
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2069121832
Short name T384
Test name
Test status
Simulation time 65391162 ps
CPU time 2.74 seconds
Started Aug 04 05:15:17 PM PDT 24
Finished Aug 04 05:15:20 PM PDT 24
Peak memory 209196 kb
Host smart-03571135-c096-4891-81eb-d62076ea6fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069121832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2069121832
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1463678062
Short name T833
Test name
Test status
Simulation time 803836043 ps
CPU time 21.75 seconds
Started Aug 04 05:15:14 PM PDT 24
Finished Aug 04 05:15:36 PM PDT 24
Peak memory 208748 kb
Host smart-27db908a-6b32-45d5-9a59-16084e1eb168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463678062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1463678062
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3515122232
Short name T425
Test name
Test status
Simulation time 224303389 ps
CPU time 4.18 seconds
Started Aug 04 05:15:17 PM PDT 24
Finished Aug 04 05:15:21 PM PDT 24
Peak memory 214556 kb
Host smart-405948bc-0fcc-4104-93b9-a1c61b1a809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515122232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3515122232
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4039534514
Short name T54
Test name
Test status
Simulation time 239654179 ps
CPU time 2.46 seconds
Started Aug 04 05:15:18 PM PDT 24
Finished Aug 04 05:15:21 PM PDT 24
Peak memory 209776 kb
Host smart-b95a7920-4573-4e30-8627-f46cce74cad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039534514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4039534514
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1048597186
Short name T611
Test name
Test status
Simulation time 15717012 ps
CPU time 0.83 seconds
Started Aug 04 05:15:25 PM PDT 24
Finished Aug 04 05:15:26 PM PDT 24
Peak memory 205928 kb
Host smart-c3fc0708-fd03-419e-8de5-3a4f2b372c4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048597186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1048597186
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2594376395
Short name T392
Test name
Test status
Simulation time 240175441 ps
CPU time 4.08 seconds
Started Aug 04 05:15:19 PM PDT 24
Finished Aug 04 05:15:23 PM PDT 24
Peak memory 214304 kb
Host smart-0595fa6b-1cf1-49bc-b7fe-2f5b5e0ee0f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594376395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2594376395
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.946191484
Short name T70
Test name
Test status
Simulation time 324037522 ps
CPU time 6.38 seconds
Started Aug 04 05:15:18 PM PDT 24
Finished Aug 04 05:15:25 PM PDT 24
Peak memory 209540 kb
Host smart-6872dfe3-595f-4755-9e3d-2bac09048aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946191484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.946191484
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2011877799
Short name T564
Test name
Test status
Simulation time 419569946 ps
CPU time 4.64 seconds
Started Aug 04 05:15:19 PM PDT 24
Finished Aug 04 05:15:24 PM PDT 24
Peak memory 219648 kb
Host smart-52ef6527-c17d-43a2-a70e-7963414ad1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011877799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2011877799
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1090737590
Short name T701
Test name
Test status
Simulation time 3747021749 ps
CPU time 42.97 seconds
Started Aug 04 05:15:19 PM PDT 24
Finished Aug 04 05:16:02 PM PDT 24
Peak memory 214380 kb
Host smart-dbc8df75-f175-4b23-b847-a6fd75c3e5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090737590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1090737590
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2131500181
Short name T251
Test name
Test status
Simulation time 90315746 ps
CPU time 2.32 seconds
Started Aug 04 05:15:18 PM PDT 24
Finished Aug 04 05:15:21 PM PDT 24
Peak memory 214140 kb
Host smart-49cc2ba5-8fe5-4edb-9a3b-ce57c261c80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131500181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2131500181
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3646876844
Short name T522
Test name
Test status
Simulation time 621361483 ps
CPU time 2.27 seconds
Started Aug 04 05:15:21 PM PDT 24
Finished Aug 04 05:15:23 PM PDT 24
Peak memory 206016 kb
Host smart-f41ea265-598f-4d4e-b417-58d0aa5966cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646876844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3646876844
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2034452865
Short name T493
Test name
Test status
Simulation time 1285802585 ps
CPU time 8.81 seconds
Started Aug 04 05:15:18 PM PDT 24
Finished Aug 04 05:15:27 PM PDT 24
Peak memory 218268 kb
Host smart-225dad22-6c3c-4413-938e-d2bd8592ddc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034452865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2034452865
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.253296255
Short name T454
Test name
Test status
Simulation time 938676156 ps
CPU time 6.11 seconds
Started Aug 04 05:15:18 PM PDT 24
Finished Aug 04 05:15:25 PM PDT 24
Peak memory 207076 kb
Host smart-f2511cf2-f8ca-4fce-950d-4a9c06237988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253296255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.253296255
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3462001957
Short name T459
Test name
Test status
Simulation time 60663108 ps
CPU time 3.05 seconds
Started Aug 04 05:15:17 PM PDT 24
Finished Aug 04 05:15:20 PM PDT 24
Peak memory 208680 kb
Host smart-012fc2ad-667e-46ed-9dce-fd0e95949e28
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462001957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3462001957
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1813109371
Short name T498
Test name
Test status
Simulation time 1027903372 ps
CPU time 6.96 seconds
Started Aug 04 05:15:22 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 207952 kb
Host smart-e40ce03c-55a8-4524-955c-da82ee2bf980
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813109371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1813109371
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3206286121
Short name T361
Test name
Test status
Simulation time 127961083 ps
CPU time 3.11 seconds
Started Aug 04 05:15:21 PM PDT 24
Finished Aug 04 05:15:24 PM PDT 24
Peak memory 208840 kb
Host smart-c59838e8-3945-4088-b43b-e77dd077c2ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206286121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3206286121
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1010992913
Short name T682
Test name
Test status
Simulation time 46126734 ps
CPU time 2.13 seconds
Started Aug 04 05:15:19 PM PDT 24
Finished Aug 04 05:15:21 PM PDT 24
Peak memory 209600 kb
Host smart-1c024635-5d10-4aab-bda5-e68b47212c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010992913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1010992913
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2720615627
Short name T431
Test name
Test status
Simulation time 203516208 ps
CPU time 5.63 seconds
Started Aug 04 05:15:17 PM PDT 24
Finished Aug 04 05:15:23 PM PDT 24
Peak memory 208508 kb
Host smart-49140294-b15d-4823-b4ea-863c08404bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720615627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2720615627
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2353516868
Short name T187
Test name
Test status
Simulation time 648861848 ps
CPU time 15.56 seconds
Started Aug 04 05:15:20 PM PDT 24
Finished Aug 04 05:15:36 PM PDT 24
Peak memory 222440 kb
Host smart-131fd883-2e81-49c7-8fa2-82e7bdb88f59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353516868 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2353516868
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1391885748
Short name T254
Test name
Test status
Simulation time 596260816 ps
CPU time 10.59 seconds
Started Aug 04 05:15:17 PM PDT 24
Finished Aug 04 05:15:27 PM PDT 24
Peak memory 218240 kb
Host smart-dcd6f288-0ba5-4ca4-bc53-e0a704613146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391885748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1391885748
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3433066130
Short name T757
Test name
Test status
Simulation time 1731683106 ps
CPU time 17.99 seconds
Started Aug 04 05:15:15 PM PDT 24
Finished Aug 04 05:15:33 PM PDT 24
Peak memory 211044 kb
Host smart-4c7d849d-1482-496e-a124-1004dcd401e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433066130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3433066130
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.337168394
Short name T408
Test name
Test status
Simulation time 46892373 ps
CPU time 0.74 seconds
Started Aug 04 05:15:27 PM PDT 24
Finished Aug 04 05:15:28 PM PDT 24
Peak memory 205856 kb
Host smart-39918d0c-9a53-4dfa-b9c5-d47d43983b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337168394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.337168394
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2112381071
Short name T37
Test name
Test status
Simulation time 216505407 ps
CPU time 2.19 seconds
Started Aug 04 05:15:25 PM PDT 24
Finished Aug 04 05:15:28 PM PDT 24
Peak memory 214144 kb
Host smart-0aceb35a-accf-4284-8930-80fbe0640798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112381071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2112381071
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3362062945
Short name T610
Test name
Test status
Simulation time 222327221 ps
CPU time 2.74 seconds
Started Aug 04 05:15:26 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 208876 kb
Host smart-013c7ed6-4960-4142-9c23-daf96d72d890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362062945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3362062945
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1812367490
Short name T241
Test name
Test status
Simulation time 748124791 ps
CPU time 5.99 seconds
Started Aug 04 05:15:23 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 220932 kb
Host smart-b0c99305-8258-4ffa-97ef-7f0232f659fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812367490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1812367490
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3834259419
Short name T233
Test name
Test status
Simulation time 146132624 ps
CPU time 4.66 seconds
Started Aug 04 05:15:24 PM PDT 24
Finished Aug 04 05:15:28 PM PDT 24
Peak memory 222464 kb
Host smart-034eb49c-0c58-42ee-afd4-d9c79aea3378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834259419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3834259419
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.158099455
Short name T892
Test name
Test status
Simulation time 60883963 ps
CPU time 3.51 seconds
Started Aug 04 05:15:22 PM PDT 24
Finished Aug 04 05:15:25 PM PDT 24
Peak memory 209664 kb
Host smart-8f090251-1cb5-4fcf-8853-3a9e1d1de43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158099455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.158099455
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1180248062
Short name T450
Test name
Test status
Simulation time 125707829 ps
CPU time 3.32 seconds
Started Aug 04 05:15:20 PM PDT 24
Finished Aug 04 05:15:24 PM PDT 24
Peak memory 206880 kb
Host smart-b1dda797-b780-4451-a7b8-7d3bc3029906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180248062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1180248062
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.157500685
Short name T407
Test name
Test status
Simulation time 110888466 ps
CPU time 3.8 seconds
Started Aug 04 05:15:22 PM PDT 24
Finished Aug 04 05:15:25 PM PDT 24
Peak memory 208000 kb
Host smart-4d8d9b0c-a04a-440f-8a2b-fc8f49249d03
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157500685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.157500685
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3950001939
Short name T754
Test name
Test status
Simulation time 117823912 ps
CPU time 3.14 seconds
Started Aug 04 05:15:27 PM PDT 24
Finished Aug 04 05:15:30 PM PDT 24
Peak memory 208532 kb
Host smart-da3ec0fe-29f4-48ab-9a4b-bc072e2b3217
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950001939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3950001939
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2395140113
Short name T816
Test name
Test status
Simulation time 277906516 ps
CPU time 3.56 seconds
Started Aug 04 05:15:24 PM PDT 24
Finished Aug 04 05:15:28 PM PDT 24
Peak memory 206844 kb
Host smart-cefe50fc-aff7-447c-a53c-af7de804bf95
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395140113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2395140113
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.539493911
Short name T707
Test name
Test status
Simulation time 64829158 ps
CPU time 3.03 seconds
Started Aug 04 05:15:24 PM PDT 24
Finished Aug 04 05:15:27 PM PDT 24
Peak memory 208172 kb
Host smart-8122cc0e-c2c7-4bdd-b197-5fbbbe9cb40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539493911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.539493911
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1084797001
Short name T872
Test name
Test status
Simulation time 53832977 ps
CPU time 2.42 seconds
Started Aug 04 05:15:25 PM PDT 24
Finished Aug 04 05:15:28 PM PDT 24
Peak memory 208712 kb
Host smart-c77b8ad8-9679-4fc3-9460-a040161beab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084797001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1084797001
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2068131559
Short name T401
Test name
Test status
Simulation time 37720065 ps
CPU time 0.99 seconds
Started Aug 04 05:15:22 PM PDT 24
Finished Aug 04 05:15:23 PM PDT 24
Peak memory 206036 kb
Host smart-511c0561-4596-4893-ba26-723e99c8b3fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068131559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2068131559
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1089626787
Short name T183
Test name
Test status
Simulation time 661739812 ps
CPU time 12.32 seconds
Started Aug 04 05:15:20 PM PDT 24
Finished Aug 04 05:15:32 PM PDT 24
Peak memory 222528 kb
Host smart-25fa0e0f-ba84-4dc5-bef9-735492859b28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089626787 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1089626787
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.979907897
Short name T88
Test name
Test status
Simulation time 109869189 ps
CPU time 5.09 seconds
Started Aug 04 05:15:24 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 218212 kb
Host smart-5df4f057-3597-4b44-bfa4-a4f30e7fc473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979907897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.979907897
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2792207318
Short name T888
Test name
Test status
Simulation time 103932222 ps
CPU time 2.91 seconds
Started Aug 04 05:15:22 PM PDT 24
Finished Aug 04 05:15:25 PM PDT 24
Peak memory 210740 kb
Host smart-ac03fc32-80fb-4c92-9eeb-2d42c9b667b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792207318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2792207318
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.938704565
Short name T103
Test name
Test status
Simulation time 11824928 ps
CPU time 0.77 seconds
Started Aug 04 05:15:26 PM PDT 24
Finished Aug 04 05:15:27 PM PDT 24
Peak memory 205972 kb
Host smart-a2e2c7d9-d46a-4ea1-baa4-39247a1dc15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938704565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.938704565
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.955295243
Short name T326
Test name
Test status
Simulation time 571007591 ps
CPU time 13.98 seconds
Started Aug 04 05:15:28 PM PDT 24
Finished Aug 04 05:15:42 PM PDT 24
Peak memory 215268 kb
Host smart-5fda701b-b344-4b0f-a6aa-a2f17078bb31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955295243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.955295243
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.4238709452
Short name T615
Test name
Test status
Simulation time 64011311 ps
CPU time 2.41 seconds
Started Aug 04 05:15:32 PM PDT 24
Finished Aug 04 05:15:34 PM PDT 24
Peak memory 210208 kb
Host smart-fa787add-74e0-4dee-827d-e3fbcaf83275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238709452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.4238709452
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2990282899
Short name T279
Test name
Test status
Simulation time 51419357 ps
CPU time 2.67 seconds
Started Aug 04 05:15:26 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 214220 kb
Host smart-635e9acb-c53d-4bf2-a5cf-d26ef123fe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990282899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2990282899
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1601552512
Short name T340
Test name
Test status
Simulation time 557565308 ps
CPU time 3.77 seconds
Started Aug 04 05:15:26 PM PDT 24
Finished Aug 04 05:15:30 PM PDT 24
Peak memory 214532 kb
Host smart-059d20d2-46a3-4713-9a14-903f3e93cfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601552512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1601552512
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1450488837
Short name T344
Test name
Test status
Simulation time 32121209 ps
CPU time 1.98 seconds
Started Aug 04 05:15:29 PM PDT 24
Finished Aug 04 05:15:31 PM PDT 24
Peak memory 214156 kb
Host smart-73fa6e9d-1c73-4efd-8b24-7e5116a495e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450488837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1450488837
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3739554211
Short name T347
Test name
Test status
Simulation time 167750566 ps
CPU time 4.61 seconds
Started Aug 04 05:15:29 PM PDT 24
Finished Aug 04 05:15:34 PM PDT 24
Peak memory 214304 kb
Host smart-092c77ba-31c2-499e-961b-0346830587e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739554211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3739554211
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2596011845
Short name T578
Test name
Test status
Simulation time 49819192 ps
CPU time 2.98 seconds
Started Aug 04 05:15:29 PM PDT 24
Finished Aug 04 05:15:33 PM PDT 24
Peak memory 207504 kb
Host smart-c753f65e-452d-43f2-8f24-4713a5e5caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596011845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2596011845
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.55272595
Short name T683
Test name
Test status
Simulation time 1645808231 ps
CPU time 8.51 seconds
Started Aug 04 05:15:22 PM PDT 24
Finished Aug 04 05:15:31 PM PDT 24
Peak memory 208376 kb
Host smart-f7b6401a-1a82-48d7-a9b2-ff5b008f6f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55272595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.55272595
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3969772643
Short name T417
Test name
Test status
Simulation time 224866347 ps
CPU time 2.91 seconds
Started Aug 04 05:15:25 PM PDT 24
Finished Aug 04 05:15:28 PM PDT 24
Peak memory 206872 kb
Host smart-9dd75af6-7383-432e-927b-6463a1ff4d72
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969772643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3969772643
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.500674673
Short name T484
Test name
Test status
Simulation time 121058974 ps
CPU time 3.43 seconds
Started Aug 04 05:15:22 PM PDT 24
Finished Aug 04 05:15:25 PM PDT 24
Peak memory 208684 kb
Host smart-c6d6308b-1c16-45a9-b2c9-c87e152a9f81
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500674673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.500674673
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3323430996
Short name T353
Test name
Test status
Simulation time 37417732 ps
CPU time 2.3 seconds
Started Aug 04 05:15:26 PM PDT 24
Finished Aug 04 05:15:28 PM PDT 24
Peak memory 206844 kb
Host smart-585ec276-1821-4e35-9d35-cd401a13ecdd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323430996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3323430996
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1113102493
Short name T694
Test name
Test status
Simulation time 427280320 ps
CPU time 4.71 seconds
Started Aug 04 05:15:25 PM PDT 24
Finished Aug 04 05:15:30 PM PDT 24
Peak memory 214248 kb
Host smart-79631ddc-1350-49ca-bcbc-89b4ef44df57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113102493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1113102493
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3856094819
Short name T517
Test name
Test status
Simulation time 79947472 ps
CPU time 3.33 seconds
Started Aug 04 05:15:24 PM PDT 24
Finished Aug 04 05:15:28 PM PDT 24
Peak memory 208200 kb
Host smart-7df869db-410f-4740-b25f-d7cee755cbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856094819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3856094819
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3432329575
Short name T635
Test name
Test status
Simulation time 2404627351 ps
CPU time 19.7 seconds
Started Aug 04 05:15:24 PM PDT 24
Finished Aug 04 05:15:44 PM PDT 24
Peak memory 222504 kb
Host smart-f607f519-a027-4dbd-9492-1e984611f66d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432329575 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3432329575
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1734121873
Short name T535
Test name
Test status
Simulation time 185545955 ps
CPU time 4.56 seconds
Started Aug 04 05:15:25 PM PDT 24
Finished Aug 04 05:15:30 PM PDT 24
Peak memory 208672 kb
Host smart-eb5bb72e-58d7-46e5-9ca9-ead7185bc231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734121873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1734121873
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3251593412
Short name T729
Test name
Test status
Simulation time 128456266 ps
CPU time 2.19 seconds
Started Aug 04 05:15:25 PM PDT 24
Finished Aug 04 05:15:27 PM PDT 24
Peak memory 210056 kb
Host smart-4ac62e4a-bd14-40c3-8e70-d0e9b195b99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251593412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3251593412
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3477613770
Short name T576
Test name
Test status
Simulation time 35855392 ps
CPU time 0.75 seconds
Started Aug 04 05:15:26 PM PDT 24
Finished Aug 04 05:15:27 PM PDT 24
Peak memory 205944 kb
Host smart-0f90cbaf-60e1-4002-bcbd-95f72dd67982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477613770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3477613770
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2327484826
Short name T244
Test name
Test status
Simulation time 1607791261 ps
CPU time 41.94 seconds
Started Aug 04 05:15:26 PM PDT 24
Finished Aug 04 05:16:08 PM PDT 24
Peak memory 214328 kb
Host smart-f67bfa5a-2414-4868-bbc7-74cf29415640
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2327484826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2327484826
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2249859655
Short name T885
Test name
Test status
Simulation time 53677839 ps
CPU time 2.51 seconds
Started Aug 04 05:15:30 PM PDT 24
Finished Aug 04 05:15:33 PM PDT 24
Peak memory 209856 kb
Host smart-cb69a840-1126-4b4e-8e73-22415965330e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249859655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2249859655
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1391318291
Short name T789
Test name
Test status
Simulation time 67178165 ps
CPU time 2.75 seconds
Started Aug 04 05:15:26 PM PDT 24
Finished Aug 04 05:15:28 PM PDT 24
Peak memory 207156 kb
Host smart-f4a806e5-28c3-47c8-9882-e78916a5f77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391318291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1391318291
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.478264058
Short name T806
Test name
Test status
Simulation time 1249641327 ps
CPU time 3.23 seconds
Started Aug 04 05:15:26 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 214340 kb
Host smart-0ebf929c-57de-4269-89b1-b714a2fdc654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478264058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.478264058
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.4159881532
Short name T192
Test name
Test status
Simulation time 130120133 ps
CPU time 3.76 seconds
Started Aug 04 05:15:28 PM PDT 24
Finished Aug 04 05:15:32 PM PDT 24
Peak memory 221788 kb
Host smart-a37c01a6-c008-4e39-9619-cc51573c3293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159881532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.4159881532
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.229378182
Short name T609
Test name
Test status
Simulation time 310036423 ps
CPU time 4.96 seconds
Started Aug 04 05:15:32 PM PDT 24
Finished Aug 04 05:15:37 PM PDT 24
Peak memory 222404 kb
Host smart-9a9c9aee-c66c-4146-9dfb-8ae71c93254c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229378182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.229378182
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.486766228
Short name T736
Test name
Test status
Simulation time 781494214 ps
CPU time 6.24 seconds
Started Aug 04 05:15:28 PM PDT 24
Finished Aug 04 05:15:35 PM PDT 24
Peak memory 209516 kb
Host smart-a356a6b7-11a5-4904-9765-a16dd9877caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486766228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.486766228
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2068145701
Short name T110
Test name
Test status
Simulation time 80304296 ps
CPU time 3.66 seconds
Started Aug 04 05:15:29 PM PDT 24
Finished Aug 04 05:15:33 PM PDT 24
Peak memory 208636 kb
Host smart-dfa4e766-4321-42b8-8b4b-6537122ee099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068145701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2068145701
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.598832972
Short name T499
Test name
Test status
Simulation time 191469639 ps
CPU time 2.82 seconds
Started Aug 04 05:15:32 PM PDT 24
Finished Aug 04 05:15:35 PM PDT 24
Peak memory 206892 kb
Host smart-ee345b82-ff8a-4c92-8497-b969e4eee1d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598832972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.598832972
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1316227383
Short name T750
Test name
Test status
Simulation time 134419863 ps
CPU time 4.39 seconds
Started Aug 04 05:15:25 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 208004 kb
Host smart-e49c511d-2fc1-43d9-bdb2-e15ba4bef371
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316227383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1316227383
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.564848981
Short name T570
Test name
Test status
Simulation time 113754719 ps
CPU time 4.42 seconds
Started Aug 04 05:15:24 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 208260 kb
Host smart-f965cd5b-7fd6-458c-a73e-c1763ea0ad02
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564848981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.564848981
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.4126290092
Short name T211
Test name
Test status
Simulation time 593222816 ps
CPU time 2.94 seconds
Started Aug 04 05:15:25 PM PDT 24
Finished Aug 04 05:15:28 PM PDT 24
Peak memory 215608 kb
Host smart-24801f87-a20d-467b-8cd0-cef646adcdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126290092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.4126290092
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.236957330
Short name T616
Test name
Test status
Simulation time 146059489 ps
CPU time 2.61 seconds
Started Aug 04 05:15:26 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 207900 kb
Host smart-97fe3be8-de80-4320-befe-05ae37262720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236957330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.236957330
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2687700826
Short name T374
Test name
Test status
Simulation time 807573391 ps
CPU time 9.76 seconds
Started Aug 04 05:15:31 PM PDT 24
Finished Aug 04 05:15:40 PM PDT 24
Peak memory 214220 kb
Host smart-99a88e00-c998-4083-b74c-a4262cf8d921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687700826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2687700826
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.601964002
Short name T742
Test name
Test status
Simulation time 189567532 ps
CPU time 5.71 seconds
Started Aug 04 05:15:25 PM PDT 24
Finished Aug 04 05:15:31 PM PDT 24
Peak memory 210004 kb
Host smart-779c49dd-e91f-4749-93ee-8db4c54debb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601964002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.601964002
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.4273041350
Short name T191
Test name
Test status
Simulation time 124991386 ps
CPU time 2.46 seconds
Started Aug 04 05:15:29 PM PDT 24
Finished Aug 04 05:15:32 PM PDT 24
Peak memory 210192 kb
Host smart-0960c402-500c-4739-90a6-a77b3d980c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273041350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.4273041350
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3596931268
Short name T894
Test name
Test status
Simulation time 17608667 ps
CPU time 0.81 seconds
Started Aug 04 05:13:16 PM PDT 24
Finished Aug 04 05:13:16 PM PDT 24
Peak memory 205856 kb
Host smart-77bc1aa9-486c-4ff0-a6e9-eb2fa5d3771c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596931268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3596931268
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.795101360
Short name T791
Test name
Test status
Simulation time 128347933 ps
CPU time 2.75 seconds
Started Aug 04 05:13:10 PM PDT 24
Finished Aug 04 05:13:13 PM PDT 24
Peak memory 214148 kb
Host smart-9531530c-c74d-4392-a6f4-594393e4f60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795101360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.795101360
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3170971785
Short name T332
Test name
Test status
Simulation time 75282298 ps
CPU time 3.25 seconds
Started Aug 04 05:13:11 PM PDT 24
Finished Aug 04 05:13:14 PM PDT 24
Peak memory 214276 kb
Host smart-dcc623c8-c832-4b18-9ad6-50ef7655401e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170971785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3170971785
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2883669352
Short name T843
Test name
Test status
Simulation time 85475988 ps
CPU time 3.46 seconds
Started Aug 04 05:13:13 PM PDT 24
Finished Aug 04 05:13:17 PM PDT 24
Peak memory 214388 kb
Host smart-72d5c310-696d-42da-9449-f392b511ffc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883669352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2883669352
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3221276468
Short name T875
Test name
Test status
Simulation time 84814120 ps
CPU time 3 seconds
Started Aug 04 05:13:09 PM PDT 24
Finished Aug 04 05:13:12 PM PDT 24
Peak memory 207364 kb
Host smart-277ee58a-b9f5-439d-8009-f5d755b64726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221276468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3221276468
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3988806552
Short name T619
Test name
Test status
Simulation time 440225694 ps
CPU time 3.15 seconds
Started Aug 04 05:13:13 PM PDT 24
Finished Aug 04 05:13:16 PM PDT 24
Peak memory 214196 kb
Host smart-cf8d35e6-4081-40b8-9b9a-d869252dbd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988806552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3988806552
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3490899888
Short name T753
Test name
Test status
Simulation time 2204192095 ps
CPU time 8.35 seconds
Started Aug 04 05:13:09 PM PDT 24
Finished Aug 04 05:13:18 PM PDT 24
Peak memory 218616 kb
Host smart-8a71ac82-8953-445c-a351-10e90e794408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490899888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3490899888
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2418736297
Short name T455
Test name
Test status
Simulation time 637121453 ps
CPU time 9.19 seconds
Started Aug 04 05:13:13 PM PDT 24
Finished Aug 04 05:13:22 PM PDT 24
Peak memory 208788 kb
Host smart-74b2f473-3191-47e1-8da4-49678aa385f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418736297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2418736297
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1807296720
Short name T901
Test name
Test status
Simulation time 65742351 ps
CPU time 3.18 seconds
Started Aug 04 05:13:12 PM PDT 24
Finished Aug 04 05:13:15 PM PDT 24
Peak memory 208572 kb
Host smart-6365ccbe-2baf-4889-b7c4-9a43ddbd4806
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807296720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1807296720
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2549181281
Short name T420
Test name
Test status
Simulation time 467576791 ps
CPU time 12.34 seconds
Started Aug 04 05:13:11 PM PDT 24
Finished Aug 04 05:13:23 PM PDT 24
Peak memory 207800 kb
Host smart-d6bdc10c-b147-41af-9aa8-7898da5f3095
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549181281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2549181281
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.69747804
Short name T762
Test name
Test status
Simulation time 658210536 ps
CPU time 6.25 seconds
Started Aug 04 05:13:13 PM PDT 24
Finished Aug 04 05:13:20 PM PDT 24
Peak memory 207768 kb
Host smart-2804405c-3c76-48a1-9032-5172901d51ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69747804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.69747804
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3886001719
Short name T526
Test name
Test status
Simulation time 191754531 ps
CPU time 3.83 seconds
Started Aug 04 05:13:14 PM PDT 24
Finished Aug 04 05:13:18 PM PDT 24
Peak memory 218340 kb
Host smart-9c38faa0-aedc-4c07-8804-40d8702a01ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886001719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3886001719
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2874298105
Short name T89
Test name
Test status
Simulation time 11321390197 ps
CPU time 26.76 seconds
Started Aug 04 05:13:11 PM PDT 24
Finished Aug 04 05:13:38 PM PDT 24
Peak memory 208048 kb
Host smart-d9727b91-39d6-4e89-b5ad-ec89865a63dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874298105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2874298105
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.984207776
Short name T136
Test name
Test status
Simulation time 1589977185 ps
CPU time 10.06 seconds
Started Aug 04 05:13:14 PM PDT 24
Finished Aug 04 05:13:25 PM PDT 24
Peak memory 222528 kb
Host smart-03a5fce8-9cb8-4272-bc45-7e8f864a9ece
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984207776 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.984207776
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.800300654
Short name T731
Test name
Test status
Simulation time 85989351 ps
CPU time 3.99 seconds
Started Aug 04 05:13:13 PM PDT 24
Finished Aug 04 05:13:17 PM PDT 24
Peak memory 209084 kb
Host smart-4afe92d8-557a-46ff-9563-2907bed1c5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800300654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.800300654
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3102072772
Short name T515
Test name
Test status
Simulation time 83844820 ps
CPU time 1.42 seconds
Started Aug 04 05:13:13 PM PDT 24
Finished Aug 04 05:13:15 PM PDT 24
Peak memory 209628 kb
Host smart-58172ba2-3db0-4741-b60c-1c9e9844bf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102072772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3102072772
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1555791877
Short name T819
Test name
Test status
Simulation time 13996595 ps
CPU time 0.75 seconds
Started Aug 04 05:13:17 PM PDT 24
Finished Aug 04 05:13:18 PM PDT 24
Peak memory 205944 kb
Host smart-ce67b4e8-7996-4fe3-b336-1f52023a3c00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555791877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1555791877
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.159514859
Short name T389
Test name
Test status
Simulation time 148844824 ps
CPU time 7.55 seconds
Started Aug 04 05:13:17 PM PDT 24
Finished Aug 04 05:13:24 PM PDT 24
Peak memory 214216 kb
Host smart-41aad96b-695d-4d71-8161-7011b81955e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=159514859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.159514859
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2373537521
Short name T232
Test name
Test status
Simulation time 200466696 ps
CPU time 2.95 seconds
Started Aug 04 05:13:15 PM PDT 24
Finished Aug 04 05:13:18 PM PDT 24
Peak memory 209416 kb
Host smart-e1c4ebdd-2fd0-4a2e-9d48-b8b6c0fcc335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373537521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2373537521
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.843284403
Short name T593
Test name
Test status
Simulation time 107421809 ps
CPU time 1.76 seconds
Started Aug 04 05:13:17 PM PDT 24
Finished Aug 04 05:13:19 PM PDT 24
Peak memory 207340 kb
Host smart-58bb3ea0-5b2a-4b9a-917d-25ca020d6be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843284403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.843284403
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3920390380
Short name T240
Test name
Test status
Simulation time 268352892 ps
CPU time 8.95 seconds
Started Aug 04 05:13:13 PM PDT 24
Finished Aug 04 05:13:22 PM PDT 24
Peak memory 222320 kb
Host smart-a5ffef5a-e24d-4582-a0d1-ce6dc28af49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920390380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3920390380
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.162972169
Short name T295
Test name
Test status
Simulation time 132428080 ps
CPU time 2.41 seconds
Started Aug 04 05:13:15 PM PDT 24
Finished Aug 04 05:13:17 PM PDT 24
Peak memory 219548 kb
Host smart-656580f6-bb71-4aad-8474-ad3ef5fc8492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162972169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.162972169
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.168531076
Short name T676
Test name
Test status
Simulation time 87518958 ps
CPU time 2.1 seconds
Started Aug 04 05:13:14 PM PDT 24
Finished Aug 04 05:13:16 PM PDT 24
Peak memory 215108 kb
Host smart-9250d40e-6515-4296-8bd5-2fb42dc3b652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168531076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.168531076
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1797909884
Short name T258
Test name
Test status
Simulation time 42074357 ps
CPU time 3 seconds
Started Aug 04 05:13:13 PM PDT 24
Finished Aug 04 05:13:16 PM PDT 24
Peak memory 222368 kb
Host smart-845643de-6558-4f4d-b377-66d9d39c2dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797909884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1797909884
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2423869280
Short name T530
Test name
Test status
Simulation time 127846919 ps
CPU time 2.45 seconds
Started Aug 04 05:13:18 PM PDT 24
Finished Aug 04 05:13:20 PM PDT 24
Peak memory 206376 kb
Host smart-1973e357-d99a-4339-acce-cb93708294eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423869280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2423869280
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3270237834
Short name T790
Test name
Test status
Simulation time 303703591 ps
CPU time 4.62 seconds
Started Aug 04 05:13:14 PM PDT 24
Finished Aug 04 05:13:18 PM PDT 24
Peak memory 208656 kb
Host smart-e753cd84-dc29-464f-a919-cf706d4d8ebb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270237834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3270237834
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2391679009
Short name T758
Test name
Test status
Simulation time 242267599 ps
CPU time 2.52 seconds
Started Aug 04 05:13:14 PM PDT 24
Finished Aug 04 05:13:16 PM PDT 24
Peak memory 206936 kb
Host smart-5b8ea7b1-4831-420b-bd17-aab3274b8024
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391679009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2391679009
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.54851814
Short name T768
Test name
Test status
Simulation time 232105118 ps
CPU time 7.13 seconds
Started Aug 04 05:13:17 PM PDT 24
Finished Aug 04 05:13:24 PM PDT 24
Peak memory 208116 kb
Host smart-c7c588c7-8086-40f9-90b0-7f3e2393ce4a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54851814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.54851814
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.4284791520
Short name T582
Test name
Test status
Simulation time 267961253 ps
CPU time 2.29 seconds
Started Aug 04 05:13:15 PM PDT 24
Finished Aug 04 05:13:17 PM PDT 24
Peak memory 208056 kb
Host smart-3b265075-ac32-4d7c-ab7e-6206231a7efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284791520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.4284791520
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3309255475
Short name T585
Test name
Test status
Simulation time 341964484 ps
CPU time 2.89 seconds
Started Aug 04 05:13:14 PM PDT 24
Finished Aug 04 05:13:17 PM PDT 24
Peak memory 208740 kb
Host smart-091d1804-316c-4545-a92e-6750d9e7af52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309255475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3309255475
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1198271527
Short name T661
Test name
Test status
Simulation time 719752021 ps
CPU time 8.33 seconds
Started Aug 04 05:13:15 PM PDT 24
Finished Aug 04 05:13:23 PM PDT 24
Peak memory 215060 kb
Host smart-2b4c8370-7392-4abc-b2d4-69598c057c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198271527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1198271527
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1495730793
Short name T860
Test name
Test status
Simulation time 109008363 ps
CPU time 3.5 seconds
Started Aug 04 05:13:18 PM PDT 24
Finished Aug 04 05:13:21 PM PDT 24
Peak memory 207136 kb
Host smart-b8eeb40d-ad50-4da3-89ed-aac95069c299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495730793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1495730793
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.190470948
Short name T911
Test name
Test status
Simulation time 83650975 ps
CPU time 3.45 seconds
Started Aug 04 05:13:18 PM PDT 24
Finished Aug 04 05:13:21 PM PDT 24
Peak memory 210124 kb
Host smart-ae0bb457-e709-4fdc-b7e5-096fc2fc5b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190470948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.190470948
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3264341776
Short name T565
Test name
Test status
Simulation time 10328619 ps
CPU time 0.9 seconds
Started Aug 04 05:13:19 PM PDT 24
Finished Aug 04 05:13:21 PM PDT 24
Peak memory 205944 kb
Host smart-22560715-41ba-4871-8ee9-fda1809ed1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264341776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3264341776
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.4193880335
Short name T144
Test name
Test status
Simulation time 86594143 ps
CPU time 3.01 seconds
Started Aug 04 05:13:20 PM PDT 24
Finished Aug 04 05:13:24 PM PDT 24
Peak memory 214220 kb
Host smart-901c75df-dc86-4b60-858d-5cbb322e320b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193880335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.4193880335
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1663133092
Short name T10
Test name
Test status
Simulation time 225082865 ps
CPU time 2.04 seconds
Started Aug 04 05:13:21 PM PDT 24
Finished Aug 04 05:13:24 PM PDT 24
Peak memory 214732 kb
Host smart-c3b878bc-39ae-469e-b8bc-e0a5c9d4e9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663133092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1663133092
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3261380291
Short name T630
Test name
Test status
Simulation time 117842568 ps
CPU time 2.75 seconds
Started Aug 04 05:13:18 PM PDT 24
Finished Aug 04 05:13:21 PM PDT 24
Peak memory 207616 kb
Host smart-b80daa55-6bd2-4d3b-bf20-609cbf0f3251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261380291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3261380291
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.771327259
Short name T319
Test name
Test status
Simulation time 877671293 ps
CPU time 18.51 seconds
Started Aug 04 05:13:19 PM PDT 24
Finished Aug 04 05:13:38 PM PDT 24
Peak memory 214328 kb
Host smart-83f9289a-bcbc-4991-b290-2a6a3a7ccbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771327259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.771327259
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2564196410
Short name T621
Test name
Test status
Simulation time 315084756 ps
CPU time 3.55 seconds
Started Aug 04 05:13:19 PM PDT 24
Finished Aug 04 05:13:22 PM PDT 24
Peak memory 221584 kb
Host smart-a6e760a2-e15c-460d-ae55-b635536f5ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564196410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2564196410
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1241974781
Short name T485
Test name
Test status
Simulation time 113812158 ps
CPU time 4.03 seconds
Started Aug 04 05:13:21 PM PDT 24
Finished Aug 04 05:13:26 PM PDT 24
Peak memory 215452 kb
Host smart-64a656e7-32c9-4dcf-b8b1-56e61b53c84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241974781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1241974781
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1770000683
Short name T197
Test name
Test status
Simulation time 744320048 ps
CPU time 5.43 seconds
Started Aug 04 05:13:20 PM PDT 24
Finished Aug 04 05:13:26 PM PDT 24
Peak memory 210204 kb
Host smart-450d20da-5b1e-4ea6-aa05-4d1b78c79e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770000683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1770000683
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1350507417
Short name T725
Test name
Test status
Simulation time 62195728 ps
CPU time 2.97 seconds
Started Aug 04 05:13:15 PM PDT 24
Finished Aug 04 05:13:18 PM PDT 24
Peak memory 208444 kb
Host smart-1868e444-8de4-4966-af47-5ab887dcb4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350507417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1350507417
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.308240230
Short name T321
Test name
Test status
Simulation time 214300851 ps
CPU time 2.94 seconds
Started Aug 04 05:13:21 PM PDT 24
Finished Aug 04 05:13:24 PM PDT 24
Peak memory 208464 kb
Host smart-23d0165b-eb87-4ed1-b39e-9b3514ec8622
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308240230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.308240230
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.259945318
Short name T435
Test name
Test status
Simulation time 112813947 ps
CPU time 4.03 seconds
Started Aug 04 05:13:18 PM PDT 24
Finished Aug 04 05:13:23 PM PDT 24
Peak memory 206920 kb
Host smart-49bb1997-d117-4a52-9c46-784bc09ef59e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259945318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.259945318
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3217896745
Short name T851
Test name
Test status
Simulation time 55680219 ps
CPU time 2.63 seconds
Started Aug 04 05:13:19 PM PDT 24
Finished Aug 04 05:13:22 PM PDT 24
Peak memory 208048 kb
Host smart-8b2f1848-ab07-481a-9377-c941b7833e82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217896745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3217896745
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1880447877
Short name T428
Test name
Test status
Simulation time 96423531 ps
CPU time 1.56 seconds
Started Aug 04 05:13:19 PM PDT 24
Finished Aug 04 05:13:21 PM PDT 24
Peak memory 207300 kb
Host smart-8fb03ee4-8dff-452b-84d9-508e6f891e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880447877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1880447877
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1212792558
Short name T756
Test name
Test status
Simulation time 33963514 ps
CPU time 2.13 seconds
Started Aug 04 05:13:15 PM PDT 24
Finished Aug 04 05:13:18 PM PDT 24
Peak memory 206848 kb
Host smart-8ab1300e-2cc2-4af1-8440-a5e3878401b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212792558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1212792558
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3905524406
Short name T372
Test name
Test status
Simulation time 408215202 ps
CPU time 9.98 seconds
Started Aug 04 05:13:23 PM PDT 24
Finished Aug 04 05:13:33 PM PDT 24
Peak memory 220804 kb
Host smart-d4954501-f25e-4e08-bcdb-68bd5c68c577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905524406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3905524406
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3843610833
Short name T847
Test name
Test status
Simulation time 689801081 ps
CPU time 22.19 seconds
Started Aug 04 05:13:19 PM PDT 24
Finished Aug 04 05:13:41 PM PDT 24
Peak memory 208156 kb
Host smart-630debf5-40c8-48ac-96e9-6602dabf1076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843610833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3843610833
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.4278787417
Short name T604
Test name
Test status
Simulation time 273005470 ps
CPU time 3.1 seconds
Started Aug 04 05:13:23 PM PDT 24
Finished Aug 04 05:13:26 PM PDT 24
Peak memory 210260 kb
Host smart-7f691320-8b24-4ec4-a1e7-b05259cb268a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278787417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.4278787417
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2752157501
Short name T461
Test name
Test status
Simulation time 48845764 ps
CPU time 0.82 seconds
Started Aug 04 05:13:25 PM PDT 24
Finished Aug 04 05:13:26 PM PDT 24
Peak memory 205944 kb
Host smart-2ff04ce8-ed52-407c-a270-b7a40d9e1357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752157501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2752157501
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1754654443
Short name T155
Test name
Test status
Simulation time 44266246 ps
CPU time 3.06 seconds
Started Aug 04 05:13:25 PM PDT 24
Finished Aug 04 05:13:28 PM PDT 24
Peak memory 214232 kb
Host smart-8f94b6ca-08b3-462d-bda2-b679a23b0078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1754654443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1754654443
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.13872350
Short name T863
Test name
Test status
Simulation time 205923391 ps
CPU time 5.61 seconds
Started Aug 04 05:13:24 PM PDT 24
Finished Aug 04 05:13:30 PM PDT 24
Peak memory 217332 kb
Host smart-8c2fa70a-d972-494f-9ee5-b9a353c1a06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13872350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.13872350
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2036958892
Short name T802
Test name
Test status
Simulation time 209343225 ps
CPU time 2.06 seconds
Started Aug 04 05:13:23 PM PDT 24
Finished Aug 04 05:13:25 PM PDT 24
Peak memory 208720 kb
Host smart-2669ca42-7998-4af7-b7a0-b260f5d2e18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036958892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2036958892
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1993532346
Short name T512
Test name
Test status
Simulation time 213809107 ps
CPU time 4.65 seconds
Started Aug 04 05:13:23 PM PDT 24
Finished Aug 04 05:13:28 PM PDT 24
Peak memory 214208 kb
Host smart-48e9360a-85d0-4564-aeca-ea442398fa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993532346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1993532346
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.4169912695
Short name T298
Test name
Test status
Simulation time 83805580 ps
CPU time 1.91 seconds
Started Aug 04 05:13:21 PM PDT 24
Finished Aug 04 05:13:24 PM PDT 24
Peak memory 214200 kb
Host smart-5a083a46-1b66-40b3-8fef-902af1af1a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169912695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.4169912695
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.191356310
Short name T231
Test name
Test status
Simulation time 41327479 ps
CPU time 2.81 seconds
Started Aug 04 05:13:22 PM PDT 24
Finished Aug 04 05:13:25 PM PDT 24
Peak memory 210128 kb
Host smart-b223d91e-a339-42e1-b9c8-fc16e4b37e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191356310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.191356310
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3298855419
Short name T779
Test name
Test status
Simulation time 224645945 ps
CPU time 3.51 seconds
Started Aug 04 05:13:22 PM PDT 24
Finished Aug 04 05:13:26 PM PDT 24
Peak memory 214368 kb
Host smart-043dc44d-9b72-42c5-b655-faffad01f45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298855419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3298855419
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1681483210
Short name T760
Test name
Test status
Simulation time 261764071 ps
CPU time 2.34 seconds
Started Aug 04 05:13:20 PM PDT 24
Finished Aug 04 05:13:23 PM PDT 24
Peak memory 207184 kb
Host smart-6cd9a505-772b-4562-8078-3a0f5c61bcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681483210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1681483210
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2241164183
Short name T865
Test name
Test status
Simulation time 640868957 ps
CPU time 4.96 seconds
Started Aug 04 05:13:23 PM PDT 24
Finished Aug 04 05:13:28 PM PDT 24
Peak memory 208916 kb
Host smart-7103129c-eeda-4950-b614-6bdbb50f4cf3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241164183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2241164183
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2253633466
Short name T714
Test name
Test status
Simulation time 323232562 ps
CPU time 3.81 seconds
Started Aug 04 05:13:21 PM PDT 24
Finished Aug 04 05:13:25 PM PDT 24
Peak memory 208772 kb
Host smart-8890cbd3-846a-4a75-abfa-f902e5a66fb1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253633466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2253633466
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3037965380
Short name T909
Test name
Test status
Simulation time 83506945 ps
CPU time 3.52 seconds
Started Aug 04 05:13:23 PM PDT 24
Finished Aug 04 05:13:27 PM PDT 24
Peak memory 208668 kb
Host smart-6ec439d0-b296-433d-b73f-be12424a6660
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037965380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3037965380
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2664422159
Short name T594
Test name
Test status
Simulation time 27901688 ps
CPU time 1.95 seconds
Started Aug 04 05:13:21 PM PDT 24
Finished Aug 04 05:13:24 PM PDT 24
Peak memory 208312 kb
Host smart-13849662-caea-4b85-887b-9f33403439dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664422159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2664422159
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3092105816
Short name T208
Test name
Test status
Simulation time 80148357 ps
CPU time 3.06 seconds
Started Aug 04 05:13:19 PM PDT 24
Finished Aug 04 05:13:22 PM PDT 24
Peak memory 208400 kb
Host smart-e0ecdbeb-41f0-466b-a304-f46221f1aa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092105816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3092105816
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3691335389
Short name T207
Test name
Test status
Simulation time 635656432 ps
CPU time 13.74 seconds
Started Aug 04 05:13:21 PM PDT 24
Finished Aug 04 05:13:35 PM PDT 24
Peak memory 209852 kb
Host smart-0574f1bf-2819-43f6-97ce-cdae95eae736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691335389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3691335389
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.354141213
Short name T887
Test name
Test status
Simulation time 41256864 ps
CPU time 1.49 seconds
Started Aug 04 05:13:24 PM PDT 24
Finished Aug 04 05:13:26 PM PDT 24
Peak memory 209460 kb
Host smart-f05446ba-88dc-4f7e-8300-492d63aab9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354141213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.354141213
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2326923340
Short name T713
Test name
Test status
Simulation time 44642567 ps
CPU time 0.86 seconds
Started Aug 04 05:13:29 PM PDT 24
Finished Aug 04 05:13:30 PM PDT 24
Peak memory 205856 kb
Host smart-9c412def-841a-4889-884d-6e604b4d92e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326923340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2326923340
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3182391071
Short name T396
Test name
Test status
Simulation time 128708926 ps
CPU time 6.3 seconds
Started Aug 04 05:13:35 PM PDT 24
Finished Aug 04 05:13:41 PM PDT 24
Peak memory 214080 kb
Host smart-d88944a0-9b18-4c0f-9098-f27ce6db9dd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3182391071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3182391071
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4122320418
Short name T337
Test name
Test status
Simulation time 191018408 ps
CPU time 5.1 seconds
Started Aug 04 05:13:28 PM PDT 24
Finished Aug 04 05:13:33 PM PDT 24
Peak memory 208968 kb
Host smart-e0a860b2-3e8c-4c58-9d11-807907319c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122320418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4122320418
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3436564206
Short name T870
Test name
Test status
Simulation time 257797225 ps
CPU time 2.82 seconds
Started Aug 04 05:13:26 PM PDT 24
Finished Aug 04 05:13:29 PM PDT 24
Peak memory 214224 kb
Host smart-6dc2b2a4-27dd-4f89-b558-6f9a0175e7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436564206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3436564206
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3321804415
Short name T56
Test name
Test status
Simulation time 346183129 ps
CPU time 4.45 seconds
Started Aug 04 05:13:30 PM PDT 24
Finished Aug 04 05:13:35 PM PDT 24
Peak memory 222496 kb
Host smart-219eebfb-00e9-42ea-a7fd-d2fab1c48faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321804415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3321804415
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1024946411
Short name T371
Test name
Test status
Simulation time 416190492 ps
CPU time 8.07 seconds
Started Aug 04 05:13:26 PM PDT 24
Finished Aug 04 05:13:34 PM PDT 24
Peak memory 209472 kb
Host smart-1b7c8b2d-3372-4497-b5e6-968a908b98ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024946411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1024946411
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1113543327
Short name T92
Test name
Test status
Simulation time 97435315 ps
CPU time 3.24 seconds
Started Aug 04 05:13:27 PM PDT 24
Finished Aug 04 05:13:30 PM PDT 24
Peak memory 206828 kb
Host smart-1233ca0d-1f15-49cc-92a5-2e3775964223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113543327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1113543327
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3398060285
Short name T414
Test name
Test status
Simulation time 623666882 ps
CPU time 2.72 seconds
Started Aug 04 05:13:35 PM PDT 24
Finished Aug 04 05:13:38 PM PDT 24
Peak memory 208436 kb
Host smart-0d02beb4-7a05-4ace-bf1f-602473b13506
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398060285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3398060285
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1560813050
Short name T636
Test name
Test status
Simulation time 87720103 ps
CPU time 3.99 seconds
Started Aug 04 05:13:29 PM PDT 24
Finished Aug 04 05:13:33 PM PDT 24
Peak memory 208720 kb
Host smart-543e8bb9-17a3-46fc-975f-bb2325637ee9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560813050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1560813050
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1941998419
Short name T133
Test name
Test status
Simulation time 168161328 ps
CPU time 2.47 seconds
Started Aug 04 05:13:27 PM PDT 24
Finished Aug 04 05:13:30 PM PDT 24
Peak memory 208424 kb
Host smart-9ca570c3-ecfc-42a6-83a3-f193e131e3d5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941998419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1941998419
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.853580989
Short name T740
Test name
Test status
Simulation time 19974226 ps
CPU time 1.65 seconds
Started Aug 04 05:13:35 PM PDT 24
Finished Aug 04 05:13:36 PM PDT 24
Peak memory 207392 kb
Host smart-f31dc06a-91df-4670-bc50-5dc4e155d576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853580989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.853580989
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1009322762
Short name T857
Test name
Test status
Simulation time 2492608997 ps
CPU time 10.09 seconds
Started Aug 04 05:13:26 PM PDT 24
Finished Aug 04 05:13:36 PM PDT 24
Peak memory 208256 kb
Host smart-ccf72cdd-fdf4-4258-a3a9-fb75d2c09cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009322762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1009322762
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.48320328
Short name T786
Test name
Test status
Simulation time 1193615967 ps
CPU time 31.9 seconds
Started Aug 04 05:13:27 PM PDT 24
Finished Aug 04 05:13:59 PM PDT 24
Peak memory 216232 kb
Host smart-7e9a3c78-586d-4606-bb9b-e42c84f21339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48320328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.48320328
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1152348361
Short name T482
Test name
Test status
Simulation time 1006120281 ps
CPU time 7.14 seconds
Started Aug 04 05:13:27 PM PDT 24
Finished Aug 04 05:13:34 PM PDT 24
Peak memory 209856 kb
Host smart-e99b2c66-e36b-4df6-be92-772cf58e1df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152348361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1152348361
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2434964096
Short name T734
Test name
Test status
Simulation time 302578930 ps
CPU time 4.81 seconds
Started Aug 04 05:13:28 PM PDT 24
Finished Aug 04 05:13:33 PM PDT 24
Peak memory 210004 kb
Host smart-fd46cb5d-cc95-468e-bdd3-8a9e151a76d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434964096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2434964096
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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