Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.10	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	72	258	78.18

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	53	227	81.07	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4683

1

T1

2

T2

9

T3

3

auto[1]

510

1

T12

4

T14

2

T18

3

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4683

1

T1

2

T2

9

T3

3

auto[1]

510

1

T12

4

T14

2

T18

3

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4696

1

T1

2

T2

9

T3

3

auto[1]

497

1

T14

6

T19

1

T127

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4696

1

T1

2

T2

9

T3

3

auto[1]

497

1

T14

6

T19

1

T127

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	416	1			T1	1		T14	2		T18	1
auto[OpGenId]	1084	1			T2	2		T13	1		T14	1
auto[OpGenSwOut]	1104	1			T1	1		T2	3		T3	2
auto[OpGenHwOut]	2526	1			T2	4		T3	1		T12	11
auto[OpDisable]	63	1			T49	1		T46	2		T50	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	416	1			T1	1		T14	2		T18	1
auto[OpGenId]	1084	1			T2	2		T13	1		T14	1
auto[OpGenSwOut]	1104	1			T1	1		T2	3		T3	2
auto[OpGenHwOut]	2526	1			T2	4		T3	1		T12	11
auto[OpDisable]	63	1			T49	1		T46	2		T50	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4647

1

T2

8

T3

3

T12

11

auto[1]

546

1

T1

2

T2

1

T14

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4647

1

T2

8

T3

3

T12

11

auto[1]

546

1

T1

2

T2

1

T14

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4870

1

T1

2

T2

9

T3

3

auto[1]

323

1

T14

5

T34

3

T127

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1748	1			T1	1		T2	3		T3	2
auto[1]	727	1			T2	1		T3	1		T12	2
auto[2]	678	1			T1	1		T2	2		T18	2
auto[3]	638	1			T2	1		T12	2		T14	7
auto[4]	350	1			T12	1		T38	1		T34	2
auto[5]	326	1			T2	2		T12	1		T18	1
auto[6]	342	1			T34	1		T19	1		T203	2
auto[7]	384	1			T12	1		T18	3		T34	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1402	1			T2	2		T12	3		T18	4
clear_one[1]	727	1			T2	1		T3	1		T12	2
clear_one[2]	678	1			T1	1		T2	2		T18	2
clear_one[3]	638	1			T2	1		T12	2		T14	7
clear_none	1748	1			T1	1		T2	3		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1005	1			T2	3		T3	2		T12	3
auto[StInit]	611	1			T2	1		T3	1		T12	1
auto[StCreatorRootKey]	558	1			T2	1		T12	1		T14	1
auto[StOwnerIntKey]	505	1			T1	1		T2	1		T12	1
auto[StOwnerKey]	461	1			T2	1		T12	1		T14	1
auto[StDisabled]	1791	1			T1	1		T2	2		T12	4
auto[StInvalid]	262	1			T37	6		T38	3		T27	6

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1005	1			T2	3		T3	2		T12	3
auto[StInit]	611	1			T2	1		T3	1		T12	1
auto[StCreatorRootKey]	558	1			T2	1		T12	1		T14	1
auto[StOwnerIntKey]	505	1			T1	1		T2	1		T12	1
auto[StOwnerKey]	461	1			T2	1		T12	1		T14	1
auto[StDisabled]	1791	1			T1	1		T2	2		T12	4
auto[StInvalid]	262	1			T37	6		T38	3		T27	6

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	53	227	81.07	53

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T228	1		T229	1		T230	1
auto[0]	auto[StReset]	auto[OpGenId]	158	1			T18	2		T37	1		T34	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	155	1			T2	1		T3	2		T14	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	260	1			T2	1		T12	2		T37	2
auto[0]	auto[StInit]	auto[OpAdvance]	45	1			T231	1		T48	1		T51	1
auto[0]	auto[StInit]	auto[OpGenId]	95	1			T2	1		T18	1		T19	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	81	1			T47	1		T196	1		T28	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	146	1			T45	1		T202	1		T194	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	16	1			T64	1		T232	1		T233	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	54	1			T18	1		T231	1		T6	3
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	51	1			T46	1		T50	2		T47	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	82	1			T18	2		T19	1		T46	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	19	1			T18	1		T6	1		T234	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	33	1			T13	1		T18	1		T47	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	24	1			T1	1		T127	2		T197	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	53	1			T47	1		T204	1		T200	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T235	1		T236	1		T237	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	16	1			T18	1		T6	1		T61	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T81	1		T109	1		T64	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T194	1		T61	1		T82	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	16	1			T54	1		T238	1		T239	1
auto[0]	auto[StDisabled]	auto[OpGenId]	56	1			T34	1		T46	1		T197	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T197	1		T47	1		T109	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	172	1			T12	2		T14	2		T202	3
auto[0]	auto[StDisabled]	auto[OpDisable]	22	1			T5	1		T240	1		T69	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	11	1			T38	1		T52	1		T24	1
auto[0]	auto[StInvalid]	auto[OpGenId]	21	1			T86	1		T85	1		T198	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T27	1		T88	1		T241	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T37	1		T85	1		T114	1
auto[1]	auto[StReset]	auto[OpGenId]	15	1			T18	1		T6	1		T242	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	18	1			T60	1		T243	1		T244	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	64	1			T12	1		T203	1		T47	1
auto[1]	auto[StInit]	auto[OpAdvance]	7	1			T245	2		T76	1		T246	1
auto[1]	auto[StInit]	auto[OpGenId]	8	1			T247	1		T248	1		T93	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	13	1			T107	1		T61	1		T125	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	20	1			T3	1		T61	1		T249	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T60	1		T250	1		T251	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T45	1		T49	1		T61	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T47	1		T130	3		T252	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T6	1		T253	1		T254	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T255	1		T248	1		T75	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T19	1		T47	1		T256	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T2	1		T61	1		T83	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	38	1			T46	1		T196	1		T84	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T104	1		T257	1		T258	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	13	1			T70	1		T211	2		T259	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T36	1		T201	1		T108	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T19	1		T202	1		T197	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	23	1			T19	1		T201	1		T260	1
auto[1]	auto[StDisabled]	auto[OpGenId]	53	1			T47	1		T113	1		T245	3
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T197	1		T231	1		T47	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	159	1			T12	1		T34	2		T203	1
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T61	2		T261	1		T262	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T263	1		T264	1		T265	1
auto[1]	auto[StInvalid]	auto[OpGenId]	16	1			T241	1		T89	1		T266	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T27	1		T267	1		T198	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T37	1		T27	1		T24	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T257	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	14	1			T61	1		T211	1		T77	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	21	1			T34	1		T20	1		T85	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	42	1			T140	1		T204	2		T130	1
auto[2]	auto[StInit]	auto[OpAdvance]	10	1			T24	1		T32	1		T95	1
auto[2]	auto[StInit]	auto[OpGenId]	11	1			T126	1		T56	1		T268	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	10	1			T130	1		T92	1		T269	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	23	1			T36	1		T205	1		T270	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T271	1		T73	1		T272	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T126	1		T140	1		T273	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T2	1		T140	1		T23	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T203	1		T196	1		T61	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T45	1		T274	1		T275	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T46	1		T276	1		T277	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T82	1		T242	1		T129	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	49	1			T205	1		T278	1		T279	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T127	1		T107	1		T280	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	16	1			T231	1		T61	1		T56	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T50	1		T113	1		T281	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	36	1			T204	1		T6	1		T249	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	23	1			T1	1		T50	1		T140	3
auto[2]	auto[StDisabled]	auto[OpGenId]	50	1			T46	1		T47	1		T140	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	54	1			T18	1		T19	1		T46	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	151	1			T2	1		T18	1		T194	1
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T46	1		T50	1		T282	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	11	1			T85	1		T283	1		T284	1
auto[2]	auto[StInvalid]	auto[OpGenId]	8	1			T37	1		T27	1		T241	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T37	1		T89	1		T285	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T38	1		T52	1		T267	1
auto[3]	auto[StReset]	auto[OpGenId]	14	1			T243	1		T70	1		T262	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	17	1			T51	1		T140	1		T6	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	49	1			T203	1		T204	1		T249	1
auto[3]	auto[StInit]	auto[OpAdvance]	6	1			T34	1		T140	1		T286	1
auto[3]	auto[StInit]	auto[OpGenId]	7	1			T69	1		T287	1		T288	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	11	1			T61	1		T289	1		T211	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	26	1			T14	1		T290	1		T291	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T14	1		T130	1		T292	2
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T34	1		T46	1		T293	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T19	1		T6	1		T64	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	31	1			T84	1		T294	1		T286	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T286	1		T295	1		T229	3
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T14	1		T56	2		T268	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T131	2		T118	1		T286	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	38	1			T294	1		T270	1		T296	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T131	1		T70	1		T76	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	22	1			T107	1		T297	1		T298	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T14	1		T18	1		T130	2
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T12	1		T203	1		T205	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	27	1			T14	1		T107	1		T196	1
auto[3]	auto[StDisabled]	auto[OpGenId]	39	1			T2	1		T127	2		T61	2
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	49	1			T14	2		T18	1		T127	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	137	1			T12	1		T203	1		T46	1
auto[3]	auto[StDisabled]	auto[OpDisable]	5	1			T74	1		T55	1		T299	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	4	1			T86	1		T300	1		T301	1
auto[3]	auto[StInvalid]	auto[OpGenId]	13	1			T37	1		T198	1		T302	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T27	1		T86	1		T114	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T78	2		T303	1		T304	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T132	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T305	1		T129	1		T306	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	12	1			T85	1		T132	1		T305	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	29	1			T84	1		T249	1		T66	2
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T307	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	7	1			T132	2		T92	1		T306	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T132	3		T70	1		T308	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	14	1			T12	1		T29	1		T309	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T235	1		T310	2		T236	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T132	2		T287	1		T129	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T243	1		T104	1		T23	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T311	1		T312	1		T313	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T314	1		T310	1		T251	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T140	1		T201	1		T280	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T46	1		T192	1		T236	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T202	1		T61	1		T315	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T6	1		T257	1		T310	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	5	1			T316	1		T70	1		T224	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T293	1		T292	3		T317	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	12	1			T296	1		T110	1		T254	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	16	1			T130	1		T260	1		T211	1
auto[4]	auto[StDisabled]	auto[OpGenId]	33	1			T34	1		T81	1		T201	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	34	1			T34	1		T197	1		T47	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T203	1		T50	1		T47	1
auto[4]	auto[StDisabled]	auto[OpDisable]	2	1			T211	1		T77	1		-	-
auto[4]	auto[StInvalid]	auto[OpAdvance]	5	1			T38	1		T241	2		T318	1
auto[4]	auto[StInvalid]	auto[OpGenId]	2	1			T87	1		T319	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T86	1		T320	1		T321	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T241	1		T91	1		T322	1
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T78	1		T56	1		T132	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	7	1			T283	1		T192	1		T217	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	18	1			T2	1		T205	1		T291	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T94	1		T323	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	1	1			T239	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenSwOut]	4	1			T324	1		T325	1		T323	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	7	1			T203	1		T84	1		T313	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T326	1		T323	1		T327	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T23	1		T328	1		T329	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T46	1		T330	1		T192	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T202	1		T194	1		T278	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T50	1		T316	1		T239	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T70	1		T73	1		T331	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T64	1		T328	1		T147	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T12	1		T313	1		T332	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T239	1		T101	1		T74	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	3	1			T65	1		T180	1		T236	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T333	1		T334	1		T335	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T2	1		T234	1		T336	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	8	1			T64	1		T337	2		T236	1
auto[5]	auto[StDisabled]	auto[OpGenId]	30	1			T18	1		T83	1		T338	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T71	1		T54	1		T255	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T19	1		T49	1		T202	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T70	2		T190	1		T339	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T198	1		T266	1		T340	1
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T27	1		T86	1		T283	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T37	1		T78	1		T85	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T86	1		T91	1		T300	1
auto[6]	auto[StReset]	auto[OpGenId]	5	1			T34	1		T52	1		T320	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	14	1			T140	1		T341	1		T125	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	22	1			T56	1		T342	1		T185	1
auto[6]	auto[StInit]	auto[OpAdvance]	5	1			T298	1		T292	1		T343	1
auto[6]	auto[StInit]	auto[OpGenId]	5	1			T192	1		T344	1		T345	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	3	1			T314	1		T346	1		T347	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	13	1			T47	1		T254	1		T348	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T75	1		T349	2		T350	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T338	1		T351	1		T352	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T65	1		T98	1		T224	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T205	1		T353	1		T354	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T140	1		T333	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T231	1		T245	1		T349	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T336	1		T211	1		T235	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T203	1		T355	1		T356	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T245	1		T292	1		T357	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T61	1		T358	1		T64	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T50	1		T359	1		T360	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T56	1		T361	1		T353	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	7	1			T245	1		T325	1		T362	1
auto[6]	auto[StDisabled]	auto[OpGenId]	34	1			T50	1		T140	1		T199	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	38	1			T19	1		T5	1		T81	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	66	1			T203	1		T50	1		T84	1
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T363	1		T344	1		T364	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T87	1		T341	1		T365	1
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T302	1		T303	1		T366	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T114	1		T320	1		T301	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T85	1		T367	1		T269	1
auto[7]	auto[StReset]	auto[OpGenId]	9	1			T107	1		T280	1		T64	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	13	1			T18	1		T34	1		T6	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	25	1			T51	1		T205	1		T6	1
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T73	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T227	1		T336	1		T255	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T281	1		T368	1		T369	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	15	1			T204	1		T370	1		T371	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T227	1		T372	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T282	1		T373	1		T374	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T107	1		T375	1		T74	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T12	1		T18	1		T290	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T19	1		T132	1		T376	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T18	1		T325	1		T377	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T74	1		T181	2		T378	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T194	1		T57	1		T311	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T379	2		T380	1		T306	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	8	1			T381	1		T382	1		T95	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T379	3		T383	1		T378	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T312	1		T348	1		T384	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	9	1			T100	1		T187	1		T64	1
auto[7]	auto[StDisabled]	auto[OpGenId]	26	1			T231	1		T50	1		T107	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T130	1		T61	1		T131	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	97	1			T127	1		T196	1		T205	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T49	1		T46	1		T64	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T385	1		T319	1		T386	1
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T267	1		T341	1		T303	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T198	1		T341	1		T387	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T52	1		T88	1		T283	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1402

1

T2

2

T12

3

T18

4

clear_one[1]

auto[0]

auto[0]

auto[0]

439

1

T2

1

T3

1

T12

2

clear_one[1]

auto[0]

auto[0]

auto[1]

117

1

T34

2

T19

1

T197

1

clear_one[1]

auto[0]

auto[1]

auto[0]

126

1

T203

1

T204

1

T61

2

clear_one[1]

auto[0]

auto[1]

auto[1]

45

1

T19

1

T197

1

T47

1

clear_one[2]

auto[0]

auto[0]

auto[0]

398

1

T2

1

T18

1

T37

2

clear_one[2]

auto[0]

auto[0]

auto[1]

127

1

T1

1

T2

1

T126

1

clear_one[2]

auto[1]

auto[0]

auto[0]

113

1

T18

1

T140

4

T6

1

clear_one[2]

auto[1]

auto[0]

auto[1]

40

1

T19

1

T46

2

T107

1

clear_one[3]

auto[0]

auto[0]

auto[0]

402

1

T2

1

T14

3

T18

2

clear_one[3]

auto[0]

auto[1]

auto[0]

96

1

T14

4

T203

2

T205

4

clear_one[3]

auto[1]

auto[0]

auto[0]

107

1

T12

2

T19

1

T50

1

clear_one[3]

auto[1]

auto[1]

auto[0]

33

1

T61

1

T108

1

T109

1

clear_none

auto[0]

auto[0]

auto[0]

1254

1

T2

3

T3

2

T12

2

clear_none

auto[0]

auto[0]

auto[1]

133

1

T1

1

T19

1

T46

1

clear_none

auto[0]

auto[1]

auto[0]

112

1

T127

1

T50

1

T204

3

clear_none

auto[0]

auto[1]

auto[1]

32

1

T197

2

T47

1

T388

1

clear_none

auto[1]

auto[0]

auto[0]

133

1

T12

2

T18

2

T202

3

clear_none

auto[1]

auto[0]

auto[1]

31

1

T46

1

T107

1

T6

1

clear_none

auto[1]

auto[1]

auto[0]

32

1

T14

1

T61

1

T260

1

clear_none

auto[1]

auto[1]

auto[1]

21

1

T14

1

T6

1

T81

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1289	1			T2	2		T12	3		T18	4
clear_all	auto[1]	113	1			T34	1		T127	1		T140	1
clear_one[1]	auto[0]	652	1			T2	1		T3	1		T12	2
clear_one[1]	auto[1]	75	1			T34	1		T130	2		T132	2
clear_one[2]	auto[0]	644	1			T1	1		T2	2		T18	2
clear_one[2]	auto[1]	34	1			T140	4		T109	2		T245	1
clear_one[3]	auto[0]	592	1			T2	1		T12	2		T14	3
clear_one[3]	auto[1]	46	1			T14	4		T34	1		T127	2
clear_none	auto[0]	1693	1			T1	1		T2	3		T3	2
clear_none	auto[1]	55	1			T14	1		T127	1		T140	1