Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10738

1

T1

9

T2

10

T3

16

auto[Attestation]

7107

1

T1

12

T2

7

T3

1

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2534	1			T1	6		T2	4		T3	3
auto[Aes]	3264	1			T1	3		T2	3		T3	4
auto[Kmac]	3208	1			T1	5		T2	2		T3	3
auto[Otbn]	3260	1			T1	4		T2	4		T3	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7242	1			T1	8		T2	8		T3	1
auto[OpGenId]	5579	1			T1	3		T2	4		T3	4
auto[OpGenSwOut]	5512	1			T1	8		T2	5		T3	7
auto[OpGenHwOut]	6754	1			T1	10		T2	8		T3	6
auto[OpDisable]	130	1			T49	1		T46	2		T50	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9970

1

T1

14

T2

8

T3

1

auto[OpDoneFail]

15247

1

T1

15

T2

17

T3

17

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6291	1			T1	1		T2	10		T3	13
auto[StInit]	3565	1			T1	3		T2	2		T3	5
auto[StCreatorRootKey]	2996	1			T1	4		T2	2		T12	2
auto[StOwnerIntKey]	2623	1			T1	3		T2	2		T12	2
auto[StOwnerKey]	2264	1			T1	5		T2	2		T12	2
auto[StDisabled]	7478	1			T1	13		T2	7		T12	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	319	1			T2	1		T14	1		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	97	1			T1	1		T3	2		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	83	1			T18	2		T47	2		T107	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T14	1		T47	1		T107	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	54	1			T34	1		T47	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	196	1			T1	1		T34	1		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	341	1			T3	2		T17	2		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	95	1			T15	1		T34	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	74	1			T14	1		T15	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	55	1			T127	2		T46	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	56	1			T46	1		T197	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	210	1			T14	1		T18	2		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	290	1			T3	2		T15	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	79	1			T19	1		T50	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	73	1			T1	1		T18	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	57	1			T18	1		T196	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	56	1			T46	1		T47	2		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	229	1			T1	1		T2	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	356	1			T2	1		T3	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	94	1			T34	1		T35	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T35	1		T47	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	79	1			T50	1		T47	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	57	1			T14	1		T18	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	209	1			T15	1		T17	1		T18	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	57	1			T61	5		T198	2		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	86	1			T18	2		T46	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	75	1			T13	1		T14	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	57	1			T2	1		T18	2		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T15	1		T17	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	214	1			T18	3		T127	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	66	1			T199	1		T61	1		T198	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	111	1			T17	1		T126	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	68	1			T18	1		T46	1		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	70	1			T17	1		T34	2		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	61	1			T18	2		T140	2		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	204	1			T1	1		T18	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	70	1			T46	1		T61	2		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	94	1			T18	1		T36	1		T39	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	65	1			T46	1		T50	1		T195	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	67	1			T47	1		T107	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	59	1			T50	1		T47	2		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	190	1			T1	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	47	1			T107	1		T6	2		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	81	1			T19	1		T50	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	72	1			T2	1		T19	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T1	1		T18	1		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	62	1			T1	1		T34	1		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	202	1			T18	3		T19	1		T127	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	253	1			T2	1		T3	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	96	1			T1	1		T18	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	65	1			T18	1		T45	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	56	1			T46	1		T200	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	46	1			T47	1		T36	1		T107	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	174	1			T1	1		T18	1		T127	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	507	1			T2	3		T3	1		T12	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	108	1			T3	1		T14	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	98	1			T12	1		T18	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	101	1			T12	1		T107	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	82	1			T202	1		T50	2		T6	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	258	1			T1	1		T12	2		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	525	1			T2	1		T3	1		T203	9
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	104	1			T196	1		T204	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	108	1			T18	1		T126	1		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	83	1			T127	1		T46	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	83	1			T14	1		T47	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	274	1			T49	1		T203	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	455	1			T3	2		T18	2		T37	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	128	1			T46	1		T197	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T1	1		T19	2		T126	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	76	1			T13	1		T107	1		T194	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	80	1			T14	1		T197	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	280	1			T14	1		T19	2		T127	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	55	1			T198	1		T56	3		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	82	1			T14	1		T46	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	66	1			T1	1		T18	1		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	73	1			T1	1		T46	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	45	1			T48	1		T107	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	159	1			T2	1		T34	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	50	1			T50	1		T56	3		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	109	1			T12	1		T34	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	96	1			T49	1		T46	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	97	1			T202	1		T36	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	70	1			T12	1		T18	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	277	1			T1	1		T12	2		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	45	1			T6	1		T61	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	114	1			T45	1		T203	1		T107	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T205	1		T39	1		T61	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T45	2		T203	1		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	81	1			T1	1		T19	1		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	257	1			T1	1		T18	1		T203	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	58	1			T56	1		T69	2		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	102	1			T49	1		T194	1		T20	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	119	1			T14	1		T18	2		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	85	1			T13	1		T50	1		T107	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	72	1			T2	1		T47	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	287	1			T1	1		T2	1		T14	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	184	1			T14	1		T18	2		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	632	1			T1	2		T2	1		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	172	1			T14	1		T15	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	659	1			T3	2		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	174	1			T1	1		T18	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	610	1			T1	1		T2	1		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	197	1			T14	1		T18	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	675	1			T2	1		T3	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	181	1			T2	1		T13	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	367	1			T18	5		T127	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	186	1			T17	1		T18	1		T34	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	394	1			T1	1		T17	1		T18	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	175	1			T46	1		T50	2		T47	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	370	1			T1	1		T17	1		T18	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	194	1			T1	2		T2	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	342	1			T18	4		T19	3		T127	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	158	1			T18	1		T45	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	532	1			T1	2		T2	1		T3	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	254	1			T12	2		T18	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	900	1			T1	1		T2	3		T3	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	264	1			T14	1		T18	1		T126	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	913	1			T2	1		T3	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	252	1			T1	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	877	1			T3	2		T14	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	159	1			T1	2		T18	1		T46	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	321	1			T2	1		T14	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	238	1			T12	1		T19	1		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	461	1			T1	1		T12	3		T18	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	277	1			T1	1		T45	2		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	425	1			T1	1		T18	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	255	1			T2	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	468	1			T1	1		T2	1		T14	1