Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30984

1

T1

34

T2

31

T3

20

auto[1]

328

1

T14

3

T34

10

T127

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30997	1			T1	34		T2	31		T3	20
auto[134217728:268435455]	10	1			T34	1		T140	1		T132	2
auto[268435456:402653183]	12	1			T130	1		T132	2		T358	1
auto[402653184:536870911]	11	1			T358	1		T228	1		T257	1
auto[536870912:671088639]	7	1			T409	1		T292	1		T310	1
auto[671088640:805306367]	10	1			T140	1		T409	1		T132	1
auto[805306368:939524095]	11	1			T34	2		T131	1		T132	1
auto[939524096:1073741823]	8	1			T131	1		T132	1		T245	2
auto[1073741824:1207959551]	11	1			T127	1		T245	1		T274	1
auto[1207959552:1342177279]	14	1			T14	1		T130	1		T132	1
auto[1342177280:1476395007]	4	1			T379	1		T358	1		T410	1
auto[1476395008:1610612735]	11	1			T109	2		T245	1		T239	1
auto[1610612736:1744830463]	10	1			T127	1		T132	1		T358	1
auto[1744830464:1879048191]	14	1			T14	1		T34	1		T292	1
auto[1879048192:2013265919]	8	1			T130	1		T132	1		T228	1
auto[2013265920:2147483647]	11	1			T34	1		T379	1		T410	1
auto[2147483648:2281701375]	12	1			T127	1		T132	2		T245	1
auto[2281701376:2415919103]	11	1			T34	1		T127	1		T130	1
auto[2415919104:2550136831]	6	1			T409	1		T245	1		T411	1
auto[2550136832:2684354559]	13	1			T109	1		T132	2		T292	1
auto[2684354560:2818572287]	6	1			T228	1		T334	1		T350	1
auto[2818572288:2952790015]	9	1			T34	1		T131	1		T409	1
auto[2952790016:3087007743]	14	1			T34	1		T127	1		T131	1
auto[3087007744:3221225471]	11	1			T410	2		T323	1		T412	1
auto[3221225472:3355443199]	7	1			T379	1		T274	1		T413	1
auto[3355443200:3489660927]	12	1			T127	1		T131	1		T409	1
auto[3489660928:3623878655]	8	1			T140	1		T130	1		T131	1
auto[3623878656:3758096383]	18	1			T34	1		T140	1		T358	3
auto[3758096384:3892314111]	8	1			T379	2		T228	1		T414	1
auto[3892314112:4026531839]	7	1			T132	1		T292	1		T337	1
auto[4026531840:4160749567]	8	1			T409	2		T415	1		T337	1
auto[4160749568:4294967295]	13	1			T34	1		T130	1		T109	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30984	1			T1	34		T2	31		T3	20
auto[0:134217727]	auto[1]	13	1			T14	1		T130	1		T132	1
auto[134217728:268435455]	auto[1]	10	1			T34	1		T140	1		T132	2
auto[268435456:402653183]	auto[1]	12	1			T130	1		T132	2		T358	1
auto[402653184:536870911]	auto[1]	11	1			T358	1		T228	1		T257	1
auto[536870912:671088639]	auto[1]	7	1			T409	1		T292	1		T310	1
auto[671088640:805306367]	auto[1]	10	1			T140	1		T409	1		T132	1
auto[805306368:939524095]	auto[1]	11	1			T34	2		T131	1		T132	1
auto[939524096:1073741823]	auto[1]	8	1			T131	1		T132	1		T245	2
auto[1073741824:1207959551]	auto[1]	11	1			T127	1		T245	1		T274	1
auto[1207959552:1342177279]	auto[1]	14	1			T14	1		T130	1		T132	1
auto[1342177280:1476395007]	auto[1]	4	1			T379	1		T358	1		T410	1
auto[1476395008:1610612735]	auto[1]	11	1			T109	2		T245	1		T239	1
auto[1610612736:1744830463]	auto[1]	10	1			T127	1		T132	1		T358	1
auto[1744830464:1879048191]	auto[1]	14	1			T14	1		T34	1		T292	1
auto[1879048192:2013265919]	auto[1]	8	1			T130	1		T132	1		T228	1
auto[2013265920:2147483647]	auto[1]	11	1			T34	1		T379	1		T410	1
auto[2147483648:2281701375]	auto[1]	12	1			T127	1		T132	2		T245	1
auto[2281701376:2415919103]	auto[1]	11	1			T34	1		T127	1		T130	1
auto[2415919104:2550136831]	auto[1]	6	1			T409	1		T245	1		T411	1
auto[2550136832:2684354559]	auto[1]	13	1			T109	1		T132	2		T292	1
auto[2684354560:2818572287]	auto[1]	6	1			T228	1		T334	1		T350	1
auto[2818572288:2952790015]	auto[1]	9	1			T34	1		T131	1		T409	1
auto[2952790016:3087007743]	auto[1]	14	1			T34	1		T127	1		T131	1
auto[3087007744:3221225471]	auto[1]	11	1			T410	2		T323	1		T412	1
auto[3221225472:3355443199]	auto[1]	7	1			T379	1		T274	1		T413	1
auto[3355443200:3489660927]	auto[1]	12	1			T127	1		T131	1		T409	1
auto[3489660928:3623878655]	auto[1]	8	1			T140	1		T130	1		T131	1
auto[3623878656:3758096383]	auto[1]	18	1			T34	1		T140	1		T358	3
auto[3758096384:3892314111]	auto[1]	8	1			T379	2		T228	1		T414	1
auto[3892314112:4026531839]	auto[1]	7	1			T132	1		T292	1		T337	1
auto[4026531840:4160749567]	auto[1]	8	1			T409	2		T415	1		T337	1
auto[4160749568:4294967295]	auto[1]	13	1			T34	1		T130	1		T109	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1502

1

T1

4

T3

3

T14

2

auto[1]

1639

1

T1

2

T13

1

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T18	2		T46	1		T197	1
auto[134217728:268435455]	104	1			T38	1		T34	1		T46	1
auto[268435456:402653183]	98	1			T3	1		T127	1		T197	1
auto[402653184:536870911]	86	1			T18	1		T37	1		T231	1
auto[536870912:671088639]	99	1			T37	1		T4	1		T46	1
auto[671088640:805306367]	97	1			T19	2		T46	2		T47	1
auto[805306368:939524095]	95	1			T1	2		T13	1		T37	1
auto[939524096:1073741823]	110	1			T1	1		T14	1		T18	1
auto[1073741824:1207959551]	96	1			T18	1		T37	3		T19	3
auto[1207959552:1342177279]	89	1			T18	1		T46	1		T6	2
auto[1342177280:1476395007]	94	1			T38	2		T19	1		T127	1
auto[1476395008:1610612735]	109	1			T14	1		T38	1		T49	1
auto[1610612736:1744830463]	90	1			T19	1		T47	1		T6	1
auto[1744830464:1879048191]	87	1			T19	1		T4	1		T27	1
auto[1879048192:2013265919]	93	1			T50	1		T28	1		T200	1
auto[2013265920:2147483647]	93	1			T19	1		T127	1		T46	1
auto[2147483648:2281701375]	98	1			T14	1		T37	1		T27	1
auto[2281701376:2415919103]	85	1			T47	2		T130	1		T199	1
auto[2415919104:2550136831]	109	1			T14	1		T127	1		T28	1
auto[2550136832:2684354559]	100	1			T18	2		T19	1		T46	1
auto[2684354560:2818572287]	113	1			T14	1		T38	1		T47	1
auto[2818572288:2952790015]	104	1			T197	1		T231	1		T107	1
auto[2952790016:3087007743]	110	1			T18	1		T34	1		T36	1
auto[3087007744:3221225471]	90	1			T38	1		T4	1		T107	1
auto[3221225472:3355443199]	97	1			T49	1		T126	1		T47	3
auto[3355443200:3489660927]	84	1			T197	1		T231	1		T47	2
auto[3489660928:3623878655]	98	1			T1	1		T3	1		T18	1
auto[3623878656:3758096383]	104	1			T18	1		T37	1		T47	2
auto[3758096384:3892314111]	97	1			T20	1		T140	1		T53	1
auto[3892314112:4026531839]	88	1			T34	1		T50	3		T48	1
auto[4026531840:4160749567]	103	1			T1	2		T3	1		T18	1
auto[4160749568:4294967295]	111	1			T38	1		T19	1		T50	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T46	1		T47	1		T51	1
auto[0:134217727]	auto[1]	64	1			T18	2		T197	1		T140	1
auto[134217728:268435455]	auto[0]	51	1			T34	1		T47	1		T61	1
auto[134217728:268435455]	auto[1]	53	1			T38	1		T46	1		T47	1
auto[268435456:402653183]	auto[0]	52	1			T3	1		T107	1		T20	1
auto[268435456:402653183]	auto[1]	46	1			T127	1		T197	1		T6	1
auto[402653184:536870911]	auto[0]	33	1			T37	1		T231	1		T47	1
auto[402653184:536870911]	auto[1]	53	1			T18	1		T47	1		T107	1
auto[536870912:671088639]	auto[0]	39	1			T4	1		T78	1		T226	1
auto[536870912:671088639]	auto[1]	60	1			T37	1		T46	1		T48	1
auto[671088640:805306367]	auto[0]	39	1			T46	2		T47	1		T130	1
auto[671088640:805306367]	auto[1]	58	1			T19	2		T6	1		T60	1
auto[805306368:939524095]	auto[0]	51	1			T1	1		T50	1		T6	1
auto[805306368:939524095]	auto[1]	44	1			T1	1		T13	1		T37	1
auto[939524096:1073741823]	auto[0]	55	1			T1	1		T18	1		T37	1
auto[939524096:1073741823]	auto[1]	55	1			T14	1		T38	1		T47	1
auto[1073741824:1207959551]	auto[0]	45	1			T18	1		T37	1		T47	3
auto[1073741824:1207959551]	auto[1]	51	1			T37	2		T19	3		T46	1
auto[1207959552:1342177279]	auto[0]	42	1			T6	1		T66	1		T131	1
auto[1207959552:1342177279]	auto[1]	47	1			T18	1		T46	1		T6	1
auto[1342177280:1476395007]	auto[0]	44	1			T38	1		T127	1		T50	1
auto[1342177280:1476395007]	auto[1]	50	1			T38	1		T19	1		T60	1
auto[1476395008:1610612735]	auto[0]	55	1			T46	1		T48	1		T5	2
auto[1476395008:1610612735]	auto[1]	54	1			T14	1		T38	1		T49	1
auto[1610612736:1744830463]	auto[0]	43	1			T6	1		T132	2		T388	1
auto[1610612736:1744830463]	auto[1]	47	1			T19	1		T47	1		T61	1
auto[1744830464:1879048191]	auto[0]	43	1			T4	1		T27	1		T50	1
auto[1744830464:1879048191]	auto[1]	44	1			T19	1		T60	1		T61	1
auto[1879048192:2013265919]	auto[0]	46	1			T28	1		T53	1		T280	1
auto[1879048192:2013265919]	auto[1]	47	1			T50	1		T200	1		T6	1
auto[2013265920:2147483647]	auto[0]	42	1			T47	1		T20	1		T52	1
auto[2013265920:2147483647]	auto[1]	51	1			T19	1		T127	1		T46	1
auto[2147483648:2281701375]	auto[0]	49	1			T14	1		T37	1		T6	1
auto[2147483648:2281701375]	auto[1]	49	1			T27	1		T107	1		T52	1
auto[2281701376:2415919103]	auto[0]	45	1			T130	1		T199	1		T86	1
auto[2281701376:2415919103]	auto[1]	40	1			T47	2		T5	1		T6	2
auto[2415919104:2550136831]	auto[0]	44	1			T416	1		T70	1		T71	1
auto[2415919104:2550136831]	auto[1]	65	1			T14	1		T127	1		T28	1
auto[2550136832:2684354559]	auto[0]	39	1			T18	1		T19	1		T46	1
auto[2550136832:2684354559]	auto[1]	61	1			T18	1		T47	1		T48	1
auto[2684354560:2818572287]	auto[0]	64	1			T14	1		T38	1		T47	1
auto[2684354560:2818572287]	auto[1]	49	1			T118	1		T417	1		T409	1
auto[2818572288:2952790015]	auto[0]	55	1			T231	1		T107	1		T61	1
auto[2818572288:2952790015]	auto[1]	49	1			T197	1		T196	1		T6	1
auto[2952790016:3087007743]	auto[0]	64	1			T18	1		T34	1		T36	1
auto[2952790016:3087007743]	auto[1]	46	1			T40	1		T140	1		T61	2
auto[3087007744:3221225471]	auto[0]	36	1			T38	1		T4	1		T86	1
auto[3087007744:3221225471]	auto[1]	54	1			T107	1		T61	1		T338	1
auto[3221225472:3355443199]	auto[0]	48	1			T53	1		T5	1		T61	1
auto[3221225472:3355443199]	auto[1]	49	1			T49	1		T126	1		T47	3
auto[3355443200:3489660927]	auto[0]	40	1			T197	1		T47	2		T141	1
auto[3355443200:3489660927]	auto[1]	44	1			T231	1		T36	1		T107	2
auto[3489660928:3623878655]	auto[0]	53	1			T3	1		T18	1		T53	1
auto[3489660928:3623878655]	auto[1]	45	1			T1	1		T49	1		T46	1
auto[3623878656:3758096383]	auto[0]	53	1			T18	1		T47	1		T6	1
auto[3623878656:3758096383]	auto[1]	51	1			T37	1		T47	1		T196	1
auto[3758096384:3892314111]	auto[0]	43	1			T53	1		T60	1		T61	1
auto[3758096384:3892314111]	auto[1]	54	1			T20	1		T140	1		T82	1
auto[3892314112:4026531839]	auto[0]	40	1			T34	1		T50	1		T48	1
auto[3892314112:4026531839]	auto[1]	48	1			T50	2		T196	1		T66	1
auto[4026531840:4160749567]	auto[0]	48	1			T1	2		T3	1		T18	1
auto[4026531840:4160749567]	auto[1]	55	1			T37	1		T231	1		T50	1
auto[4160749568:4294967295]	auto[0]	55	1			T19	1		T20	1		T53	1
auto[4160749568:4294967295]	auto[1]	56	1			T38	1		T50	2		T47	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1520

1

T1

3

T3

3

T14

1

auto[1]

1621

1

T1

3

T13

1

T14

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	83	1			T37	1		T38	1		T34	1
auto[134217728:268435455]	94	1			T14	1		T18	1		T19	1
auto[268435456:402653183]	72	1			T47	2		T200	1		T61	1
auto[402653184:536870911]	99	1			T1	1		T38	1		T231	1
auto[536870912:671088639]	97	1			T4	1		T50	1		T36	1
auto[671088640:805306367]	95	1			T1	1		T46	1		T47	1
auto[805306368:939524095]	117	1			T38	1		T46	1		T47	5
auto[939524096:1073741823]	100	1			T3	1		T49	1		T46	2
auto[1073741824:1207959551]	107	1			T3	1		T13	1		T37	1
auto[1207959552:1342177279]	95	1			T1	1		T38	1		T4	1
auto[1342177280:1476395007]	108	1			T14	1		T231	1		T40	1
auto[1476395008:1610612735]	94	1			T46	1		T20	2		T52	1
auto[1610612736:1744830463]	82	1			T1	1		T18	1		T38	1
auto[1744830464:1879048191]	94	1			T3	1		T18	1		T37	1
auto[1879048192:2013265919]	86	1			T18	1		T46	2		T57	1
auto[2013265920:2147483647]	117	1			T37	1		T38	1		T34	2
auto[2147483648:2281701375]	104	1			T37	1		T127	2		T46	1
auto[2281701376:2415919103]	107	1			T37	2		T38	1		T19	1
auto[2415919104:2550136831]	98	1			T1	1		T14	1		T37	1
auto[2550136832:2684354559]	96	1			T18	1		T37	1		T19	1
auto[2684354560:2818572287]	108	1			T47	1		T196	1		T6	3
auto[2818572288:2952790015]	101	1			T47	1		T6	1		T86	1
auto[2952790016:3087007743]	100	1			T18	2		T19	2		T49	1
auto[3087007744:3221225471]	88	1			T14	1		T19	1		T126	1
auto[3221225472:3355443199]	102	1			T18	1		T19	1		T197	1
auto[3355443200:3489660927]	102	1			T19	3		T47	1		T130	1
auto[3489660928:3623878655]	92	1			T14	1		T47	1		T6	1
auto[3623878656:3758096383]	118	1			T1	1		T18	3		T47	4
auto[3758096384:3892314111]	80	1			T34	1		T46	1		T47	1
auto[3892314112:4026531839]	115	1			T197	1		T50	1		T48	1
auto[4026531840:4160749567]	101	1			T18	1		T38	1		T49	1
auto[4160749568:4294967295]	89	1			T37	1		T47	1		T51	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	41	1			T37	1		T38	1		T34	1
auto[0:134217727]	auto[1]	42	1			T231	1		T6	1		T60	1
auto[134217728:268435455]	auto[0]	44	1			T18	1		T196	1		T200	1
auto[134217728:268435455]	auto[1]	50	1			T14	1		T19	1		T46	1
auto[268435456:402653183]	auto[0]	33	1			T61	1		T78	1		T85	1
auto[268435456:402653183]	auto[1]	39	1			T47	2		T200	1		T226	1
auto[402653184:536870911]	auto[0]	48	1			T1	1		T47	2		T48	1
auto[402653184:536870911]	auto[1]	51	1			T38	1		T231	1		T50	1
auto[536870912:671088639]	auto[0]	45	1			T4	1		T50	1		T36	1
auto[536870912:671088639]	auto[1]	52	1			T78	1		T65	1		T56	1
auto[671088640:805306367]	auto[0]	42	1			T46	1		T130	1		T6	2
auto[671088640:805306367]	auto[1]	53	1			T1	1		T47	1		T65	1
auto[805306368:939524095]	auto[0]	49	1			T38	1		T47	3		T36	1
auto[805306368:939524095]	auto[1]	68	1			T46	1		T47	2		T48	1
auto[939524096:1073741823]	auto[0]	44	1			T3	1		T46	1		T107	1
auto[939524096:1073741823]	auto[1]	56	1			T49	1		T46	1		T114	1
auto[1073741824:1207959551]	auto[0]	57	1			T3	1		T47	1		T6	1
auto[1073741824:1207959551]	auto[1]	50	1			T13	1		T37	1		T107	1
auto[1207959552:1342177279]	auto[0]	54	1			T1	1		T38	1		T4	1
auto[1207959552:1342177279]	auto[1]	41	1			T6	1		T280	1		T418	1
auto[1342177280:1476395007]	auto[0]	49	1			T40	1		T61	2		T78	1
auto[1342177280:1476395007]	auto[1]	59	1			T14	1		T231	1		T6	1
auto[1476395008:1610612735]	auto[0]	44	1			T20	2		T52	1		T28	1
auto[1476395008:1610612735]	auto[1]	50	1			T46	1		T140	1		T86	1
auto[1610612736:1744830463]	auto[0]	37	1			T1	1		T18	1		T38	1
auto[1610612736:1744830463]	auto[1]	45	1			T6	1		T60	1		T78	1
auto[1744830464:1879048191]	auto[0]	45	1			T3	1		T18	1		T61	2
auto[1744830464:1879048191]	auto[1]	49	1			T37	1		T197	1		T47	1
auto[1879048192:2013265919]	auto[0]	34	1			T46	1		T28	1		T5	1
auto[1879048192:2013265919]	auto[1]	52	1			T18	1		T46	1		T57	1
auto[2013265920:2147483647]	auto[0]	61	1			T37	1		T231	2		T6	2
auto[2013265920:2147483647]	auto[1]	56	1			T38	1		T34	2		T46	1
auto[2147483648:2281701375]	auto[0]	51	1			T37	1		T196	1		T53	1
auto[2147483648:2281701375]	auto[1]	53	1			T127	2		T46	1		T50	2
auto[2281701376:2415919103]	auto[0]	59	1			T37	1		T47	2		T86	1
auto[2281701376:2415919103]	auto[1]	48	1			T37	1		T38	1		T19	1
auto[2415919104:2550136831]	auto[0]	44	1			T107	1		T28	1		T6	1
auto[2415919104:2550136831]	auto[1]	54	1			T1	1		T14	1		T37	1
auto[2550136832:2684354559]	auto[0]	53	1			T50	1		T107	1		T196	1
auto[2550136832:2684354559]	auto[1]	43	1			T18	1		T37	1		T19	1
auto[2684354560:2818572287]	auto[0]	48	1			T47	1		T6	1		T86	1
auto[2684354560:2818572287]	auto[1]	60	1			T196	1		T6	2		T61	2
auto[2818572288:2952790015]	auto[0]	53	1			T47	1		T86	1		T26	1
auto[2818572288:2952790015]	auto[1]	48	1			T6	1		T60	1		T65	2
auto[2952790016:3087007743]	auto[0]	48	1			T18	1		T19	2		T6	1
auto[2952790016:3087007743]	auto[1]	52	1			T18	1		T49	1		T196	1
auto[3087007744:3221225471]	auto[0]	46	1			T14	1		T50	1		T47	1
auto[3087007744:3221225471]	auto[1]	42	1			T19	1		T126	1		T27	1
auto[3221225472:3355443199]	auto[0]	40	1			T50	1		T6	1		T61	1
auto[3221225472:3355443199]	auto[1]	62	1			T18	1		T19	1		T197	1
auto[3355443200:3489660927]	auto[0]	48	1			T19	3		T130	1		T5	1
auto[3355443200:3489660927]	auto[1]	54	1			T47	1		T61	1		T240	1
auto[3489660928:3623878655]	auto[0]	45	1			T6	1		T108	1		T305	1
auto[3489660928:3623878655]	auto[1]	47	1			T14	1		T47	1		T61	1
auto[3623878656:3758096383]	auto[0]	56	1			T18	2		T47	2		T199	2
auto[3623878656:3758096383]	auto[1]	62	1			T1	1		T18	1		T47	2
auto[3758096384:3892314111]	auto[0]	39	1			T34	1		T61	1		T81	1
auto[3758096384:3892314111]	auto[1]	41	1			T46	1		T47	1		T140	3
auto[3892314112:4026531839]	auto[0]	65	1			T197	1		T48	1		T53	1
auto[3892314112:4026531839]	auto[1]	50	1			T50	1		T200	1		T66	1
auto[4026531840:4160749567]	auto[0]	50	1			T18	1		T49	1		T53	1
auto[4026531840:4160749567]	auto[1]	51	1			T38	1		T4	1		T47	1
auto[4160749568:4294967295]	auto[0]	48	1			T6	1		T60	1		T88	1
auto[4160749568:4294967295]	auto[1]	41	1			T37	1		T47	1		T51	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1493

1

T1

4

T3

3

T14

1

auto[1]

1647

1

T1

2

T13

1

T14

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T19	1		T50	1		T47	1
auto[134217728:268435455]	105	1			T38	1		T46	1		T47	1
auto[268435456:402653183]	78	1			T37	1		T34	1		T47	1
auto[402653184:536870911]	98	1			T14	1		T50	2		T47	2
auto[536870912:671088639]	96	1			T3	1		T14	1		T38	1
auto[671088640:805306367]	97	1			T18	2		T38	1		T19	1
auto[805306368:939524095]	94	1			T18	1		T37	1		T197	1
auto[939524096:1073741823]	95	1			T18	1		T37	1		T38	1
auto[1073741824:1207959551]	91	1			T1	1		T4	1		T46	1
auto[1207959552:1342177279]	114	1			T1	1		T197	1		T231	1
auto[1342177280:1476395007]	110	1			T19	1		T47	2		T52	1
auto[1476395008:1610612735]	91	1			T19	1		T197	1		T47	1
auto[1610612736:1744830463]	77	1			T18	2		T127	1		T4	1
auto[1744830464:1879048191]	105	1			T19	1		T140	2		T53	2
auto[1879048192:2013265919]	102	1			T37	1		T38	2		T48	1
auto[2013265920:2147483647]	105	1			T1	1		T14	1		T34	1
auto[2147483648:2281701375]	100	1			T14	1		T46	1		T107	1
auto[2281701376:2415919103]	120	1			T18	1		T37	1		T46	1
auto[2415919104:2550136831]	96	1			T18	2		T37	2		T19	1
auto[2550136832:2684354559]	93	1			T18	1		T46	1		T47	1
auto[2684354560:2818572287]	95	1			T38	1		T34	1		T19	1
auto[2818572288:2952790015]	101	1			T18	1		T19	1		T50	1
auto[2952790016:3087007743]	87	1			T1	1		T50	1		T61	1
auto[3087007744:3221225471]	80	1			T3	1		T27	1		T107	1
auto[3221225472:3355443199]	101	1			T37	2		T38	1		T34	1
auto[3355443200:3489660927]	108	1			T3	1		T37	1		T127	1
auto[3489660928:3623878655]	92	1			T1	1		T49	1		T4	1
auto[3623878656:3758096383]	97	1			T13	1		T14	1		T46	1
auto[3758096384:3892314111]	97	1			T231	1		T36	1		T107	1
auto[3892314112:4026531839]	114	1			T1	1		T49	2		T48	1
auto[4026531840:4160749567]	88	1			T18	1		T19	1		T46	1
auto[4160749568:4294967295]	105	1			T47	1		T20	1		T53	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T107	1		T28	1		T200	1
auto[0:134217727]	auto[1]	56	1			T19	1		T50	1		T47	1
auto[134217728:268435455]	auto[0]	46	1			T47	1		T61	2		T78	2
auto[134217728:268435455]	auto[1]	59	1			T38	1		T46	1		T107	1
auto[268435456:402653183]	auto[0]	40	1			T34	1		T47	1		T199	1
auto[268435456:402653183]	auto[1]	38	1			T37	1		T57	1		T6	4
auto[402653184:536870911]	auto[0]	46	1			T50	1		T47	2		T196	1
auto[402653184:536870911]	auto[1]	52	1			T14	1		T50	1		T140	1
auto[536870912:671088639]	auto[0]	42	1			T3	1		T38	1		T200	1
auto[536870912:671088639]	auto[1]	54	1			T14	1		T127	1		T231	1
auto[671088640:805306367]	auto[0]	50	1			T46	1		T47	2		T53	1
auto[671088640:805306367]	auto[1]	47	1			T18	2		T38	1		T19	1
auto[805306368:939524095]	auto[0]	50	1			T18	1		T37	1		T197	1
auto[805306368:939524095]	auto[1]	44	1			T47	1		T6	2		T271	1
auto[939524096:1073741823]	auto[0]	50	1			T18	1		T47	1		T48	1
auto[939524096:1073741823]	auto[1]	45	1			T37	1		T38	1		T19	1
auto[1073741824:1207959551]	auto[0]	42	1			T4	1		T46	1		T47	1
auto[1073741824:1207959551]	auto[1]	49	1			T1	1		T50	1		T6	1
auto[1207959552:1342177279]	auto[0]	61	1			T1	1		T197	1		T199	1
auto[1207959552:1342177279]	auto[1]	53	1			T231	1		T82	1		T271	1
auto[1342177280:1476395007]	auto[0]	57	1			T47	1		T52	1		T53	1
auto[1342177280:1476395007]	auto[1]	53	1			T19	1		T47	1		T81	1
auto[1476395008:1610612735]	auto[0]	42	1			T130	1		T6	1		T85	1
auto[1476395008:1610612735]	auto[1]	49	1			T19	1		T197	1		T47	1
auto[1610612736:1744830463]	auto[0]	33	1			T18	1		T46	2		T53	1
auto[1610612736:1744830463]	auto[1]	44	1			T18	1		T127	1		T4	1
auto[1744830464:1879048191]	auto[0]	49	1			T53	2		T6	2		T61	1
auto[1744830464:1879048191]	auto[1]	56	1			T19	1		T140	2		T61	1
auto[1879048192:2013265919]	auto[0]	56	1			T37	1		T38	1		T86	1
auto[1879048192:2013265919]	auto[1]	46	1			T38	1		T48	1		T6	1
auto[2013265920:2147483647]	auto[0]	55	1			T1	1		T50	1		T48	1
auto[2013265920:2147483647]	auto[1]	50	1			T14	1		T34	1		T130	1
auto[2147483648:2281701375]	auto[0]	47	1			T196	1		T61	2		T381	1
auto[2147483648:2281701375]	auto[1]	53	1			T14	1		T46	1		T107	1
auto[2281701376:2415919103]	auto[0]	56	1			T46	1		T47	1		T20	1
auto[2281701376:2415919103]	auto[1]	64	1			T18	1		T37	1		T231	1
auto[2415919104:2550136831]	auto[0]	42	1			T18	1		T37	1		T19	1
auto[2415919104:2550136831]	auto[1]	54	1			T18	1		T37	1		T126	1
auto[2550136832:2684354559]	auto[0]	44	1			T18	1		T46	1		T47	1
auto[2550136832:2684354559]	auto[1]	49	1			T196	1		T52	1		T201	1
auto[2684354560:2818572287]	auto[0]	40	1			T34	1		T231	1		T6	3
auto[2684354560:2818572287]	auto[1]	55	1			T38	1		T19	1		T197	1
auto[2818572288:2952790015]	auto[0]	46	1			T18	1		T50	1		T20	1
auto[2818572288:2952790015]	auto[1]	55	1			T19	1		T61	2		T114	1
auto[2952790016:3087007743]	auto[0]	47	1			T1	1		T50	1		T198	1
auto[2952790016:3087007743]	auto[1]	40	1			T61	1		T78	1		T104	1
auto[3087007744:3221225471]	auto[0]	41	1			T3	1		T27	1		T6	1
auto[3087007744:3221225471]	auto[1]	39	1			T107	1		T196	1		T6	1
auto[3221225472:3355443199]	auto[0]	45	1			T37	1		T38	1		T34	1
auto[3221225472:3355443199]	auto[1]	56	1			T37	1		T127	1		T47	2
auto[3355443200:3489660927]	auto[0]	56	1			T3	1		T47	1		T61	1
auto[3355443200:3489660927]	auto[1]	52	1			T37	1		T127	1		T27	1
auto[3489660928:3623878655]	auto[0]	46	1			T4	1		T47	2		T36	1
auto[3489660928:3623878655]	auto[1]	46	1			T1	1		T49	1		T50	1
auto[3623878656:3758096383]	auto[0]	40	1			T14	1		T6	2		T66	1
auto[3623878656:3758096383]	auto[1]	57	1			T13	1		T46	1		T81	1
auto[3758096384:3892314111]	auto[0]	39	1			T231	1		T61	1		T85	2
auto[3758096384:3892314111]	auto[1]	58	1			T36	1		T107	1		T65	1
auto[3892314112:4026531839]	auto[0]	56	1			T1	1		T49	1		T53	1
auto[3892314112:4026531839]	auto[1]	58	1			T49	1		T48	1		T140	1
auto[4026531840:4160749567]	auto[0]	26	1			T46	1		T50	1		T28	1
auto[4026531840:4160749567]	auto[1]	62	1			T18	1		T19	1		T50	1
auto[4160749568:4294967295]	auto[0]	51	1			T20	1		T53	1		T109	1
auto[4160749568:4294967295]	auto[1]	54	1			T47	1		T5	1		T243	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1493

1

T1

3

T3

3

T14

1

auto[1]

1648

1

T1

3

T13

1

T14

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T1	2		T18	1		T197	1
auto[134217728:268435455]	98	1			T18	1		T34	1		T4	1
auto[268435456:402653183]	90	1			T46	1		T197	1		T47	3
auto[402653184:536870911]	109	1			T1	1		T46	1		T47	1
auto[536870912:671088639]	112	1			T18	1		T37	1		T50	1
auto[671088640:805306367]	97	1			T38	1		T19	1		T50	1
auto[805306368:939524095]	114	1			T1	1		T14	1		T37	1
auto[939524096:1073741823]	93	1			T38	1		T49	1		T107	1
auto[1073741824:1207959551]	115	1			T3	1		T18	1		T37	2
auto[1207959552:1342177279]	90	1			T1	1		T19	1		T140	2
auto[1342177280:1476395007]	98	1			T37	1		T38	1		T197	1
auto[1476395008:1610612735]	98	1			T197	1		T50	1		T47	1
auto[1610612736:1744830463]	97	1			T127	1		T47	1		T140	1
auto[1744830464:1879048191]	100	1			T18	2		T37	1		T19	1
auto[1879048192:2013265919]	101	1			T3	1		T14	2		T46	1
auto[2013265920:2147483647]	86	1			T46	1		T231	1		T47	2
auto[2147483648:2281701375]	90	1			T19	1		T46	1		T27	1
auto[2281701376:2415919103]	86	1			T1	1		T46	2		T6	2
auto[2415919104:2550136831]	87	1			T3	1		T18	1		T107	1
auto[2550136832:2684354559]	85	1			T18	1		T19	1		T127	1
auto[2684354560:2818572287]	104	1			T38	2		T19	1		T50	3
auto[2818572288:2952790015]	110	1			T38	1		T19	1		T126	1
auto[2952790016:3087007743]	84	1			T37	1		T49	1		T231	1
auto[3087007744:3221225471]	101	1			T18	2		T38	1		T47	1
auto[3221225472:3355443199]	108	1			T37	1		T4	1		T50	1
auto[3355443200:3489660927]	100	1			T14	1		T22	1		T66	1
auto[3489660928:3623878655]	102	1			T19	2		T231	1		T47	2
auto[3623878656:3758096383]	106	1			T127	1		T4	1		T20	1
auto[3758096384:3892314111]	93	1			T13	1		T14	1		T50	1
auto[3892314112:4026531839]	100	1			T18	1		T19	1		T46	2
auto[4026531840:4160749567]	96	1			T34	1		T19	1		T46	1
auto[4160749568:4294967295]	89	1			T18	1		T37	2		T34	1