Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2780

1

T1

6

T3

2

T13

1

auto[1]

311

1

T14

3

T34

5

T127

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T37	1		T34	1		T127	1
auto[134217728:268435455]	104	1			T37	1		T38	1		T34	1
auto[268435456:402653183]	92	1			T18	1		T37	1		T46	1
auto[402653184:536870911]	109	1			T197	1		T107	1		T130	1
auto[536870912:671088639]	90	1			T18	1		T37	1		T50	1
auto[671088640:805306367]	105	1			T18	1		T37	2		T49	1
auto[805306368:939524095]	108	1			T13	1		T19	1		T46	1
auto[939524096:1073741823]	99	1			T37	1		T46	1		T50	1
auto[1073741824:1207959551]	101	1			T18	1		T37	1		T38	1
auto[1207959552:1342177279]	91	1			T19	1		T107	1		T130	1
auto[1342177280:1476395007]	100	1			T34	1		T46	1		T231	1
auto[1476395008:1610612735]	100	1			T1	1		T14	1		T38	2
auto[1610612736:1744830463]	113	1			T1	1		T38	1		T19	2
auto[1744830464:1879048191]	94	1			T34	2		T19	1		T27	2
auto[1879048192:2013265919]	78	1			T18	1		T34	1		T36	1
auto[2013265920:2147483647]	102	1			T18	1		T47	3		T53	1
auto[2147483648:2281701375]	104	1			T1	2		T18	1		T50	1
auto[2281701376:2415919103]	80	1			T3	1		T37	1		T231	1
auto[2415919104:2550136831]	101	1			T14	1		T127	1		T231	1
auto[2550136832:2684354559]	99	1			T46	1		T196	2		T130	3
auto[2684354560:2818572287]	83	1			T1	1		T14	1		T34	1
auto[2818572288:2952790015]	102	1			T14	1		T18	2		T38	1
auto[2952790016:3087007743]	93	1			T14	1		T19	1		T231	1
auto[3087007744:3221225471]	82	1			T14	1		T18	1		T19	1
auto[3221225472:3355443199]	102	1			T60	1		T201	1		T118	1
auto[3355443200:3489660927]	102	1			T47	1		T52	1		T140	1
auto[3489660928:3623878655]	86	1			T18	1		T38	2		T231	1
auto[3623878656:3758096383]	86	1			T1	1		T3	1		T14	1
auto[3758096384:3892314111]	87	1			T14	1		T37	1		T52	1
auto[3892314112:4026531839]	90	1			T50	1		T47	1		T140	1
auto[4026531840:4160749567]	105	1			T126	1		T127	1		T46	1
auto[4160749568:4294967295]	96	1			T127	1		T50	1		T130	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	96	1			T37	1		T34	1		T197	1
auto[0:134217727]	auto[1]	11	1			T127	1		T358	1		T274	1
auto[134217728:268435455]	auto[0]	93	1			T37	1		T38	1		T50	1
auto[134217728:268435455]	auto[1]	11	1			T34	1		T358	1		T415	1
auto[268435456:402653183]	auto[0]	84	1			T18	1		T37	1		T46	1
auto[268435456:402653183]	auto[1]	8	1			T245	1		T415	1		T410	1
auto[402653184:536870911]	auto[0]	98	1			T197	1		T107	1		T6	3
auto[402653184:536870911]	auto[1]	11	1			T130	1		T409	2		T358	1
auto[536870912:671088639]	auto[0]	82	1			T18	1		T37	1		T50	1
auto[536870912:671088639]	auto[1]	8	1			T413	1		T310	1		T424	1
auto[671088640:805306367]	auto[0]	100	1			T18	1		T37	2		T49	1
auto[671088640:805306367]	auto[1]	5	1			T127	1		T245	1		T413	2
auto[805306368:939524095]	auto[0]	97	1			T13	1		T19	1		T46	1
auto[805306368:939524095]	auto[1]	11	1			T109	1		T286	1		T395	1
auto[939524096:1073741823]	auto[0]	89	1			T37	1		T46	1		T50	1
auto[939524096:1073741823]	auto[1]	10	1			T130	2		T132	1		T245	1
auto[1073741824:1207959551]	auto[0]	97	1			T18	1		T37	1		T38	1
auto[1073741824:1207959551]	auto[1]	4	1			T274	1		T411	1		T425	1
auto[1207959552:1342177279]	auto[0]	83	1			T19	1		T107	1		T130	1
auto[1207959552:1342177279]	auto[1]	8	1			T358	1		T228	1		T229	1
auto[1342177280:1476395007]	auto[0]	90	1			T46	1		T231	1		T47	2
auto[1342177280:1476395007]	auto[1]	10	1			T34	1		T358	1		T292	1
auto[1476395008:1610612735]	auto[0]	87	1			T1	1		T38	2		T19	2
auto[1476395008:1610612735]	auto[1]	13	1			T14	1		T130	1		T409	1
auto[1610612736:1744830463]	auto[0]	102	1			T1	1		T38	1		T19	2
auto[1610612736:1744830463]	auto[1]	11	1			T245	1		T239	1		T413	2
auto[1744830464:1879048191]	auto[0]	86	1			T34	1		T19	1		T27	2
auto[1744830464:1879048191]	auto[1]	8	1			T34	1		T409	1		T358	1
auto[1879048192:2013265919]	auto[0]	71	1			T18	1		T36	1		T20	1
auto[1879048192:2013265919]	auto[1]	7	1			T34	1		T334	1		T412	1
auto[2013265920:2147483647]	auto[0]	93	1			T18	1		T47	3		T53	1
auto[2013265920:2147483647]	auto[1]	9	1			T409	1		T379	1		T310	1
auto[2147483648:2281701375]	auto[0]	93	1			T1	2		T18	1		T50	1
auto[2147483648:2281701375]	auto[1]	11	1			T132	1		T411	1		T323	1
auto[2281701376:2415919103]	auto[0]	71	1			T3	1		T37	1		T231	1
auto[2281701376:2415919103]	auto[1]	9	1			T132	1		T358	1		T413	1
auto[2415919104:2550136831]	auto[0]	89	1			T14	1		T127	1		T231	1
auto[2415919104:2550136831]	auto[1]	12	1			T131	1		T132	1		T379	1
auto[2550136832:2684354559]	auto[0]	88	1			T46	1		T196	2		T130	2
auto[2550136832:2684354559]	auto[1]	11	1			T130	1		T109	1		T409	2
auto[2684354560:2818572287]	auto[0]	76	1			T1	1		T14	1		T34	1
auto[2684354560:2818572287]	auto[1]	7	1			T130	1		T358	2		T257	1
auto[2818572288:2952790015]	auto[0]	88	1			T14	1		T18	2		T38	1
auto[2818572288:2952790015]	auto[1]	14	1			T34	1		T131	1		T132	1
auto[2952790016:3087007743]	auto[0]	77	1			T19	1		T231	1		T47	1
auto[2952790016:3087007743]	auto[1]	16	1			T14	1		T130	1		T131	1
auto[3087007744:3221225471]	auto[0]	76	1			T18	1		T19	1		T49	2
auto[3087007744:3221225471]	auto[1]	6	1			T14	1		T130	1		T358	1
auto[3221225472:3355443199]	auto[0]	89	1			T60	1		T201	1		T118	1
auto[3221225472:3355443199]	auto[1]	13	1			T132	1		T379	1		T358	1
auto[3355443200:3489660927]	auto[0]	90	1			T47	1		T52	1		T140	1
auto[3355443200:3489660927]	auto[1]	12	1			T131	1		T228	1		T310	3
auto[3489660928:3623878655]	auto[0]	80	1			T18	1		T38	2		T231	1
auto[3489660928:3623878655]	auto[1]	6	1			T245	1		T413	1		T228	1
auto[3623878656:3758096383]	auto[0]	75	1			T1	1		T3	1		T14	1
auto[3623878656:3758096383]	auto[1]	11	1			T140	1		T131	1		T245	1
auto[3758096384:3892314111]	auto[0]	80	1			T14	1		T37	1		T52	1
auto[3758096384:3892314111]	auto[1]	7	1			T109	1		T239	1		T248	1
auto[3892314112:4026531839]	auto[0]	80	1			T50	1		T47	1		T6	1
auto[3892314112:4026531839]	auto[1]	10	1			T140	1		T286	1		T358	1
auto[4026531840:4160749567]	auto[0]	95	1			T126	1		T46	1		T197	1
auto[4026531840:4160749567]	auto[1]	10	1			T127	1		T130	1		T286	1
auto[4160749568:4294967295]	auto[0]	85	1			T127	1		T50	1		T53	1
auto[4160749568:4294967295]	auto[1]	11	1			T130	1		T131	1		T379	1