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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2781 1 T1 6 T3 2 T13 1
auto[1] 311 1 T14 7 T34 3 T127 4



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 99 1 T1 1 T19 1 T127 1
auto[134217728:268435455] 93 1 T34 1 T107 1 T196 1
auto[268435456:402653183] 102 1 T127 1 T46 1 T47 1
auto[402653184:536870911] 96 1 T3 1 T18 2 T130 2
auto[536870912:671088639] 85 1 T14 1 T18 1 T46 1
auto[671088640:805306367] 86 1 T1 1 T14 1 T52 1
auto[805306368:939524095] 92 1 T18 1 T231 1 T47 1
auto[939524096:1073741823] 86 1 T18 1 T37 1 T127 2
auto[1073741824:1207959551] 82 1 T1 1 T231 1 T47 1
auto[1207959552:1342177279] 93 1 T38 1 T126 1 T231 2
auto[1342177280:1476395007] 103 1 T19 1 T197 1 T140 1
auto[1476395008:1610612735] 102 1 T1 1 T14 1 T18 1
auto[1610612736:1744830463] 92 1 T38 1 T50 1 T47 1
auto[1744830464:1879048191] 96 1 T19 1 T27 2 T47 2
auto[1879048192:2013265919] 105 1 T18 1 T37 1 T38 1
auto[2013265920:2147483647] 87 1 T47 1 T51 1 T140 1
auto[2147483648:2281701375] 77 1 T13 1 T34 1 T6 1
auto[2281701376:2415919103] 115 1 T37 1 T46 1 T197 1
auto[2415919104:2550136831] 88 1 T14 1 T49 1 T46 2
auto[2550136832:2684354559] 116 1 T18 1 T38 1 T197 1
auto[2684354560:2818572287] 110 1 T3 1 T14 1 T49 1
auto[2818572288:2952790015] 103 1 T14 1 T38 1 T19 1
auto[2952790016:3087007743] 89 1 T14 2 T38 1 T19 1
auto[3087007744:3221225471] 91 1 T37 1 T38 1 T46 1
auto[3221225472:3355443199] 92 1 T37 1 T50 1 T47 2
auto[3355443200:3489660927] 108 1 T14 1 T38 1 T19 2
auto[3489660928:3623878655] 115 1 T1 1 T14 1 T18 1
auto[3623878656:3758096383] 83 1 T1 1 T14 1 T50 1
auto[3758096384:3892314111] 88 1 T18 1 T34 1 T19 1
auto[3892314112:4026531839] 107 1 T14 1 T127 1 T46 1
auto[4026531840:4160749567] 104 1 T37 1 T34 1 T50 1
auto[4160749568:4294967295] 107 1 T18 1 T37 1 T34 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 88 1 T1 1 T19 1 T50 2
auto[0:134217727] auto[1] 11 1 T127 1 T140 2 T131 1
auto[134217728:268435455] auto[0] 83 1 T34 1 T107 1 T196 1
auto[134217728:268435455] auto[1] 10 1 T130 1 T245 1 T379 2
auto[268435456:402653183] auto[0] 90 1 T46 1 T47 1 T107 1
auto[268435456:402653183] auto[1] 12 1 T127 1 T132 1 T358 1
auto[402653184:536870911] auto[0] 88 1 T3 1 T18 2 T130 1
auto[402653184:536870911] auto[1] 8 1 T130 1 T274 1 T292 1
auto[536870912:671088639] auto[0] 73 1 T14 1 T18 1 T46 1
auto[536870912:671088639] auto[1] 12 1 T130 1 T132 1 T257 1
auto[671088640:805306367] auto[0] 75 1 T1 1 T52 1 T61 1
auto[671088640:805306367] auto[1] 11 1 T14 1 T358 1 T239 1
auto[805306368:939524095] auto[0] 79 1 T18 1 T231 1 T47 1
auto[805306368:939524095] auto[1] 13 1 T132 1 T232 1 T413 1
auto[939524096:1073741823] auto[0] 76 1 T18 1 T37 1 T127 1
auto[939524096:1073741823] auto[1] 10 1 T127 1 T130 1 T109 1
auto[1073741824:1207959551] auto[0] 78 1 T1 1 T231 1 T47 1
auto[1073741824:1207959551] auto[1] 4 1 T334 1 T427 1 T428 1
auto[1207959552:1342177279] auto[0] 77 1 T38 1 T126 1 T231 2
auto[1207959552:1342177279] auto[1] 16 1 T140 1 T109 1 T131 1
auto[1342177280:1476395007] auto[0] 92 1 T19 1 T197 1 T140 1
auto[1342177280:1476395007] auto[1] 11 1 T130 2 T239 1 T413 1
auto[1476395008:1610612735] auto[0] 97 1 T1 1 T18 1 T37 2
auto[1476395008:1610612735] auto[1] 5 1 T14 1 T337 1 T323 1
auto[1610612736:1744830463] auto[0] 84 1 T38 1 T50 1 T47 1
auto[1610612736:1744830463] auto[1] 8 1 T132 1 T358 1 T232 1
auto[1744830464:1879048191] auto[0] 89 1 T19 1 T27 2 T47 2
auto[1744830464:1879048191] auto[1] 7 1 T109 1 T358 1 T292 1
auto[1879048192:2013265919] auto[0] 92 1 T18 1 T37 1 T38 1
auto[1879048192:2013265919] auto[1] 13 1 T140 1 T274 1 T228 1
auto[2013265920:2147483647] auto[0] 82 1 T47 1 T51 1 T130 1
auto[2013265920:2147483647] auto[1] 5 1 T140 1 T358 1 T413 1
auto[2147483648:2281701375] auto[0] 71 1 T13 1 T34 1 T6 1
auto[2147483648:2281701375] auto[1] 6 1 T109 1 T358 1 T257 1
auto[2281701376:2415919103] auto[0] 108 1 T37 1 T46 1 T197 1
auto[2281701376:2415919103] auto[1] 7 1 T130 2 T228 1 T334 1
auto[2415919104:2550136831] auto[0] 81 1 T49 1 T46 2 T50 1
auto[2415919104:2550136831] auto[1] 7 1 T14 1 T358 1 T232 1
auto[2550136832:2684354559] auto[0] 101 1 T18 1 T38 1 T197 1
auto[2550136832:2684354559] auto[1] 15 1 T130 1 T409 2 T245 1
auto[2684354560:2818572287] auto[0] 98 1 T3 1 T14 1 T49 1
auto[2684354560:2818572287] auto[1] 12 1 T409 1 T358 1 T228 1
auto[2818572288:2952790015] auto[0] 98 1 T38 1 T19 1 T49 1
auto[2818572288:2952790015] auto[1] 5 1 T14 1 T245 1 T379 1
auto[2952790016:3087007743] auto[0] 83 1 T14 2 T38 1 T19 1
auto[2952790016:3087007743] auto[1] 6 1 T127 1 T379 1 T228 1
auto[3087007744:3221225471] auto[0] 86 1 T37 1 T38 1 T46 1
auto[3087007744:3221225471] auto[1] 5 1 T292 1 T334 1 T229 1
auto[3221225472:3355443199] auto[0] 81 1 T37 1 T50 1 T47 2
auto[3221225472:3355443199] auto[1] 11 1 T130 1 T109 1 T228 2
auto[3355443200:3489660927] auto[0] 95 1 T38 1 T19 2 T127 1
auto[3355443200:3489660927] auto[1] 13 1 T14 1 T132 1 T245 1
auto[3489660928:3623878655] auto[0] 102 1 T1 1 T18 1 T37 1
auto[3489660928:3623878655] auto[1] 13 1 T14 1 T34 1 T130 1
auto[3623878656:3758096383] auto[0] 74 1 T1 1 T14 1 T50 1
auto[3623878656:3758096383] auto[1] 9 1 T239 1 T323 1 T424 1
auto[3758096384:3892314111] auto[0] 76 1 T18 1 T19 1 T107 1
auto[3758096384:3892314111] auto[1] 12 1 T34 1 T130 1 T379 1
auto[3892314112:4026531839] auto[0] 94 1 T127 1 T46 1 T47 1
auto[3892314112:4026531839] auto[1] 13 1 T14 1 T358 2 T292 1
auto[4026531840:4160749567] auto[0] 95 1 T37 1 T50 1 T47 2
auto[4026531840:4160749567] auto[1] 9 1 T34 1 T132 1 T239 1
auto[4160749568:4294967295] auto[0] 95 1 T18 1 T37 1 T34 2
auto[4160749568:4294967295] auto[1] 12 1 T130 1 T131 1 T257 1

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