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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.04 98.07 98.58 100.00 99.02 98.41 91.24


Total test records in report: 1082
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T1005 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1810358438 Aug 05 04:28:44 PM PDT 24 Aug 05 04:28:45 PM PDT 24 48361556 ps
T1006 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.514203564 Aug 05 04:28:23 PM PDT 24 Aug 05 04:28:32 PM PDT 24 413215203 ps
T1007 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2503447935 Aug 05 04:28:43 PM PDT 24 Aug 05 04:28:46 PM PDT 24 516473844 ps
T1008 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.628680639 Aug 05 04:28:30 PM PDT 24 Aug 05 04:28:40 PM PDT 24 3812567077 ps
T156 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1999430785 Aug 05 04:28:14 PM PDT 24 Aug 05 04:28:20 PM PDT 24 1100691957 ps
T1009 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2048172499 Aug 05 04:28:34 PM PDT 24 Aug 05 04:28:42 PM PDT 24 683785079 ps
T1010 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3567478383 Aug 05 04:28:40 PM PDT 24 Aug 05 04:28:46 PM PDT 24 165552919 ps
T1011 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1786368105 Aug 05 04:28:15 PM PDT 24 Aug 05 04:28:19 PM PDT 24 139102708 ps
T1012 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4264983612 Aug 05 04:28:52 PM PDT 24 Aug 05 04:28:53 PM PDT 24 32478020 ps
T1013 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2682891304 Aug 05 04:28:35 PM PDT 24 Aug 05 04:28:37 PM PDT 24 12902057 ps
T1014 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3125337132 Aug 05 04:28:11 PM PDT 24 Aug 05 04:28:13 PM PDT 24 72400608 ps
T1015 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3584555563 Aug 05 04:28:49 PM PDT 24 Aug 05 04:28:50 PM PDT 24 36260238 ps
T1016 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.873860729 Aug 05 04:29:05 PM PDT 24 Aug 05 04:29:06 PM PDT 24 13583594 ps
T1017 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.4271246702 Aug 05 04:28:54 PM PDT 24 Aug 05 04:28:55 PM PDT 24 35802952 ps
T1018 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.130605056 Aug 05 04:28:34 PM PDT 24 Aug 05 04:28:35 PM PDT 24 78999224 ps
T1019 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2431543224 Aug 05 04:28:43 PM PDT 24 Aug 05 04:28:51 PM PDT 24 339277974 ps
T1020 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.649619271 Aug 05 04:28:43 PM PDT 24 Aug 05 04:28:44 PM PDT 24 10525084 ps
T1021 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3399259173 Aug 05 04:28:38 PM PDT 24 Aug 05 04:28:38 PM PDT 24 27896326 ps
T1022 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4135369655 Aug 05 04:28:16 PM PDT 24 Aug 05 04:28:25 PM PDT 24 323952652 ps
T1023 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3677850738 Aug 05 04:28:41 PM PDT 24 Aug 05 04:28:42 PM PDT 24 76571021 ps
T1024 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2125264157 Aug 05 04:28:47 PM PDT 24 Aug 05 04:28:48 PM PDT 24 34678846 ps
T1025 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1926520318 Aug 05 04:28:56 PM PDT 24 Aug 05 04:28:57 PM PDT 24 12504491 ps
T1026 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1022939205 Aug 05 04:28:49 PM PDT 24 Aug 05 04:28:49 PM PDT 24 31825919 ps
T1027 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2624842794 Aug 05 04:28:33 PM PDT 24 Aug 05 04:28:35 PM PDT 24 190550219 ps
T1028 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2732286793 Aug 05 04:28:30 PM PDT 24 Aug 05 04:28:32 PM PDT 24 55795749 ps
T1029 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3832045776 Aug 05 04:28:37 PM PDT 24 Aug 05 04:28:41 PM PDT 24 1893396066 ps
T1030 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3562933416 Aug 05 04:28:26 PM PDT 24 Aug 05 04:28:28 PM PDT 24 36909517 ps
T1031 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3040481825 Aug 05 04:28:27 PM PDT 24 Aug 05 04:28:29 PM PDT 24 201826507 ps
T1032 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1178376817 Aug 05 04:28:24 PM PDT 24 Aug 05 04:28:25 PM PDT 24 15442365 ps
T1033 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3735153917 Aug 05 04:28:44 PM PDT 24 Aug 05 04:28:46 PM PDT 24 30746026 ps
T1034 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3796153135 Aug 05 04:28:33 PM PDT 24 Aug 05 04:28:33 PM PDT 24 53978375 ps
T1035 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4204843975 Aug 05 04:28:16 PM PDT 24 Aug 05 04:28:21 PM PDT 24 186269520 ps
T1036 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.782146777 Aug 05 04:28:16 PM PDT 24 Aug 05 04:28:17 PM PDT 24 13777232 ps
T1037 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2198364087 Aug 05 04:28:41 PM PDT 24 Aug 05 04:28:43 PM PDT 24 55113994 ps
T1038 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3149317645 Aug 05 04:28:43 PM PDT 24 Aug 05 04:28:45 PM PDT 24 107092910 ps
T1039 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3978045240 Aug 05 04:28:38 PM PDT 24 Aug 05 04:28:42 PM PDT 24 813088207 ps
T1040 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2878523736 Aug 05 04:28:36 PM PDT 24 Aug 05 04:28:37 PM PDT 24 500569899 ps
T1041 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3140040710 Aug 05 04:28:45 PM PDT 24 Aug 05 04:28:47 PM PDT 24 102404300 ps
T1042 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2878130736 Aug 05 04:28:38 PM PDT 24 Aug 05 04:28:40 PM PDT 24 177333723 ps
T164 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3503497060 Aug 05 04:28:43 PM PDT 24 Aug 05 04:28:46 PM PDT 24 185907992 ps
T172 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1805530842 Aug 05 04:28:28 PM PDT 24 Aug 05 04:28:30 PM PDT 24 69645310 ps
T1043 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.909231455 Aug 05 04:28:57 PM PDT 24 Aug 05 04:28:58 PM PDT 24 41428338 ps
T1044 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2050262553 Aug 05 04:28:18 PM PDT 24 Aug 05 04:28:28 PM PDT 24 740019622 ps
T1045 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3140319960 Aug 05 04:28:35 PM PDT 24 Aug 05 04:28:36 PM PDT 24 69719955 ps
T1046 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3256792348 Aug 05 04:28:40 PM PDT 24 Aug 05 04:28:43 PM PDT 24 385168980 ps
T1047 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1735075773 Aug 05 04:28:42 PM PDT 24 Aug 05 04:28:44 PM PDT 24 50680354 ps
T1048 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3571907451 Aug 05 04:28:18 PM PDT 24 Aug 05 04:28:20 PM PDT 24 316159735 ps
T1049 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3993077714 Aug 05 04:28:39 PM PDT 24 Aug 05 04:28:40 PM PDT 24 68689025 ps
T1050 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2677383719 Aug 05 04:28:22 PM PDT 24 Aug 05 04:28:24 PM PDT 24 86025854 ps
T1051 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.223648442 Aug 05 04:28:48 PM PDT 24 Aug 05 04:28:50 PM PDT 24 37006636 ps
T1052 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1614325924 Aug 05 04:28:18 PM PDT 24 Aug 05 04:28:19 PM PDT 24 18326731 ps
T1053 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1407889272 Aug 05 04:28:13 PM PDT 24 Aug 05 04:28:14 PM PDT 24 20745665 ps
T1054 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4292133061 Aug 05 04:28:30 PM PDT 24 Aug 05 04:28:32 PM PDT 24 18126434 ps
T1055 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3120393238 Aug 05 04:28:48 PM PDT 24 Aug 05 04:28:54 PM PDT 24 202892409 ps
T1056 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3817984518 Aug 05 04:28:43 PM PDT 24 Aug 05 04:28:45 PM PDT 24 239240641 ps
T1057 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1674485679 Aug 05 04:28:49 PM PDT 24 Aug 05 04:28:50 PM PDT 24 51682037 ps
T1058 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.641864856 Aug 05 04:28:51 PM PDT 24 Aug 05 04:28:52 PM PDT 24 40789317 ps
T1059 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1080138890 Aug 05 04:28:37 PM PDT 24 Aug 05 04:28:42 PM PDT 24 152691985 ps
T1060 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2779005525 Aug 05 04:28:34 PM PDT 24 Aug 05 04:28:38 PM PDT 24 436099661 ps
T1061 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1439792615 Aug 05 04:28:49 PM PDT 24 Aug 05 04:28:50 PM PDT 24 52865290 ps
T1062 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.332098453 Aug 05 04:28:42 PM PDT 24 Aug 05 04:28:46 PM PDT 24 343877353 ps
T1063 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2065032150 Aug 05 04:28:37 PM PDT 24 Aug 05 04:28:38 PM PDT 24 9233196 ps
T1064 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.183382076 Aug 05 04:28:21 PM PDT 24 Aug 05 04:28:23 PM PDT 24 540994521 ps
T1065 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2944664981 Aug 05 04:28:42 PM PDT 24 Aug 05 04:28:43 PM PDT 24 22092563 ps
T1066 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3602388129 Aug 05 04:28:20 PM PDT 24 Aug 05 04:28:21 PM PDT 24 113466037 ps
T1067 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1355049227 Aug 05 04:28:54 PM PDT 24 Aug 05 04:28:55 PM PDT 24 8979119 ps
T1068 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2765811916 Aug 05 04:28:42 PM PDT 24 Aug 05 04:28:46 PM PDT 24 267964661 ps
T1069 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3601057265 Aug 05 04:28:30 PM PDT 24 Aug 05 04:28:31 PM PDT 24 11057534 ps
T162 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.52481483 Aug 05 04:28:21 PM PDT 24 Aug 05 04:28:27 PM PDT 24 397762846 ps
T1070 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4139790462 Aug 05 04:28:10 PM PDT 24 Aug 05 04:28:11 PM PDT 24 11772663 ps
T1071 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3288838671 Aug 05 04:28:49 PM PDT 24 Aug 05 04:28:51 PM PDT 24 13238129 ps
T1072 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.583884369 Aug 05 04:28:35 PM PDT 24 Aug 05 04:28:36 PM PDT 24 13384781 ps
T1073 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.307617935 Aug 05 04:28:19 PM PDT 24 Aug 05 04:28:21 PM PDT 24 280738667 ps
T1074 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1821404120 Aug 05 04:28:50 PM PDT 24 Aug 05 04:28:52 PM PDT 24 81482428 ps
T1075 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.305056212 Aug 05 04:28:23 PM PDT 24 Aug 05 04:28:25 PM PDT 24 127193038 ps
T1076 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.4166918353 Aug 05 04:28:22 PM PDT 24 Aug 05 04:28:27 PM PDT 24 117538693 ps
T1077 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2072790336 Aug 05 04:28:20 PM PDT 24 Aug 05 04:28:30 PM PDT 24 1654877339 ps
T1078 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2190742580 Aug 05 04:28:21 PM PDT 24 Aug 05 04:28:22 PM PDT 24 7588781 ps
T1079 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.633841258 Aug 05 04:28:14 PM PDT 24 Aug 05 04:28:23 PM PDT 24 733337815 ps
T1080 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3125222886 Aug 05 04:28:37 PM PDT 24 Aug 05 04:28:41 PM PDT 24 398099124 ps
T1081 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.128331358 Aug 05 04:28:39 PM PDT 24 Aug 05 04:28:41 PM PDT 24 18381193 ps
T1082 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.805639514 Aug 05 04:28:13 PM PDT 24 Aug 05 04:28:15 PM PDT 24 45151200 ps

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.487428107
Short name T18
Test name
Test status
Simulation time 1992801217 ps
CPU time 23.25 seconds
Started Aug 05 04:34:09 PM PDT 24
Finished Aug 05 04:34:33 PM PDT 24
Peak memory 222360 kb
Host smart-d120e398-3fb4-43d7-9a1d-90a8180c4c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487428107 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.487428107
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1485796033
Short name T61
Test name
Test status
Simulation time 13902281134 ps
CPU time 44.34 seconds
Started Aug 05 04:34:40 PM PDT 24
Finished Aug 05 04:35:24 PM PDT 24
Peak memory 214708 kb
Host smart-dd4dd3a4-bc98-44f6-a228-5da1f98b1318
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485796033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1485796033
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.465096892
Short name T6
Test name
Test status
Simulation time 4118937870 ps
CPU time 59.04 seconds
Started Aug 05 04:33:11 PM PDT 24
Finished Aug 05 04:34:10 PM PDT 24
Peak memory 217216 kb
Host smart-fa089eb4-81ab-480b-a1ed-d9afe496c2db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465096892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.465096892
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3047876478
Short name T9
Test name
Test status
Simulation time 4246103588 ps
CPU time 10.58 seconds
Started Aug 05 04:32:49 PM PDT 24
Finished Aug 05 04:32:59 PM PDT 24
Peak memory 229424 kb
Host smart-f4f4f1bf-b79f-452f-b1b4-eb8617453a80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047876478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3047876478
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.4151942130
Short name T72
Test name
Test status
Simulation time 193966141 ps
CPU time 7.83 seconds
Started Aug 05 04:34:28 PM PDT 24
Finished Aug 05 04:34:36 PM PDT 24
Peak memory 222364 kb
Host smart-f45b1262-28c4-49f1-ab29-5a9e0c4ddb10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151942130 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.4151942130
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3646141121
Short name T47
Test name
Test status
Simulation time 6464281682 ps
CPU time 104.39 seconds
Started Aug 05 04:33:26 PM PDT 24
Finished Aug 05 04:35:11 PM PDT 24
Peak memory 216240 kb
Host smart-9e3e2229-3b6e-4081-a50d-c6f6fef8b55c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646141121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3646141121
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3939666712
Short name T37
Test name
Test status
Simulation time 114510760 ps
CPU time 4.34 seconds
Started Aug 05 04:33:34 PM PDT 24
Finished Aug 05 04:33:39 PM PDT 24
Peak memory 214272 kb
Host smart-f937bacd-9e90-4085-9924-3fddd4ffa75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939666712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3939666712
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3423604308
Short name T56
Test name
Test status
Simulation time 841962583 ps
CPU time 14.27 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:33:09 PM PDT 24
Peak memory 222380 kb
Host smart-2b441edd-0c42-48db-a7a8-c53b3ddd9f5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423604308 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3423604308
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.69229797
Short name T358
Test name
Test status
Simulation time 5426945949 ps
CPU time 135.83 seconds
Started Aug 05 04:33:16 PM PDT 24
Finished Aug 05 04:35:32 PM PDT 24
Peak memory 215608 kb
Host smart-9e80a2c1-67a5-432b-8ec8-0e792f09f848
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=69229797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.69229797
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3405386791
Short name T7
Test name
Test status
Simulation time 128612116 ps
CPU time 5.39 seconds
Started Aug 05 04:33:13 PM PDT 24
Finished Aug 05 04:33:19 PM PDT 24
Peak memory 210636 kb
Host smart-80811238-07e6-441e-92c0-f0378519ee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405386791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3405386791
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.4069478870
Short name T115
Test name
Test status
Simulation time 589825216 ps
CPU time 7.08 seconds
Started Aug 05 04:28:25 PM PDT 24
Finished Aug 05 04:28:32 PM PDT 24
Peak memory 214492 kb
Host smart-8a535e42-61ca-4291-952f-0ad34b71e0c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069478870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.4069478870
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3219019791
Short name T130
Test name
Test status
Simulation time 1142868692 ps
CPU time 62.75 seconds
Started Aug 05 04:34:19 PM PDT 24
Finished Aug 05 04:35:22 PM PDT 24
Peak memory 222264 kb
Host smart-7f367ba8-9966-4737-a03e-5fb35ad6acdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3219019791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3219019791
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2609180674
Short name T323
Test name
Test status
Simulation time 169991165 ps
CPU time 9.25 seconds
Started Aug 05 04:33:20 PM PDT 24
Finished Aug 05 04:33:30 PM PDT 24
Peak memory 215452 kb
Host smart-2e0a676b-950e-4872-89ad-a25373559102
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609180674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2609180674
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1331401191
Short name T46
Test name
Test status
Simulation time 365663518 ps
CPU time 14.77 seconds
Started Aug 05 04:32:40 PM PDT 24
Finished Aug 05 04:32:55 PM PDT 24
Peak memory 222320 kb
Host smart-d05f7a72-12a0-4917-b15b-e8e7295b297c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331401191 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1331401191
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3364326608
Short name T36
Test name
Test status
Simulation time 74021362 ps
CPU time 3.74 seconds
Started Aug 05 04:32:56 PM PDT 24
Finished Aug 05 04:33:00 PM PDT 24
Peak memory 218432 kb
Host smart-f8dd3d49-54d1-4f38-b047-0b4fed4136ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364326608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3364326608
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1810922653
Short name T93
Test name
Test status
Simulation time 11588555006 ps
CPU time 75.2 seconds
Started Aug 05 04:32:48 PM PDT 24
Finished Aug 05 04:34:03 PM PDT 24
Peak memory 214212 kb
Host smart-f464c82b-c534-4295-a51f-b9f338cd138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810922653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1810922653
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1734960405
Short name T425
Test name
Test status
Simulation time 409498957 ps
CPU time 21.3 seconds
Started Aug 05 04:34:20 PM PDT 24
Finished Aug 05 04:34:41 PM PDT 24
Peak memory 214864 kb
Host smart-429eba11-d2c2-4564-a93d-1433dd51ffca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734960405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1734960405
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.162900093
Short name T64
Test name
Test status
Simulation time 942730822 ps
CPU time 37.23 seconds
Started Aug 05 04:33:48 PM PDT 24
Finished Aug 05 04:34:25 PM PDT 24
Peak memory 222448 kb
Host smart-f2d751c1-8bec-4c8e-80e8-c29b064a892a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162900093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.162900093
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2368399623
Short name T22
Test name
Test status
Simulation time 134576753 ps
CPU time 5.47 seconds
Started Aug 05 04:33:03 PM PDT 24
Finished Aug 05 04:33:08 PM PDT 24
Peak memory 215880 kb
Host smart-cc84b996-7a11-4097-9488-4a61b766ae54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368399623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2368399623
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.671477317
Short name T116
Test name
Test status
Simulation time 478440490 ps
CPU time 2.21 seconds
Started Aug 05 04:28:25 PM PDT 24
Finished Aug 05 04:28:33 PM PDT 24
Peak memory 214412 kb
Host smart-553322a2-ef10-4ddf-acfc-c6d0d568a155
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671477317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.671477317
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.802853140
Short name T85
Test name
Test status
Simulation time 152485954 ps
CPU time 3.01 seconds
Started Aug 05 04:32:48 PM PDT 24
Finished Aug 05 04:32:51 PM PDT 24
Peak memory 222212 kb
Host smart-a36f1dd8-b3ed-49a0-ad07-bb24de7987df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802853140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.802853140
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3496941815
Short name T132
Test name
Test status
Simulation time 326366139 ps
CPU time 9.27 seconds
Started Aug 05 04:34:08 PM PDT 24
Finished Aug 05 04:34:17 PM PDT 24
Peak memory 215548 kb
Host smart-3178deef-ba47-4bd3-8933-b70fc090b8cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3496941815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3496941815
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3731600136
Short name T379
Test name
Test status
Simulation time 4604123670 ps
CPU time 16.45 seconds
Started Aug 05 04:33:58 PM PDT 24
Finished Aug 05 04:34:25 PM PDT 24
Peak memory 214264 kb
Host smart-55f2f004-3f25-4ec6-8a17-01d6c68dceee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731600136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3731600136
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.4254404837
Short name T70
Test name
Test status
Simulation time 17582686173 ps
CPU time 91.95 seconds
Started Aug 05 04:34:14 PM PDT 24
Finished Aug 05 04:35:46 PM PDT 24
Peak memory 216080 kb
Host smart-1986b3ce-ce16-4dc5-befa-c73cf7ff5c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254404837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.4254404837
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2270061139
Short name T23
Test name
Test status
Simulation time 965137579 ps
CPU time 6.97 seconds
Started Aug 05 04:34:15 PM PDT 24
Finished Aug 05 04:34:22 PM PDT 24
Peak memory 208936 kb
Host smart-0267e2e4-47a6-4ece-afd5-6830acd6e478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270061139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2270061139
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1471380003
Short name T54
Test name
Test status
Simulation time 624507362 ps
CPU time 20.35 seconds
Started Aug 05 04:33:45 PM PDT 24
Finished Aug 05 04:34:05 PM PDT 24
Peak memory 222480 kb
Host smart-5d1b20e6-7f12-4fc7-8d66-7458ae614c36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471380003 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1471380003
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2544686321
Short name T229
Test name
Test status
Simulation time 557026510 ps
CPU time 9.75 seconds
Started Aug 05 04:33:11 PM PDT 24
Finished Aug 05 04:33:21 PM PDT 24
Peak memory 214112 kb
Host smart-d2ff50b9-0941-46a8-8566-a40fae4a191c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544686321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2544686321
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3417131933
Short name T147
Test name
Test status
Simulation time 169504231 ps
CPU time 3.32 seconds
Started Aug 05 04:32:45 PM PDT 24
Finished Aug 05 04:32:48 PM PDT 24
Peak memory 222428 kb
Host smart-d7b09af7-a507-4cdd-aff5-ce4f3f7d7aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417131933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3417131933
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.112424953
Short name T486
Test name
Test status
Simulation time 68722006 ps
CPU time 3.23 seconds
Started Aug 05 04:34:06 PM PDT 24
Finished Aug 05 04:34:10 PM PDT 24
Peak memory 222276 kb
Host smart-05c59aa2-d7d5-4696-83e1-5afa1a4842f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112424953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.112424953
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2616973064
Short name T409
Test name
Test status
Simulation time 651207737 ps
CPU time 8.4 seconds
Started Aug 05 04:33:48 PM PDT 24
Finished Aug 05 04:33:57 PM PDT 24
Peak memory 214784 kb
Host smart-042f918c-3291-4bc0-85f9-8a6dd1725e7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2616973064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2616973064
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3024274694
Short name T58
Test name
Test status
Simulation time 187007717 ps
CPU time 2.23 seconds
Started Aug 05 04:33:45 PM PDT 24
Finished Aug 05 04:33:47 PM PDT 24
Peak memory 210008 kb
Host smart-a1a92588-1dbf-40b1-8d1a-70e28acfa2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024274694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3024274694
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1061702155
Short name T19
Test name
Test status
Simulation time 576158066 ps
CPU time 9.28 seconds
Started Aug 05 04:34:52 PM PDT 24
Finished Aug 05 04:35:01 PM PDT 24
Peak memory 215136 kb
Host smart-8c0ce305-e20b-458a-bb68-f2e98c2d9737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061702155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1061702155
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3782524649
Short name T437
Test name
Test status
Simulation time 41333028 ps
CPU time 0.74 seconds
Started Aug 05 04:33:29 PM PDT 24
Finished Aug 05 04:33:30 PM PDT 24
Peak memory 205820 kb
Host smart-f6b97039-c920-44a0-81ff-b0386750a5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782524649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3782524649
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1999430785
Short name T156
Test name
Test status
Simulation time 1100691957 ps
CPU time 5.95 seconds
Started Aug 05 04:28:14 PM PDT 24
Finished Aug 05 04:28:20 PM PDT 24
Peak memory 214260 kb
Host smart-595b5d3a-c8a0-42f9-9ff6-be3534ba786d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999430785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1999430785
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2242090968
Short name T378
Test name
Test status
Simulation time 332446518 ps
CPU time 9.47 seconds
Started Aug 05 04:33:54 PM PDT 24
Finished Aug 05 04:34:04 PM PDT 24
Peak memory 215512 kb
Host smart-a7456575-2df0-48a0-8df6-818920a03179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2242090968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2242090968
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.879576643
Short name T325
Test name
Test status
Simulation time 1168307839 ps
CPU time 42.06 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:43 PM PDT 24
Peak memory 222352 kb
Host smart-789909ab-ea39-4837-99ed-b6c6fa140d96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879576643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.879576643
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3271540740
Short name T161
Test name
Test status
Simulation time 1420262960 ps
CPU time 10.11 seconds
Started Aug 05 04:28:19 PM PDT 24
Finished Aug 05 04:28:29 PM PDT 24
Peak memory 214184 kb
Host smart-504ead6f-48bd-44d5-b55e-cf5f0e9194d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271540740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3271540740
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2355249596
Short name T246
Test name
Test status
Simulation time 35450487 ps
CPU time 2.56 seconds
Started Aug 05 04:34:01 PM PDT 24
Finished Aug 05 04:34:03 PM PDT 24
Peak memory 220236 kb
Host smart-a228a8f1-20a7-49e0-b849-8876960f5353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355249596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2355249596
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1961683445
Short name T211
Test name
Test status
Simulation time 4258083313 ps
CPU time 42.76 seconds
Started Aug 05 04:34:20 PM PDT 24
Finished Aug 05 04:35:13 PM PDT 24
Peak memory 215340 kb
Host smart-87761b32-40f5-4776-8856-36a2ee6114b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961683445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1961683445
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3780316114
Short name T74
Test name
Test status
Simulation time 11619620785 ps
CPU time 45.87 seconds
Started Aug 05 04:34:37 PM PDT 24
Finished Aug 05 04:35:23 PM PDT 24
Peak memory 222412 kb
Host smart-2e68f06f-31b7-4b59-b4d5-2e09b62c6b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780316114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3780316114
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1192295073
Short name T236
Test name
Test status
Simulation time 42430683210 ps
CPU time 491.83 seconds
Started Aug 05 04:33:36 PM PDT 24
Finished Aug 05 04:41:48 PM PDT 24
Peak memory 222488 kb
Host smart-cb1f9fc6-e681-48ac-a7e4-d35707a448cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192295073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1192295073
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1482538125
Short name T91
Test name
Test status
Simulation time 101549542 ps
CPU time 3.22 seconds
Started Aug 05 04:34:12 PM PDT 24
Finished Aug 05 04:34:15 PM PDT 24
Peak memory 222332 kb
Host smart-69b95add-aebb-455d-a32b-6ee9911c0a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482538125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1482538125
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2660861941
Short name T26
Test name
Test status
Simulation time 150082282 ps
CPU time 7.1 seconds
Started Aug 05 04:33:18 PM PDT 24
Finished Aug 05 04:33:25 PM PDT 24
Peak memory 214384 kb
Host smart-9032ba59-0cef-4ee5-8fe4-22abef3b22a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660861941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2660861941
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2528798671
Short name T104
Test name
Test status
Simulation time 240453176 ps
CPU time 3.27 seconds
Started Aug 05 04:33:20 PM PDT 24
Finished Aug 05 04:33:25 PM PDT 24
Peak memory 213588 kb
Host smart-f58ad8e3-db5d-408d-8c50-935b5ba4f3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528798671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2528798671
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1172496518
Short name T146
Test name
Test status
Simulation time 333248075 ps
CPU time 3.32 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 218376 kb
Host smart-13df663f-6601-4147-b3f5-ee25a049361e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172496518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1172496518
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.978330343
Short name T303
Test name
Test status
Simulation time 111650135 ps
CPU time 2.32 seconds
Started Aug 05 04:33:16 PM PDT 24
Finished Aug 05 04:33:19 PM PDT 24
Peak memory 213580 kb
Host smart-53c756af-f5f2-48a0-a318-fcc39a3eed1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978330343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.978330343
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1773432489
Short name T251
Test name
Test status
Simulation time 47970258563 ps
CPU time 484.11 seconds
Started Aug 05 04:33:09 PM PDT 24
Finished Aug 05 04:41:14 PM PDT 24
Peak memory 216720 kb
Host smart-a093dfa7-b34a-41c6-9102-03fb1f808819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773432489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1773432489
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2313621820
Short name T369
Test name
Test status
Simulation time 4952229486 ps
CPU time 36.62 seconds
Started Aug 05 04:34:27 PM PDT 24
Finished Aug 05 04:35:04 PM PDT 24
Peak memory 222420 kb
Host smart-88eab1e0-267b-4fd8-8597-b0410d4f6cbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313621820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2313621820
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3004105994
Short name T387
Test name
Test status
Simulation time 222843874 ps
CPU time 4.89 seconds
Started Aug 05 04:33:17 PM PDT 24
Finished Aug 05 04:33:22 PM PDT 24
Peak memory 220308 kb
Host smart-30cdaa4a-b7a7-4b47-be26-569eda07ebd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004105994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3004105994
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3854577497
Short name T140
Test name
Test status
Simulation time 229037170 ps
CPU time 4.24 seconds
Started Aug 05 04:33:52 PM PDT 24
Finished Aug 05 04:33:57 PM PDT 24
Peak memory 215744 kb
Host smart-4c66ba7d-45f1-42fd-86e8-3afef1c8fe08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854577497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3854577497
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3099093965
Short name T128
Test name
Test status
Simulation time 1080173265 ps
CPU time 2.3 seconds
Started Aug 05 04:34:25 PM PDT 24
Finished Aug 05 04:34:27 PM PDT 24
Peak memory 209732 kb
Host smart-447123df-73e2-4f01-a477-86f64c708825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099093965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3099093965
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2093923000
Short name T192
Test name
Test status
Simulation time 118321390890 ps
CPU time 224.23 seconds
Started Aug 05 04:34:26 PM PDT 24
Finished Aug 05 04:38:10 PM PDT 24
Peak memory 216420 kb
Host smart-f096434a-2edf-4f72-ad0f-69409905b047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093923000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2093923000
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3971242546
Short name T203
Test name
Test status
Simulation time 278585550 ps
CPU time 3.4 seconds
Started Aug 05 04:32:58 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 208700 kb
Host smart-b3f98646-6e19-4f19-8982-2f90d3a178be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971242546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3971242546
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1251107181
Short name T245
Test name
Test status
Simulation time 141957938 ps
CPU time 7.76 seconds
Started Aug 05 04:34:28 PM PDT 24
Finished Aug 05 04:34:35 PM PDT 24
Peak memory 214204 kb
Host smart-24ff2d55-66ef-4b33-a526-054dfcaa4276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1251107181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1251107181
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4100344798
Short name T160
Test name
Test status
Simulation time 444161139 ps
CPU time 5.94 seconds
Started Aug 05 04:28:30 PM PDT 24
Finished Aug 05 04:28:37 PM PDT 24
Peak memory 205988 kb
Host smart-89aa58c0-b364-498f-8851-332d836826d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100344798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4100344798
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3317021184
Short name T170
Test name
Test status
Simulation time 206868091 ps
CPU time 3.74 seconds
Started Aug 05 04:28:29 PM PDT 24
Finished Aug 05 04:28:38 PM PDT 24
Peak memory 206020 kb
Host smart-2492c715-d8bd-47b1-a80e-18caf31c2f62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317021184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3317021184
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1853934058
Short name T165
Test name
Test status
Simulation time 228912666 ps
CPU time 3.44 seconds
Started Aug 05 04:28:36 PM PDT 24
Finished Aug 05 04:28:40 PM PDT 24
Peak memory 214168 kb
Host smart-0c355a6e-fcc4-408f-8259-98f8d7e1c4d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853934058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1853934058
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2986786811
Short name T150
Test name
Test status
Simulation time 331775562 ps
CPU time 4.34 seconds
Started Aug 05 04:34:09 PM PDT 24
Finished Aug 05 04:34:13 PM PDT 24
Peak memory 222424 kb
Host smart-2e75c136-b9ab-4121-8d6a-b24dd6fac45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986786811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2986786811
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2908874558
Short name T148
Test name
Test status
Simulation time 103817631 ps
CPU time 1.91 seconds
Started Aug 05 04:34:25 PM PDT 24
Finished Aug 05 04:34:27 PM PDT 24
Peak memory 216604 kb
Host smart-da34e0f4-61e3-47b3-8a41-f778b302cd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908874558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2908874558
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3588932470
Short name T143
Test name
Test status
Simulation time 335074114 ps
CPU time 5.01 seconds
Started Aug 05 04:33:28 PM PDT 24
Finished Aug 05 04:33:33 PM PDT 24
Peak memory 218076 kb
Host smart-8ebbcd0f-948d-413b-91d9-bc7adde003cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588932470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3588932470
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2985958579
Short name T194
Test name
Test status
Simulation time 43978020 ps
CPU time 2.34 seconds
Started Aug 05 04:33:55 PM PDT 24
Finished Aug 05 04:33:58 PM PDT 24
Peak memory 207984 kb
Host smart-8c1bc9c6-79a7-4907-aaea-ba642e7bc2be
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985958579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2985958579
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4120131224
Short name T86
Test name
Test status
Simulation time 138098418 ps
CPU time 3.36 seconds
Started Aug 05 04:34:35 PM PDT 24
Finished Aug 05 04:34:39 PM PDT 24
Peak memory 214172 kb
Host smart-bc61d476-7a85-4483-af0a-d761404eec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120131224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4120131224
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.992034132
Short name T227
Test name
Test status
Simulation time 92460987 ps
CPU time 3.19 seconds
Started Aug 05 04:32:52 PM PDT 24
Finished Aug 05 04:32:55 PM PDT 24
Peak memory 210432 kb
Host smart-821af32a-07ae-45ab-a403-5cad5e0a1659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992034132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.992034132
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1470485931
Short name T169
Test name
Test status
Simulation time 162725817 ps
CPU time 4 seconds
Started Aug 05 04:28:54 PM PDT 24
Finished Aug 05 04:28:58 PM PDT 24
Peak memory 214180 kb
Host smart-42530d94-0e10-47cc-a406-6aa15af4be81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470485931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1470485931
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1444314617
Short name T142
Test name
Test status
Simulation time 79705320 ps
CPU time 2.69 seconds
Started Aug 05 04:34:00 PM PDT 24
Finished Aug 05 04:34:03 PM PDT 24
Peak memory 217528 kb
Host smart-70fe01db-54fe-4d39-86fd-f2d0de8a26e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444314617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1444314617
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3371968490
Short name T144
Test name
Test status
Simulation time 300098272 ps
CPU time 3.11 seconds
Started Aug 05 04:33:03 PM PDT 24
Finished Aug 05 04:33:06 PM PDT 24
Peak memory 222484 kb
Host smart-bc79f036-a7d9-4c6e-bddb-e29e2d26a9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371968490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3371968490
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.4292008929
Short name T51
Test name
Test status
Simulation time 139749835 ps
CPU time 3.94 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 222448 kb
Host smart-70885c4e-fc98-4195-b3c8-b53813a8fb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292008929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.4292008929
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.764568966
Short name T210
Test name
Test status
Simulation time 370674752 ps
CPU time 8.64 seconds
Started Aug 05 04:32:42 PM PDT 24
Finished Aug 05 04:32:50 PM PDT 24
Peak memory 214180 kb
Host smart-7905451e-72f8-46d9-9d36-59732e87cdb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764568966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.764568966
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1060456132
Short name T428
Test name
Test status
Simulation time 265633570 ps
CPU time 4.42 seconds
Started Aug 05 04:32:54 PM PDT 24
Finished Aug 05 04:32:58 PM PDT 24
Peak memory 214276 kb
Host smart-2f9a79d8-dbc6-46b8-b99a-e745c3cd267a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1060456132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1060456132
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1214564384
Short name T848
Test name
Test status
Simulation time 258466316 ps
CPU time 7.11 seconds
Started Aug 05 04:33:02 PM PDT 24
Finished Aug 05 04:33:09 PM PDT 24
Peak memory 222344 kb
Host smart-f2ebbeb9-52c1-43e1-966e-c7933af2d233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214564384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1214564384
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1971898680
Short name T60
Test name
Test status
Simulation time 42946753 ps
CPU time 3.03 seconds
Started Aug 05 04:33:00 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 210108 kb
Host smart-8ac84b62-fe9b-4630-b9db-b11f194f0b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971898680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1971898680
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.4003829934
Short name T263
Test name
Test status
Simulation time 256695978 ps
CPU time 2.52 seconds
Started Aug 05 04:33:23 PM PDT 24
Finished Aug 05 04:33:25 PM PDT 24
Peak memory 221228 kb
Host smart-028c2e1c-d9d9-43bb-85aa-932da980de4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003829934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.4003829934
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3768479706
Short name T75
Test name
Test status
Simulation time 4115131309 ps
CPU time 40.36 seconds
Started Aug 05 04:33:29 PM PDT 24
Finished Aug 05 04:34:09 PM PDT 24
Peak memory 222416 kb
Host smart-2fe8f4c1-066b-4a8f-aa1e-7335500d6616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768479706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3768479706
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1326806931
Short name T340
Test name
Test status
Simulation time 237269182 ps
CPU time 5.99 seconds
Started Aug 05 04:33:37 PM PDT 24
Finished Aug 05 04:33:43 PM PDT 24
Peak memory 222308 kb
Host smart-4f4227dc-cf91-491c-b0a5-b2cb7322adf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326806931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1326806931
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2025333232
Short name T524
Test name
Test status
Simulation time 278934103 ps
CPU time 2.88 seconds
Started Aug 05 04:33:30 PM PDT 24
Finished Aug 05 04:33:33 PM PDT 24
Peak memory 207208 kb
Host smart-42c1abe3-8b61-4edd-b6b4-03d2fbd55827
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025333232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2025333232
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2109179798
Short name T88
Test name
Test status
Simulation time 109931903 ps
CPU time 2.26 seconds
Started Aug 05 04:33:49 PM PDT 24
Finished Aug 05 04:33:51 PM PDT 24
Peak memory 214552 kb
Host smart-d1b2b3d1-f074-4dfe-9495-6594ceeb17ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109179798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2109179798
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1209776863
Short name T224
Test name
Test status
Simulation time 3898241640 ps
CPU time 40.63 seconds
Started Aug 05 04:33:55 PM PDT 24
Finished Aug 05 04:34:36 PM PDT 24
Peak memory 216256 kb
Host smart-7959268a-1e24-4a42-9984-fbd2ad03ab0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209776863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1209776863
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.4270971080
Short name T319
Test name
Test status
Simulation time 192061795 ps
CPU time 4.43 seconds
Started Aug 05 04:32:54 PM PDT 24
Finished Aug 05 04:32:58 PM PDT 24
Peak memory 222248 kb
Host smart-f94db063-86b8-435c-8439-87fd8e66f3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270971080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.4270971080
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2545615986
Short name T153
Test name
Test status
Simulation time 522174934 ps
CPU time 10.89 seconds
Started Aug 05 04:28:20 PM PDT 24
Finished Aug 05 04:28:31 PM PDT 24
Peak memory 214200 kb
Host smart-f927b3f5-a1d7-4321-a36d-f609d4baa405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545615986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2545615986
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.494567266
Short name T175
Test name
Test status
Simulation time 308190370 ps
CPU time 3.12 seconds
Started Aug 05 04:28:18 PM PDT 24
Finished Aug 05 04:28:21 PM PDT 24
Peak memory 213324 kb
Host smart-2f8ad6d4-d443-49bd-80ab-4946a4fbfbea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494567266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
494567266
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.188515039
Short name T10
Test name
Test status
Simulation time 574217097 ps
CPU time 6.82 seconds
Started Aug 05 04:33:26 PM PDT 24
Finished Aug 05 04:33:33 PM PDT 24
Peak memory 237044 kb
Host smart-fb25540e-e905-49a2-8d5c-f4f1bba2452a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188515039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.188515039
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3799369326
Short name T96
Test name
Test status
Simulation time 394575567 ps
CPU time 4.56 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:05 PM PDT 24
Peak memory 209044 kb
Host smart-a9962e2c-2de6-416a-bef8-6b5e598add5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799369326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3799369326
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1354045913
Short name T63
Test name
Test status
Simulation time 156727472 ps
CPU time 2.07 seconds
Started Aug 05 04:34:08 PM PDT 24
Finished Aug 05 04:34:15 PM PDT 24
Peak memory 210144 kb
Host smart-1d233b61-fbd4-4f12-a06c-e32121254130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354045913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1354045913
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3844862574
Short name T173
Test name
Test status
Simulation time 54998668 ps
CPU time 1.87 seconds
Started Aug 05 04:32:58 PM PDT 24
Finished Aug 05 04:33:00 PM PDT 24
Peak memory 209904 kb
Host smart-bf41fb92-d2ff-4045-b983-45acce8fb101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844862574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3844862574
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2315980211
Short name T145
Test name
Test status
Simulation time 164119604 ps
CPU time 2.58 seconds
Started Aug 05 04:34:11 PM PDT 24
Finished Aug 05 04:34:13 PM PDT 24
Peak memory 217692 kb
Host smart-089e2a1e-a28b-4c5c-a09c-cf5b42ae5950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315980211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2315980211
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2041933467
Short name T149
Test name
Test status
Simulation time 86626152 ps
CPU time 2.03 seconds
Started Aug 05 04:33:03 PM PDT 24
Finished Aug 05 04:33:10 PM PDT 24
Peak memory 217872 kb
Host smart-e84fe5a2-8e88-42f7-804d-b33913b513b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041933467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2041933467
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.788058859
Short name T429
Test name
Test status
Simulation time 175495944 ps
CPU time 9.95 seconds
Started Aug 05 04:32:34 PM PDT 24
Finished Aug 05 04:32:44 PM PDT 24
Peak memory 214828 kb
Host smart-ec9e0704-cef0-4091-a4b4-0b517bf14057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=788058859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.788058859
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.119511025
Short name T347
Test name
Test status
Simulation time 38101405 ps
CPU time 2.88 seconds
Started Aug 05 04:32:34 PM PDT 24
Finished Aug 05 04:32:37 PM PDT 24
Peak memory 214236 kb
Host smart-59589626-2c6b-41dc-af77-0deaf6292906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119511025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.119511025
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2363629600
Short name T320
Test name
Test status
Simulation time 381977305 ps
CPU time 3.53 seconds
Started Aug 05 04:32:46 PM PDT 24
Finished Aug 05 04:32:50 PM PDT 24
Peak memory 214192 kb
Host smart-dab6205e-6dcd-4994-b28f-507bd49f9b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363629600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2363629600
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.4280368047
Short name T269
Test name
Test status
Simulation time 213571021 ps
CPU time 6.42 seconds
Started Aug 05 04:32:47 PM PDT 24
Finished Aug 05 04:32:54 PM PDT 24
Peak memory 214324 kb
Host smart-90d91eca-b0fb-4d67-b074-b534ffc5fadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280368047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4280368047
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.714363051
Short name T560
Test name
Test status
Simulation time 50118584 ps
CPU time 1.68 seconds
Started Aug 05 04:32:47 PM PDT 24
Finished Aug 05 04:32:49 PM PDT 24
Peak memory 209924 kb
Host smart-c8b9debf-a041-4d51-a7ed-7b1a663e2837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714363051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.714363051
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.387771600
Short name T257
Test name
Test status
Simulation time 140095553 ps
CPU time 2.95 seconds
Started Aug 05 04:33:21 PM PDT 24
Finished Aug 05 04:33:24 PM PDT 24
Peak memory 214628 kb
Host smart-58327f9b-85ad-4f3b-a01d-a9e9e457fcd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387771600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.387771600
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1020188075
Short name T780
Test name
Test status
Simulation time 310408432 ps
CPU time 5.75 seconds
Started Aug 05 04:33:25 PM PDT 24
Finished Aug 05 04:33:31 PM PDT 24
Peak memory 214160 kb
Host smart-b6e32ae7-f343-4c33-bc23-978019c2bc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020188075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1020188075
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3412206965
Short name T207
Test name
Test status
Simulation time 34211029 ps
CPU time 2.39 seconds
Started Aug 05 04:33:10 PM PDT 24
Finished Aug 05 04:33:12 PM PDT 24
Peak memory 209356 kb
Host smart-1eb1ae79-792f-45eb-a9ba-ba1f373b298b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412206965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3412206965
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3618838687
Short name T412
Test name
Test status
Simulation time 625450206 ps
CPU time 6.61 seconds
Started Aug 05 04:33:38 PM PDT 24
Finished Aug 05 04:33:45 PM PDT 24
Peak memory 214148 kb
Host smart-553c525b-0f86-442a-a14a-74048d922c53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618838687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3618838687
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1465933540
Short name T363
Test name
Test status
Simulation time 270551866 ps
CPU time 3.11 seconds
Started Aug 05 04:33:41 PM PDT 24
Finished Aug 05 04:33:45 PM PDT 24
Peak memory 208412 kb
Host smart-c49ddbea-ba7a-44ee-9a62-92303bb27fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465933540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1465933540
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3870759470
Short name T109
Test name
Test status
Simulation time 209679024 ps
CPU time 3.9 seconds
Started Aug 05 04:33:43 PM PDT 24
Finished Aug 05 04:33:47 PM PDT 24
Peak memory 222356 kb
Host smart-ef629117-a9db-43ee-b28a-0a3a14799a12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3870759470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3870759470
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3546718822
Short name T214
Test name
Test status
Simulation time 162216524 ps
CPU time 5.81 seconds
Started Aug 05 04:33:36 PM PDT 24
Finished Aug 05 04:33:42 PM PDT 24
Peak memory 210152 kb
Host smart-12d61c5d-e59b-4762-b286-613e80a7a37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546718822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3546718822
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.161077278
Short name T365
Test name
Test status
Simulation time 384657663 ps
CPU time 3.48 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:01 PM PDT 24
Peak memory 214204 kb
Host smart-a5dee2bd-a138-430c-a7b2-cf6d15134a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161077278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.161077278
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3598885425
Short name T73
Test name
Test status
Simulation time 10222528763 ps
CPU time 26.94 seconds
Started Aug 05 04:34:03 PM PDT 24
Finished Aug 05 04:34:31 PM PDT 24
Peak memory 222424 kb
Host smart-aa1ff61d-8f15-4315-8bb2-01b8abbf15c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598885425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3598885425
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1402611306
Short name T307
Test name
Test status
Simulation time 80775487 ps
CPU time 3.84 seconds
Started Aug 05 04:34:17 PM PDT 24
Finished Aug 05 04:34:21 PM PDT 24
Peak memory 214184 kb
Host smart-e0f1c2c0-6c7a-48d7-96e7-cfcc3266e685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402611306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1402611306
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.897942316
Short name T389
Test name
Test status
Simulation time 454458475 ps
CPU time 18.58 seconds
Started Aug 05 04:34:40 PM PDT 24
Finished Aug 05 04:34:58 PM PDT 24
Peak memory 222364 kb
Host smart-f76e62df-b953-4a4d-9de7-6e621a86cf55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897942316 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.897942316
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1505246664
Short name T239
Test name
Test status
Simulation time 60846540 ps
CPU time 3.97 seconds
Started Aug 05 04:35:15 PM PDT 24
Finished Aug 05 04:35:19 PM PDT 24
Peak memory 215100 kb
Host smart-d84cfecf-8e99-47f9-a65c-85fccd5057ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505246664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1505246664
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3014577688
Short name T225
Test name
Test status
Simulation time 798661230 ps
CPU time 3.5 seconds
Started Aug 05 04:33:00 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 209892 kb
Host smart-f3917f38-b19f-4c08-8d4e-855b09566924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014577688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3014577688
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2778211854
Short name T139
Test name
Test status
Simulation time 73662851 ps
CPU time 4.78 seconds
Started Aug 05 04:28:10 PM PDT 24
Finished Aug 05 04:28:15 PM PDT 24
Peak memory 205892 kb
Host smart-c6632625-796c-4bfc-8426-f3680d7f7a98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778211854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
778211854
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3799720634
Short name T929
Test name
Test status
Simulation time 257989601 ps
CPU time 6.47 seconds
Started Aug 05 04:28:22 PM PDT 24
Finished Aug 05 04:28:29 PM PDT 24
Peak memory 205604 kb
Host smart-3de4c09d-6544-4a95-8229-9e3f49450af7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799720634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
799720634
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3898013074
Short name T928
Test name
Test status
Simulation time 111620470 ps
CPU time 1.44 seconds
Started Aug 05 04:28:07 PM PDT 24
Finished Aug 05 04:28:09 PM PDT 24
Peak memory 206008 kb
Host smart-d96ec5e3-7872-41f0-abfb-e12d17aa197b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898013074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
898013074
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.305056212
Short name T1075
Test name
Test status
Simulation time 127193038 ps
CPU time 1.68 seconds
Started Aug 05 04:28:23 PM PDT 24
Finished Aug 05 04:28:25 PM PDT 24
Peak memory 214340 kb
Host smart-acb95e34-c0bb-45a9-bf24-ec920f900490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305056212 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.305056212
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1614325924
Short name T1052
Test name
Test status
Simulation time 18326731 ps
CPU time 0.88 seconds
Started Aug 05 04:28:18 PM PDT 24
Finished Aug 05 04:28:19 PM PDT 24
Peak memory 205820 kb
Host smart-d2206e8b-d141-4871-91cf-e4f837098baf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614325924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1614325924
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.782146777
Short name T1036
Test name
Test status
Simulation time 13777232 ps
CPU time 0.86 seconds
Started Aug 05 04:28:16 PM PDT 24
Finished Aug 05 04:28:17 PM PDT 24
Peak memory 205936 kb
Host smart-7f73493c-8e87-4727-9abd-bc083863502f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782146777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.782146777
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.776567440
Short name T964
Test name
Test status
Simulation time 64431945 ps
CPU time 2.64 seconds
Started Aug 05 04:28:16 PM PDT 24
Finished Aug 05 04:28:19 PM PDT 24
Peak memory 205984 kb
Host smart-f814550f-0173-4146-a1bc-c78d59eee584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776567440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.776567440
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2573165618
Short name T121
Test name
Test status
Simulation time 103430232 ps
CPU time 2.97 seconds
Started Aug 05 04:28:17 PM PDT 24
Finished Aug 05 04:28:20 PM PDT 24
Peak memory 219052 kb
Host smart-c241dcfc-9365-4ed1-97f3-d4d826bc1e7e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573165618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2573165618
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1734948517
Short name T997
Test name
Test status
Simulation time 121477396 ps
CPU time 4.5 seconds
Started Aug 05 04:28:12 PM PDT 24
Finished Aug 05 04:28:17 PM PDT 24
Peak memory 214488 kb
Host smart-d0f5dc1a-bb15-4ef1-80d3-884ebd7bb89d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734948517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1734948517
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.738010148
Short name T945
Test name
Test status
Simulation time 383818190 ps
CPU time 2.08 seconds
Started Aug 05 04:28:23 PM PDT 24
Finished Aug 05 04:28:25 PM PDT 24
Peak memory 214104 kb
Host smart-ae7cc95c-f488-4171-ad50-c6e3601b2e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738010148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.738010148
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2050262553
Short name T1044
Test name
Test status
Simulation time 740019622 ps
CPU time 9.58 seconds
Started Aug 05 04:28:18 PM PDT 24
Finished Aug 05 04:28:28 PM PDT 24
Peak memory 205992 kb
Host smart-8ff09f99-c477-41df-9a12-da3f1116367d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050262553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
050262553
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.4267816508
Short name T988
Test name
Test status
Simulation time 1035951843 ps
CPU time 14.91 seconds
Started Aug 05 04:28:12 PM PDT 24
Finished Aug 05 04:28:27 PM PDT 24
Peak memory 206064 kb
Host smart-1b450821-e9fb-44df-9258-0e0d6ff5f820
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267816508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.4
267816508
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3336698205
Short name T936
Test name
Test status
Simulation time 51192980 ps
CPU time 1.08 seconds
Started Aug 05 04:28:24 PM PDT 24
Finished Aug 05 04:28:25 PM PDT 24
Peak memory 205940 kb
Host smart-0a8b9e92-9513-4f5f-bc3d-ddb0e3eb79d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336698205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
336698205
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2458553519
Short name T158
Test name
Test status
Simulation time 31055175 ps
CPU time 1.53 seconds
Started Aug 05 04:28:17 PM PDT 24
Finished Aug 05 04:28:19 PM PDT 24
Peak memory 214232 kb
Host smart-3be6bb38-aa1a-4f54-96b2-3f4479433561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458553519 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2458553519
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2639747548
Short name T930
Test name
Test status
Simulation time 86959560 ps
CPU time 1.16 seconds
Started Aug 05 04:28:19 PM PDT 24
Finished Aug 05 04:28:20 PM PDT 24
Peak memory 206080 kb
Host smart-93d2a116-6f60-49f1-a78b-5bff3bc378a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639747548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2639747548
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4139790462
Short name T1070
Test name
Test status
Simulation time 11772663 ps
CPU time 0.91 seconds
Started Aug 05 04:28:10 PM PDT 24
Finished Aug 05 04:28:11 PM PDT 24
Peak memory 205796 kb
Host smart-7103da54-72e6-4ce3-9951-030b9801dae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139790462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4139790462
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.805639514
Short name T1082
Test name
Test status
Simulation time 45151200 ps
CPU time 1.41 seconds
Started Aug 05 04:28:13 PM PDT 24
Finished Aug 05 04:28:15 PM PDT 24
Peak memory 205988 kb
Host smart-47d51b36-2466-4f18-8c2d-309824d64ee7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805639514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.805639514
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2547920189
Short name T1001
Test name
Test status
Simulation time 117254625 ps
CPU time 2.93 seconds
Started Aug 05 04:28:23 PM PDT 24
Finished Aug 05 04:28:26 PM PDT 24
Peak memory 214504 kb
Host smart-0e1ab189-692e-4e4d-bba2-d317ff3200c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547920189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2547920189
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4135369655
Short name T1022
Test name
Test status
Simulation time 323952652 ps
CPU time 9.09 seconds
Started Aug 05 04:28:16 PM PDT 24
Finished Aug 05 04:28:25 PM PDT 24
Peak memory 214424 kb
Host smart-91473ba9-d36d-4ad1-840f-1fb8d53f04b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135369655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.4135369655
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3571907451
Short name T1048
Test name
Test status
Simulation time 316159735 ps
CPU time 2.44 seconds
Started Aug 05 04:28:18 PM PDT 24
Finished Aug 05 04:28:20 PM PDT 24
Peak memory 214412 kb
Host smart-d679ab48-cd0b-4e43-80c8-4c5d1432b6c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571907451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3571907451
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3730305996
Short name T166
Test name
Test status
Simulation time 187799490 ps
CPU time 2.54 seconds
Started Aug 05 04:28:15 PM PDT 24
Finished Aug 05 04:28:18 PM PDT 24
Peak memory 213032 kb
Host smart-b74716c3-a203-4c11-8c41-417a1e93a6cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730305996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3730305996
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2878130736
Short name T1042
Test name
Test status
Simulation time 177333723 ps
CPU time 1.91 seconds
Started Aug 05 04:28:38 PM PDT 24
Finished Aug 05 04:28:40 PM PDT 24
Peak memory 206088 kb
Host smart-a2c2f8ad-4c65-4002-8b1d-d3365bc433f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878130736 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2878130736
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2682891304
Short name T1013
Test name
Test status
Simulation time 12902057 ps
CPU time 1.07 seconds
Started Aug 05 04:28:35 PM PDT 24
Finished Aug 05 04:28:37 PM PDT 24
Peak memory 205988 kb
Host smart-c8673227-e3da-490c-8ffe-9eb9b3bd3573
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682891304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2682891304
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3934561276
Short name T958
Test name
Test status
Simulation time 38894162 ps
CPU time 0.76 seconds
Started Aug 05 04:28:41 PM PDT 24
Finished Aug 05 04:28:42 PM PDT 24
Peak memory 205764 kb
Host smart-513c6f62-02ac-420f-887b-f560669c0f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934561276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3934561276
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3817984518
Short name T1056
Test name
Test status
Simulation time 239240641 ps
CPU time 2.29 seconds
Started Aug 05 04:28:43 PM PDT 24
Finished Aug 05 04:28:45 PM PDT 24
Peak memory 206080 kb
Host smart-11870af3-46ce-457d-a311-8943e731040f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817984518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3817984518
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1816905476
Short name T940
Test name
Test status
Simulation time 632671140 ps
CPU time 4.61 seconds
Started Aug 05 04:28:34 PM PDT 24
Finished Aug 05 04:28:39 PM PDT 24
Peak memory 214504 kb
Host smart-4e415df7-1b97-454a-96dc-58a0313bc820
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816905476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1816905476
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.628680639
Short name T1008
Test name
Test status
Simulation time 3812567077 ps
CPU time 9.28 seconds
Started Aug 05 04:28:30 PM PDT 24
Finished Aug 05 04:28:40 PM PDT 24
Peak memory 214576 kb
Host smart-6f32f48d-c79c-4e3d-be5e-402af32ba7e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628680639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.628680639
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3140040710
Short name T1041
Test name
Test status
Simulation time 102404300 ps
CPU time 1.93 seconds
Started Aug 05 04:28:45 PM PDT 24
Finished Aug 05 04:28:47 PM PDT 24
Peak memory 214160 kb
Host smart-b9ddad73-8b8b-4114-adb7-b7a2bb163d66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140040710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3140040710
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.709918443
Short name T163
Test name
Test status
Simulation time 400924486 ps
CPU time 3.37 seconds
Started Aug 05 04:28:42 PM PDT 24
Finished Aug 05 04:28:45 PM PDT 24
Peak memory 214204 kb
Host smart-a888e569-6421-4140-8b16-3d52bdc6ea4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709918443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.709918443
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2931024997
Short name T918
Test name
Test status
Simulation time 31650243 ps
CPU time 1.79 seconds
Started Aug 05 04:28:51 PM PDT 24
Finished Aug 05 04:28:53 PM PDT 24
Peak memory 214344 kb
Host smart-3ce584a7-bcfc-4342-911c-ade518a52d53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931024997 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2931024997
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3988229947
Short name T134
Test name
Test status
Simulation time 30156329 ps
CPU time 0.99 seconds
Started Aug 05 04:28:42 PM PDT 24
Finished Aug 05 04:28:43 PM PDT 24
Peak memory 205796 kb
Host smart-cc8617f4-8361-4b68-ad33-24c0e15fc9bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988229947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3988229947
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.475302587
Short name T953
Test name
Test status
Simulation time 12171866 ps
CPU time 0.72 seconds
Started Aug 05 04:28:36 PM PDT 24
Finished Aug 05 04:28:37 PM PDT 24
Peak memory 205772 kb
Host smart-966616b0-7a6b-4e80-bba5-c43c25126472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475302587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.475302587
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1674485679
Short name T1057
Test name
Test status
Simulation time 51682037 ps
CPU time 1.6 seconds
Started Aug 05 04:28:49 PM PDT 24
Finished Aug 05 04:28:50 PM PDT 24
Peak memory 206080 kb
Host smart-a3432286-dfa0-400b-b7f2-e75fe73bf66e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674485679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1674485679
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2687220877
Short name T943
Test name
Test status
Simulation time 599201977 ps
CPU time 3.55 seconds
Started Aug 05 04:28:35 PM PDT 24
Finished Aug 05 04:28:38 PM PDT 24
Peak memory 214508 kb
Host smart-5fba065f-c721-4ae8-8189-b4b4201074b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687220877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2687220877
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1855801284
Short name T120
Test name
Test status
Simulation time 337746455 ps
CPU time 8.61 seconds
Started Aug 05 04:28:46 PM PDT 24
Finished Aug 05 04:28:55 PM PDT 24
Peak memory 214488 kb
Host smart-7ff01245-4388-4385-8834-04939e40ac44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855801284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1855801284
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3978045240
Short name T1039
Test name
Test status
Simulation time 813088207 ps
CPU time 4.09 seconds
Started Aug 05 04:28:38 PM PDT 24
Finished Aug 05 04:28:42 PM PDT 24
Peak memory 214240 kb
Host smart-b441b0e2-9662-499c-9510-18341bbf0487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978045240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3978045240
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.4187918869
Short name T155
Test name
Test status
Simulation time 255855449 ps
CPU time 6.63 seconds
Started Aug 05 04:28:31 PM PDT 24
Finished Aug 05 04:28:38 PM PDT 24
Peak memory 216732 kb
Host smart-80b1e75a-7a34-45c4-8061-526fed9132d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187918869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.4187918869
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3150548496
Short name T394
Test name
Test status
Simulation time 39654908 ps
CPU time 1.34 seconds
Started Aug 05 04:28:26 PM PDT 24
Finished Aug 05 04:28:28 PM PDT 24
Peak memory 214308 kb
Host smart-ef2b10df-66a0-4c93-8fff-a7913468bc49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150548496 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3150548496
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1541602309
Short name T916
Test name
Test status
Simulation time 141634957 ps
CPU time 1.21 seconds
Started Aug 05 04:28:47 PM PDT 24
Finished Aug 05 04:28:49 PM PDT 24
Peak memory 205140 kb
Host smart-c60d07da-56eb-4afa-8820-f62057ae4931
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541602309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1541602309
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3399259173
Short name T1021
Test name
Test status
Simulation time 27896326 ps
CPU time 0.7 seconds
Started Aug 05 04:28:38 PM PDT 24
Finished Aug 05 04:28:38 PM PDT 24
Peak memory 205768 kb
Host smart-d9d364e3-120d-4ca8-a93b-fbd73b48b874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399259173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3399259173
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.876889748
Short name T136
Test name
Test status
Simulation time 96735159 ps
CPU time 3.53 seconds
Started Aug 05 04:28:28 PM PDT 24
Finished Aug 05 04:28:31 PM PDT 24
Peak memory 214148 kb
Host smart-b8ac0bfa-3b2f-4e13-9c6c-3529beccab7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876889748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.876889748
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.650761311
Short name T119
Test name
Test status
Simulation time 166896640 ps
CPU time 1.89 seconds
Started Aug 05 04:28:27 PM PDT 24
Finished Aug 05 04:28:29 PM PDT 24
Peak memory 214508 kb
Host smart-873cad9b-b956-4545-83f2-47a2ac9288c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650761311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.650761311
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3038726250
Short name T996
Test name
Test status
Simulation time 740580522 ps
CPU time 7.12 seconds
Started Aug 05 04:28:40 PM PDT 24
Finished Aug 05 04:28:48 PM PDT 24
Peak memory 222684 kb
Host smart-dab00c41-6b52-46ad-a4e1-76fb0f9eee5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038726250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3038726250
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3930264594
Short name T934
Test name
Test status
Simulation time 75055571 ps
CPU time 1.74 seconds
Started Aug 05 04:28:26 PM PDT 24
Finished Aug 05 04:28:27 PM PDT 24
Peak memory 214256 kb
Host smart-98c879f6-d0c8-4a18-a780-48f4c700c47c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930264594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3930264594
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3503497060
Short name T164
Test name
Test status
Simulation time 185907992 ps
CPU time 2.52 seconds
Started Aug 05 04:28:43 PM PDT 24
Finished Aug 05 04:28:46 PM PDT 24
Peak memory 214292 kb
Host smart-392d50d5-b422-4553-958f-de03f4029500
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503497060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3503497060
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.223648442
Short name T1051
Test name
Test status
Simulation time 37006636 ps
CPU time 1.89 seconds
Started Aug 05 04:28:48 PM PDT 24
Finished Aug 05 04:28:50 PM PDT 24
Peak memory 214224 kb
Host smart-3f5e1a42-4f1c-4223-be84-4aeadae87e28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223648442 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.223648442
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2122594415
Short name T151
Test name
Test status
Simulation time 21298978 ps
CPU time 1.11 seconds
Started Aug 05 04:28:23 PM PDT 24
Finished Aug 05 04:28:24 PM PDT 24
Peak memory 205972 kb
Host smart-3597b98a-cbf4-40e1-baf0-2fbe18529e89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122594415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2122594415
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.130605056
Short name T1018
Test name
Test status
Simulation time 78999224 ps
CPU time 0.76 seconds
Started Aug 05 04:28:34 PM PDT 24
Finished Aug 05 04:28:35 PM PDT 24
Peak memory 205772 kb
Host smart-acd7278e-8b20-49a6-986c-b74368e127de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130605056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.130605056
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2173826926
Short name T967
Test name
Test status
Simulation time 82781382 ps
CPU time 1.38 seconds
Started Aug 05 04:28:29 PM PDT 24
Finished Aug 05 04:28:31 PM PDT 24
Peak memory 206004 kb
Host smart-47a28e1d-45d2-4747-b0f8-a6a9349f41f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173826926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2173826926
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1080138890
Short name T1059
Test name
Test status
Simulation time 152691985 ps
CPU time 4.54 seconds
Started Aug 05 04:28:37 PM PDT 24
Finished Aug 05 04:28:42 PM PDT 24
Peak memory 214584 kb
Host smart-f8a03029-cc5b-49ed-bfef-4ecf7b399a6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080138890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1080138890
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.514203564
Short name T1006
Test name
Test status
Simulation time 413215203 ps
CPU time 9.11 seconds
Started Aug 05 04:28:23 PM PDT 24
Finished Aug 05 04:28:32 PM PDT 24
Peak memory 214632 kb
Host smart-671f3e48-ef1a-479e-bd58-871bf9814b40
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514203564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.514203564
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2982140890
Short name T985
Test name
Test status
Simulation time 280583734 ps
CPU time 2.85 seconds
Started Aug 05 04:28:32 PM PDT 24
Finished Aug 05 04:28:35 PM PDT 24
Peak memory 214180 kb
Host smart-7765fe9d-b6e2-48ed-906d-cd603486b8a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982140890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2982140890
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3120393238
Short name T1055
Test name
Test status
Simulation time 202892409 ps
CPU time 6.46 seconds
Started Aug 05 04:28:48 PM PDT 24
Finished Aug 05 04:28:54 PM PDT 24
Peak memory 214216 kb
Host smart-3abb732d-76c0-4c6e-acf9-21c478e732a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120393238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3120393238
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4292133061
Short name T1054
Test name
Test status
Simulation time 18126434 ps
CPU time 1.32 seconds
Started Aug 05 04:28:30 PM PDT 24
Finished Aug 05 04:28:32 PM PDT 24
Peak memory 214168 kb
Host smart-86d61227-0db6-4294-9100-1e301198fcec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292133061 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.4292133061
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1950905523
Short name T954
Test name
Test status
Simulation time 59736186 ps
CPU time 1.25 seconds
Started Aug 05 04:28:45 PM PDT 24
Finished Aug 05 04:28:46 PM PDT 24
Peak memory 205996 kb
Host smart-0e1ee925-8c41-4d65-9354-ca65cf3d1671
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950905523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1950905523
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1317919035
Short name T933
Test name
Test status
Simulation time 20742249 ps
CPU time 0.84 seconds
Started Aug 05 04:28:32 PM PDT 24
Finished Aug 05 04:28:33 PM PDT 24
Peak memory 206144 kb
Host smart-8c8372da-e084-4926-a4df-c9c6a3f1d0de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317919035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1317919035
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3562933416
Short name T1030
Test name
Test status
Simulation time 36909517 ps
CPU time 2.05 seconds
Started Aug 05 04:28:26 PM PDT 24
Finished Aug 05 04:28:28 PM PDT 24
Peak memory 206056 kb
Host smart-cc1c29db-0731-4b13-aafd-9877621f33cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562933416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3562933416
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.209925743
Short name T942
Test name
Test status
Simulation time 140688552 ps
CPU time 2.19 seconds
Started Aug 05 04:28:39 PM PDT 24
Finished Aug 05 04:28:41 PM PDT 24
Peak memory 214516 kb
Host smart-e4fea7e1-5e7b-4678-aabd-d147d3572a17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209925743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.209925743
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2863168920
Short name T947
Test name
Test status
Simulation time 448084210 ps
CPU time 12.07 seconds
Started Aug 05 04:28:42 PM PDT 24
Finished Aug 05 04:28:54 PM PDT 24
Peak memory 220684 kb
Host smart-e8945335-b1a7-4b17-940a-be61e37292f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863168920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2863168920
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.823769489
Short name T994
Test name
Test status
Simulation time 255126782 ps
CPU time 4.54 seconds
Started Aug 05 04:28:35 PM PDT 24
Finished Aug 05 04:28:39 PM PDT 24
Peak memory 214140 kb
Host smart-b6c31e98-1807-4484-a248-2d72eded54ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823769489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.823769489
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.128331358
Short name T1081
Test name
Test status
Simulation time 18381193 ps
CPU time 1.39 seconds
Started Aug 05 04:28:39 PM PDT 24
Finished Aug 05 04:28:41 PM PDT 24
Peak memory 214276 kb
Host smart-b4d89b28-cfa6-45ca-98a8-45de0371e6cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128331358 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.128331358
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1769448098
Short name T138
Test name
Test status
Simulation time 18368764 ps
CPU time 1.1 seconds
Started Aug 05 04:28:43 PM PDT 24
Finished Aug 05 04:28:45 PM PDT 24
Peak memory 206008 kb
Host smart-b3f69436-2dc1-400e-8926-e46c07b28247
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769448098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1769448098
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3235283893
Short name T966
Test name
Test status
Simulation time 12492521 ps
CPU time 0.84 seconds
Started Aug 05 04:28:39 PM PDT 24
Finished Aug 05 04:28:40 PM PDT 24
Peak memory 205776 kb
Host smart-d33a7621-acf2-450a-861e-b219fb64f304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235283893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3235283893
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2049330407
Short name T971
Test name
Test status
Simulation time 97482011 ps
CPU time 1.47 seconds
Started Aug 05 04:28:34 PM PDT 24
Finished Aug 05 04:28:35 PM PDT 24
Peak memory 205960 kb
Host smart-50195c8a-de0f-4f5c-92af-c78bea83e10d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049330407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2049330407
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2624842794
Short name T1027
Test name
Test status
Simulation time 190550219 ps
CPU time 1.81 seconds
Started Aug 05 04:28:33 PM PDT 24
Finished Aug 05 04:28:35 PM PDT 24
Peak memory 214412 kb
Host smart-3cbb28bf-2f06-486b-a690-477d6d9c7268
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624842794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2624842794
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3165519302
Short name T973
Test name
Test status
Simulation time 630335589 ps
CPU time 6.6 seconds
Started Aug 05 04:28:48 PM PDT 24
Finished Aug 05 04:28:55 PM PDT 24
Peak memory 214428 kb
Host smart-36f836e3-5793-4237-bfb3-132f84d7ad75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165519302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3165519302
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.538587458
Short name T995
Test name
Test status
Simulation time 194774480 ps
CPU time 2.77 seconds
Started Aug 05 04:28:40 PM PDT 24
Finished Aug 05 04:28:43 PM PDT 24
Peak memory 214160 kb
Host smart-81f58754-1612-46a2-a1bc-47c3aaf68b01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538587458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.538587458
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2732286793
Short name T1028
Test name
Test status
Simulation time 55795749 ps
CPU time 1.66 seconds
Started Aug 05 04:28:30 PM PDT 24
Finished Aug 05 04:28:32 PM PDT 24
Peak memory 214296 kb
Host smart-d7ec2c61-2fa0-4ff0-9e99-30589f9be5d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732286793 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2732286793
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3149317645
Short name T1038
Test name
Test status
Simulation time 107092910 ps
CPU time 1.2 seconds
Started Aug 05 04:28:43 PM PDT 24
Finished Aug 05 04:28:45 PM PDT 24
Peak memory 206020 kb
Host smart-5a573f5a-b908-4223-b011-7637e4d609ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149317645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3149317645
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2065032150
Short name T1063
Test name
Test status
Simulation time 9233196 ps
CPU time 0.81 seconds
Started Aug 05 04:28:37 PM PDT 24
Finished Aug 05 04:28:38 PM PDT 24
Peak memory 205768 kb
Host smart-fafbf198-09ad-4883-9a7d-d19bc2b962be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065032150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2065032150
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4133235128
Short name T949
Test name
Test status
Simulation time 84830308 ps
CPU time 2.53 seconds
Started Aug 05 04:28:31 PM PDT 24
Finished Aug 05 04:28:34 PM PDT 24
Peak memory 205976 kb
Host smart-12bf21c6-f378-4024-8ee6-df9e65763bf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133235128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.4133235128
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.808649093
Short name T974
Test name
Test status
Simulation time 325128167 ps
CPU time 2.32 seconds
Started Aug 05 04:28:36 PM PDT 24
Finished Aug 05 04:28:39 PM PDT 24
Peak memory 214464 kb
Host smart-b9c651d9-d207-4ad0-9df7-c79e82cbaeb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808649093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.808649093
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2431543224
Short name T1019
Test name
Test status
Simulation time 339277974 ps
CPU time 8 seconds
Started Aug 05 04:28:43 PM PDT 24
Finished Aug 05 04:28:51 PM PDT 24
Peak memory 214496 kb
Host smart-71374f2c-84df-4bc8-8da4-c728fcf3021b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431543224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2431543224
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2503447935
Short name T1007
Test name
Test status
Simulation time 516473844 ps
CPU time 3.48 seconds
Started Aug 05 04:28:43 PM PDT 24
Finished Aug 05 04:28:46 PM PDT 24
Peak memory 214280 kb
Host smart-394f67a7-f137-4245-a408-5121c0316cec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503447935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2503447935
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1889910698
Short name T152
Test name
Test status
Simulation time 283013951 ps
CPU time 5.53 seconds
Started Aug 05 04:28:41 PM PDT 24
Finished Aug 05 04:28:47 PM PDT 24
Peak memory 214196 kb
Host smart-05bafb21-d79c-4e92-aa20-e01e7c0473c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889910698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1889910698
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3902688975
Short name T157
Test name
Test status
Simulation time 24623530 ps
CPU time 1.63 seconds
Started Aug 05 04:28:29 PM PDT 24
Finished Aug 05 04:28:31 PM PDT 24
Peak memory 214280 kb
Host smart-2fc34a09-a012-4532-9ca5-65e77f8ae561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902688975 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3902688975
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3276977916
Short name T972
Test name
Test status
Simulation time 44780643 ps
CPU time 1.09 seconds
Started Aug 05 04:28:43 PM PDT 24
Finished Aug 05 04:28:44 PM PDT 24
Peak memory 206004 kb
Host smart-f5e58e79-25b0-431b-a19c-89d9c313425f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276977916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3276977916
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2339873067
Short name T976
Test name
Test status
Simulation time 13508338 ps
CPU time 0.77 seconds
Started Aug 05 04:28:49 PM PDT 24
Finished Aug 05 04:28:50 PM PDT 24
Peak memory 205740 kb
Host smart-69f62e0f-e645-4aa8-a7a5-9f4bd26f12c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339873067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2339873067
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1192775733
Short name T925
Test name
Test status
Simulation time 32744398 ps
CPU time 2.33 seconds
Started Aug 05 04:28:37 PM PDT 24
Finished Aug 05 04:28:39 PM PDT 24
Peak memory 206044 kb
Host smart-99288cba-89c8-48c0-95cf-7bb74b6724e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192775733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1192775733
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.531532037
Short name T122
Test name
Test status
Simulation time 319365562 ps
CPU time 2.5 seconds
Started Aug 05 04:28:34 PM PDT 24
Finished Aug 05 04:28:37 PM PDT 24
Peak memory 214548 kb
Host smart-29e96813-d1a7-465a-bfd0-1152b4ac64fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531532037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.531532037
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2765811916
Short name T1068
Test name
Test status
Simulation time 267964661 ps
CPU time 4.09 seconds
Started Aug 05 04:28:42 PM PDT 24
Finished Aug 05 04:28:46 PM PDT 24
Peak memory 214592 kb
Host smart-b78b3a4f-97e5-4fb4-8726-1adb9330c6c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765811916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2765811916
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1821404120
Short name T1074
Test name
Test status
Simulation time 81482428 ps
CPU time 1.33 seconds
Started Aug 05 04:28:50 PM PDT 24
Finished Aug 05 04:28:52 PM PDT 24
Peak memory 214400 kb
Host smart-9124c79d-36c3-4ce4-b52f-5345a8603cc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821404120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1821404120
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.655362924
Short name T938
Test name
Test status
Simulation time 725965854 ps
CPU time 2.32 seconds
Started Aug 05 04:28:36 PM PDT 24
Finished Aug 05 04:28:38 PM PDT 24
Peak memory 214188 kb
Host smart-481dafbb-4b1f-412b-b964-1ecda57db46d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655362924 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.655362924
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3735153917
Short name T1033
Test name
Test status
Simulation time 30746026 ps
CPU time 1.21 seconds
Started Aug 05 04:28:44 PM PDT 24
Finished Aug 05 04:28:46 PM PDT 24
Peak memory 206012 kb
Host smart-bce5e501-bd31-4146-a2d2-e5b3c5345e1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735153917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3735153917
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1246997892
Short name T1000
Test name
Test status
Simulation time 7870232 ps
CPU time 0.7 seconds
Started Aug 05 04:28:42 PM PDT 24
Finished Aug 05 04:28:43 PM PDT 24
Peak memory 205732 kb
Host smart-2ac89137-5ce9-477d-92fe-32f56737f5ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246997892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1246997892
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.332098453
Short name T1062
Test name
Test status
Simulation time 343877353 ps
CPU time 3.56 seconds
Started Aug 05 04:28:42 PM PDT 24
Finished Aug 05 04:28:46 PM PDT 24
Peak memory 206048 kb
Host smart-7e4347bc-ce10-41e9-84a1-5770650024d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332098453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.332098453
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3256792348
Short name T1046
Test name
Test status
Simulation time 385168980 ps
CPU time 2.77 seconds
Started Aug 05 04:28:40 PM PDT 24
Finished Aug 05 04:28:43 PM PDT 24
Peak memory 214420 kb
Host smart-a7793096-d507-41a0-a9dc-2b4b06c71092
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256792348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3256792348
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4248774389
Short name T981
Test name
Test status
Simulation time 504559559 ps
CPU time 8.85 seconds
Started Aug 05 04:28:46 PM PDT 24
Finished Aug 05 04:28:55 PM PDT 24
Peak memory 222776 kb
Host smart-1b98b974-dadb-4028-8ac9-44ffedc7354e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248774389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.4248774389
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1735075773
Short name T1047
Test name
Test status
Simulation time 50680354 ps
CPU time 1.94 seconds
Started Aug 05 04:28:42 PM PDT 24
Finished Aug 05 04:28:44 PM PDT 24
Peak memory 214264 kb
Host smart-07cfab4a-2e82-4fb0-aeda-b0b99085469b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735075773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1735075773
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1805530842
Short name T172
Test name
Test status
Simulation time 69645310 ps
CPU time 2.57 seconds
Started Aug 05 04:28:28 PM PDT 24
Finished Aug 05 04:28:30 PM PDT 24
Peak memory 214020 kb
Host smart-7a93071d-4ee5-429d-8e03-11b00ed93bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805530842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1805530842
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.4293349442
Short name T932
Test name
Test status
Simulation time 36190326 ps
CPU time 1.27 seconds
Started Aug 05 04:28:51 PM PDT 24
Finished Aug 05 04:28:53 PM PDT 24
Peak memory 214316 kb
Host smart-912385d3-5e90-4319-8a1a-3e2f7fee5431
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293349442 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.4293349442
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1810358438
Short name T1005
Test name
Test status
Simulation time 48361556 ps
CPU time 1.43 seconds
Started Aug 05 04:28:44 PM PDT 24
Finished Aug 05 04:28:45 PM PDT 24
Peak memory 205976 kb
Host smart-de5dd8a8-b4d4-40e5-8526-81d6164cbcc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810358438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1810358438
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3140319960
Short name T1045
Test name
Test status
Simulation time 69719955 ps
CPU time 0.73 seconds
Started Aug 05 04:28:35 PM PDT 24
Finished Aug 05 04:28:36 PM PDT 24
Peak memory 205700 kb
Host smart-104bcfee-b7ca-416e-837e-13460349a8c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140319960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3140319960
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3832045776
Short name T1029
Test name
Test status
Simulation time 1893396066 ps
CPU time 3.71 seconds
Started Aug 05 04:28:37 PM PDT 24
Finished Aug 05 04:28:41 PM PDT 24
Peak memory 214208 kb
Host smart-d3f84554-fa76-434c-8e1a-ef5b380bdf41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832045776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3832045776
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.259602452
Short name T950
Test name
Test status
Simulation time 375687082 ps
CPU time 2.89 seconds
Started Aug 05 04:28:43 PM PDT 24
Finished Aug 05 04:28:46 PM PDT 24
Peak memory 214452 kb
Host smart-c812950f-f761-4b3b-9532-83903ce58cb6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259602452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.259602452
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2048172499
Short name T1009
Test name
Test status
Simulation time 683785079 ps
CPU time 8.35 seconds
Started Aug 05 04:28:34 PM PDT 24
Finished Aug 05 04:28:42 PM PDT 24
Peak memory 214528 kb
Host smart-b3109293-62ec-47c3-92ca-72a7660b1fad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048172499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2048172499
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2170718918
Short name T977
Test name
Test status
Simulation time 96115819 ps
CPU time 2.55 seconds
Started Aug 05 04:28:30 PM PDT 24
Finished Aug 05 04:28:33 PM PDT 24
Peak memory 214300 kb
Host smart-51e7226d-0221-4f5e-adb3-c9732c6013f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170718918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2170718918
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2788167580
Short name T167
Test name
Test status
Simulation time 718445737 ps
CPU time 4.29 seconds
Started Aug 05 04:28:42 PM PDT 24
Finished Aug 05 04:28:47 PM PDT 24
Peak memory 214200 kb
Host smart-21584fad-c1a7-4d1d-967c-e5cad478d559
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788167580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2788167580
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3909418553
Short name T923
Test name
Test status
Simulation time 185865757 ps
CPU time 5.05 seconds
Started Aug 05 04:28:12 PM PDT 24
Finished Aug 05 04:28:17 PM PDT 24
Peak memory 205828 kb
Host smart-a84b3fed-fad0-4bec-a4b9-307896cd5a71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909418553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
909418553
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2856993649
Short name T924
Test name
Test status
Simulation time 14267486145 ps
CPU time 23.48 seconds
Started Aug 05 04:28:12 PM PDT 24
Finished Aug 05 04:28:36 PM PDT 24
Peak memory 206368 kb
Host smart-5ae322ee-8db3-467d-8f81-4c1e9b4d5974
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856993649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
856993649
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3337171450
Short name T952
Test name
Test status
Simulation time 58930916 ps
CPU time 1.47 seconds
Started Aug 05 04:28:11 PM PDT 24
Finished Aug 05 04:28:13 PM PDT 24
Peak memory 205988 kb
Host smart-976f0321-4794-4043-9c09-d9611977e581
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337171450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
337171450
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3040481825
Short name T1031
Test name
Test status
Simulation time 201826507 ps
CPU time 1.7 seconds
Started Aug 05 04:28:27 PM PDT 24
Finished Aug 05 04:28:29 PM PDT 24
Peak memory 214404 kb
Host smart-a44d3521-6759-4d20-86d4-3dbd678eeaf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040481825 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3040481825
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3908342774
Short name T982
Test name
Test status
Simulation time 76484354 ps
CPU time 1.22 seconds
Started Aug 05 04:28:19 PM PDT 24
Finished Aug 05 04:28:21 PM PDT 24
Peak memory 205932 kb
Host smart-d2321b63-ea85-41cf-b323-2d5bec81fe18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908342774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3908342774
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1178376817
Short name T1032
Test name
Test status
Simulation time 15442365 ps
CPU time 0.83 seconds
Started Aug 05 04:28:24 PM PDT 24
Finished Aug 05 04:28:25 PM PDT 24
Peak memory 205752 kb
Host smart-0ac71c3b-e51f-410f-876f-08febc5f2052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178376817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1178376817
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3790528960
Short name T951
Test name
Test status
Simulation time 901287244 ps
CPU time 2.47 seconds
Started Aug 05 04:28:29 PM PDT 24
Finished Aug 05 04:28:32 PM PDT 24
Peak memory 205984 kb
Host smart-deead732-ecfd-4181-b4e2-eeda226afdeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790528960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3790528960
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.839424522
Short name T123
Test name
Test status
Simulation time 75390522 ps
CPU time 1.65 seconds
Started Aug 05 04:28:18 PM PDT 24
Finished Aug 05 04:28:20 PM PDT 24
Peak memory 214512 kb
Host smart-8ecac2fd-1ee5-46ac-9e8e-9d7303db1b5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839424522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.839424522
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.74421839
Short name T970
Test name
Test status
Simulation time 157126596 ps
CPU time 7.12 seconds
Started Aug 05 04:28:18 PM PDT 24
Finished Aug 05 04:28:25 PM PDT 24
Peak memory 214524 kb
Host smart-0373b71e-3b37-4a79-8853-9e39c4928d05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74421839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.ke
ymgr_shadow_reg_errors_with_csr_rw.74421839
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2357071957
Short name T955
Test name
Test status
Simulation time 91908228 ps
CPU time 3.26 seconds
Started Aug 05 04:28:25 PM PDT 24
Finished Aug 05 04:28:28 PM PDT 24
Peak memory 217732 kb
Host smart-503b16cb-f76a-4738-a09c-7b56f31ef55c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357071957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2357071957
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.4195926743
Short name T992
Test name
Test status
Simulation time 58021225 ps
CPU time 0.74 seconds
Started Aug 05 04:28:50 PM PDT 24
Finished Aug 05 04:28:51 PM PDT 24
Peak memory 205748 kb
Host smart-66a42d56-59e1-4ec3-bfed-4a9c7520fda7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195926743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.4195926743
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3993077714
Short name T1049
Test name
Test status
Simulation time 68689025 ps
CPU time 0.76 seconds
Started Aug 05 04:28:39 PM PDT 24
Finished Aug 05 04:28:40 PM PDT 24
Peak memory 205744 kb
Host smart-464b14a6-ed23-43b6-903b-0639b97cb9d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993077714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3993077714
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2369005361
Short name T914
Test name
Test status
Simulation time 16653199 ps
CPU time 0.65 seconds
Started Aug 05 04:28:48 PM PDT 24
Finished Aug 05 04:28:49 PM PDT 24
Peak memory 205688 kb
Host smart-d923471d-7384-4006-9f30-9df4fbeea0b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369005361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2369005361
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.909231455
Short name T1043
Test name
Test status
Simulation time 41428338 ps
CPU time 0.8 seconds
Started Aug 05 04:28:57 PM PDT 24
Finished Aug 05 04:28:58 PM PDT 24
Peak memory 205740 kb
Host smart-4992b5b1-8a2a-4195-a00d-d8fcc3564fc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909231455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.909231455
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3742028612
Short name T969
Test name
Test status
Simulation time 41617130 ps
CPU time 0.72 seconds
Started Aug 05 04:28:41 PM PDT 24
Finished Aug 05 04:28:42 PM PDT 24
Peak memory 205728 kb
Host smart-1159b63e-7276-4034-9c7d-6343b00d0699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742028612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3742028612
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3154216079
Short name T983
Test name
Test status
Simulation time 47610888 ps
CPU time 0.86 seconds
Started Aug 05 04:28:38 PM PDT 24
Finished Aug 05 04:28:39 PM PDT 24
Peak memory 205752 kb
Host smart-37a2419a-c428-4c2d-9531-7686b647cea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154216079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3154216079
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2304194073
Short name T975
Test name
Test status
Simulation time 11509276 ps
CPU time 0.75 seconds
Started Aug 05 04:28:48 PM PDT 24
Finished Aug 05 04:28:49 PM PDT 24
Peak memory 205772 kb
Host smart-aa916bce-5597-4725-bff8-7483b75a735b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304194073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2304194073
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1022939205
Short name T1026
Test name
Test status
Simulation time 31825919 ps
CPU time 0.67 seconds
Started Aug 05 04:28:49 PM PDT 24
Finished Aug 05 04:28:49 PM PDT 24
Peak memory 205768 kb
Host smart-417c132c-52a7-4d48-8cf9-4891509d0270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022939205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1022939205
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2944664981
Short name T1065
Test name
Test status
Simulation time 22092563 ps
CPU time 0.83 seconds
Started Aug 05 04:28:42 PM PDT 24
Finished Aug 05 04:28:43 PM PDT 24
Peak memory 205768 kb
Host smart-102ccdc0-c156-40ea-9dbc-4021a8dd3874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944664981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2944664981
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1574882199
Short name T917
Test name
Test status
Simulation time 8552659 ps
CPU time 0.81 seconds
Started Aug 05 04:28:35 PM PDT 24
Finished Aug 05 04:28:36 PM PDT 24
Peak memory 205772 kb
Host smart-89e97620-9cc7-4023-98c0-dcf5bab4433a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574882199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1574882199
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.633841258
Short name T1079
Test name
Test status
Simulation time 733337815 ps
CPU time 9.2 seconds
Started Aug 05 04:28:14 PM PDT 24
Finished Aug 05 04:28:23 PM PDT 24
Peak memory 206040 kb
Host smart-e4910843-c1f3-4daa-b026-05d1553249ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633841258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.633841258
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3549842947
Short name T998
Test name
Test status
Simulation time 251297113 ps
CPU time 7.5 seconds
Started Aug 05 04:28:09 PM PDT 24
Finished Aug 05 04:28:17 PM PDT 24
Peak memory 205928 kb
Host smart-b26a099b-bfa3-4878-8ea3-17dcb2d54a7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549842947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
549842947
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1407889272
Short name T1053
Test name
Test status
Simulation time 20745665 ps
CPU time 1.16 seconds
Started Aug 05 04:28:13 PM PDT 24
Finished Aug 05 04:28:14 PM PDT 24
Peak memory 205908 kb
Host smart-23827462-2cf8-43c6-bf4e-ec6030ca82f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407889272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
407889272
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.307617935
Short name T1073
Test name
Test status
Simulation time 280738667 ps
CPU time 1.92 seconds
Started Aug 05 04:28:19 PM PDT 24
Finished Aug 05 04:28:21 PM PDT 24
Peak memory 214284 kb
Host smart-53fdc5a2-b5f7-4e2a-b896-db853c6acd72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307617935 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.307617935
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2826423269
Short name T960
Test name
Test status
Simulation time 24575022 ps
CPU time 1.42 seconds
Started Aug 05 04:28:14 PM PDT 24
Finished Aug 05 04:28:16 PM PDT 24
Peak memory 205980 kb
Host smart-4b7615c9-abef-4e33-959c-a6ea1fec80da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826423269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2826423269
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3622696223
Short name T915
Test name
Test status
Simulation time 35467350 ps
CPU time 0.8 seconds
Started Aug 05 04:28:18 PM PDT 24
Finished Aug 05 04:28:19 PM PDT 24
Peak memory 205780 kb
Host smart-aab78201-add1-475d-bab2-c43ef9cfc549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622696223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3622696223
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.773728052
Short name T941
Test name
Test status
Simulation time 125452362 ps
CPU time 2.73 seconds
Started Aug 05 04:28:13 PM PDT 24
Finished Aug 05 04:28:16 PM PDT 24
Peak memory 205940 kb
Host smart-8d7b2154-3ef3-43bf-924b-873e38546f99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773728052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.773728052
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3266835642
Short name T987
Test name
Test status
Simulation time 76464392 ps
CPU time 1.64 seconds
Started Aug 05 04:28:12 PM PDT 24
Finished Aug 05 04:28:13 PM PDT 24
Peak memory 214600 kb
Host smart-1e9f089a-275d-4dad-a44e-5264224b1683
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266835642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3266835642
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1786368105
Short name T1011
Test name
Test status
Simulation time 139102708 ps
CPU time 3.98 seconds
Started Aug 05 04:28:15 PM PDT 24
Finished Aug 05 04:28:19 PM PDT 24
Peak memory 214624 kb
Host smart-293a4d01-94e3-4cb3-a8d0-35e206a469d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786368105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1786368105
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1578117992
Short name T957
Test name
Test status
Simulation time 56344354 ps
CPU time 1.9 seconds
Started Aug 05 04:28:11 PM PDT 24
Finished Aug 05 04:28:13 PM PDT 24
Peak memory 214252 kb
Host smart-5613df3a-624b-4db5-95f3-3c37e2a72dff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578117992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1578117992
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.689190051
Short name T926
Test name
Test status
Simulation time 21815387 ps
CPU time 0.8 seconds
Started Aug 05 04:28:34 PM PDT 24
Finished Aug 05 04:28:35 PM PDT 24
Peak memory 205820 kb
Host smart-9eaa1592-c107-4a5b-b67c-7c950825f5e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689190051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.689190051
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.4271246702
Short name T1017
Test name
Test status
Simulation time 35802952 ps
CPU time 0.79 seconds
Started Aug 05 04:28:54 PM PDT 24
Finished Aug 05 04:28:55 PM PDT 24
Peak memory 205776 kb
Host smart-319a5ef0-84d8-4091-bbcb-e1d7509c3e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271246702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.4271246702
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1355049227
Short name T1067
Test name
Test status
Simulation time 8979119 ps
CPU time 0.82 seconds
Started Aug 05 04:28:54 PM PDT 24
Finished Aug 05 04:28:55 PM PDT 24
Peak memory 205960 kb
Host smart-1710c94e-4c00-48bf-b9ea-0e2eedb9596c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355049227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1355049227
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3601057265
Short name T1069
Test name
Test status
Simulation time 11057534 ps
CPU time 0.85 seconds
Started Aug 05 04:28:30 PM PDT 24
Finished Aug 05 04:28:31 PM PDT 24
Peak memory 205772 kb
Host smart-7256b637-09bd-49d5-be01-2d0b2608ae1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601057265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3601057265
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1439792615
Short name T1061
Test name
Test status
Simulation time 52865290 ps
CPU time 0.93 seconds
Started Aug 05 04:28:49 PM PDT 24
Finished Aug 05 04:28:50 PM PDT 24
Peak memory 205784 kb
Host smart-5a43dbd6-12a0-4dda-b997-b7fd7e92b6db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439792615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1439792615
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3677850738
Short name T1023
Test name
Test status
Simulation time 76571021 ps
CPU time 0.9 seconds
Started Aug 05 04:28:41 PM PDT 24
Finished Aug 05 04:28:42 PM PDT 24
Peak memory 205904 kb
Host smart-627014d3-381d-4409-b750-834143cfc281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677850738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3677850738
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.583884369
Short name T1072
Test name
Test status
Simulation time 13384781 ps
CPU time 0.74 seconds
Started Aug 05 04:28:35 PM PDT 24
Finished Aug 05 04:28:36 PM PDT 24
Peak memory 205748 kb
Host smart-e974d718-cd63-4451-8ed3-dc97c93f1c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583884369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.583884369
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3584555563
Short name T1015
Test name
Test status
Simulation time 36260238 ps
CPU time 0.81 seconds
Started Aug 05 04:28:49 PM PDT 24
Finished Aug 05 04:28:50 PM PDT 24
Peak memory 205792 kb
Host smart-42618a1b-ad1f-464a-8801-7b8dc278bfc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584555563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3584555563
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2175425149
Short name T961
Test name
Test status
Simulation time 17669159 ps
CPU time 0.68 seconds
Started Aug 05 04:28:32 PM PDT 24
Finished Aug 05 04:28:33 PM PDT 24
Peak memory 205708 kb
Host smart-b869eb60-6685-48aa-8ba1-640b752bec6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175425149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2175425149
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.649619271
Short name T1020
Test name
Test status
Simulation time 10525084 ps
CPU time 0.78 seconds
Started Aug 05 04:28:43 PM PDT 24
Finished Aug 05 04:28:44 PM PDT 24
Peak memory 205768 kb
Host smart-9cc6f997-d3ac-423c-9053-2577cb6344b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649619271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.649619271
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2118570205
Short name T1004
Test name
Test status
Simulation time 134055769 ps
CPU time 4.17 seconds
Started Aug 05 04:28:19 PM PDT 24
Finished Aug 05 04:28:23 PM PDT 24
Peak memory 206056 kb
Host smart-e0690aaf-96fa-4765-9845-231389e637b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118570205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
118570205
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2863364005
Short name T999
Test name
Test status
Simulation time 883066560 ps
CPU time 23.77 seconds
Started Aug 05 04:28:22 PM PDT 24
Finished Aug 05 04:28:46 PM PDT 24
Peak memory 205980 kb
Host smart-064637d1-3b99-4cc0-9221-50864765d67d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863364005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
863364005
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2809820800
Short name T1003
Test name
Test status
Simulation time 26633712 ps
CPU time 0.86 seconds
Started Aug 05 04:28:09 PM PDT 24
Finished Aug 05 04:28:10 PM PDT 24
Peak memory 205816 kb
Host smart-60908c3c-a26b-4993-9c1e-30c9f8be66cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809820800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
809820800
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1963414711
Short name T944
Test name
Test status
Simulation time 102109483 ps
CPU time 1.17 seconds
Started Aug 05 04:28:24 PM PDT 24
Finished Aug 05 04:28:26 PM PDT 24
Peak memory 206052 kb
Host smart-ba51ac7f-277b-4b92-92e3-b2e67eb07fc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963414711 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1963414711
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3600244239
Short name T959
Test name
Test status
Simulation time 96088828 ps
CPU time 1.13 seconds
Started Aug 05 04:28:21 PM PDT 24
Finished Aug 05 04:28:22 PM PDT 24
Peak memory 205996 kb
Host smart-69ec8c36-9e27-4a5f-9942-04e10238d94e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600244239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3600244239
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3359271595
Short name T919
Test name
Test status
Simulation time 15302260 ps
CPU time 0.99 seconds
Started Aug 05 04:28:15 PM PDT 24
Finished Aug 05 04:28:16 PM PDT 24
Peak memory 205036 kb
Host smart-e4308621-16fe-4fd5-ada1-1847e31f8371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359271595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3359271595
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3037194014
Short name T927
Test name
Test status
Simulation time 39402051 ps
CPU time 1.27 seconds
Started Aug 05 04:28:26 PM PDT 24
Finished Aug 05 04:28:27 PM PDT 24
Peak memory 206076 kb
Host smart-afe31652-eb8d-4681-a989-13f08e738f3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037194014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3037194014
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1552578163
Short name T939
Test name
Test status
Simulation time 937250522 ps
CPU time 3.22 seconds
Started Aug 05 04:28:35 PM PDT 24
Finished Aug 05 04:28:38 PM PDT 24
Peak memory 214544 kb
Host smart-152151aa-1652-483c-b73a-ebe8b43dc336
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552578163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1552578163
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2785525677
Short name T1002
Test name
Test status
Simulation time 1281000752 ps
CPU time 4.15 seconds
Started Aug 05 04:28:11 PM PDT 24
Finished Aug 05 04:28:15 PM PDT 24
Peak memory 220688 kb
Host smart-654fe618-02bd-4cbb-9638-59e3dd5e36a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785525677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2785525677
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2677383719
Short name T1050
Test name
Test status
Simulation time 86025854 ps
CPU time 2.44 seconds
Started Aug 05 04:28:22 PM PDT 24
Finished Aug 05 04:28:24 PM PDT 24
Peak memory 214256 kb
Host smart-dfdd980b-edaf-4b00-b907-970c123fcb24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677383719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2677383719
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3288838671
Short name T1071
Test name
Test status
Simulation time 13238129 ps
CPU time 0.93 seconds
Started Aug 05 04:28:49 PM PDT 24
Finished Aug 05 04:28:51 PM PDT 24
Peak memory 205076 kb
Host smart-ce1087d1-1d49-4c94-8305-cc27036f78be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288838671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3288838671
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2125264157
Short name T1024
Test name
Test status
Simulation time 34678846 ps
CPU time 0.83 seconds
Started Aug 05 04:28:47 PM PDT 24
Finished Aug 05 04:28:48 PM PDT 24
Peak memory 204936 kb
Host smart-462a3e6d-0015-4e40-af9e-f8b477c6119e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125264157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2125264157
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1853954738
Short name T921
Test name
Test status
Simulation time 21595567 ps
CPU time 0.74 seconds
Started Aug 05 04:28:51 PM PDT 24
Finished Aug 05 04:28:51 PM PDT 24
Peak memory 205788 kb
Host smart-fa50d06f-f564-4e23-a511-69ca3c79ff8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853954738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1853954738
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4264983612
Short name T1012
Test name
Test status
Simulation time 32478020 ps
CPU time 0.72 seconds
Started Aug 05 04:28:52 PM PDT 24
Finished Aug 05 04:28:53 PM PDT 24
Peak memory 205792 kb
Host smart-d63cff80-8530-4a2e-912f-8db3200ed820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264983612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4264983612
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.641864856
Short name T1058
Test name
Test status
Simulation time 40789317 ps
CPU time 0.88 seconds
Started Aug 05 04:28:51 PM PDT 24
Finished Aug 05 04:28:52 PM PDT 24
Peak memory 205820 kb
Host smart-d1a53466-cd6d-448a-8319-a048fe755f27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641864856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.641864856
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1949028692
Short name T989
Test name
Test status
Simulation time 14026052 ps
CPU time 0.68 seconds
Started Aug 05 04:28:58 PM PDT 24
Finished Aug 05 04:28:59 PM PDT 24
Peak memory 205776 kb
Host smart-d0e603b3-2bab-4bf6-a8c3-c7ad3bf62955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949028692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1949028692
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1926520318
Short name T1025
Test name
Test status
Simulation time 12504491 ps
CPU time 0.87 seconds
Started Aug 05 04:28:56 PM PDT 24
Finished Aug 05 04:28:57 PM PDT 24
Peak memory 205772 kb
Host smart-731fe7b5-d9a9-49b7-81cf-99b8f0b8dc42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926520318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1926520318
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3136294140
Short name T956
Test name
Test status
Simulation time 129363302 ps
CPU time 0.7 seconds
Started Aug 05 04:28:47 PM PDT 24
Finished Aug 05 04:28:47 PM PDT 24
Peak memory 205776 kb
Host smart-b33c79d3-9541-423c-a9c5-a114bc54dd5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136294140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3136294140
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.873860729
Short name T1016
Test name
Test status
Simulation time 13583594 ps
CPU time 0.9 seconds
Started Aug 05 04:29:05 PM PDT 24
Finished Aug 05 04:29:06 PM PDT 24
Peak memory 205808 kb
Host smart-71d4d1d1-a35b-49fa-b082-69eb27dfe55f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873860729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.873860729
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4246481616
Short name T979
Test name
Test status
Simulation time 11156313 ps
CPU time 0.71 seconds
Started Aug 05 04:29:09 PM PDT 24
Finished Aug 05 04:29:10 PM PDT 24
Peak memory 205744 kb
Host smart-1a0de920-844f-40fd-996a-cf58049295e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246481616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4246481616
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3009197043
Short name T931
Test name
Test status
Simulation time 45635638 ps
CPU time 1.62 seconds
Started Aug 05 04:28:31 PM PDT 24
Finished Aug 05 04:28:33 PM PDT 24
Peak memory 214300 kb
Host smart-071f4888-a388-46c7-a91c-d1db7ceacf58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009197043 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3009197043
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2878523736
Short name T1040
Test name
Test status
Simulation time 500569899 ps
CPU time 1.28 seconds
Started Aug 05 04:28:36 PM PDT 24
Finished Aug 05 04:28:37 PM PDT 24
Peak memory 206020 kb
Host smart-f2262a66-509b-4ce8-bb99-3394d7840086
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878523736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2878523736
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3796153135
Short name T1034
Test name
Test status
Simulation time 53978375 ps
CPU time 0.71 seconds
Started Aug 05 04:28:33 PM PDT 24
Finished Aug 05 04:28:33 PM PDT 24
Peak memory 205836 kb
Host smart-4639a0f6-3ad7-43a5-b4ac-b57bb2d4420b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796153135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3796153135
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.432147822
Short name T137
Test name
Test status
Simulation time 55520706 ps
CPU time 1.58 seconds
Started Aug 05 04:28:26 PM PDT 24
Finished Aug 05 04:28:27 PM PDT 24
Peak memory 205964 kb
Host smart-e997a8b6-c90f-47e6-a165-fc3382facc40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432147822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.432147822
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2715129149
Short name T965
Test name
Test status
Simulation time 281285533 ps
CPU time 2.91 seconds
Started Aug 05 04:28:24 PM PDT 24
Finished Aug 05 04:28:27 PM PDT 24
Peak memory 214528 kb
Host smart-f5190533-f4fe-4f66-a9e5-c620ac0710bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715129149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2715129149
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2022919562
Short name T980
Test name
Test status
Simulation time 185023489 ps
CPU time 3.59 seconds
Started Aug 05 04:28:23 PM PDT 24
Finished Aug 05 04:28:32 PM PDT 24
Peak memory 214332 kb
Host smart-cd0187a3-78bd-474c-8506-f7a87b034bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022919562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2022919562
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.4203058293
Short name T920
Test name
Test status
Simulation time 108707399 ps
CPU time 2.95 seconds
Started Aug 05 04:28:17 PM PDT 24
Finished Aug 05 04:28:20 PM PDT 24
Peak memory 215344 kb
Host smart-a903ad35-69e5-47a2-8b78-d2c40f20e077
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203058293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.4203058293
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2949943047
Short name T984
Test name
Test status
Simulation time 77528239 ps
CPU time 1.94 seconds
Started Aug 05 04:28:15 PM PDT 24
Finished Aug 05 04:28:17 PM PDT 24
Peak memory 213876 kb
Host smart-3250315b-e8ca-4739-9f35-e3fbcabb5846
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949943047 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2949943047
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4130179999
Short name T993
Test name
Test status
Simulation time 24769967 ps
CPU time 1.18 seconds
Started Aug 05 04:28:10 PM PDT 24
Finished Aug 05 04:28:12 PM PDT 24
Peak memory 205988 kb
Host smart-8102f97c-19cf-406e-89b1-c4985668355b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130179999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.4130179999
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3602388129
Short name T1066
Test name
Test status
Simulation time 113466037 ps
CPU time 0.78 seconds
Started Aug 05 04:28:20 PM PDT 24
Finished Aug 05 04:28:21 PM PDT 24
Peak memory 205768 kb
Host smart-a57db3c3-476b-420a-9c28-12e91cf75e3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602388129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3602388129
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.4166918353
Short name T1076
Test name
Test status
Simulation time 117538693 ps
CPU time 4.15 seconds
Started Aug 05 04:28:22 PM PDT 24
Finished Aug 05 04:28:27 PM PDT 24
Peak memory 205988 kb
Host smart-23e15ab8-cf84-4d2c-a4ad-5c8e823b4d49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166918353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.4166918353
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3125337132
Short name T1014
Test name
Test status
Simulation time 72400608 ps
CPU time 2.36 seconds
Started Aug 05 04:28:11 PM PDT 24
Finished Aug 05 04:28:13 PM PDT 24
Peak memory 214560 kb
Host smart-11e819d4-6bba-4aad-8907-920de2a853b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125337132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3125337132
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2892555554
Short name T117
Test name
Test status
Simulation time 150094348 ps
CPU time 4 seconds
Started Aug 05 04:28:16 PM PDT 24
Finished Aug 05 04:28:20 PM PDT 24
Peak memory 220552 kb
Host smart-28824c56-9d91-4bfd-8d7a-bd86e3ad2aca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892555554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2892555554
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3571622645
Short name T990
Test name
Test status
Simulation time 45158509 ps
CPU time 2.73 seconds
Started Aug 05 04:28:20 PM PDT 24
Finished Aug 05 04:28:23 PM PDT 24
Peak memory 216928 kb
Host smart-e9e7e00c-a102-428c-8932-806b64c4a2c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571622645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3571622645
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.530255588
Short name T991
Test name
Test status
Simulation time 635186023 ps
CPU time 3.53 seconds
Started Aug 05 04:28:21 PM PDT 24
Finished Aug 05 04:28:24 PM PDT 24
Peak memory 214112 kb
Host smart-b387e52c-c1e4-4bfb-a6e8-be02f4b3cea5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530255588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
530255588
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2408142090
Short name T922
Test name
Test status
Simulation time 23372053 ps
CPU time 1.08 seconds
Started Aug 05 04:28:15 PM PDT 24
Finished Aug 05 04:28:17 PM PDT 24
Peak memory 204760 kb
Host smart-7aab2b27-70a3-4548-93ea-d0d2e308acfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408142090 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2408142090
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2646091693
Short name T948
Test name
Test status
Simulation time 9822546 ps
CPU time 0.93 seconds
Started Aug 05 04:28:29 PM PDT 24
Finished Aug 05 04:28:30 PM PDT 24
Peak memory 206080 kb
Host smart-e0f53842-63c0-4a6b-b3e3-4c24fb3d52ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646091693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2646091693
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2190742580
Short name T1078
Test name
Test status
Simulation time 7588781 ps
CPU time 0.71 seconds
Started Aug 05 04:28:21 PM PDT 24
Finished Aug 05 04:28:22 PM PDT 24
Peak memory 205720 kb
Host smart-ed15d2b6-89eb-4501-b8db-56bc895f7279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190742580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2190742580
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3990386527
Short name T133
Test name
Test status
Simulation time 89680868 ps
CPU time 3.25 seconds
Started Aug 05 04:28:36 PM PDT 24
Finished Aug 05 04:28:40 PM PDT 24
Peak memory 205988 kb
Host smart-91f5d53e-dbb0-450a-acd7-93222b471ba4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990386527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3990386527
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2072790336
Short name T1077
Test name
Test status
Simulation time 1654877339 ps
CPU time 10.43 seconds
Started Aug 05 04:28:20 PM PDT 24
Finished Aug 05 04:28:30 PM PDT 24
Peak memory 220644 kb
Host smart-5c854b42-6f18-4467-b1c1-3335a2bcd0ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072790336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2072790336
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4110578230
Short name T937
Test name
Test status
Simulation time 278468846 ps
CPU time 3.3 seconds
Started Aug 05 04:28:21 PM PDT 24
Finished Aug 05 04:28:25 PM PDT 24
Peak memory 214340 kb
Host smart-40e6749e-17ee-4370-92c2-b7f573e7d1cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110578230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4110578230
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2145378048
Short name T986
Test name
Test status
Simulation time 280197713 ps
CPU time 1.48 seconds
Started Aug 05 04:28:30 PM PDT 24
Finished Aug 05 04:28:31 PM PDT 24
Peak memory 214240 kb
Host smart-47d2778c-4b83-4902-aaa6-faf3726dcb14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145378048 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2145378048
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3116404137
Short name T135
Test name
Test status
Simulation time 24650057 ps
CPU time 1.13 seconds
Started Aug 05 04:28:38 PM PDT 24
Finished Aug 05 04:28:40 PM PDT 24
Peak memory 205996 kb
Host smart-4d7ffe1e-84e3-4351-98e8-11070bd8c005
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116404137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3116404137
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2246670290
Short name T946
Test name
Test status
Simulation time 39231227 ps
CPU time 0.68 seconds
Started Aug 05 04:28:38 PM PDT 24
Finished Aug 05 04:28:38 PM PDT 24
Peak memory 205768 kb
Host smart-c103aefa-9cd8-4982-a6af-d740238d146b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246670290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2246670290
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2312385994
Short name T968
Test name
Test status
Simulation time 162454514 ps
CPU time 3.23 seconds
Started Aug 05 04:28:47 PM PDT 24
Finished Aug 05 04:28:51 PM PDT 24
Peak memory 206060 kb
Host smart-40426289-3931-43e3-a421-1fb09f8760ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312385994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2312385994
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3125222886
Short name T1080
Test name
Test status
Simulation time 398099124 ps
CPU time 3.84 seconds
Started Aug 05 04:28:37 PM PDT 24
Finished Aug 05 04:28:41 PM PDT 24
Peak memory 214524 kb
Host smart-3e6d8d79-e321-4fa8-bbde-2c6353f95697
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125222886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3125222886
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3567478383
Short name T1010
Test name
Test status
Simulation time 165552919 ps
CPU time 6.3 seconds
Started Aug 05 04:28:40 PM PDT 24
Finished Aug 05 04:28:46 PM PDT 24
Peak memory 214436 kb
Host smart-7124c993-3c0c-4b5d-b465-d0eaabe9a9a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567478383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3567478383
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2198364087
Short name T1037
Test name
Test status
Simulation time 55113994 ps
CPU time 1.72 seconds
Started Aug 05 04:28:41 PM PDT 24
Finished Aug 05 04:28:43 PM PDT 24
Peak memory 214280 kb
Host smart-88619289-d2ce-4e1a-ac5f-0153fee1d7b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198364087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2198364087
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.52481483
Short name T162
Test name
Test status
Simulation time 397762846 ps
CPU time 5.17 seconds
Started Aug 05 04:28:21 PM PDT 24
Finished Aug 05 04:28:27 PM PDT 24
Peak memory 215588 kb
Host smart-fb34dcb1-f14b-4bce-927d-d278e4f57ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52481483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.52481483
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.183382076
Short name T1064
Test name
Test status
Simulation time 540994521 ps
CPU time 2.28 seconds
Started Aug 05 04:28:21 PM PDT 24
Finished Aug 05 04:28:23 PM PDT 24
Peak memory 205984 kb
Host smart-4b99cdd9-8c5a-4734-80d2-cadb88448374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183382076 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.183382076
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1483849223
Short name T963
Test name
Test status
Simulation time 17314716 ps
CPU time 1.11 seconds
Started Aug 05 04:28:21 PM PDT 24
Finished Aug 05 04:28:22 PM PDT 24
Peak memory 206068 kb
Host smart-195be93e-d764-4d6a-b0ae-83e187ae8582
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483849223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1483849223
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3705186103
Short name T935
Test name
Test status
Simulation time 31841953 ps
CPU time 0.8 seconds
Started Aug 05 04:28:26 PM PDT 24
Finished Aug 05 04:28:26 PM PDT 24
Peak memory 205804 kb
Host smart-77ccab7f-41bb-4be2-aa98-bf11bdba2517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705186103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3705186103
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2779005525
Short name T1060
Test name
Test status
Simulation time 436099661 ps
CPU time 3.87 seconds
Started Aug 05 04:28:34 PM PDT 24
Finished Aug 05 04:28:38 PM PDT 24
Peak memory 205964 kb
Host smart-d7677337-08c9-40a9-bb70-992d0fe802b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779005525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2779005525
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4204843975
Short name T1035
Test name
Test status
Simulation time 186269520 ps
CPU time 4.72 seconds
Started Aug 05 04:28:16 PM PDT 24
Finished Aug 05 04:28:21 PM PDT 24
Peak memory 214544 kb
Host smart-def59b92-7ba4-458c-aba6-393a8f92ae97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204843975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4204843975
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.636294195
Short name T978
Test name
Test status
Simulation time 1512262454 ps
CPU time 5.26 seconds
Started Aug 05 04:28:39 PM PDT 24
Finished Aug 05 04:28:45 PM PDT 24
Peak memory 214324 kb
Host smart-db4d7b1a-9aab-4f07-9bd9-cd6fc15a5e88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636294195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.636294195
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1654403595
Short name T962
Test name
Test status
Simulation time 55174274 ps
CPU time 3.74 seconds
Started Aug 05 04:28:24 PM PDT 24
Finished Aug 05 04:28:28 PM PDT 24
Peak memory 214328 kb
Host smart-a99f8abe-8a38-4044-ba39-fc4d67247655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654403595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1654403595
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1450518750
Short name T392
Test name
Test status
Simulation time 146811253 ps
CPU time 4.44 seconds
Started Aug 05 04:28:24 PM PDT 24
Finished Aug 05 04:28:29 PM PDT 24
Peak memory 214200 kb
Host smart-73affda1-0b1a-405d-9bc8-c08d7f0d3729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450518750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1450518750
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1469882823
Short name T809
Test name
Test status
Simulation time 42720275 ps
CPU time 0.84 seconds
Started Aug 05 04:32:48 PM PDT 24
Finished Aug 05 04:32:49 PM PDT 24
Peak memory 205772 kb
Host smart-31e1054b-6db8-446f-bbf8-5797fc70b2bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469882823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1469882823
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1363068240
Short name T661
Test name
Test status
Simulation time 55153016 ps
CPU time 2.42 seconds
Started Aug 05 04:32:34 PM PDT 24
Finished Aug 05 04:32:36 PM PDT 24
Peak memory 222452 kb
Host smart-298f4fd3-2397-475c-ab45-cf8b81160fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363068240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1363068240
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2609064113
Short name T805
Test name
Test status
Simulation time 287057621 ps
CPU time 3.79 seconds
Started Aug 05 04:32:58 PM PDT 24
Finished Aug 05 04:33:02 PM PDT 24
Peak memory 219824 kb
Host smart-c5ff403b-64ba-4bf9-8024-a7fe902865fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609064113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2609064113
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1995924765
Short name T624
Test name
Test status
Simulation time 542133681 ps
CPU time 4.17 seconds
Started Aug 05 04:32:44 PM PDT 24
Finished Aug 05 04:32:48 PM PDT 24
Peak memory 211620 kb
Host smart-887c1782-1115-422b-8166-37288cf03c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995924765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1995924765
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.4251966041
Short name T238
Test name
Test status
Simulation time 510949265 ps
CPU time 3.76 seconds
Started Aug 05 04:32:41 PM PDT 24
Finished Aug 05 04:32:45 PM PDT 24
Peak memory 209944 kb
Host smart-ae714eb9-e25a-4576-9713-3c07bdd8d9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251966041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.4251966041
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.77419506
Short name T528
Test name
Test status
Simulation time 489749301 ps
CPU time 9.91 seconds
Started Aug 05 04:32:38 PM PDT 24
Finished Aug 05 04:32:48 PM PDT 24
Peak memory 214148 kb
Host smart-5cba9360-0262-4659-b0f8-2f43ec6f4e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77419506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.77419506
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.157502958
Short name T696
Test name
Test status
Simulation time 4546139289 ps
CPU time 28.3 seconds
Started Aug 05 04:32:53 PM PDT 24
Finished Aug 05 04:33:22 PM PDT 24
Peak memory 208404 kb
Host smart-1a1512bc-2b5a-4414-aea8-5bdd181fccc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157502958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.157502958
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3067391007
Short name T459
Test name
Test status
Simulation time 83819598 ps
CPU time 2.45 seconds
Started Aug 05 04:32:45 PM PDT 24
Finished Aug 05 04:32:47 PM PDT 24
Peak memory 206732 kb
Host smart-2c79d53f-2632-4cdd-8e49-e3ccbd6cd1b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067391007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3067391007
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.4046184761
Short name T270
Test name
Test status
Simulation time 1514676068 ps
CPU time 7.19 seconds
Started Aug 05 04:32:44 PM PDT 24
Finished Aug 05 04:32:51 PM PDT 24
Peak memory 208652 kb
Host smart-692cbad0-c718-42a0-8918-8e0a93951120
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046184761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.4046184761
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3503035587
Short name T546
Test name
Test status
Simulation time 140668681 ps
CPU time 3.82 seconds
Started Aug 05 04:32:43 PM PDT 24
Finished Aug 05 04:32:47 PM PDT 24
Peak memory 208332 kb
Host smart-33ef59bf-a970-4230-9511-24ddf228e36c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503035587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3503035587
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.4213747209
Short name T475
Test name
Test status
Simulation time 275231888 ps
CPU time 4.09 seconds
Started Aug 05 04:32:48 PM PDT 24
Finished Aug 05 04:32:52 PM PDT 24
Peak memory 209552 kb
Host smart-c0544a49-7a2e-4cda-aeff-6484ab5ce856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213747209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4213747209
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2905062955
Short name T858
Test name
Test status
Simulation time 1027083744 ps
CPU time 4.59 seconds
Started Aug 05 04:32:40 PM PDT 24
Finished Aug 05 04:32:45 PM PDT 24
Peak memory 207636 kb
Host smart-272d61df-defe-4f42-aa16-150718edb618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905062955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2905062955
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1606827634
Short name T183
Test name
Test status
Simulation time 3501481918 ps
CPU time 22.34 seconds
Started Aug 05 04:32:45 PM PDT 24
Finished Aug 05 04:33:08 PM PDT 24
Peak memory 222408 kb
Host smart-812da4b0-6caa-4f04-a5c7-acdd17ade30c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606827634 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1606827634
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3266646830
Short name T324
Test name
Test status
Simulation time 692916416 ps
CPU time 8.23 seconds
Started Aug 05 04:32:45 PM PDT 24
Finished Aug 05 04:32:54 PM PDT 24
Peak memory 222252 kb
Host smart-7009e8dc-bc99-4d77-80e1-0a1aebc4321a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266646830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3266646830
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.866147856
Short name T794
Test name
Test status
Simulation time 138084976 ps
CPU time 2.23 seconds
Started Aug 05 04:33:00 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 209600 kb
Host smart-77ad9eee-7ab9-4267-9e9f-ce3e44308140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866147856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.866147856
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.256536008
Short name T509
Test name
Test status
Simulation time 39975235 ps
CPU time 0.85 seconds
Started Aug 05 04:32:44 PM PDT 24
Finished Aug 05 04:32:45 PM PDT 24
Peak memory 205820 kb
Host smart-53b8d53f-55cf-4df7-9a0d-611dc3ce944a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256536008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.256536008
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2030824033
Short name T427
Test name
Test status
Simulation time 33021556 ps
CPU time 2.44 seconds
Started Aug 05 04:32:53 PM PDT 24
Finished Aug 05 04:32:56 PM PDT 24
Peak memory 214168 kb
Host smart-d69a5aa4-fc54-48a4-a13c-5f97aea01e57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030824033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2030824033
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3838994198
Short name T745
Test name
Test status
Simulation time 195142620 ps
CPU time 3.54 seconds
Started Aug 05 04:32:44 PM PDT 24
Finished Aug 05 04:32:48 PM PDT 24
Peak memory 214172 kb
Host smart-54c1a83e-b2dd-4d87-b0eb-ccfb0a07a940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838994198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3838994198
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1934795940
Short name T176
Test name
Test status
Simulation time 106092688 ps
CPU time 4.48 seconds
Started Aug 05 04:32:45 PM PDT 24
Finished Aug 05 04:32:50 PM PDT 24
Peak memory 214208 kb
Host smart-013c4726-e7f9-4093-aee0-1367b4bc7617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934795940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1934795940
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1134548960
Short name T197
Test name
Test status
Simulation time 3031595182 ps
CPU time 12.9 seconds
Started Aug 05 04:32:51 PM PDT 24
Finished Aug 05 04:33:04 PM PDT 24
Peak memory 214204 kb
Host smart-377f7c17-1b65-4c47-a049-5829dc808f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134548960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1134548960
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2478422827
Short name T256
Test name
Test status
Simulation time 554696204 ps
CPU time 6.5 seconds
Started Aug 05 04:32:58 PM PDT 24
Finished Aug 05 04:33:04 PM PDT 24
Peak memory 207984 kb
Host smart-764acb76-e6a0-4cb5-a109-df801fdf4a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478422827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2478422827
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.91984432
Short name T583
Test name
Test status
Simulation time 178591330 ps
CPU time 6.01 seconds
Started Aug 05 04:32:57 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 208268 kb
Host smart-74c40ef3-5e2f-41f7-9cf1-041395ad023f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91984432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.91984432
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1556844578
Short name T290
Test name
Test status
Simulation time 151903107 ps
CPU time 2.74 seconds
Started Aug 05 04:32:43 PM PDT 24
Finished Aug 05 04:32:46 PM PDT 24
Peak memory 208640 kb
Host smart-0e62ae86-5cdb-421b-b8f8-a8afb4286c19
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556844578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1556844578
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.997291239
Short name T278
Test name
Test status
Simulation time 6614454616 ps
CPU time 42.71 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:42 PM PDT 24
Peak memory 208348 kb
Host smart-fdf10e38-0f93-4fc8-9581-39ccba1183ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997291239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.997291239
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4264449999
Short name T608
Test name
Test status
Simulation time 4389779223 ps
CPU time 22.01 seconds
Started Aug 05 04:32:40 PM PDT 24
Finished Aug 05 04:33:02 PM PDT 24
Peak memory 209128 kb
Host smart-1286bfd9-8f25-4f2d-83ab-af4a47b41b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264449999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4264449999
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2980988641
Short name T403
Test name
Test status
Simulation time 100214675 ps
CPU time 2.47 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:32:58 PM PDT 24
Peak memory 206704 kb
Host smart-98cc358b-479d-4aa9-84db-21884cf90c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980988641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2980988641
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3656123079
Short name T775
Test name
Test status
Simulation time 454360626 ps
CPU time 17.48 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:17 PM PDT 24
Peak memory 220552 kb
Host smart-c3dec566-5538-4e43-9f21-243f4832709e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656123079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3656123079
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.4192577071
Short name T899
Test name
Test status
Simulation time 99616444 ps
CPU time 4.37 seconds
Started Aug 05 04:32:52 PM PDT 24
Finished Aug 05 04:32:56 PM PDT 24
Peak memory 218020 kb
Host smart-5c99b812-8e00-4f44-ac00-a5d7ad1df13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192577071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4192577071
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1191406516
Short name T670
Test name
Test status
Simulation time 48053457 ps
CPU time 0.79 seconds
Started Aug 05 04:33:12 PM PDT 24
Finished Aug 05 04:33:13 PM PDT 24
Peak memory 205816 kb
Host smart-5f2e531d-064a-4e4a-87bb-18389ea70863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191406516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1191406516
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.11093941
Short name T777
Test name
Test status
Simulation time 615642020 ps
CPU time 2.94 seconds
Started Aug 05 04:33:06 PM PDT 24
Finished Aug 05 04:33:09 PM PDT 24
Peak memory 210272 kb
Host smart-e35a1237-eb00-478b-b102-f7f5fef4c03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11093941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.11093941
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1799904250
Short name T694
Test name
Test status
Simulation time 102798932 ps
CPU time 1.57 seconds
Started Aug 05 04:33:21 PM PDT 24
Finished Aug 05 04:33:23 PM PDT 24
Peak memory 209460 kb
Host smart-0d9e7215-fd0f-4370-819a-5568fd89f38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799904250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1799904250
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3395681684
Short name T101
Test name
Test status
Simulation time 1226980916 ps
CPU time 12.36 seconds
Started Aug 05 04:33:06 PM PDT 24
Finished Aug 05 04:33:19 PM PDT 24
Peak memory 214160 kb
Host smart-ef26f88d-918e-4c40-a5ed-e0dfc7867780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395681684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3395681684
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1563988223
Short name T241
Test name
Test status
Simulation time 85597356 ps
CPU time 3.45 seconds
Started Aug 05 04:33:09 PM PDT 24
Finished Aug 05 04:33:12 PM PDT 24
Peak memory 221388 kb
Host smart-0f19f956-3f02-4ea1-b7df-8f18c6754a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563988223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1563988223
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.140392051
Short name T535
Test name
Test status
Simulation time 141339283 ps
CPU time 2.29 seconds
Started Aug 05 04:33:24 PM PDT 24
Finished Aug 05 04:33:26 PM PDT 24
Peak memory 214200 kb
Host smart-4f015b58-e58a-48bb-bede-a7dd0c5b64a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140392051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.140392051
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1936514478
Short name T316
Test name
Test status
Simulation time 33344142 ps
CPU time 2.52 seconds
Started Aug 05 04:33:19 PM PDT 24
Finished Aug 05 04:33:22 PM PDT 24
Peak memory 207436 kb
Host smart-be0712f6-dae8-4543-b0f0-5cc0998f41e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936514478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1936514478
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3281294078
Short name T276
Test name
Test status
Simulation time 66158745 ps
CPU time 2.52 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:02 PM PDT 24
Peak memory 206828 kb
Host smart-fb6628bd-8519-439d-a315-f3a422314efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281294078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3281294078
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2419629279
Short name T655
Test name
Test status
Simulation time 80789077 ps
CPU time 2.44 seconds
Started Aug 05 04:32:56 PM PDT 24
Finished Aug 05 04:32:58 PM PDT 24
Peak memory 206676 kb
Host smart-bc1179f6-ae6f-4de2-85e7-e8ca1ec4449c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419629279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2419629279
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3587131988
Short name T479
Test name
Test status
Simulation time 149615922 ps
CPU time 3.88 seconds
Started Aug 05 04:33:11 PM PDT 24
Finished Aug 05 04:33:15 PM PDT 24
Peak memory 208008 kb
Host smart-7fde9a9c-1904-4dcf-9afb-00c0c369bc7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587131988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3587131988
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1326778763
Short name T188
Test name
Test status
Simulation time 940556311 ps
CPU time 7.31 seconds
Started Aug 05 04:33:00 PM PDT 24
Finished Aug 05 04:33:08 PM PDT 24
Peak memory 208724 kb
Host smart-3d90cb19-cd3c-41e1-a679-3ed8436e0140
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326778763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1326778763
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.270177122
Short name T838
Test name
Test status
Simulation time 188241779 ps
CPU time 3.81 seconds
Started Aug 05 04:33:04 PM PDT 24
Finished Aug 05 04:33:08 PM PDT 24
Peak memory 208888 kb
Host smart-9406840f-7588-41e8-bc09-f1bb7db5479f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270177122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.270177122
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3339626488
Short name T402
Test name
Test status
Simulation time 280157694 ps
CPU time 3.3 seconds
Started Aug 05 04:33:16 PM PDT 24
Finished Aug 05 04:33:20 PM PDT 24
Peak memory 208440 kb
Host smart-8cb66a85-590a-423f-8909-48af724222ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339626488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3339626488
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3203362937
Short name T272
Test name
Test status
Simulation time 2094473097 ps
CPU time 56.41 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 218692 kb
Host smart-712c6570-0af6-4273-8210-2fd3f72e7cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203362937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3203362937
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.539630821
Short name T393
Test name
Test status
Simulation time 141095929 ps
CPU time 3.36 seconds
Started Aug 05 04:33:21 PM PDT 24
Finished Aug 05 04:33:24 PM PDT 24
Peak memory 209628 kb
Host smart-5e4c3ec4-70d1-47c5-8b09-cad2b776d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539630821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.539630821
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2682720519
Short name T516
Test name
Test status
Simulation time 29478778 ps
CPU time 0.9 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:00 PM PDT 24
Peak memory 205948 kb
Host smart-2b926574-e995-4e71-b9cb-2d93c93caf15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682720519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2682720519
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1969342755
Short name T337
Test name
Test status
Simulation time 256232156 ps
CPU time 4.35 seconds
Started Aug 05 04:33:17 PM PDT 24
Finished Aug 05 04:33:22 PM PDT 24
Peak memory 214924 kb
Host smart-ebf37a02-0e0d-418e-ab24-5a42532af25c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969342755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1969342755
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.533673406
Short name T491
Test name
Test status
Simulation time 927086436 ps
CPU time 7.66 seconds
Started Aug 05 04:33:17 PM PDT 24
Finished Aug 05 04:33:25 PM PDT 24
Peak memory 218036 kb
Host smart-dde18af9-23d7-4f23-9c2e-e70ce50807dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533673406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.533673406
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3867142878
Short name T864
Test name
Test status
Simulation time 73240996 ps
CPU time 2.66 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:04 PM PDT 24
Peak memory 217880 kb
Host smart-55997787-5529-40d0-a9f5-3694c875129b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867142878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3867142878
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.353092793
Short name T456
Test name
Test status
Simulation time 45354319 ps
CPU time 2.94 seconds
Started Aug 05 04:33:03 PM PDT 24
Finished Aug 05 04:33:06 PM PDT 24
Peak memory 221800 kb
Host smart-7d90a624-9536-4576-9914-1095b53afa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353092793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.353092793
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2014847285
Short name T418
Test name
Test status
Simulation time 726456234 ps
CPU time 3.69 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:05 PM PDT 24
Peak memory 214184 kb
Host smart-b2edde1f-5803-4d96-9e06-a6319c5fc548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014847285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2014847285
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1434710635
Short name T377
Test name
Test status
Simulation time 178574076 ps
CPU time 3.17 seconds
Started Aug 05 04:33:13 PM PDT 24
Finished Aug 05 04:33:17 PM PDT 24
Peak memory 214152 kb
Host smart-54275027-35ca-48b9-aaac-b150aa7cb47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434710635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1434710635
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3510970266
Short name T789
Test name
Test status
Simulation time 813586345 ps
CPU time 17.37 seconds
Started Aug 05 04:33:19 PM PDT 24
Finished Aug 05 04:33:36 PM PDT 24
Peak memory 208836 kb
Host smart-cf2bd280-cac2-4ba0-ab55-222111e0f4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510970266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3510970266
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1669847068
Short name T342
Test name
Test status
Simulation time 774267834 ps
CPU time 8 seconds
Started Aug 05 04:33:20 PM PDT 24
Finished Aug 05 04:33:28 PM PDT 24
Peak memory 208880 kb
Host smart-c834fbd6-72e0-4d64-b3f6-3241a462d223
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669847068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1669847068
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3054731260
Short name T589
Test name
Test status
Simulation time 216418415 ps
CPU time 3.48 seconds
Started Aug 05 04:33:11 PM PDT 24
Finished Aug 05 04:33:15 PM PDT 24
Peak memory 208428 kb
Host smart-89a6f67b-0c31-495c-bec6-e2a7ff6b7132
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054731260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3054731260
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3412994394
Short name T866
Test name
Test status
Simulation time 149006013 ps
CPU time 2.84 seconds
Started Aug 05 04:33:04 PM PDT 24
Finished Aug 05 04:33:07 PM PDT 24
Peak memory 208820 kb
Host smart-f16558ea-45c5-4ec0-8f6c-376551b9e236
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412994394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3412994394
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.198042794
Short name T771
Test name
Test status
Simulation time 32748226 ps
CPU time 1.91 seconds
Started Aug 05 04:33:19 PM PDT 24
Finished Aug 05 04:33:21 PM PDT 24
Peak memory 215340 kb
Host smart-0f7272f4-2dd1-45aa-993a-553faba90979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198042794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.198042794
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3192905707
Short name T433
Test name
Test status
Simulation time 1143976784 ps
CPU time 8.76 seconds
Started Aug 05 04:33:02 PM PDT 24
Finished Aug 05 04:33:11 PM PDT 24
Peak memory 207680 kb
Host smart-6753a8a3-4313-49e7-8ca9-98eca4ebe8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192905707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3192905707
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1838834071
Short name T55
Test name
Test status
Simulation time 1997400441 ps
CPU time 26.55 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:33:22 PM PDT 24
Peak memory 222264 kb
Host smart-35622ffc-04b5-4b23-8edc-f31e3f4b0fb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838834071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1838834071
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.170653036
Short name T644
Test name
Test status
Simulation time 121094935 ps
CPU time 2.45 seconds
Started Aug 05 04:33:08 PM PDT 24
Finished Aug 05 04:33:11 PM PDT 24
Peak memory 207720 kb
Host smart-b3854733-601e-4404-ad68-7cf8007e04e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170653036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.170653036
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3902085636
Short name T481
Test name
Test status
Simulation time 30971137 ps
CPU time 1.98 seconds
Started Aug 05 04:33:09 PM PDT 24
Finished Aug 05 04:33:12 PM PDT 24
Peak memory 209964 kb
Host smart-f5431ed7-c671-4de8-9f55-3e092b12d4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902085636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3902085636
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2964051766
Short name T442
Test name
Test status
Simulation time 67904299 ps
CPU time 0.79 seconds
Started Aug 05 04:33:13 PM PDT 24
Finished Aug 05 04:33:14 PM PDT 24
Peak memory 205832 kb
Host smart-c6e8dd0a-ad61-484d-9bb5-22e7efbbe0dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964051766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2964051766
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.426298765
Short name T640
Test name
Test status
Simulation time 221477357 ps
CPU time 2.69 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:34 PM PDT 24
Peak memory 209468 kb
Host smart-1ee04f74-2139-4584-88ab-652f593bef64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426298765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.426298765
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.827111409
Short name T264
Test name
Test status
Simulation time 26182806 ps
CPU time 1.91 seconds
Started Aug 05 04:33:05 PM PDT 24
Finished Aug 05 04:33:07 PM PDT 24
Peak memory 214260 kb
Host smart-e71b430d-c473-4c61-885d-78039e9634d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827111409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.827111409
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2447058960
Short name T839
Test name
Test status
Simulation time 47089742 ps
CPU time 2.34 seconds
Started Aug 05 04:33:00 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 222356 kb
Host smart-f418243a-664f-4d7f-ace2-b6571202fa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447058960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2447058960
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.283310959
Short name T464
Test name
Test status
Simulation time 2106733423 ps
CPU time 10.66 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:12 PM PDT 24
Peak memory 214164 kb
Host smart-e77ff4f6-4a26-4f24-8051-301073b63cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283310959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.283310959
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3555165226
Short name T888
Test name
Test status
Simulation time 154051204 ps
CPU time 3.07 seconds
Started Aug 05 04:33:02 PM PDT 24
Finished Aug 05 04:33:05 PM PDT 24
Peak memory 206576 kb
Host smart-71260b55-4ee1-4022-b83f-d4e605c7dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555165226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3555165226
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1934680773
Short name T756
Test name
Test status
Simulation time 100540662 ps
CPU time 3.3 seconds
Started Aug 05 04:33:03 PM PDT 24
Finished Aug 05 04:33:06 PM PDT 24
Peak memory 208500 kb
Host smart-c1670425-1715-4449-8023-68a9839626ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934680773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1934680773
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2700636951
Short name T447
Test name
Test status
Simulation time 900621640 ps
CPU time 3.01 seconds
Started Aug 05 04:33:09 PM PDT 24
Finished Aug 05 04:33:12 PM PDT 24
Peak memory 208736 kb
Host smart-4ceb4221-d453-4ac5-b046-3711f7e366f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700636951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2700636951
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3802028181
Short name T443
Test name
Test status
Simulation time 287874705 ps
CPU time 4.09 seconds
Started Aug 05 04:33:07 PM PDT 24
Finished Aug 05 04:33:11 PM PDT 24
Peak memory 208000 kb
Host smart-58310b28-d7b0-4c60-ba92-5f95b556f61c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802028181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3802028181
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3751933837
Short name T531
Test name
Test status
Simulation time 77183451 ps
CPU time 3.51 seconds
Started Aug 05 04:33:19 PM PDT 24
Finished Aug 05 04:33:23 PM PDT 24
Peak memory 209136 kb
Host smart-8c674da1-c9da-4d86-96a9-77f64e14a98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751933837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3751933837
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3259148715
Short name T448
Test name
Test status
Simulation time 34213841 ps
CPU time 2.22 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 206768 kb
Host smart-c8fdcbe5-df87-4294-93ef-5648874e7b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259148715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3259148715
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.313145002
Short name T665
Test name
Test status
Simulation time 457316253 ps
CPU time 5.79 seconds
Started Aug 05 04:33:14 PM PDT 24
Finished Aug 05 04:33:20 PM PDT 24
Peak memory 221812 kb
Host smart-1b8663e9-23e4-4cfc-ad37-408a0703447b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313145002 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.313145002
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2647933433
Short name T614
Test name
Test status
Simulation time 154331407 ps
CPU time 5.98 seconds
Started Aug 05 04:33:16 PM PDT 24
Finished Aug 05 04:33:22 PM PDT 24
Peak memory 222304 kb
Host smart-60dba05e-6198-401a-98f7-a61430aa251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647933433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2647933433
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3151442440
Short name T586
Test name
Test status
Simulation time 63988976 ps
CPU time 2.3 seconds
Started Aug 05 04:33:21 PM PDT 24
Finished Aug 05 04:33:23 PM PDT 24
Peak memory 209880 kb
Host smart-4d86a4c8-247c-4615-b514-bed0dac954e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151442440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3151442440
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2669651681
Short name T563
Test name
Test status
Simulation time 13953789 ps
CPU time 0.92 seconds
Started Aug 05 04:33:15 PM PDT 24
Finished Aug 05 04:33:16 PM PDT 24
Peak memory 205936 kb
Host smart-a225f867-522e-4953-9931-19aa97631217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669651681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2669651681
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2820212980
Short name T768
Test name
Test status
Simulation time 470395956 ps
CPU time 4.42 seconds
Started Aug 05 04:33:33 PM PDT 24
Finished Aug 05 04:33:38 PM PDT 24
Peak memory 207824 kb
Host smart-5562f79a-d6df-4e12-b282-271ea0f7d960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820212980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2820212980
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3916811488
Short name T690
Test name
Test status
Simulation time 268695963 ps
CPU time 3.69 seconds
Started Aug 05 04:33:07 PM PDT 24
Finished Aug 05 04:33:11 PM PDT 24
Peak memory 220148 kb
Host smart-b78779e7-f108-4e4a-9fb8-cb27c62acafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916811488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3916811488
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_random.388214549
Short name T400
Test name
Test status
Simulation time 267604185 ps
CPU time 7.08 seconds
Started Aug 05 04:33:24 PM PDT 24
Finished Aug 05 04:33:31 PM PDT 24
Peak memory 210076 kb
Host smart-57ac7757-a1f7-4ba3-95d0-9c74f5329ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388214549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.388214549
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2723904236
Short name T547
Test name
Test status
Simulation time 159341401 ps
CPU time 3.78 seconds
Started Aug 05 04:33:18 PM PDT 24
Finished Aug 05 04:33:21 PM PDT 24
Peak memory 208332 kb
Host smart-a4601cae-013c-4449-a01d-abff093092ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723904236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2723904236
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.17258572
Short name T438
Test name
Test status
Simulation time 78489949 ps
CPU time 1.81 seconds
Started Aug 05 04:33:02 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 207576 kb
Host smart-f05eb638-8209-484e-acad-8d9fe3feae9d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17258572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.17258572
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2797532028
Short name T532
Test name
Test status
Simulation time 141911321 ps
CPU time 5.8 seconds
Started Aug 05 04:33:10 PM PDT 24
Finished Aug 05 04:33:15 PM PDT 24
Peak memory 206932 kb
Host smart-1f7c57f0-dae2-45e8-922d-3b3de30e4c29
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797532028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2797532028
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2748926089
Short name T599
Test name
Test status
Simulation time 482208289 ps
CPU time 3.08 seconds
Started Aug 05 04:33:15 PM PDT 24
Finished Aug 05 04:33:18 PM PDT 24
Peak memory 206724 kb
Host smart-338777c9-331d-456e-9bad-481349ab691c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748926089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2748926089
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1739674925
Short name T454
Test name
Test status
Simulation time 230619126 ps
CPU time 2.37 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:07 PM PDT 24
Peak memory 215104 kb
Host smart-f9658042-027b-4bd1-aed7-8b12ad6676c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739674925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1739674925
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.231977764
Short name T523
Test name
Test status
Simulation time 73294669 ps
CPU time 2.12 seconds
Started Aug 05 04:33:24 PM PDT 24
Finished Aug 05 04:33:26 PM PDT 24
Peak memory 207008 kb
Host smart-3180e825-95c7-4895-b3c2-162bfebca453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231977764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.231977764
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1530724931
Short name T125
Test name
Test status
Simulation time 460195764 ps
CPU time 18.46 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:20 PM PDT 24
Peak memory 222424 kb
Host smart-7c7695e5-062f-4119-9339-572a1311ef97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530724931 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1530724931
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.840811047
Short name T571
Test name
Test status
Simulation time 748476751 ps
CPU time 6.98 seconds
Started Aug 05 04:33:20 PM PDT 24
Finished Aug 05 04:33:27 PM PDT 24
Peak memory 214176 kb
Host smart-52f9837a-d9cd-4530-9482-f3c36275f883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840811047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.840811047
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1583080703
Short name T754
Test name
Test status
Simulation time 151566379 ps
CPU time 2.36 seconds
Started Aug 05 04:33:28 PM PDT 24
Finished Aug 05 04:33:31 PM PDT 24
Peak memory 210308 kb
Host smart-4baf9834-b9b2-40fd-a0e5-72338893138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583080703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1583080703
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2663178203
Short name T127
Test name
Test status
Simulation time 50856234 ps
CPU time 3.82 seconds
Started Aug 05 04:33:27 PM PDT 24
Finished Aug 05 04:33:31 PM PDT 24
Peak memory 214492 kb
Host smart-7cdf0c07-52a5-47af-8abc-1ab1097e6658
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663178203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2663178203
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.4163230959
Short name T474
Test name
Test status
Simulation time 139649535 ps
CPU time 3.38 seconds
Started Aug 05 04:33:20 PM PDT 24
Finished Aug 05 04:33:23 PM PDT 24
Peak memory 218124 kb
Host smart-b02d8bb3-1ef4-4f18-94b1-f84bb04f7842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163230959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.4163230959
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1133194108
Short name T386
Test name
Test status
Simulation time 138155111 ps
CPU time 1.7 seconds
Started Aug 05 04:33:30 PM PDT 24
Finished Aug 05 04:33:31 PM PDT 24
Peak memory 214292 kb
Host smart-720814f8-3587-4c58-baab-e0ae67591f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133194108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1133194108
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.590099572
Short name T545
Test name
Test status
Simulation time 1872961818 ps
CPU time 3.9 seconds
Started Aug 05 04:33:37 PM PDT 24
Finished Aug 05 04:33:41 PM PDT 24
Peak memory 219756 kb
Host smart-fbd76f9f-c640-4619-bd9f-632d3caf9cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590099572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.590099572
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3237404338
Short name T684
Test name
Test status
Simulation time 7412235956 ps
CPU time 55.21 seconds
Started Aug 05 04:33:18 PM PDT 24
Finished Aug 05 04:34:14 PM PDT 24
Peak memory 214324 kb
Host smart-24ab688e-7b7c-4ee9-89b4-60e6cbcb9da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237404338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3237404338
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.388835754
Short name T731
Test name
Test status
Simulation time 78903018 ps
CPU time 3.41 seconds
Started Aug 05 04:33:17 PM PDT 24
Finished Aug 05 04:33:20 PM PDT 24
Peak memory 208604 kb
Host smart-43fad6f8-4582-4a80-a9fa-9344facb39b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388835754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.388835754
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1582157851
Short name T313
Test name
Test status
Simulation time 136220453 ps
CPU time 2.65 seconds
Started Aug 05 04:33:13 PM PDT 24
Finished Aug 05 04:33:16 PM PDT 24
Peak memory 208440 kb
Host smart-b0ca2faa-524d-42c1-9438-bb27d001b17c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582157851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1582157851
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1756295040
Short name T444
Test name
Test status
Simulation time 537188447 ps
CPU time 14.79 seconds
Started Aug 05 04:33:00 PM PDT 24
Finished Aug 05 04:33:15 PM PDT 24
Peak memory 208264 kb
Host smart-15e83565-a792-4cdb-a1e3-f82a135ca44b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756295040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1756295040
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.126462507
Short name T585
Test name
Test status
Simulation time 53440433 ps
CPU time 2.18 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:04 PM PDT 24
Peak memory 208672 kb
Host smart-8528a19e-b11d-4129-a462-21ce7bc60463
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126462507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.126462507
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1467082037
Short name T422
Test name
Test status
Simulation time 68283274 ps
CPU time 2.03 seconds
Started Aug 05 04:33:21 PM PDT 24
Finished Aug 05 04:33:23 PM PDT 24
Peak memory 209572 kb
Host smart-70093f3d-f0d8-4737-8150-a059560740d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467082037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1467082037
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3792502460
Short name T488
Test name
Test status
Simulation time 59353332 ps
CPU time 2.58 seconds
Started Aug 05 04:33:15 PM PDT 24
Finished Aug 05 04:33:18 PM PDT 24
Peak memory 208116 kb
Host smart-84239d8b-c25a-44e5-8fa3-99b6346dc37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792502460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3792502460
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.152721611
Short name T199
Test name
Test status
Simulation time 215766139 ps
CPU time 5.75 seconds
Started Aug 05 04:33:23 PM PDT 24
Finished Aug 05 04:33:29 PM PDT 24
Peak memory 220308 kb
Host smart-6c43a3b9-1a7a-4299-8c87-dec592c2b7c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152721611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.152721611
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1900835423
Short name T609
Test name
Test status
Simulation time 367120494 ps
CPU time 4.56 seconds
Started Aug 05 04:33:06 PM PDT 24
Finished Aug 05 04:33:11 PM PDT 24
Peak memory 207296 kb
Host smart-2ccdc280-ff84-4a86-b6ac-d412ebea5af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900835423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1900835423
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2874015362
Short name T781
Test name
Test status
Simulation time 175751316 ps
CPU time 2.18 seconds
Started Aug 05 04:33:11 PM PDT 24
Finished Aug 05 04:33:13 PM PDT 24
Peak memory 209880 kb
Host smart-d54189fc-556c-4e0e-ba82-4d34ca79bf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874015362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2874015362
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1082069286
Short name T504
Test name
Test status
Simulation time 52781453 ps
CPU time 0.76 seconds
Started Aug 05 04:34:03 PM PDT 24
Finished Aug 05 04:34:05 PM PDT 24
Peak memory 205044 kb
Host smart-1a888dbb-f268-4842-adc7-409b44bb30c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082069286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1082069286
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3642445584
Short name T310
Test name
Test status
Simulation time 480462228 ps
CPU time 6.45 seconds
Started Aug 05 04:33:10 PM PDT 24
Finished Aug 05 04:33:17 PM PDT 24
Peak memory 215036 kb
Host smart-2795fe05-d523-480c-838e-198ad9d454cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3642445584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3642445584
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.395693780
Short name T573
Test name
Test status
Simulation time 63866522 ps
CPU time 2.25 seconds
Started Aug 05 04:33:29 PM PDT 24
Finished Aug 05 04:33:31 PM PDT 24
Peak memory 214344 kb
Host smart-4fd2b1ca-a2be-446f-a251-ff5fc9e8a2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395693780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.395693780
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1888854473
Short name T776
Test name
Test status
Simulation time 22439842 ps
CPU time 1.88 seconds
Started Aug 05 04:33:27 PM PDT 24
Finished Aug 05 04:33:29 PM PDT 24
Peak memory 207380 kb
Host smart-0bfa41a4-adbf-431e-8706-7fd6586b7bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888854473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1888854473
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1430381302
Short name T226
Test name
Test status
Simulation time 341656301 ps
CPU time 8.62 seconds
Started Aug 05 04:33:35 PM PDT 24
Finished Aug 05 04:33:44 PM PDT 24
Peak memory 222300 kb
Host smart-17927670-5ffb-4cf0-8d58-10e39ddff2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430381302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1430381302
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1791852597
Short name T837
Test name
Test status
Simulation time 677305571 ps
CPU time 4.84 seconds
Started Aug 05 04:33:17 PM PDT 24
Finished Aug 05 04:33:22 PM PDT 24
Peak memory 218296 kb
Host smart-bdc7f3da-cfd9-498c-b4d0-57c53003cebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791852597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1791852597
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.245958082
Short name T698
Test name
Test status
Simulation time 47382881 ps
CPU time 2.41 seconds
Started Aug 05 04:33:28 PM PDT 24
Finished Aug 05 04:33:30 PM PDT 24
Peak memory 206940 kb
Host smart-4d5f7b7b-1d53-4f68-95ca-471c67fedecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245958082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.245958082
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1427249271
Short name T841
Test name
Test status
Simulation time 319388343 ps
CPU time 3.69 seconds
Started Aug 05 04:33:13 PM PDT 24
Finished Aug 05 04:33:17 PM PDT 24
Peak memory 208720 kb
Host smart-45b0a41a-c1f0-42ba-b447-012413bdfe45
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427249271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1427249271
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.245482050
Short name T659
Test name
Test status
Simulation time 46535796 ps
CPU time 1.99 seconds
Started Aug 05 04:33:14 PM PDT 24
Finished Aug 05 04:33:16 PM PDT 24
Peak memory 208644 kb
Host smart-7c233157-f7b4-434e-988f-4853bb1af5e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245482050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.245482050
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3639326714
Short name T405
Test name
Test status
Simulation time 94825839 ps
CPU time 2.67 seconds
Started Aug 05 04:33:13 PM PDT 24
Finished Aug 05 04:33:16 PM PDT 24
Peak memory 206828 kb
Host smart-b8ae833f-ad8a-42cc-96a6-395fd2561707
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639326714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3639326714
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1281391696
Short name T860
Test name
Test status
Simulation time 1949703370 ps
CPU time 10.69 seconds
Started Aug 05 04:33:12 PM PDT 24
Finished Aug 05 04:33:23 PM PDT 24
Peak memory 208452 kb
Host smart-252ddb0a-ec8a-4be3-a388-d4daa67d3414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281391696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1281391696
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2671857892
Short name T724
Test name
Test status
Simulation time 433601579 ps
CPU time 19.59 seconds
Started Aug 05 04:33:24 PM PDT 24
Finished Aug 05 04:33:44 PM PDT 24
Peak memory 221060 kb
Host smart-f552a89b-d6e1-4480-b7ef-fc63feaea191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671857892 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2671857892
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.564422609
Short name T559
Test name
Test status
Simulation time 123603094 ps
CPU time 5.5 seconds
Started Aug 05 04:33:20 PM PDT 24
Finished Aug 05 04:33:26 PM PDT 24
Peak memory 218092 kb
Host smart-e0a59bd8-8227-49a0-9c0c-49f0dc3ff111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564422609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.564422609
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.4104333056
Short name T391
Test name
Test status
Simulation time 1496595431 ps
CPU time 4.04 seconds
Started Aug 05 04:33:16 PM PDT 24
Finished Aug 05 04:33:21 PM PDT 24
Peak memory 210488 kb
Host smart-4ab74249-4f31-403a-973b-da7fe09e085b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104333056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.4104333056
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1119751569
Short name T435
Test name
Test status
Simulation time 104504281 ps
CPU time 0.86 seconds
Started Aug 05 04:33:27 PM PDT 24
Finished Aug 05 04:33:28 PM PDT 24
Peak memory 205836 kb
Host smart-8e2397e5-56f6-4eb3-95e8-b32691da28d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119751569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1119751569
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3784714657
Short name T274
Test name
Test status
Simulation time 31520087 ps
CPU time 2.64 seconds
Started Aug 05 04:33:28 PM PDT 24
Finished Aug 05 04:33:31 PM PDT 24
Peak memory 214208 kb
Host smart-923dc0f9-b9f0-4bf7-8b74-a9ed9f414154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784714657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3784714657
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3067294039
Short name T779
Test name
Test status
Simulation time 412358616 ps
CPU time 4.6 seconds
Started Aug 05 04:33:21 PM PDT 24
Finished Aug 05 04:33:26 PM PDT 24
Peak memory 209184 kb
Host smart-aba6d6c9-aae1-4c7b-8331-8f9efa543c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067294039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3067294039
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.767430616
Short name T597
Test name
Test status
Simulation time 54847250 ps
CPU time 2.2 seconds
Started Aug 05 04:33:30 PM PDT 24
Finished Aug 05 04:33:32 PM PDT 24
Peak memory 207576 kb
Host smart-8ecd1f54-2623-4fcd-bac5-55c9e65ba3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767430616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.767430616
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_random.1443486954
Short name T346
Test name
Test status
Simulation time 260402886 ps
CPU time 7.65 seconds
Started Aug 05 04:33:21 PM PDT 24
Finished Aug 05 04:33:29 PM PDT 24
Peak memory 209828 kb
Host smart-b1af74d2-e6fa-46ef-9149-271f19a48105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443486954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1443486954
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1499478404
Short name T293
Test name
Test status
Simulation time 1425218724 ps
CPU time 41.17 seconds
Started Aug 05 04:33:41 PM PDT 24
Finished Aug 05 04:34:23 PM PDT 24
Peak memory 208400 kb
Host smart-c862ce17-f272-4fbe-878b-53cc1be4cca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499478404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1499478404
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.398367841
Short name T581
Test name
Test status
Simulation time 1521813902 ps
CPU time 9.9 seconds
Started Aug 05 04:33:09 PM PDT 24
Finished Aug 05 04:33:19 PM PDT 24
Peak memory 208628 kb
Host smart-3c4c8e4a-b2e9-4091-b17f-fedbeca8f5a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398367841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.398367841
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3726700931
Short name T736
Test name
Test status
Simulation time 197572927 ps
CPU time 2.72 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:34 PM PDT 24
Peak memory 206856 kb
Host smart-778d9898-bcac-48a2-a1b5-2d8bdcee4cd9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726700931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3726700931
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2340197896
Short name T657
Test name
Test status
Simulation time 198747742 ps
CPU time 2.97 seconds
Started Aug 05 04:33:23 PM PDT 24
Finished Aug 05 04:33:26 PM PDT 24
Peak memory 207304 kb
Host smart-73da428a-9045-4733-ab65-189608c86a31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340197896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2340197896
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2700703498
Short name T600
Test name
Test status
Simulation time 51436899 ps
CPU time 2 seconds
Started Aug 05 04:33:12 PM PDT 24
Finished Aug 05 04:33:14 PM PDT 24
Peak memory 214196 kb
Host smart-a821dcf3-a6bd-4960-9b7c-ce98a2479bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700703498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2700703498
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2256709537
Short name T863
Test name
Test status
Simulation time 305531910 ps
CPU time 3.38 seconds
Started Aug 05 04:33:07 PM PDT 24
Finished Aug 05 04:33:10 PM PDT 24
Peak memory 206796 kb
Host smart-5181d3e3-cd5a-4167-81b2-81af44d9bc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256709537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2256709537
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.4147701185
Short name T222
Test name
Test status
Simulation time 1456713702 ps
CPU time 50.39 seconds
Started Aug 05 04:33:20 PM PDT 24
Finished Aug 05 04:34:10 PM PDT 24
Peak memory 216160 kb
Host smart-06bfeb63-140a-4849-986f-191d8f0e780b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147701185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.4147701185
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1910999577
Short name T129
Test name
Test status
Simulation time 293965234 ps
CPU time 6.77 seconds
Started Aug 05 04:33:21 PM PDT 24
Finished Aug 05 04:33:28 PM PDT 24
Peak memory 222392 kb
Host smart-1951e169-7897-40b1-911a-0b1601aa85cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910999577 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1910999577
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4185479666
Short name T682
Test name
Test status
Simulation time 142355059 ps
CPU time 3.38 seconds
Started Aug 05 04:33:08 PM PDT 24
Finished Aug 05 04:33:12 PM PDT 24
Peak memory 207912 kb
Host smart-0e5ceddd-1ee0-42e2-89c7-787af92e37a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185479666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4185479666
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.288600794
Short name T430
Test name
Test status
Simulation time 84680723 ps
CPU time 0.98 seconds
Started Aug 05 04:33:25 PM PDT 24
Finished Aug 05 04:33:26 PM PDT 24
Peak memory 205984 kb
Host smart-18826236-5ce6-4329-922a-977a9301994a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288600794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.288600794
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3527166517
Short name T3
Test name
Test status
Simulation time 565168177 ps
CPU time 5.66 seconds
Started Aug 05 04:33:21 PM PDT 24
Finished Aug 05 04:33:27 PM PDT 24
Peak memory 214148 kb
Host smart-9fc8b63c-2599-4808-a668-022215993658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527166517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3527166517
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2960074211
Short name T71
Test name
Test status
Simulation time 337394327 ps
CPU time 2.59 seconds
Started Aug 05 04:33:25 PM PDT 24
Finished Aug 05 04:33:28 PM PDT 24
Peak memory 207964 kb
Host smart-19966cb4-f161-4ede-84be-3e9f76cc8cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960074211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2960074211
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2263540773
Short name T697
Test name
Test status
Simulation time 298659400 ps
CPU time 2.79 seconds
Started Aug 05 04:33:46 PM PDT 24
Finished Aug 05 04:33:48 PM PDT 24
Peak memory 214116 kb
Host smart-7812e67f-b15d-497f-8226-4da5ae9f0af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263540773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2263540773
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2254077366
Short name T878
Test name
Test status
Simulation time 36241820 ps
CPU time 2.52 seconds
Started Aug 05 04:33:24 PM PDT 24
Finished Aug 05 04:33:27 PM PDT 24
Peak memory 221840 kb
Host smart-41a05d55-96ec-4080-954d-8c893718e3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254077366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2254077366
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.4224209324
Short name T500
Test name
Test status
Simulation time 75542931 ps
CPU time 3.6 seconds
Started Aug 05 04:33:04 PM PDT 24
Finished Aug 05 04:33:08 PM PDT 24
Peak memory 220116 kb
Host smart-8f0a7591-514c-416f-99ec-99de65acaa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224209324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.4224209324
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.774933107
Short name T814
Test name
Test status
Simulation time 1482107583 ps
CPU time 27.53 seconds
Started Aug 05 04:33:16 PM PDT 24
Finished Aug 05 04:33:44 PM PDT 24
Peak memory 209384 kb
Host smart-97873e78-9dc4-425b-86ec-d092766d9c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774933107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.774933107
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2833380353
Short name T885
Test name
Test status
Simulation time 36186340 ps
CPU time 2.46 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:33 PM PDT 24
Peak memory 208304 kb
Host smart-57bb3b18-cde7-4895-8946-03546592922b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833380353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2833380353
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3298159150
Short name T503
Test name
Test status
Simulation time 231489831 ps
CPU time 2.95 seconds
Started Aug 05 04:33:29 PM PDT 24
Finished Aug 05 04:33:32 PM PDT 24
Peak memory 208964 kb
Host smart-f24fb527-f9e5-4eb0-9a7a-440bd1dbbbc3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298159150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3298159150
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2080668719
Short name T817
Test name
Test status
Simulation time 347520582 ps
CPU time 4.17 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:36 PM PDT 24
Peak memory 208960 kb
Host smart-02c8b6b4-8673-41b9-9fe5-5e836e71010f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080668719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2080668719
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3463088203
Short name T494
Test name
Test status
Simulation time 504226292 ps
CPU time 4.01 seconds
Started Aug 05 04:33:34 PM PDT 24
Finished Aug 05 04:33:38 PM PDT 24
Peak memory 208044 kb
Host smart-30d7885f-83c6-476e-9b8d-61ad63313afa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463088203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3463088203
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.790464417
Short name T529
Test name
Test status
Simulation time 194973179 ps
CPU time 4.82 seconds
Started Aug 05 04:33:19 PM PDT 24
Finished Aug 05 04:33:24 PM PDT 24
Peak memory 208680 kb
Host smart-1e9e3068-156a-4936-8664-6c13788a5094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790464417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.790464417
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.941603425
Short name T906
Test name
Test status
Simulation time 38889502 ps
CPU time 1.94 seconds
Started Aug 05 04:33:14 PM PDT 24
Finished Aug 05 04:33:16 PM PDT 24
Peak memory 208548 kb
Host smart-4ab2e1eb-3ddd-4148-be77-8b12204fb7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941603425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.941603425
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1149500836
Short name T221
Test name
Test status
Simulation time 6815299743 ps
CPU time 37.63 seconds
Started Aug 05 04:33:48 PM PDT 24
Finished Aug 05 04:34:26 PM PDT 24
Peak memory 216472 kb
Host smart-2b49ee70-19a4-4a9d-a3b2-76f1e37de62f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149500836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1149500836
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2241997763
Short name T182
Test name
Test status
Simulation time 197179879 ps
CPU time 7 seconds
Started Aug 05 04:33:06 PM PDT 24
Finished Aug 05 04:33:13 PM PDT 24
Peak memory 222420 kb
Host smart-cb7fa02c-2a16-49f1-90cd-d8cf991e7498
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241997763 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2241997763
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1840719794
Short name T602
Test name
Test status
Simulation time 268795421 ps
CPU time 4.57 seconds
Started Aug 05 04:33:09 PM PDT 24
Finished Aug 05 04:33:14 PM PDT 24
Peak memory 218140 kb
Host smart-4d458e0a-3e11-4ee5-a345-063285deb9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840719794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1840719794
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.901569642
Short name T42
Test name
Test status
Simulation time 72093770 ps
CPU time 2.23 seconds
Started Aug 05 04:33:26 PM PDT 24
Finished Aug 05 04:33:29 PM PDT 24
Peak memory 209716 kb
Host smart-46d2c93f-c677-4520-8e8a-08861e027d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901569642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.901569642
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.4014935386
Short name T668
Test name
Test status
Simulation time 12797000 ps
CPU time 0.78 seconds
Started Aug 05 04:33:24 PM PDT 24
Finished Aug 05 04:33:30 PM PDT 24
Peak memory 205832 kb
Host smart-2f536cdf-03f7-451c-a608-0138cf5d6ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014935386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.4014935386
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.281818395
Short name T421
Test name
Test status
Simulation time 1771378375 ps
CPU time 6.44 seconds
Started Aug 05 04:33:24 PM PDT 24
Finished Aug 05 04:33:30 PM PDT 24
Peak memory 214552 kb
Host smart-5de63d84-232c-4c29-8a7a-7080b8ec7aec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281818395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.281818395
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1502061508
Short name T67
Test name
Test status
Simulation time 91846237 ps
CPU time 4.05 seconds
Started Aug 05 04:33:30 PM PDT 24
Finished Aug 05 04:33:34 PM PDT 24
Peak memory 221624 kb
Host smart-26f3fc19-d9e6-4acf-8ffc-e547daaa99ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502061508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1502061508
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2601815902
Short name T190
Test name
Test status
Simulation time 456755434 ps
CPU time 3.87 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:35 PM PDT 24
Peak memory 210016 kb
Host smart-778dfd75-bc1e-4a5e-8684-04659e6a1688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601815902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2601815902
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3992750437
Short name T102
Test name
Test status
Simulation time 480671440 ps
CPU time 7.92 seconds
Started Aug 05 04:33:32 PM PDT 24
Finished Aug 05 04:33:40 PM PDT 24
Peak memory 222388 kb
Host smart-01ee5306-a24f-424f-89aa-38e9b326543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992750437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3992750437
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3268922100
Short name T267
Test name
Test status
Simulation time 388550369 ps
CPU time 3.61 seconds
Started Aug 05 04:33:16 PM PDT 24
Finished Aug 05 04:33:19 PM PDT 24
Peak memory 221560 kb
Host smart-9c65ed39-c817-4349-8971-33c747419b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268922100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3268922100
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4225849868
Short name T558
Test name
Test status
Simulation time 1476133077 ps
CPU time 4.21 seconds
Started Aug 05 04:33:29 PM PDT 24
Finished Aug 05 04:33:33 PM PDT 24
Peak memory 209252 kb
Host smart-e3ba8993-665d-494b-a95b-f30c117c7161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225849868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4225849868
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.760201825
Short name T792
Test name
Test status
Simulation time 16091794147 ps
CPU time 46.01 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:34:17 PM PDT 24
Peak memory 214232 kb
Host smart-4819af81-9c57-4e00-af46-5763ac3aedee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760201825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.760201825
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2411609237
Short name T520
Test name
Test status
Simulation time 461755132 ps
CPU time 3.68 seconds
Started Aug 05 04:33:43 PM PDT 24
Finished Aug 05 04:33:47 PM PDT 24
Peak memory 206712 kb
Host smart-19a4bb4b-8d8f-4e9e-a5d4-9116c18c3276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411609237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2411609237
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1554316134
Short name T348
Test name
Test status
Simulation time 183092994 ps
CPU time 3.13 seconds
Started Aug 05 04:33:26 PM PDT 24
Finished Aug 05 04:33:29 PM PDT 24
Peak memory 208752 kb
Host smart-0eb63dbd-5f63-426d-adba-056b7adbcdab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554316134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1554316134
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2838732730
Short name T821
Test name
Test status
Simulation time 36202306 ps
CPU time 2.43 seconds
Started Aug 05 04:33:30 PM PDT 24
Finished Aug 05 04:33:33 PM PDT 24
Peak memory 208544 kb
Host smart-414dc3a6-41f9-4037-9f9d-666a0a0d0656
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838732730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2838732730
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.631387883
Short name T890
Test name
Test status
Simulation time 35749494 ps
CPU time 2.21 seconds
Started Aug 05 04:33:36 PM PDT 24
Finished Aug 05 04:33:38 PM PDT 24
Peak memory 207816 kb
Host smart-9712da80-c2b1-436f-b1fe-b634271e8dab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631387883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.631387883
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.216530066
Short name T703
Test name
Test status
Simulation time 302360911 ps
CPU time 4.32 seconds
Started Aug 05 04:33:40 PM PDT 24
Finished Aug 05 04:33:45 PM PDT 24
Peak memory 218432 kb
Host smart-7f3c5d89-906f-44d5-9806-9a5c6bc637d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216530066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.216530066
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3124893566
Short name T591
Test name
Test status
Simulation time 1456354945 ps
CPU time 18.24 seconds
Started Aug 05 04:33:39 PM PDT 24
Finished Aug 05 04:34:03 PM PDT 24
Peak memory 207628 kb
Host smart-bf3bd53c-6279-4244-a14e-a18edabc057b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124893566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3124893566
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3881599927
Short name T193
Test name
Test status
Simulation time 668800395 ps
CPU time 12.71 seconds
Started Aug 05 04:33:38 PM PDT 24
Finished Aug 05 04:33:51 PM PDT 24
Peak memory 220120 kb
Host smart-bb2d2309-4788-48aa-a1df-cfeb2700948c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881599927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3881599927
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2904526817
Short name T77
Test name
Test status
Simulation time 820773399 ps
CPU time 16.32 seconds
Started Aug 05 04:33:38 PM PDT 24
Finished Aug 05 04:33:54 PM PDT 24
Peak memory 221044 kb
Host smart-a7946c9d-15b1-49de-8976-7ff363398938
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904526817 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2904526817
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2482125779
Short name T660
Test name
Test status
Simulation time 508869539 ps
CPU time 11.46 seconds
Started Aug 05 04:33:43 PM PDT 24
Finished Aug 05 04:33:54 PM PDT 24
Peak memory 214256 kb
Host smart-11927e7c-f622-4039-b0dc-1b5bc8ff2564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482125779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2482125779
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.988794512
Short name T62
Test name
Test status
Simulation time 250596781 ps
CPU time 2.96 seconds
Started Aug 05 04:33:32 PM PDT 24
Finished Aug 05 04:33:35 PM PDT 24
Peak memory 209812 kb
Host smart-d6a18d92-bb42-4b8b-95ae-8b1edb567501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988794512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.988794512
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2263416687
Short name T666
Test name
Test status
Simulation time 58538175 ps
CPU time 0.77 seconds
Started Aug 05 04:33:32 PM PDT 24
Finished Aug 05 04:33:33 PM PDT 24
Peak memory 205824 kb
Host smart-a1183006-0455-44d1-9097-e2851cd9d8d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263416687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2263416687
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.718622079
Short name T616
Test name
Test status
Simulation time 36713961 ps
CPU time 2.31 seconds
Started Aug 05 04:33:26 PM PDT 24
Finished Aug 05 04:33:28 PM PDT 24
Peak memory 214212 kb
Host smart-6443626b-168e-470c-b381-447a6e73eb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718622079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.718622079
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1354720926
Short name T622
Test name
Test status
Simulation time 15836213 ps
CPU time 1.37 seconds
Started Aug 05 04:33:28 PM PDT 24
Finished Aug 05 04:33:29 PM PDT 24
Peak memory 207328 kb
Host smart-4ffc4102-5766-4b7c-86c3-8e64f8dfca95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354720926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1354720926
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.576355852
Short name T828
Test name
Test status
Simulation time 158499811 ps
CPU time 3.98 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:35 PM PDT 24
Peak memory 214260 kb
Host smart-70d83a70-05bf-4639-8f31-d11e0e85a428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576355852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.576355852
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1012412194
Short name T351
Test name
Test status
Simulation time 87600942 ps
CPU time 3.19 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:34 PM PDT 24
Peak memory 210072 kb
Host smart-0e12ed75-325b-4677-a009-6ab06ea4215d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012412194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1012412194
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2994586291
Short name T774
Test name
Test status
Simulation time 493926975 ps
CPU time 6.9 seconds
Started Aug 05 04:33:29 PM PDT 24
Finished Aug 05 04:33:36 PM PDT 24
Peak memory 208684 kb
Host smart-8ac8639d-5cc0-4cd0-8c88-3935996f5eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994586291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2994586291
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.546598985
Short name T113
Test name
Test status
Simulation time 761355227 ps
CPU time 3.63 seconds
Started Aug 05 04:33:32 PM PDT 24
Finished Aug 05 04:33:41 PM PDT 24
Peak memory 208620 kb
Host smart-867728f4-fbf4-4c3d-b7e8-3a0f06eef1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546598985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.546598985
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3656813877
Short name T451
Test name
Test status
Simulation time 1127004158 ps
CPU time 6.8 seconds
Started Aug 05 04:33:46 PM PDT 24
Finished Aug 05 04:33:53 PM PDT 24
Peak memory 208536 kb
Host smart-d3b5e7ff-b69e-4083-90e2-e0744e40be37
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656813877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3656813877
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4192031833
Short name T815
Test name
Test status
Simulation time 135195019 ps
CPU time 2.6 seconds
Started Aug 05 04:33:33 PM PDT 24
Finished Aug 05 04:33:36 PM PDT 24
Peak memory 206864 kb
Host smart-1f7ee094-0d2d-47cd-8d72-5002cd42ca86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192031833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4192031833
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2412340828
Short name T689
Test name
Test status
Simulation time 99137123 ps
CPU time 2.04 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:33 PM PDT 24
Peak memory 208932 kb
Host smart-a788c924-3743-4020-aa5c-48516ddc0c51
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412340828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2412340828
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2406573339
Short name T873
Test name
Test status
Simulation time 335148577 ps
CPU time 3.3 seconds
Started Aug 05 04:33:34 PM PDT 24
Finished Aug 05 04:33:37 PM PDT 24
Peak memory 210056 kb
Host smart-284ed9a2-7267-49d9-8978-e32ca1416dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406573339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2406573339
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.856766951
Short name T605
Test name
Test status
Simulation time 572893287 ps
CPU time 2.69 seconds
Started Aug 05 04:33:43 PM PDT 24
Finished Aug 05 04:33:46 PM PDT 24
Peak memory 208376 kb
Host smart-53158005-08ef-4079-b88f-3ddde9827b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856766951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.856766951
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.4112714984
Short name T629
Test name
Test status
Simulation time 128110034 ps
CPU time 3.62 seconds
Started Aug 05 04:33:42 PM PDT 24
Finished Aug 05 04:33:46 PM PDT 24
Peak memory 214916 kb
Host smart-d6f165d5-5ef2-4718-8800-c3e8ebb52bdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112714984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.4112714984
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3556645507
Short name T255
Test name
Test status
Simulation time 241288381 ps
CPU time 6.86 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:38 PM PDT 24
Peak memory 214172 kb
Host smart-994578f3-cc9f-4a64-8f69-5af5609abce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556645507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3556645507
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2514327159
Short name T480
Test name
Test status
Simulation time 187209086 ps
CPU time 1.85 seconds
Started Aug 05 04:33:20 PM PDT 24
Finished Aug 05 04:33:22 PM PDT 24
Peak memory 209364 kb
Host smart-61f85dde-3236-465c-9651-c56734279dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514327159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2514327159
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.608504873
Short name T446
Test name
Test status
Simulation time 16936259 ps
CPU time 0.94 seconds
Started Aug 05 04:32:50 PM PDT 24
Finished Aug 05 04:32:51 PM PDT 24
Peak memory 205968 kb
Host smart-bd66f5dd-43c5-494c-8c73-14da20fc133f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608504873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.608504873
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1671739058
Short name T426
Test name
Test status
Simulation time 110759459 ps
CPU time 6.21 seconds
Started Aug 05 04:32:44 PM PDT 24
Finished Aug 05 04:32:50 PM PDT 24
Peak memory 214944 kb
Host smart-3338fb0a-55c4-42f1-a5f9-41b80ecbd249
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671739058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1671739058
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.526719074
Short name T21
Test name
Test status
Simulation time 63311147 ps
CPU time 2.41 seconds
Started Aug 05 04:32:48 PM PDT 24
Finished Aug 05 04:32:51 PM PDT 24
Peak memory 215384 kb
Host smart-5995ec83-f1cc-4511-adb2-91d353b195ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526719074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.526719074
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.77833790
Short name T678
Test name
Test status
Simulation time 2667706906 ps
CPU time 16.12 seconds
Started Aug 05 04:32:49 PM PDT 24
Finished Aug 05 04:33:06 PM PDT 24
Peak memory 209408 kb
Host smart-a8887d1c-0542-4547-8420-657381d7b741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77833790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.77833790
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2981468323
Short name T304
Test name
Test status
Simulation time 118681355 ps
CPU time 2.35 seconds
Started Aug 05 04:32:56 PM PDT 24
Finished Aug 05 04:32:58 PM PDT 24
Peak memory 214176 kb
Host smart-2e508a8d-bd51-4742-9a7c-210d40cffc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981468323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2981468323
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2909425690
Short name T318
Test name
Test status
Simulation time 35835137 ps
CPU time 2.63 seconds
Started Aug 05 04:32:54 PM PDT 24
Finished Aug 05 04:32:57 PM PDT 24
Peak memory 222292 kb
Host smart-558cb098-4373-4842-a8d5-4de1b3425cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909425690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2909425690
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.427991049
Short name T653
Test name
Test status
Simulation time 115246762 ps
CPU time 4.2 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 210032 kb
Host smart-7cdefa2c-82c2-4f5e-94ac-75a84ece1a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427991049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.427991049
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1310717610
Short name T733
Test name
Test status
Simulation time 158035584 ps
CPU time 5.47 seconds
Started Aug 05 04:32:51 PM PDT 24
Finished Aug 05 04:32:57 PM PDT 24
Peak memory 210300 kb
Host smart-f475de9d-30b9-4519-8bbf-4a27d36dee37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310717610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1310717610
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2752242310
Short name T11
Test name
Test status
Simulation time 450659523 ps
CPU time 7.6 seconds
Started Aug 05 04:32:56 PM PDT 24
Finished Aug 05 04:33:04 PM PDT 24
Peak memory 231116 kb
Host smart-5ff3bd81-0e99-4de8-9bfb-fcc21f910305
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752242310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2752242310
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2075242376
Short name T871
Test name
Test status
Simulation time 97683934 ps
CPU time 2.77 seconds
Started Aug 05 04:32:41 PM PDT 24
Finished Aug 05 04:32:44 PM PDT 24
Peak memory 206784 kb
Host smart-fa12bf92-67d2-481e-a67a-753c2d81e233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075242376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2075242376
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3569055351
Short name T741
Test name
Test status
Simulation time 46673211 ps
CPU time 2.05 seconds
Started Aug 05 04:32:57 PM PDT 24
Finished Aug 05 04:32:59 PM PDT 24
Peak memory 208724 kb
Host smart-5ee4a11a-9698-43f2-9b56-546151f2ead0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569055351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3569055351
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1213724081
Short name T204
Test name
Test status
Simulation time 1711596633 ps
CPU time 3.94 seconds
Started Aug 05 04:32:57 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 208728 kb
Host smart-ddb5639b-ae40-4552-90c7-3f50455c03e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213724081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1213724081
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1074999708
Short name T555
Test name
Test status
Simulation time 61232264 ps
CPU time 2.88 seconds
Started Aug 05 04:33:00 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 208932 kb
Host smart-fe6bd1e4-ff1f-46a9-bcc7-eb70767409b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074999708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1074999708
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2754792415
Short name T625
Test name
Test status
Simulation time 71597914 ps
CPU time 3.31 seconds
Started Aug 05 04:32:48 PM PDT 24
Finished Aug 05 04:32:51 PM PDT 24
Peak memory 208620 kb
Host smart-a9adf95a-8e0a-4b71-99af-84c288d256ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754792415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2754792415
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.117430589
Short name T577
Test name
Test status
Simulation time 988910052 ps
CPU time 4.3 seconds
Started Aug 05 04:33:18 PM PDT 24
Finished Aug 05 04:33:23 PM PDT 24
Peak memory 206816 kb
Host smart-f95c2d08-b0dc-432f-b979-b90af02f9001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117430589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.117430589
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1309937700
Short name T223
Test name
Test status
Simulation time 138670190 ps
CPU time 7.15 seconds
Started Aug 05 04:32:49 PM PDT 24
Finished Aug 05 04:32:57 PM PDT 24
Peak memory 215108 kb
Host smart-44964130-7b75-4e6e-847e-86675d676728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309937700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1309937700
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2169510929
Short name T298
Test name
Test status
Simulation time 123888282 ps
CPU time 5.11 seconds
Started Aug 05 04:32:48 PM PDT 24
Finished Aug 05 04:32:53 PM PDT 24
Peak memory 209704 kb
Host smart-f2e4e43e-aece-419d-91d2-704d959b75ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169510929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2169510929
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2288273887
Short name T408
Test name
Test status
Simulation time 3968505227 ps
CPU time 29.97 seconds
Started Aug 05 04:32:45 PM PDT 24
Finished Aug 05 04:33:15 PM PDT 24
Peak memory 210828 kb
Host smart-b22df14f-911a-4531-a173-590a9410ef1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288273887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2288273887
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.862844961
Short name T441
Test name
Test status
Simulation time 36846749 ps
CPU time 0.78 seconds
Started Aug 05 04:33:30 PM PDT 24
Finished Aug 05 04:33:31 PM PDT 24
Peak memory 205824 kb
Host smart-803e1b5e-7613-441b-88a6-1ed9a4ffebd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862844961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.862844961
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3545672716
Short name T40
Test name
Test status
Simulation time 186992469 ps
CPU time 3.06 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:34 PM PDT 24
Peak memory 208420 kb
Host smart-d9bcddf1-864a-4ba3-8a9e-48255b44460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545672716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3545672716
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3742232409
Short name T266
Test name
Test status
Simulation time 444272228 ps
CPU time 2.43 seconds
Started Aug 05 04:33:35 PM PDT 24
Finished Aug 05 04:33:38 PM PDT 24
Peak memory 214208 kb
Host smart-15f63933-2b7a-464c-9680-d7304d3af11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742232409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3742232409
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2557594088
Short name T812
Test name
Test status
Simulation time 276393318 ps
CPU time 4.72 seconds
Started Aug 05 04:33:48 PM PDT 24
Finished Aug 05 04:33:52 PM PDT 24
Peak memory 219724 kb
Host smart-46e2d257-1c30-47af-aa4e-bf6a907fb1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557594088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2557594088
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.680562692
Short name T826
Test name
Test status
Simulation time 304733442 ps
CPU time 3.73 seconds
Started Aug 05 04:33:20 PM PDT 24
Finished Aug 05 04:33:24 PM PDT 24
Peak memory 214620 kb
Host smart-3ea843f5-7b3d-4566-82f1-c330529281f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680562692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.680562692
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3880910853
Short name T258
Test name
Test status
Simulation time 5042606443 ps
CPU time 15.05 seconds
Started Aug 05 04:33:32 PM PDT 24
Finished Aug 05 04:33:48 PM PDT 24
Peak memory 214240 kb
Host smart-8125afe6-23dc-4b12-8420-cab7800358c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880910853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3880910853
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1756525052
Short name T799
Test name
Test status
Simulation time 72575087 ps
CPU time 3.26 seconds
Started Aug 05 04:33:23 PM PDT 24
Finished Aug 05 04:33:26 PM PDT 24
Peak memory 208468 kb
Host smart-7a9b212e-8b02-4b45-890a-3a89f83566c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756525052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1756525052
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3759042293
Short name T811
Test name
Test status
Simulation time 222239056 ps
CPU time 5.84 seconds
Started Aug 05 04:33:38 PM PDT 24
Finished Aug 05 04:33:44 PM PDT 24
Peak memory 207860 kb
Host smart-c468381e-ac7d-41ec-9ff2-b195fedcc7e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759042293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3759042293
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4177134170
Short name T633
Test name
Test status
Simulation time 842910070 ps
CPU time 15.26 seconds
Started Aug 05 04:33:32 PM PDT 24
Finished Aug 05 04:33:47 PM PDT 24
Peak memory 208300 kb
Host smart-a876dcf9-6d8f-4c58-b085-73738c142116
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177134170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4177134170
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.4167758822
Short name T361
Test name
Test status
Simulation time 326653688 ps
CPU time 6.93 seconds
Started Aug 05 04:33:46 PM PDT 24
Finished Aug 05 04:33:53 PM PDT 24
Peak memory 208944 kb
Host smart-12fc1412-0002-446d-8da7-a39ab9498eea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167758822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4167758822
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2374116585
Short name T200
Test name
Test status
Simulation time 1016130297 ps
CPU time 17.7 seconds
Started Aug 05 04:33:40 PM PDT 24
Finished Aug 05 04:33:58 PM PDT 24
Peak memory 218400 kb
Host smart-46c8e53d-2c69-4750-b0be-f147f2da3d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374116585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2374116585
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3560763855
Short name T679
Test name
Test status
Simulation time 125158960 ps
CPU time 3.33 seconds
Started Aug 05 04:33:41 PM PDT 24
Finished Aug 05 04:33:45 PM PDT 24
Peak memory 208640 kb
Host smart-5bdf03c7-5d17-461d-8d55-3bfa226a81d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560763855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3560763855
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3994682146
Short name T180
Test name
Test status
Simulation time 2828328370 ps
CPU time 12.99 seconds
Started Aug 05 04:33:42 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 219472 kb
Host smart-61f17522-4ceb-4424-b1de-b7477ded225f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994682146 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3994682146
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2527266081
Short name T683
Test name
Test status
Simulation time 618280426 ps
CPU time 4.33 seconds
Started Aug 05 04:33:40 PM PDT 24
Finished Aug 05 04:33:44 PM PDT 24
Peak memory 207228 kb
Host smart-f8001446-2f92-4211-9495-a838edadf8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527266081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2527266081
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3086536121
Short name T891
Test name
Test status
Simulation time 42880655 ps
CPU time 2.57 seconds
Started Aug 05 04:33:27 PM PDT 24
Finished Aug 05 04:33:29 PM PDT 24
Peak memory 209672 kb
Host smart-791c420a-d409-41ec-87bc-9103a6dbff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086536121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3086536121
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3757065158
Short name T449
Test name
Test status
Simulation time 33839651 ps
CPU time 0.84 seconds
Started Aug 05 04:33:35 PM PDT 24
Finished Aug 05 04:33:36 PM PDT 24
Peak memory 205828 kb
Host smart-a6964d2c-7838-4454-8e02-90268dc24093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757065158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3757065158
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2853928626
Short name T131
Test name
Test status
Simulation time 101023504 ps
CPU time 3.81 seconds
Started Aug 05 04:33:37 PM PDT 24
Finished Aug 05 04:33:47 PM PDT 24
Peak memory 214172 kb
Host smart-c160b072-c8f3-4ff9-a598-a997994edd3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853928626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2853928626
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2901417147
Short name T32
Test name
Test status
Simulation time 116245805 ps
CPU time 4.58 seconds
Started Aug 05 04:33:30 PM PDT 24
Finished Aug 05 04:33:35 PM PDT 24
Peak memory 214184 kb
Host smart-75e7aadb-acd3-46f0-91c3-97f7202dddac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901417147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2901417147
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3238703348
Short name T489
Test name
Test status
Simulation time 95350021 ps
CPU time 2.6 seconds
Started Aug 05 04:33:37 PM PDT 24
Finished Aug 05 04:33:40 PM PDT 24
Peak memory 209268 kb
Host smart-d8973b54-f94d-4227-8616-7950c44e5e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238703348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3238703348
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3653115235
Short name T94
Test name
Test status
Simulation time 1386958912 ps
CPU time 5.8 seconds
Started Aug 05 04:33:40 PM PDT 24
Finished Aug 05 04:33:51 PM PDT 24
Peak memory 209540 kb
Host smart-63eb96f3-1ad1-4294-92ea-5b0e33270b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653115235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3653115235
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2244685808
Short name T687
Test name
Test status
Simulation time 123030764 ps
CPU time 4.82 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:36 PM PDT 24
Peak memory 209672 kb
Host smart-66b3c33a-af80-4e21-9f25-ee50cd28f8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244685808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2244685808
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3822766877
Short name T840
Test name
Test status
Simulation time 205650170 ps
CPU time 6.24 seconds
Started Aug 05 04:33:44 PM PDT 24
Finished Aug 05 04:33:50 PM PDT 24
Peak memory 208872 kb
Host smart-2b0e7897-31db-4dc5-96a5-e4cef9ecfa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822766877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3822766877
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3532337376
Short name T458
Test name
Test status
Simulation time 106701596 ps
CPU time 2.15 seconds
Started Aug 05 04:33:35 PM PDT 24
Finished Aug 05 04:33:42 PM PDT 24
Peak memory 206636 kb
Host smart-57e5c36e-389a-486e-b39f-467023087eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532337376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3532337376
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3458161156
Short name T623
Test name
Test status
Simulation time 161775024 ps
CPU time 5.05 seconds
Started Aug 05 04:33:40 PM PDT 24
Finished Aug 05 04:33:46 PM PDT 24
Peak memory 208616 kb
Host smart-2b470f9c-5c24-4fa1-a0ba-1fc0930c6280
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458161156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3458161156
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2635845996
Short name T315
Test name
Test status
Simulation time 1248162864 ps
CPU time 9.49 seconds
Started Aug 05 04:33:35 PM PDT 24
Finished Aug 05 04:33:44 PM PDT 24
Peak memory 207928 kb
Host smart-0f281b81-0f69-4838-aba9-8ab660d6b5db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635845996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2635845996
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1218526782
Short name T747
Test name
Test status
Simulation time 108677846 ps
CPU time 2.48 seconds
Started Aug 05 04:33:35 PM PDT 24
Finished Aug 05 04:33:37 PM PDT 24
Peak memory 209720 kb
Host smart-c70272e0-055f-4179-a009-b279e4218f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218526782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1218526782
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.870776632
Short name T750
Test name
Test status
Simulation time 32774910 ps
CPU time 2.18 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:33 PM PDT 24
Peak memory 208888 kb
Host smart-05f638c4-7a30-417e-8e63-2be039be697b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870776632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.870776632
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2177637586
Short name T892
Test name
Test status
Simulation time 1273251049 ps
CPU time 9.61 seconds
Started Aug 05 04:33:28 PM PDT 24
Finished Aug 05 04:33:38 PM PDT 24
Peak memory 215436 kb
Host smart-47ae313d-9362-4d04-a10e-643cfd5d83bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177637586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2177637586
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.62348208
Short name T260
Test name
Test status
Simulation time 1795425616 ps
CPU time 18.77 seconds
Started Aug 05 04:33:28 PM PDT 24
Finished Aug 05 04:33:47 PM PDT 24
Peak memory 208756 kb
Host smart-d9f62613-54ed-4ea1-bd44-b4be031180d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62348208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.62348208
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3397629542
Short name T574
Test name
Test status
Simulation time 102765404 ps
CPU time 2.14 seconds
Started Aug 05 04:33:34 PM PDT 24
Finished Aug 05 04:33:41 PM PDT 24
Peak memory 210156 kb
Host smart-aacea22a-0414-4498-8b1c-7d8cb7dc5826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397629542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3397629542
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1469067037
Short name T782
Test name
Test status
Simulation time 17199953 ps
CPU time 0.85 seconds
Started Aug 05 04:33:39 PM PDT 24
Finished Aug 05 04:33:40 PM PDT 24
Peak memory 205932 kb
Host smart-dcfa3644-868c-4cce-830c-210c1d3d41db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469067037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1469067037
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2073177698
Short name T299
Test name
Test status
Simulation time 100376484 ps
CPU time 3.88 seconds
Started Aug 05 04:33:36 PM PDT 24
Finished Aug 05 04:33:40 PM PDT 24
Peak memory 209196 kb
Host smart-b2170f6c-09b4-4c1d-9253-976f31c6f831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073177698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2073177698
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.231520154
Short name T744
Test name
Test status
Simulation time 224150455 ps
CPU time 3.15 seconds
Started Aug 05 04:34:08 PM PDT 24
Finished Aug 05 04:34:12 PM PDT 24
Peak memory 209152 kb
Host smart-f9f79228-49ab-4ba2-ba72-1ffe92a8d3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231520154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.231520154
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.169493080
Short name T507
Test name
Test status
Simulation time 331798003 ps
CPU time 6.84 seconds
Started Aug 05 04:33:39 PM PDT 24
Finished Aug 05 04:33:46 PM PDT 24
Peak memory 214216 kb
Host smart-a4c8e4d9-ecfd-4b95-8d8b-b519e9167a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169493080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.169493080
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3207453856
Short name T216
Test name
Test status
Simulation time 509240219 ps
CPU time 4.51 seconds
Started Aug 05 04:33:32 PM PDT 24
Finished Aug 05 04:33:37 PM PDT 24
Peak memory 210224 kb
Host smart-a6b7a88f-1715-4501-b77b-a4fa1bcb507e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207453856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3207453856
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3014754892
Short name T604
Test name
Test status
Simulation time 201825230 ps
CPU time 7.66 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:05 PM PDT 24
Peak memory 209600 kb
Host smart-36c95c81-3239-473b-9f22-ca0e270ab2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014754892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3014754892
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3446235610
Short name T506
Test name
Test status
Simulation time 63878294 ps
CPU time 3 seconds
Started Aug 05 04:33:45 PM PDT 24
Finished Aug 05 04:33:48 PM PDT 24
Peak memory 206776 kb
Host smart-7b79b1ba-3768-400a-9667-806d4b9f3431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446235610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3446235610
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2639894752
Short name T312
Test name
Test status
Simulation time 2608195662 ps
CPU time 24.58 seconds
Started Aug 05 04:33:36 PM PDT 24
Finished Aug 05 04:34:01 PM PDT 24
Peak memory 208268 kb
Host smart-d813f9e1-2a82-43ad-a183-f202f24750b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639894752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2639894752
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1819078140
Short name T619
Test name
Test status
Simulation time 641093912 ps
CPU time 4.24 seconds
Started Aug 05 04:33:38 PM PDT 24
Finished Aug 05 04:33:43 PM PDT 24
Peak memory 208492 kb
Host smart-fda0a834-5475-4cea-a1c9-6c73f0d0eb2a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819078140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1819078140
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2645146963
Short name T728
Test name
Test status
Simulation time 1282507215 ps
CPU time 14.46 seconds
Started Aug 05 04:33:35 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 208656 kb
Host smart-b92af852-298a-4506-b2c7-a7b76ccbdd6f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645146963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2645146963
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.43749139
Short name T295
Test name
Test status
Simulation time 605571556 ps
CPU time 14.04 seconds
Started Aug 05 04:33:40 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 208900 kb
Host smart-894854cb-7890-459e-baca-d5ab7d5942ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43749139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.43749139
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.241644614
Short name T553
Test name
Test status
Simulation time 2722777449 ps
CPU time 15.56 seconds
Started Aug 05 04:33:43 PM PDT 24
Finished Aug 05 04:33:58 PM PDT 24
Peak memory 208448 kb
Host smart-98313ec8-e018-4a7f-a7c3-8a26620156bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241644614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.241644614
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2277170701
Short name T364
Test name
Test status
Simulation time 2070028944 ps
CPU time 36.34 seconds
Started Aug 05 04:33:33 PM PDT 24
Finished Aug 05 04:34:09 PM PDT 24
Peak memory 215032 kb
Host smart-d0152f55-abee-4469-882e-2ffbca6fb23e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277170701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2277170701
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3985521011
Short name T118
Test name
Test status
Simulation time 222987337 ps
CPU time 10.89 seconds
Started Aug 05 04:33:44 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 221252 kb
Host smart-6c26d89e-441e-46b2-9857-42ea4c0ba2da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985521011 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3985521011
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1748537562
Short name T719
Test name
Test status
Simulation time 156999173 ps
CPU time 3.56 seconds
Started Aug 05 04:33:33 PM PDT 24
Finished Aug 05 04:33:37 PM PDT 24
Peak memory 207284 kb
Host smart-ffd54662-63ae-4fa8-96c7-4d059d41c071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748537562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1748537562
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1055393527
Short name T59
Test name
Test status
Simulation time 41429124 ps
CPU time 2.07 seconds
Started Aug 05 04:33:40 PM PDT 24
Finished Aug 05 04:33:42 PM PDT 24
Peak memory 209580 kb
Host smart-d79d45b3-7eda-43e3-a696-26cf9d030b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055393527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1055393527
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2717745236
Short name T465
Test name
Test status
Simulation time 10979790 ps
CPU time 0.78 seconds
Started Aug 05 04:33:44 PM PDT 24
Finished Aug 05 04:33:45 PM PDT 24
Peak memory 205792 kb
Host smart-1308b09c-d233-49b0-bdc1-3419b80b252b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717745236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2717745236
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3794476524
Short name T334
Test name
Test status
Simulation time 545974023 ps
CPU time 7.68 seconds
Started Aug 05 04:33:40 PM PDT 24
Finished Aug 05 04:33:48 PM PDT 24
Peak memory 215184 kb
Host smart-c2c6a506-0d10-4ac4-887a-0ccb39b5a39d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794476524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3794476524
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.66103563
Short name T217
Test name
Test status
Simulation time 122902184 ps
CPU time 4.01 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 214216 kb
Host smart-ead3fb6a-193a-4c96-9c02-cde69d9e9a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66103563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.66103563
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2383189857
Short name T761
Test name
Test status
Simulation time 43049433 ps
CPU time 2.21 seconds
Started Aug 05 04:33:46 PM PDT 24
Finished Aug 05 04:33:49 PM PDT 24
Peak memory 214160 kb
Host smart-f2795f47-2938-4787-8e37-7b2b9bd631ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383189857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2383189857
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4192715258
Short name T390
Test name
Test status
Simulation time 517613556 ps
CPU time 6.59 seconds
Started Aug 05 04:33:54 PM PDT 24
Finished Aug 05 04:34:01 PM PDT 24
Peak memory 208560 kb
Host smart-348d5636-6f91-495e-b573-b9fd6b57f902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192715258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4192715258
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.615915473
Short name T283
Test name
Test status
Simulation time 161950222 ps
CPU time 5.23 seconds
Started Aug 05 04:33:46 PM PDT 24
Finished Aug 05 04:33:51 PM PDT 24
Peak memory 222220 kb
Host smart-d7a5649d-0f19-49a5-92b3-45c9756bc9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615915473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.615915473
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1430702167
Short name T212
Test name
Test status
Simulation time 25378880 ps
CPU time 1.84 seconds
Started Aug 05 04:33:41 PM PDT 24
Finished Aug 05 04:33:43 PM PDT 24
Peak memory 220112 kb
Host smart-a970a7cf-f81a-4cca-93b4-1b9757a5c4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430702167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1430702167
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3401491869
Short name T676
Test name
Test status
Simulation time 335966814 ps
CPU time 4.59 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:36 PM PDT 24
Peak memory 218396 kb
Host smart-e27a7b9d-6ccb-4d77-86ad-ec807c679f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401491869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3401491869
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1675338001
Short name T632
Test name
Test status
Simulation time 518216407 ps
CPU time 7.12 seconds
Started Aug 05 04:33:31 PM PDT 24
Finished Aug 05 04:33:38 PM PDT 24
Peak memory 208764 kb
Host smart-b3db2708-5d2e-489a-a886-6ee2ea681265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675338001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1675338001
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.695253421
Short name T867
Test name
Test status
Simulation time 71451897 ps
CPU time 1.65 seconds
Started Aug 05 04:33:41 PM PDT 24
Finished Aug 05 04:33:43 PM PDT 24
Peak memory 206796 kb
Host smart-0fc356a5-e519-4d75-b844-b9b78a8bfa51
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695253421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.695253421
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1869890017
Short name T541
Test name
Test status
Simulation time 294995171 ps
CPU time 3.35 seconds
Started Aug 05 04:33:45 PM PDT 24
Finished Aug 05 04:33:48 PM PDT 24
Peak memory 208892 kb
Host smart-868bc827-7d06-40a7-8f84-e4eccaabe863
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869890017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1869890017
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2758697984
Short name T296
Test name
Test status
Simulation time 731260937 ps
CPU time 2.69 seconds
Started Aug 05 04:33:53 PM PDT 24
Finished Aug 05 04:33:56 PM PDT 24
Peak memory 206860 kb
Host smart-0721fe59-bd80-4e9b-a087-53951ef07d81
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758697984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2758697984
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.4213469614
Short name T598
Test name
Test status
Simulation time 33830221 ps
CPU time 2.34 seconds
Started Aug 05 04:33:41 PM PDT 24
Finished Aug 05 04:33:44 PM PDT 24
Peak memory 207984 kb
Host smart-37050b48-10a9-4fbc-a6b7-b5bfc5a9802e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213469614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.4213469614
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1655976679
Short name T483
Test name
Test status
Simulation time 103114047 ps
CPU time 2.54 seconds
Started Aug 05 04:33:44 PM PDT 24
Finished Aug 05 04:33:51 PM PDT 24
Peak memory 208652 kb
Host smart-4bb91af7-b79f-418a-be14-8eb754574f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655976679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1655976679
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3141214571
Short name T76
Test name
Test status
Simulation time 266167276 ps
CPU time 14.74 seconds
Started Aug 05 04:33:45 PM PDT 24
Finished Aug 05 04:34:00 PM PDT 24
Peak memory 214872 kb
Host smart-5117cc2a-179b-4a18-9c0c-35f854172813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141214571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3141214571
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.648397085
Short name T854
Test name
Test status
Simulation time 50105145 ps
CPU time 3.34 seconds
Started Aug 05 04:33:45 PM PDT 24
Finished Aug 05 04:33:48 PM PDT 24
Peak memory 207316 kb
Host smart-c175275f-57a2-418e-b18e-f535ccebf70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648397085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.648397085
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1539874129
Short name T41
Test name
Test status
Simulation time 247058608 ps
CPU time 2.45 seconds
Started Aug 05 04:33:43 PM PDT 24
Finished Aug 05 04:33:46 PM PDT 24
Peak memory 209704 kb
Host smart-de788a70-06bf-4fae-baf8-6afb93f9d837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539874129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1539874129
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3436786393
Short name T855
Test name
Test status
Simulation time 39933225 ps
CPU time 0.83 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:33:52 PM PDT 24
Peak memory 205816 kb
Host smart-6ee3f4d8-2659-4707-8d5f-d49c3f7967a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436786393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3436786393
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.959779323
Short name T802
Test name
Test status
Simulation time 197408632 ps
CPU time 5.9 seconds
Started Aug 05 04:33:49 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 214212 kb
Host smart-6668ac3d-8f06-4a13-a146-d209ffcc6f6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=959779323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.959779323
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3805866203
Short name T8
Test name
Test status
Simulation time 262223109 ps
CPU time 2.41 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:33:53 PM PDT 24
Peak memory 218276 kb
Host smart-875105f5-f07b-43cc-a4fb-53d6892735cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805866203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3805866203
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3511879124
Short name T473
Test name
Test status
Simulation time 84977162 ps
CPU time 2.63 seconds
Started Aug 05 04:33:46 PM PDT 24
Finished Aug 05 04:33:48 PM PDT 24
Peak memory 208428 kb
Host smart-1b223bc6-3664-48b1-af21-980dad512389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511879124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3511879124
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.8721347
Short name T783
Test name
Test status
Simulation time 135798022 ps
CPU time 4.98 seconds
Started Aug 05 04:33:41 PM PDT 24
Finished Aug 05 04:33:46 PM PDT 24
Peak memory 209200 kb
Host smart-07881806-735e-45c5-83b7-d8429ca9fd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8721347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.8721347
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3157755816
Short name T284
Test name
Test status
Simulation time 105712282 ps
CPU time 4.5 seconds
Started Aug 05 04:33:44 PM PDT 24
Finished Aug 05 04:33:49 PM PDT 24
Peak memory 214112 kb
Host smart-71d50591-935f-42a1-b36b-29f28595578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157755816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3157755816
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2328689058
Short name T215
Test name
Test status
Simulation time 219556627 ps
CPU time 2.82 seconds
Started Aug 05 04:33:44 PM PDT 24
Finished Aug 05 04:33:47 PM PDT 24
Peak memory 214260 kb
Host smart-371e20ff-b6dc-44d1-8c30-3584db9b89b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328689058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2328689058
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1658131476
Short name T557
Test name
Test status
Simulation time 198323639 ps
CPU time 4.66 seconds
Started Aug 05 04:34:03 PM PDT 24
Finished Aug 05 04:34:08 PM PDT 24
Peak memory 207928 kb
Host smart-301405fd-104f-4ea6-aba3-79901100f4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658131476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1658131476
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.214663719
Short name T819
Test name
Test status
Simulation time 64640632 ps
CPU time 2.99 seconds
Started Aug 05 04:34:11 PM PDT 24
Finished Aug 05 04:34:14 PM PDT 24
Peak memory 208372 kb
Host smart-47f327a3-333f-4301-868f-71f1c695c03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214663719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.214663719
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.39397436
Short name T596
Test name
Test status
Simulation time 78116936 ps
CPU time 3.43 seconds
Started Aug 05 04:33:49 PM PDT 24
Finished Aug 05 04:33:52 PM PDT 24
Peak memory 208600 kb
Host smart-2e0c415a-3f14-4463-b24c-55253161e471
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39397436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.39397436
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1853471193
Short name T471
Test name
Test status
Simulation time 108272564 ps
CPU time 2.4 seconds
Started Aug 05 04:33:42 PM PDT 24
Finished Aug 05 04:33:44 PM PDT 24
Peak memory 209052 kb
Host smart-e81d51a7-7e98-4481-b68c-14f06e479857
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853471193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1853471193
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.330362281
Short name T830
Test name
Test status
Simulation time 79028612 ps
CPU time 2.84 seconds
Started Aug 05 04:33:49 PM PDT 24
Finished Aug 05 04:33:52 PM PDT 24
Peak memory 206764 kb
Host smart-4c571ebd-6367-49b2-9376-58a148bc103b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330362281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.330362281
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2967746648
Short name T593
Test name
Test status
Simulation time 88956073 ps
CPU time 3.88 seconds
Started Aug 05 04:33:50 PM PDT 24
Finished Aug 05 04:33:54 PM PDT 24
Peak memory 214288 kb
Host smart-c2303d98-2cb3-4e96-a8a7-30937e3d089a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967746648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2967746648
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2447253751
Short name T485
Test name
Test status
Simulation time 189181533 ps
CPU time 5.7 seconds
Started Aug 05 04:33:44 PM PDT 24
Finished Aug 05 04:33:49 PM PDT 24
Peak memory 208364 kb
Host smart-20464e56-7df5-4c38-afdf-36d0cb3faf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447253751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2447253751
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1525147281
Short name T688
Test name
Test status
Simulation time 1156625399 ps
CPU time 26.36 seconds
Started Aug 05 04:33:47 PM PDT 24
Finished Aug 05 04:34:14 PM PDT 24
Peak memory 216648 kb
Host smart-dc330d8e-1412-45d0-8232-6b5c81878151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525147281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1525147281
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1919937880
Short name T250
Test name
Test status
Simulation time 86173409 ps
CPU time 4.27 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 209924 kb
Host smart-bea30848-653b-42f9-a8be-83b8c4568094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919937880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1919937880
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1476393880
Short name T874
Test name
Test status
Simulation time 57613828 ps
CPU time 1.4 seconds
Started Aug 05 04:33:47 PM PDT 24
Finished Aug 05 04:33:49 PM PDT 24
Peak memory 209764 kb
Host smart-35d858d0-4892-451d-aa0d-21d6ea01eac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476393880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1476393880
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.510901589
Short name T508
Test name
Test status
Simulation time 11899264 ps
CPU time 0.87 seconds
Started Aug 05 04:34:00 PM PDT 24
Finished Aug 05 04:34:01 PM PDT 24
Peak memory 205828 kb
Host smart-cc1f4eca-48e6-40e2-ba86-21e4031b0f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510901589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.510901589
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3547507366
Short name T230
Test name
Test status
Simulation time 866845399 ps
CPU time 10.73 seconds
Started Aug 05 04:33:46 PM PDT 24
Finished Aug 05 04:33:57 PM PDT 24
Peak memory 222284 kb
Host smart-b8c2e0ab-6935-479c-ad71-218de906d321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3547507366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3547507366
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.228040680
Short name T287
Test name
Test status
Simulation time 123494377 ps
CPU time 2.48 seconds
Started Aug 05 04:34:06 PM PDT 24
Finished Aug 05 04:34:09 PM PDT 24
Peak memory 209620 kb
Host smart-76bb1ab1-d34c-410b-a23e-eeeef70c82c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228040680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.228040680
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.4132588163
Short name T97
Test name
Test status
Simulation time 476211035 ps
CPU time 4.87 seconds
Started Aug 05 04:33:35 PM PDT 24
Finished Aug 05 04:33:40 PM PDT 24
Peak memory 214164 kb
Host smart-d7f648cd-5d37-41c3-b643-3b86165be745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132588163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.4132588163
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3823820874
Short name T695
Test name
Test status
Simulation time 285523703 ps
CPU time 7.96 seconds
Started Aug 05 04:33:50 PM PDT 24
Finished Aug 05 04:33:59 PM PDT 24
Peak memory 214416 kb
Host smart-104927fa-90ec-4142-8dda-93ea728d03d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823820874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3823820874
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1900288832
Short name T53
Test name
Test status
Simulation time 94797812 ps
CPU time 3.07 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 214584 kb
Host smart-3bcfbf48-7e48-4387-aeff-b97ac097a83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900288832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1900288832
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.963389127
Short name T548
Test name
Test status
Simulation time 94710967 ps
CPU time 4.17 seconds
Started Aug 05 04:33:54 PM PDT 24
Finished Aug 05 04:33:58 PM PDT 24
Peak memory 214108 kb
Host smart-8e167aa6-2f5d-4fe5-a026-99fffadb2df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963389127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.963389127
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2874017125
Short name T336
Test name
Test status
Simulation time 499560301 ps
CPU time 14.61 seconds
Started Aug 05 04:33:43 PM PDT 24
Finished Aug 05 04:33:57 PM PDT 24
Peak memory 208292 kb
Host smart-466eb5c1-5a95-42b8-bec1-3940a14025f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874017125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2874017125
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3123211661
Short name T763
Test name
Test status
Simulation time 77203457 ps
CPU time 3.57 seconds
Started Aug 05 04:33:56 PM PDT 24
Finished Aug 05 04:34:00 PM PDT 24
Peak memory 208564 kb
Host smart-163114b7-bca5-4dc3-aceb-7038d7ce7318
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123211661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3123211661
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1259719543
Short name T641
Test name
Test status
Simulation time 100475589 ps
CPU time 2.74 seconds
Started Aug 05 04:33:41 PM PDT 24
Finished Aug 05 04:33:45 PM PDT 24
Peak memory 206904 kb
Host smart-8836fe78-7d41-4bfe-a045-83ed69f5f7e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259719543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1259719543
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.610622026
Short name T628
Test name
Test status
Simulation time 895641316 ps
CPU time 6.19 seconds
Started Aug 05 04:33:47 PM PDT 24
Finished Aug 05 04:33:53 PM PDT 24
Peak memory 208468 kb
Host smart-fdc36fa0-2faa-4c42-b6f0-961e0e2fec19
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610622026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.610622026
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2864510630
Short name T710
Test name
Test status
Simulation time 152122288 ps
CPU time 2.66 seconds
Started Aug 05 04:33:40 PM PDT 24
Finished Aug 05 04:33:43 PM PDT 24
Peak memory 207424 kb
Host smart-7b8c5cf5-5676-4f0e-a6bf-b6fa647a9b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864510630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2864510630
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2695512531
Short name T195
Test name
Test status
Simulation time 108808964 ps
CPU time 3.86 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 208844 kb
Host smart-d1329785-dc2a-4b88-a56d-82e8a7e27724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695512531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2695512531
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2277755428
Short name T492
Test name
Test status
Simulation time 1089235690 ps
CPU time 31.95 seconds
Started Aug 05 04:33:53 PM PDT 24
Finished Aug 05 04:34:25 PM PDT 24
Peak memory 208364 kb
Host smart-8e8ba189-c2bb-4935-b56c-10a92f5f922c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277755428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2277755428
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2642063984
Short name T730
Test name
Test status
Simulation time 38962495 ps
CPU time 0.72 seconds
Started Aug 05 04:34:17 PM PDT 24
Finished Aug 05 04:34:18 PM PDT 24
Peak memory 205808 kb
Host smart-e5d6c81d-b899-4803-a274-fe77898d93f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642063984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2642063984
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3849195622
Short name T327
Test name
Test status
Simulation time 90998656 ps
CPU time 5.51 seconds
Started Aug 05 04:34:01 PM PDT 24
Finished Aug 05 04:34:07 PM PDT 24
Peak memory 214956 kb
Host smart-0b68711a-e3d1-4370-9d64-a500671bf20e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849195622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3849195622
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3510331425
Short name T20
Test name
Test status
Simulation time 139377497 ps
CPU time 2.57 seconds
Started Aug 05 04:33:54 PM PDT 24
Finished Aug 05 04:33:56 PM PDT 24
Peak memory 221040 kb
Host smart-25536078-9df3-4575-ba90-0dcdc3634787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510331425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3510331425
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3019769551
Short name T746
Test name
Test status
Simulation time 415137430 ps
CPU time 3.51 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:01 PM PDT 24
Peak memory 209332 kb
Host smart-7dad5e42-5343-4369-9417-ebec39b6220b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019769551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3019769551
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3332149386
Short name T751
Test name
Test status
Simulation time 34590250 ps
CPU time 2.33 seconds
Started Aug 05 04:33:42 PM PDT 24
Finished Aug 05 04:33:44 PM PDT 24
Peak memory 214148 kb
Host smart-6af4f95d-a5f4-4e5a-a1c6-00e4a6d6b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332149386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3332149386
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3133948606
Short name T656
Test name
Test status
Simulation time 24592253 ps
CPU time 1.93 seconds
Started Aug 05 04:33:54 PM PDT 24
Finished Aug 05 04:33:56 PM PDT 24
Peak memory 218228 kb
Host smart-0bdb9542-f1f7-4288-b382-f52bd8b0baba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133948606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3133948606
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2944537959
Short name T615
Test name
Test status
Simulation time 810128500 ps
CPU time 24.8 seconds
Started Aug 05 04:33:49 PM PDT 24
Finished Aug 05 04:34:14 PM PDT 24
Peak memory 208580 kb
Host smart-74a1df12-2d0e-43db-85eb-c2ebfe83a2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944537959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2944537959
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.60449814
Short name T297
Test name
Test status
Simulation time 144060226 ps
CPU time 5.22 seconds
Started Aug 05 04:33:53 PM PDT 24
Finished Aug 05 04:33:59 PM PDT 24
Peak memory 206880 kb
Host smart-0cea1bbe-64ed-4b7a-848d-c8d7c905769b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60449814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.60449814
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3987007361
Short name T894
Test name
Test status
Simulation time 191957606 ps
CPU time 4.42 seconds
Started Aug 05 04:33:50 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 208560 kb
Host smart-fb3a9764-4239-4994-92c7-0a896a70442f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987007361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3987007361
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3979939302
Short name T702
Test name
Test status
Simulation time 21014315 ps
CPU time 1.75 seconds
Started Aug 05 04:33:53 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 206800 kb
Host smart-17c9cd61-0fb8-4d6f-bedc-8f099a74b3c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979939302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3979939302
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.38140298
Short name T126
Test name
Test status
Simulation time 379837116 ps
CPU time 2.8 seconds
Started Aug 05 04:33:34 PM PDT 24
Finished Aug 05 04:33:37 PM PDT 24
Peak memory 209152 kb
Host smart-8599c79f-3b66-4a12-bc3b-f6725f9bfb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38140298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.38140298
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1506060845
Short name T17
Test name
Test status
Simulation time 33021533 ps
CPU time 2.28 seconds
Started Aug 05 04:34:03 PM PDT 24
Finished Aug 05 04:34:06 PM PDT 24
Peak memory 208264 kb
Host smart-29a783e1-2556-4b62-8756-b551e7288c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506060845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1506060845
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.158730482
Short name T235
Test name
Test status
Simulation time 304247853 ps
CPU time 14.87 seconds
Started Aug 05 04:34:04 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 216168 kb
Host smart-723e7cb7-cb6a-4ab5-9d32-8ad7dc8ff2f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158730482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.158730482
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.4290917492
Short name T179
Test name
Test status
Simulation time 229459486 ps
CPU time 8.68 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:34:00 PM PDT 24
Peak memory 222332 kb
Host smart-fe07fcc6-9b87-4abf-9541-37fcd74fd878
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290917492 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.4290917492
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2703276706
Short name T675
Test name
Test status
Simulation time 77633930 ps
CPU time 3.94 seconds
Started Aug 05 04:34:15 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 208876 kb
Host smart-14a42809-c580-4550-be13-bd6b4edd5c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703276706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2703276706
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2147444267
Short name T159
Test name
Test status
Simulation time 213294530 ps
CPU time 2.38 seconds
Started Aug 05 04:33:55 PM PDT 24
Finished Aug 05 04:33:57 PM PDT 24
Peak memory 209968 kb
Host smart-e2dce896-b5a6-4c51-8f6e-8350278009f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147444267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2147444267
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3110751421
Short name T468
Test name
Test status
Simulation time 23547817 ps
CPU time 0.75 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:33:52 PM PDT 24
Peak memory 205932 kb
Host smart-5aa6b670-5521-4ec2-9f99-e6352b1ca2c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110751421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3110751421
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1858764690
Short name T14
Test name
Test status
Simulation time 343958592 ps
CPU time 3.88 seconds
Started Aug 05 04:33:43 PM PDT 24
Finished Aug 05 04:33:47 PM PDT 24
Peak memory 214604 kb
Host smart-433f690a-e48e-4f6a-8d0f-dfb066155bd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858764690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1858764690
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.663098209
Short name T681
Test name
Test status
Simulation time 89892820 ps
CPU time 2.52 seconds
Started Aug 05 04:34:00 PM PDT 24
Finished Aug 05 04:34:02 PM PDT 24
Peak memory 216600 kb
Host smart-df354507-ca99-4979-907e-5e1f05d815a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663098209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.663098209
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2860779384
Short name T663
Test name
Test status
Simulation time 155340378 ps
CPU time 2.73 seconds
Started Aug 05 04:33:56 PM PDT 24
Finished Aug 05 04:33:59 PM PDT 24
Peak memory 207968 kb
Host smart-4842339d-519b-40b0-b11e-ee510814a994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860779384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2860779384
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1408551115
Short name T322
Test name
Test status
Simulation time 479006566 ps
CPU time 4.67 seconds
Started Aug 05 04:33:40 PM PDT 24
Finished Aug 05 04:33:45 PM PDT 24
Peak memory 222280 kb
Host smart-271426e6-7f3e-4df0-870e-b9fbb51de063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408551115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1408551115
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.483316925
Short name T213
Test name
Test status
Simulation time 1288029825 ps
CPU time 7.7 seconds
Started Aug 05 04:33:53 PM PDT 24
Finished Aug 05 04:34:01 PM PDT 24
Peak memory 222344 kb
Host smart-22f5af41-8d75-4483-bebd-649df1e97f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483316925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.483316925
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2077032777
Short name T343
Test name
Test status
Simulation time 264660383 ps
CPU time 3.68 seconds
Started Aug 05 04:33:49 PM PDT 24
Finished Aug 05 04:33:53 PM PDT 24
Peak memory 210340 kb
Host smart-c7d4fd91-dfad-4b59-92ea-0d4ac886f30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077032777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2077032777
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3096217541
Short name T674
Test name
Test status
Simulation time 601918895 ps
CPU time 4.23 seconds
Started Aug 05 04:33:53 PM PDT 24
Finished Aug 05 04:33:57 PM PDT 24
Peak memory 207672 kb
Host smart-3c2fbe7e-5dfa-469c-98c0-a1876f674c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096217541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3096217541
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2491402892
Short name T662
Test name
Test status
Simulation time 239574470 ps
CPU time 3.19 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:33:54 PM PDT 24
Peak memory 208772 kb
Host smart-f236675c-61ad-49e8-acc1-4d64c30c4e59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491402892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2491402892
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.982022088
Short name T667
Test name
Test status
Simulation time 109691140 ps
CPU time 2.62 seconds
Started Aug 05 04:33:47 PM PDT 24
Finished Aug 05 04:33:54 PM PDT 24
Peak memory 208636 kb
Host smart-487ad5f3-81a0-43ce-b13d-647017370665
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982022088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.982022088
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1286933740
Short name T755
Test name
Test status
Simulation time 222228376 ps
CPU time 2.87 seconds
Started Aug 05 04:34:04 PM PDT 24
Finished Aug 05 04:34:07 PM PDT 24
Peak memory 208320 kb
Host smart-cccbf4ca-0595-40e7-9fc0-74e0a8fa6b61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286933740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1286933740
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3241081785
Short name T275
Test name
Test status
Simulation time 2097080848 ps
CPU time 9.08 seconds
Started Aug 05 04:33:45 PM PDT 24
Finished Aug 05 04:33:54 PM PDT 24
Peak memory 209084 kb
Host smart-71563cbb-d224-4a4d-9349-afededeb4fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241081785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3241081785
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3461428491
Short name T398
Test name
Test status
Simulation time 79000792 ps
CPU time 2.61 seconds
Started Aug 05 04:33:56 PM PDT 24
Finished Aug 05 04:33:58 PM PDT 24
Peak memory 206784 kb
Host smart-1e0c4954-84e5-4f40-80a4-5ca2d161fded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461428491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3461428491
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1979549068
Short name T709
Test name
Test status
Simulation time 225033892 ps
CPU time 2.8 seconds
Started Aug 05 04:33:47 PM PDT 24
Finished Aug 05 04:33:50 PM PDT 24
Peak memory 208396 kb
Host smart-90e4759f-306d-43e1-a8de-e139de51771a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979549068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1979549068
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1099914162
Short name T594
Test name
Test status
Simulation time 613564348 ps
CPU time 9.08 seconds
Started Aug 05 04:33:47 PM PDT 24
Finished Aug 05 04:33:56 PM PDT 24
Peak memory 222392 kb
Host smart-7a2f9960-fc4b-4989-bbc5-b5ea7d4b02cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099914162 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1099914162
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1428024775
Short name T822
Test name
Test status
Simulation time 190130509 ps
CPU time 4.68 seconds
Started Aug 05 04:33:46 PM PDT 24
Finished Aug 05 04:33:51 PM PDT 24
Peak memory 214176 kb
Host smart-0e89aa9c-1fc6-41eb-906d-8adc8e9093a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428024775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1428024775
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1324650194
Short name T895
Test name
Test status
Simulation time 72841188 ps
CPU time 2.24 seconds
Started Aug 05 04:33:50 PM PDT 24
Finished Aug 05 04:33:53 PM PDT 24
Peak memory 210084 kb
Host smart-89a5f8bd-9074-4dc0-9e0a-5c62a58b8e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324650194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1324650194
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1079448204
Short name T16
Test name
Test status
Simulation time 17555402 ps
CPU time 0.81 seconds
Started Aug 05 04:33:53 PM PDT 24
Finished Aug 05 04:33:54 PM PDT 24
Peak memory 205792 kb
Host smart-6347e4ce-d226-4371-8b9f-fd4ac21a3cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079448204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1079448204
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.4082273208
Short name T396
Test name
Test status
Simulation time 66604588 ps
CPU time 2.63 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:33:59 PM PDT 24
Peak memory 214224 kb
Host smart-0f0cba3f-8d51-4c47-81bb-091ad7fb438d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4082273208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.4082273208
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2842248451
Short name T765
Test name
Test status
Simulation time 158360448 ps
CPU time 3.65 seconds
Started Aug 05 04:33:56 PM PDT 24
Finished Aug 05 04:34:00 PM PDT 24
Peak memory 214192 kb
Host smart-2375a90b-3472-40da-91a5-b992229363fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842248451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2842248451
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.63854974
Short name T367
Test name
Test status
Simulation time 41396210 ps
CPU time 2.91 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:33:54 PM PDT 24
Peak memory 214208 kb
Host smart-72753b8c-a5ea-48d2-b47d-f39c347345cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63854974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.63854974
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1809995889
Short name T38
Test name
Test status
Simulation time 70143805 ps
CPU time 1.93 seconds
Started Aug 05 04:34:10 PM PDT 24
Finished Aug 05 04:34:12 PM PDT 24
Peak memory 214112 kb
Host smart-486d2285-4d29-4312-829f-5cecb9dd1c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809995889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1809995889
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3312872697
Short name T66
Test name
Test status
Simulation time 183344216 ps
CPU time 5.07 seconds
Started Aug 05 04:34:11 PM PDT 24
Finished Aug 05 04:34:16 PM PDT 24
Peak memory 222416 kb
Host smart-fa463127-ff10-4afa-93eb-a2a7680eb3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312872697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3312872697
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1981260002
Short name T233
Test name
Test status
Simulation time 150576263 ps
CPU time 3.02 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:33:54 PM PDT 24
Peak memory 207764 kb
Host smart-c9d9b24d-1beb-4931-b458-ed7ecf8470ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981260002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1981260002
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1389067062
Short name T370
Test name
Test status
Simulation time 2050110800 ps
CPU time 27.46 seconds
Started Aug 05 04:34:02 PM PDT 24
Finished Aug 05 04:34:30 PM PDT 24
Peak memory 208432 kb
Host smart-cb904f3f-ecdd-4937-bb4d-bd234f147269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389067062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1389067062
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.388055597
Short name T12
Test name
Test status
Simulation time 87859554 ps
CPU time 2.56 seconds
Started Aug 05 04:34:12 PM PDT 24
Finished Aug 05 04:34:15 PM PDT 24
Peak memory 208540 kb
Host smart-64b84162-b911-4a58-ab5e-b76e18bc15d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388055597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.388055597
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3382913027
Short name T910
Test name
Test status
Simulation time 86034149 ps
CPU time 2.99 seconds
Started Aug 05 04:34:25 PM PDT 24
Finished Aug 05 04:34:29 PM PDT 24
Peak memory 206796 kb
Host smart-70a5417d-17d9-4c29-b149-803c2ad4df53
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382913027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3382913027
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.704772905
Short name T371
Test name
Test status
Simulation time 176188404 ps
CPU time 5.61 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:13 PM PDT 24
Peak memory 208632 kb
Host smart-1d493ca5-7657-4aa9-9c82-191f1c172e24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704772905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.704772905
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3901190641
Short name T705
Test name
Test status
Simulation time 135647262 ps
CPU time 3.65 seconds
Started Aug 05 04:33:50 PM PDT 24
Finished Aug 05 04:33:54 PM PDT 24
Peak memory 209676 kb
Host smart-cbc0b61b-e24c-4444-b9f5-6adf54645d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901190641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3901190641
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.466986623
Short name T542
Test name
Test status
Simulation time 470488825 ps
CPU time 4.56 seconds
Started Aug 05 04:34:05 PM PDT 24
Finished Aug 05 04:34:09 PM PDT 24
Peak memory 206616 kb
Host smart-26937fb4-a0c8-41c7-b4eb-b407b5e984ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466986623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.466986623
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3175501258
Short name T651
Test name
Test status
Simulation time 278279049 ps
CPU time 7.97 seconds
Started Aug 05 04:33:55 PM PDT 24
Finished Aug 05 04:34:03 PM PDT 24
Peak memory 222336 kb
Host smart-1ab77be6-887b-460d-8048-38e99f626e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175501258 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3175501258
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2620455451
Short name T460
Test name
Test status
Simulation time 1357709176 ps
CPU time 8.98 seconds
Started Aug 05 04:33:55 PM PDT 24
Finished Aug 05 04:34:04 PM PDT 24
Peak memory 218360 kb
Host smart-3b35d2a3-653c-475e-a730-8a4c8e379f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620455451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2620455451
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.4294306347
Short name T652
Test name
Test status
Simulation time 214667829 ps
CPU time 2.12 seconds
Started Aug 05 04:34:21 PM PDT 24
Finished Aug 05 04:34:23 PM PDT 24
Peak memory 210040 kb
Host smart-ea794737-c697-4a48-a3dc-e4d130711687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294306347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.4294306347
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3927934589
Short name T461
Test name
Test status
Simulation time 10600835 ps
CPU time 0.78 seconds
Started Aug 05 04:33:49 PM PDT 24
Finished Aug 05 04:33:50 PM PDT 24
Peak memory 205816 kb
Host smart-1e51dfe0-f0ce-4bf2-94c7-e601181ed7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927934589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3927934589
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1093147755
Short name T416
Test name
Test status
Simulation time 1136424622 ps
CPU time 4.47 seconds
Started Aug 05 04:34:07 PM PDT 24
Finished Aug 05 04:34:11 PM PDT 24
Peak memory 222328 kb
Host smart-c0d6d5e5-4b9e-48a2-80d8-2d22c4f34c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093147755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1093147755
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3062097149
Short name T385
Test name
Test status
Simulation time 102185571 ps
CPU time 2.68 seconds
Started Aug 05 04:33:56 PM PDT 24
Finished Aug 05 04:33:59 PM PDT 24
Peak memory 214212 kb
Host smart-5c86794e-9b47-4ca8-86ef-778f68a2af60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062097149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3062097149
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3936081038
Short name T735
Test name
Test status
Simulation time 401854495 ps
CPU time 2.99 seconds
Started Aug 05 04:33:58 PM PDT 24
Finished Aug 05 04:34:02 PM PDT 24
Peak memory 219564 kb
Host smart-494caf97-af0e-440c-8558-0509f2c2e7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936081038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3936081038
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2300793546
Short name T231
Test name
Test status
Simulation time 38929901 ps
CPU time 2.79 seconds
Started Aug 05 04:33:53 PM PDT 24
Finished Aug 05 04:33:56 PM PDT 24
Peak memory 208084 kb
Host smart-a869e66a-29fb-4949-a1ff-89517d3ce81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300793546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2300793546
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.38992329
Short name T352
Test name
Test status
Simulation time 11518083809 ps
CPU time 39.21 seconds
Started Aug 05 04:34:04 PM PDT 24
Finished Aug 05 04:34:43 PM PDT 24
Peak memory 209012 kb
Host smart-c032906f-47b8-4bc6-98e3-e26c767ef046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38992329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.38992329
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.4127374286
Short name T249
Test name
Test status
Simulation time 84384569 ps
CPU time 3.9 seconds
Started Aug 05 04:34:04 PM PDT 24
Finished Aug 05 04:34:08 PM PDT 24
Peak memory 208468 kb
Host smart-f4673940-0a85-41c9-b7e4-d32d2511de39
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127374286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.4127374286
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4276416109
Short name T469
Test name
Test status
Simulation time 380065092 ps
CPU time 11.7 seconds
Started Aug 05 04:34:04 PM PDT 24
Finished Aug 05 04:34:16 PM PDT 24
Peak memory 207732 kb
Host smart-5efec52d-0aaf-4a4f-9d69-a200ae3e3084
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276416109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4276416109
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3450975631
Short name T493
Test name
Test status
Simulation time 139204108 ps
CPU time 3.3 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:00 PM PDT 24
Peak memory 208248 kb
Host smart-9da24390-334b-436f-a1f6-9a869cbe8ace
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450975631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3450975631
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2290056300
Short name T784
Test name
Test status
Simulation time 144889069 ps
CPU time 4.19 seconds
Started Aug 05 04:34:04 PM PDT 24
Finished Aug 05 04:34:08 PM PDT 24
Peak memory 218624 kb
Host smart-1dea66bb-4e9d-4bf4-b229-f059e820f2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290056300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2290056300
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2854864037
Short name T490
Test name
Test status
Simulation time 554692412 ps
CPU time 3.86 seconds
Started Aug 05 04:34:07 PM PDT 24
Finished Aug 05 04:34:11 PM PDT 24
Peak memory 208444 kb
Host smart-89ea74e9-af49-4104-938e-4ea5a4568ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854864037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2854864037
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.394059556
Short name T832
Test name
Test status
Simulation time 690987855 ps
CPU time 17.67 seconds
Started Aug 05 04:34:03 PM PDT 24
Finished Aug 05 04:34:21 PM PDT 24
Peak memory 222400 kb
Host smart-6698a0cd-1afd-454c-884d-d15d9263aa42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394059556 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.394059556
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2194339068
Short name T575
Test name
Test status
Simulation time 2324239524 ps
CPU time 49.12 seconds
Started Aug 05 04:33:50 PM PDT 24
Finished Aug 05 04:34:39 PM PDT 24
Peak memory 208188 kb
Host smart-b26ee6b9-c9f5-4d23-88d1-e5334034a3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194339068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2194339068
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3618505660
Short name T712
Test name
Test status
Simulation time 336637609 ps
CPU time 3.74 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:33:55 PM PDT 24
Peak memory 210276 kb
Host smart-444372a7-9a4b-47dd-8cf4-c95dd24e1f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618505660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3618505660
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.740821962
Short name T686
Test name
Test status
Simulation time 11601274 ps
CPU time 0.87 seconds
Started Aug 05 04:32:52 PM PDT 24
Finished Aug 05 04:32:53 PM PDT 24
Peak memory 205772 kb
Host smart-a3bfd7be-c52e-4335-baa6-bad64f09e319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740821962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.740821962
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1135008185
Short name T350
Test name
Test status
Simulation time 318505815 ps
CPU time 8.53 seconds
Started Aug 05 04:32:58 PM PDT 24
Finished Aug 05 04:33:12 PM PDT 24
Peak memory 214276 kb
Host smart-5bf00468-f4f7-4fd3-a396-76691d2f53a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135008185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1135008185
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.6152165
Short name T570
Test name
Test status
Simulation time 767255690 ps
CPU time 2.83 seconds
Started Aug 05 04:32:51 PM PDT 24
Finished Aug 05 04:32:54 PM PDT 24
Peak memory 208788 kb
Host smart-3cc4302a-e47e-4e0b-bcd6-35e475ecbd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6152165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.6152165
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3924207624
Short name T613
Test name
Test status
Simulation time 103105505 ps
CPU time 2.46 seconds
Started Aug 05 04:33:08 PM PDT 24
Finished Aug 05 04:33:11 PM PDT 24
Peak memory 222364 kb
Host smart-550ad063-0ae0-4d53-837b-b494e7739356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924207624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3924207624
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1628287623
Short name T707
Test name
Test status
Simulation time 629346339 ps
CPU time 2.1 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 215184 kb
Host smart-628f87b2-bd28-4ba2-b8bb-c90a84c61d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628287623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1628287623
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2219812387
Short name T734
Test name
Test status
Simulation time 536817599 ps
CPU time 6.28 seconds
Started Aug 05 04:32:58 PM PDT 24
Finished Aug 05 04:33:05 PM PDT 24
Peak memory 209688 kb
Host smart-a6fbea15-b47d-4575-85c0-d331c346a6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219812387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2219812387
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3998651765
Short name T43
Test name
Test status
Simulation time 946210563 ps
CPU time 9.63 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:11 PM PDT 24
Peak memory 233608 kb
Host smart-bf9b64de-0c0b-4282-8d97-94c987446257
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998651765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3998651765
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1607747262
Short name T544
Test name
Test status
Simulation time 400555087 ps
CPU time 2.98 seconds
Started Aug 05 04:32:54 PM PDT 24
Finished Aug 05 04:32:57 PM PDT 24
Peak memory 208392 kb
Host smart-344fcb83-e19d-42fc-a6f3-dc6015783d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607747262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1607747262
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3829915954
Short name T186
Test name
Test status
Simulation time 214314022 ps
CPU time 5.7 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:05 PM PDT 24
Peak memory 207660 kb
Host smart-f8215a1e-6f0a-4fa7-9222-9340773b6a80
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829915954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3829915954
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1896959872
Short name T406
Test name
Test status
Simulation time 822417925 ps
CPU time 5.86 seconds
Started Aug 05 04:32:54 PM PDT 24
Finished Aug 05 04:33:00 PM PDT 24
Peak memory 207760 kb
Host smart-e33fafd0-0e2c-4d5c-a1c3-03de8a6f7c15
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896959872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1896959872
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.4012892438
Short name T646
Test name
Test status
Simulation time 169639458 ps
CPU time 6.02 seconds
Started Aug 05 04:32:56 PM PDT 24
Finished Aug 05 04:33:02 PM PDT 24
Peak memory 208116 kb
Host smart-43ceed36-3113-464d-9228-8e5621ca89c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012892438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4012892438
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2084481451
Short name T513
Test name
Test status
Simulation time 298673258 ps
CPU time 10.33 seconds
Started Aug 05 04:32:51 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 214124 kb
Host smart-6396dc71-bd6b-49f9-a3a6-dc765f22921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084481451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2084481451
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3921553853
Short name T795
Test name
Test status
Simulation time 3498143155 ps
CPU time 17.52 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:18 PM PDT 24
Peak memory 207948 kb
Host smart-cc036429-c429-4299-ac55-344c778b9be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921553853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3921553853
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3577463301
Short name T306
Test name
Test status
Simulation time 537572543 ps
CPU time 26.52 seconds
Started Aug 05 04:32:52 PM PDT 24
Finished Aug 05 04:33:18 PM PDT 24
Peak memory 222560 kb
Host smart-41c39d3a-9688-4b20-8a22-25a81a8fbd21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577463301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3577463301
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.4094761231
Short name T522
Test name
Test status
Simulation time 80415196 ps
CPU time 2.51 seconds
Started Aug 05 04:32:44 PM PDT 24
Finished Aug 05 04:32:47 PM PDT 24
Peak memory 207908 kb
Host smart-3cb15009-c69b-47fb-9683-20e3b9784aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094761231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.4094761231
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.556561499
Short name T407
Test name
Test status
Simulation time 279162518 ps
CPU time 6.37 seconds
Started Aug 05 04:32:53 PM PDT 24
Finished Aug 05 04:33:00 PM PDT 24
Peak memory 210840 kb
Host smart-d45d579c-2e45-497c-ac78-e6e3d80f108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556561499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.556561499
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3810496901
Short name T476
Test name
Test status
Simulation time 11969888 ps
CPU time 0.78 seconds
Started Aug 05 04:33:52 PM PDT 24
Finished Aug 05 04:33:52 PM PDT 24
Peak memory 205788 kb
Host smart-c9c2a31f-4fdd-4882-95d7-dfc8a4ace7bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810496901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3810496901
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.4040987279
Short name T424
Test name
Test status
Simulation time 749903715 ps
CPU time 37.57 seconds
Started Aug 05 04:34:10 PM PDT 24
Finished Aug 05 04:34:47 PM PDT 24
Peak memory 215616 kb
Host smart-1002f9c6-2855-47b5-a05b-e3957abcd6f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040987279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.4040987279
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3727932972
Short name T607
Test name
Test status
Simulation time 112717415 ps
CPU time 4.95 seconds
Started Aug 05 04:34:06 PM PDT 24
Finished Aug 05 04:34:11 PM PDT 24
Peak memory 214340 kb
Host smart-2f934da8-5c44-49e8-9087-6364de15b770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727932972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3727932972
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2260284988
Short name T807
Test name
Test status
Simulation time 61138012 ps
CPU time 2.75 seconds
Started Aug 05 04:33:59 PM PDT 24
Finished Aug 05 04:34:02 PM PDT 24
Peak memory 208076 kb
Host smart-3d77afe7-cffd-4258-a8dd-e80ff78e48f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260284988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2260284988
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3483377168
Short name T335
Test name
Test status
Simulation time 201448299 ps
CPU time 2.77 seconds
Started Aug 05 04:34:11 PM PDT 24
Finished Aug 05 04:34:14 PM PDT 24
Peak memory 208296 kb
Host smart-49ea5512-6e91-464f-af84-d47e9e6d004e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483377168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3483377168
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2760651425
Short name T639
Test name
Test status
Simulation time 102617435 ps
CPU time 4.09 seconds
Started Aug 05 04:34:09 PM PDT 24
Finished Aug 05 04:34:13 PM PDT 24
Peak memory 214124 kb
Host smart-91dbd931-756f-485a-a809-43062098dbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760651425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2760651425
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_random.4142362750
Short name T380
Test name
Test status
Simulation time 198331399 ps
CPU time 4.89 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:02 PM PDT 24
Peak memory 214192 kb
Host smart-fa256453-ed74-4509-8442-24b4feb886f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142362750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.4142362750
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1159851258
Short name T829
Test name
Test status
Simulation time 909930081 ps
CPU time 3.8 seconds
Started Aug 05 04:33:45 PM PDT 24
Finished Aug 05 04:33:49 PM PDT 24
Peak memory 208924 kb
Host smart-63587fdf-f063-4a40-bbfc-398f0e16ddb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159851258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1159851258
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1131300601
Short name T356
Test name
Test status
Simulation time 2156795425 ps
CPU time 8.5 seconds
Started Aug 05 04:33:48 PM PDT 24
Finished Aug 05 04:33:56 PM PDT 24
Peak memory 208544 kb
Host smart-35076aca-0c75-4104-8560-c812fa146f3a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131300601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1131300601
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.4179829961
Short name T630
Test name
Test status
Simulation time 117664578 ps
CPU time 3.8 seconds
Started Aug 05 04:33:58 PM PDT 24
Finished Aug 05 04:34:02 PM PDT 24
Peak memory 206876 kb
Host smart-25bc2fc3-9b60-41bc-ade3-322d3131bc58
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179829961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.4179829961
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3639282622
Short name T311
Test name
Test status
Simulation time 117203143 ps
CPU time 2.48 seconds
Started Aug 05 04:33:56 PM PDT 24
Finished Aug 05 04:33:58 PM PDT 24
Peak memory 206800 kb
Host smart-38a83c20-278e-4aa3-9e18-0253565d9e4b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639282622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3639282622
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.695565290
Short name T243
Test name
Test status
Simulation time 1413112977 ps
CPU time 19.7 seconds
Started Aug 05 04:33:56 PM PDT 24
Finished Aug 05 04:34:15 PM PDT 24
Peak memory 220528 kb
Host smart-f13077bb-f2cd-4896-a096-396e82af6a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695565290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.695565290
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3995548703
Short name T111
Test name
Test status
Simulation time 184682845 ps
CPU time 3.89 seconds
Started Aug 05 04:33:53 PM PDT 24
Finished Aug 05 04:33:57 PM PDT 24
Peak memory 208040 kb
Host smart-43b3a911-755c-4204-9c17-9ba0c4f6954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995548703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3995548703
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.605201841
Short name T722
Test name
Test status
Simulation time 332744662 ps
CPU time 17.11 seconds
Started Aug 05 04:33:52 PM PDT 24
Finished Aug 05 04:34:09 PM PDT 24
Peak memory 222436 kb
Host smart-07a39258-af99-43bf-b57b-553d727d7fa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605201841 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.605201841
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2721744737
Short name T790
Test name
Test status
Simulation time 1033337628 ps
CPU time 3.88 seconds
Started Aug 05 04:34:08 PM PDT 24
Finished Aug 05 04:34:12 PM PDT 24
Peak memory 208880 kb
Host smart-7572563b-2318-42ed-8f40-6369b7368955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721744737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2721744737
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.655706611
Short name T912
Test name
Test status
Simulation time 528773077 ps
CPU time 3.44 seconds
Started Aug 05 04:34:00 PM PDT 24
Finished Aug 05 04:34:04 PM PDT 24
Peak memory 210300 kb
Host smart-43ae7c30-4d73-4b6c-a410-2cf51a7b16b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655706611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.655706611
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.314313922
Short name T680
Test name
Test status
Simulation time 11657902 ps
CPU time 0.86 seconds
Started Aug 05 04:34:20 PM PDT 24
Finished Aug 05 04:34:21 PM PDT 24
Peak memory 205828 kb
Host smart-8a0da9f6-a52e-42f6-8be0-1127623edc96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314313922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.314313922
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2460064009
Short name T462
Test name
Test status
Simulation time 1216826047 ps
CPU time 3.92 seconds
Started Aug 05 04:34:09 PM PDT 24
Finished Aug 05 04:34:14 PM PDT 24
Peak memory 214280 kb
Host smart-d7d5bce7-afd4-4639-8e42-15f929077fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460064009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2460064009
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3057606064
Short name T870
Test name
Test status
Simulation time 217294901 ps
CPU time 2.04 seconds
Started Aug 05 04:33:55 PM PDT 24
Finished Aug 05 04:33:57 PM PDT 24
Peak memory 214212 kb
Host smart-03ce2fec-3f61-49c1-8a9e-44c6b07ee895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057606064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3057606064
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3742466506
Short name T265
Test name
Test status
Simulation time 150791998 ps
CPU time 3.79 seconds
Started Aug 05 04:33:55 PM PDT 24
Finished Aug 05 04:34:09 PM PDT 24
Peak memory 214108 kb
Host smart-90590623-e51a-4930-bf8e-07999c86e72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742466506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3742466506
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1321129530
Short name T700
Test name
Test status
Simulation time 84444967 ps
CPU time 1.95 seconds
Started Aug 05 04:33:47 PM PDT 24
Finished Aug 05 04:33:49 PM PDT 24
Peak memory 214164 kb
Host smart-b6eba206-e93c-45be-b298-84427d900e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321129530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1321129530
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3325290504
Short name T268
Test name
Test status
Simulation time 1247987516 ps
CPU time 7.1 seconds
Started Aug 05 04:34:01 PM PDT 24
Finished Aug 05 04:34:08 PM PDT 24
Peak memory 214276 kb
Host smart-fcb2bcf5-3017-41de-8ed0-4addb21ae379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325290504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3325290504
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.758867819
Short name T360
Test name
Test status
Simulation time 836948073 ps
CPU time 30.13 seconds
Started Aug 05 04:34:05 PM PDT 24
Finished Aug 05 04:34:35 PM PDT 24
Peak memory 208576 kb
Host smart-e216262a-5c30-4098-8a3f-b9c3d4750581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758867819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.758867819
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1592767909
Short name T713
Test name
Test status
Simulation time 2010289342 ps
CPU time 21.48 seconds
Started Aug 05 04:34:02 PM PDT 24
Finished Aug 05 04:34:24 PM PDT 24
Peak memory 208780 kb
Host smart-64d45f64-8e50-4901-90c3-a0c4cfc11357
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592767909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1592767909
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3278171117
Short name T913
Test name
Test status
Simulation time 304702537 ps
CPU time 3.5 seconds
Started Aug 05 04:33:56 PM PDT 24
Finished Aug 05 04:34:00 PM PDT 24
Peak memory 208668 kb
Host smart-9f9cd19e-5b44-44db-9b90-1b0c145e0fbe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278171117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3278171117
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3095021457
Short name T543
Test name
Test status
Simulation time 271927839 ps
CPU time 4.2 seconds
Started Aug 05 04:33:56 PM PDT 24
Finished Aug 05 04:34:01 PM PDT 24
Peak memory 208768 kb
Host smart-f110096c-c3ad-4dcf-a798-6cb73e1a488c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095021457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3095021457
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1124869639
Short name T517
Test name
Test status
Simulation time 187412108 ps
CPU time 3.89 seconds
Started Aug 05 04:34:08 PM PDT 24
Finished Aug 05 04:34:12 PM PDT 24
Peak memory 215848 kb
Host smart-2d7e0c30-f1a0-4f84-9b86-1ed55647586f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124869639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1124869639
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2002641692
Short name T634
Test name
Test status
Simulation time 34127894 ps
CPU time 2.03 seconds
Started Aug 05 04:34:08 PM PDT 24
Finished Aug 05 04:34:10 PM PDT 24
Peak memory 206724 kb
Host smart-da17c85d-7d64-4505-9d15-f409fc917d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002641692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2002641692
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2275994110
Short name T349
Test name
Test status
Simulation time 1034077086 ps
CPU time 14.9 seconds
Started Aug 05 04:34:30 PM PDT 24
Finished Aug 05 04:34:45 PM PDT 24
Peak memory 215268 kb
Host smart-c4239d51-8ed5-435a-962a-9cfa135bb3f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275994110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2275994110
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2637950302
Short name T50
Test name
Test status
Simulation time 1043058018 ps
CPU time 12.43 seconds
Started Aug 05 04:34:13 PM PDT 24
Finished Aug 05 04:34:25 PM PDT 24
Peak memory 219852 kb
Host smart-96115098-40ac-430f-b5ab-f7d91c2202d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637950302 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2637950302
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.210667032
Short name T669
Test name
Test status
Simulation time 99465208 ps
CPU time 4 seconds
Started Aug 05 04:34:03 PM PDT 24
Finished Aug 05 04:34:07 PM PDT 24
Peak memory 209940 kb
Host smart-aa5b6507-a60d-4679-b662-e48231d4968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210667032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.210667032
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2119080188
Short name T445
Test name
Test status
Simulation time 47850695 ps
CPU time 0.78 seconds
Started Aug 05 04:34:15 PM PDT 24
Finished Aug 05 04:34:16 PM PDT 24
Peak memory 205812 kb
Host smart-0fcf6830-1cb8-4a06-899d-b8fa488a55b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119080188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2119080188
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1380119990
Short name T228
Test name
Test status
Simulation time 1665589474 ps
CPU time 15.68 seconds
Started Aug 05 04:34:01 PM PDT 24
Finished Aug 05 04:34:16 PM PDT 24
Peak memory 214180 kb
Host smart-41557bf2-e3f4-4e42-a298-cf606dceb452
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380119990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1380119990
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3638530624
Short name T452
Test name
Test status
Simulation time 233225698 ps
CPU time 2.93 seconds
Started Aug 05 04:34:18 PM PDT 24
Finished Aug 05 04:34:21 PM PDT 24
Peak memory 218136 kb
Host smart-c3a9c2cc-d4fa-4967-80b5-18c9907e38f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638530624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3638530624
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2731824444
Short name T773
Test name
Test status
Simulation time 1424189739 ps
CPU time 4.31 seconds
Started Aug 05 04:34:02 PM PDT 24
Finished Aug 05 04:34:07 PM PDT 24
Peak memory 207992 kb
Host smart-9b790f39-a744-45ab-9a29-ffc9f6aca926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731824444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2731824444
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1861620066
Short name T732
Test name
Test status
Simulation time 30971466 ps
CPU time 2.37 seconds
Started Aug 05 04:34:15 PM PDT 24
Finished Aug 05 04:34:18 PM PDT 24
Peak memory 222276 kb
Host smart-35a2045b-b797-42fa-9b84-48c950f1d13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861620066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1861620066
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2995154502
Short name T889
Test name
Test status
Simulation time 99959002 ps
CPU time 3.97 seconds
Started Aug 05 04:34:10 PM PDT 24
Finished Aug 05 04:34:14 PM PDT 24
Peak memory 222208 kb
Host smart-fc838164-7806-4a9e-b1be-8886f29ed622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995154502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2995154502
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2133018492
Short name T772
Test name
Test status
Simulation time 79464787 ps
CPU time 3.64 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:00 PM PDT 24
Peak memory 214188 kb
Host smart-3fea7919-e6f9-498c-96d5-a81c56a5dfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133018492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2133018492
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.694708190
Short name T1
Test name
Test status
Simulation time 116391420 ps
CPU time 3.6 seconds
Started Aug 05 04:34:10 PM PDT 24
Finished Aug 05 04:34:13 PM PDT 24
Peak memory 207888 kb
Host smart-e96912af-4a76-442b-b2d7-8f03e9bd0efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694708190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.694708190
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2671246857
Short name T374
Test name
Test status
Simulation time 473284988 ps
CPU time 11.74 seconds
Started Aug 05 04:34:13 PM PDT 24
Finished Aug 05 04:34:25 PM PDT 24
Peak memory 208828 kb
Host smart-0f652ad4-5b9b-47bf-bfa4-352eccc3c170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671246857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2671246857
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3199338599
Short name T432
Test name
Test status
Simulation time 20836402 ps
CPU time 1.77 seconds
Started Aug 05 04:34:02 PM PDT 24
Finished Aug 05 04:34:04 PM PDT 24
Peak memory 207008 kb
Host smart-e42fa11f-bfcd-4276-bcba-e964583fa0df
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199338599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3199338599
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.628065153
Short name T887
Test name
Test status
Simulation time 208568586 ps
CPU time 7.26 seconds
Started Aug 05 04:34:17 PM PDT 24
Finished Aug 05 04:34:24 PM PDT 24
Peak memory 208532 kb
Host smart-efd87de5-ed02-4b7b-8a49-d8f8317e4a47
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628065153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.628065153
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3409268321
Short name T478
Test name
Test status
Simulation time 1903118703 ps
CPU time 4.04 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:20 PM PDT 24
Peak memory 206676 kb
Host smart-fd39cdf8-3b44-4220-8e79-1ef8147a8427
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409268321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3409268321
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3147318594
Short name T112
Test name
Test status
Simulation time 175927957 ps
CPU time 2.13 seconds
Started Aug 05 04:33:56 PM PDT 24
Finished Aug 05 04:33:58 PM PDT 24
Peak memory 206660 kb
Host smart-804ca1c0-dc86-4530-9915-fa2a5ec9ce83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147318594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3147318594
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3151932738
Short name T704
Test name
Test status
Simulation time 249385981 ps
CPU time 1.76 seconds
Started Aug 05 04:34:18 PM PDT 24
Finished Aug 05 04:34:20 PM PDT 24
Peak memory 205968 kb
Host smart-2e776abc-8ec6-4b78-b12a-871946409c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151932738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3151932738
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1531740742
Short name T649
Test name
Test status
Simulation time 330577259 ps
CPU time 4.77 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:21 PM PDT 24
Peak memory 222432 kb
Host smart-071512ed-295e-4a42-b3ba-0c5dcc8d4ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531740742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1531740742
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.4034924518
Short name T314
Test name
Test status
Simulation time 161939025 ps
CPU time 10.85 seconds
Started Aug 05 04:33:54 PM PDT 24
Finished Aug 05 04:34:05 PM PDT 24
Peak memory 222488 kb
Host smart-204d86db-f29f-47ef-8ab6-81975875c829
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034924518 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.4034924518
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2455438540
Short name T331
Test name
Test status
Simulation time 55016079 ps
CPU time 3.5 seconds
Started Aug 05 04:34:00 PM PDT 24
Finished Aug 05 04:34:04 PM PDT 24
Peak memory 207540 kb
Host smart-420421b0-4ed9-42fa-b160-eb32433e87b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455438540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2455438540
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2585188480
Short name T844
Test name
Test status
Simulation time 347789623 ps
CPU time 2.83 seconds
Started Aug 05 04:34:11 PM PDT 24
Finished Aug 05 04:34:14 PM PDT 24
Peak memory 210168 kb
Host smart-dfc2cc36-6ec6-4363-a533-a9aae78e1edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585188480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2585188480
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1887848368
Short name T502
Test name
Test status
Simulation time 14975747 ps
CPU time 0.75 seconds
Started Aug 05 04:34:05 PM PDT 24
Finished Aug 05 04:34:06 PM PDT 24
Peak memory 205824 kb
Host smart-2755f4cc-fbb3-4472-98d4-ccfd80df6a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887848368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1887848368
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.318273795
Short name T286
Test name
Test status
Simulation time 111988663 ps
CPU time 2.44 seconds
Started Aug 05 04:33:48 PM PDT 24
Finished Aug 05 04:33:50 PM PDT 24
Peak memory 214248 kb
Host smart-3e294bd2-acd2-4ff0-a51d-29a467c9e678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=318273795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.318273795
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1020535856
Short name T31
Test name
Test status
Simulation time 255094115 ps
CPU time 3.84 seconds
Started Aug 05 04:34:09 PM PDT 24
Finished Aug 05 04:34:13 PM PDT 24
Peak memory 214124 kb
Host smart-0c3f58d3-d668-40a3-be55-b6103f21bf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020535856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1020535856
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1892869864
Short name T726
Test name
Test status
Simulation time 147080014 ps
CPU time 1.8 seconds
Started Aug 05 04:34:03 PM PDT 24
Finished Aug 05 04:34:04 PM PDT 24
Peak memory 206876 kb
Host smart-b7a4336b-be35-4242-ba99-2f70cb470240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892869864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1892869864
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.157942532
Short name T114
Test name
Test status
Simulation time 104256612 ps
CPU time 5.04 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:02 PM PDT 24
Peak memory 222388 kb
Host smart-2a115145-8d43-4ed7-b279-2d7281a68084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157942532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.157942532
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.570872222
Short name T711
Test name
Test status
Simulation time 65269091 ps
CPU time 3.3 seconds
Started Aug 05 04:34:11 PM PDT 24
Finished Aug 05 04:34:15 PM PDT 24
Peak memory 209468 kb
Host smart-dd5a5db6-07d2-4ca8-82fb-d21114f3927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570872222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.570872222
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3182136810
Short name T706
Test name
Test status
Simulation time 90260649 ps
CPU time 3.58 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:34:00 PM PDT 24
Peak memory 207236 kb
Host smart-baf76929-cdef-4739-b54a-68e77e6d8463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182136810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3182136810
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1069379428
Short name T501
Test name
Test status
Simulation time 247684219 ps
CPU time 3.06 seconds
Started Aug 05 04:34:48 PM PDT 24
Finished Aug 05 04:34:52 PM PDT 24
Peak memory 208428 kb
Host smart-76e1562f-e771-4a1e-9b88-927ec40fa6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069379428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1069379428
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3543362027
Short name T907
Test name
Test status
Simulation time 118424473 ps
CPU time 4.02 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:01 PM PDT 24
Peak memory 208492 kb
Host smart-20e30205-8200-47b5-bc22-97249ae27fac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543362027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3543362027
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1445710052
Short name T498
Test name
Test status
Simulation time 346934128 ps
CPU time 1.82 seconds
Started Aug 05 04:34:09 PM PDT 24
Finished Aug 05 04:34:11 PM PDT 24
Peak memory 206900 kb
Host smart-10bd5424-c4a1-426b-acaf-cf7ec2dd48f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445710052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1445710052
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3058756311
Short name T497
Test name
Test status
Simulation time 101258953 ps
CPU time 2.56 seconds
Started Aug 05 04:33:55 PM PDT 24
Finished Aug 05 04:33:57 PM PDT 24
Peak memory 206728 kb
Host smart-c02c5198-8027-47a9-b1af-57d6ccb95f7c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058756311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3058756311
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3502132814
Short name T383
Test name
Test status
Simulation time 6171499260 ps
CPU time 10.59 seconds
Started Aug 05 04:34:18 PM PDT 24
Finished Aug 05 04:34:29 PM PDT 24
Peak memory 209148 kb
Host smart-7de1d197-7ef5-4dd4-9187-938ef8292c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502132814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3502132814
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1010879177
Short name T564
Test name
Test status
Simulation time 207122045 ps
CPU time 2.61 seconds
Started Aug 05 04:34:14 PM PDT 24
Finished Aug 05 04:34:17 PM PDT 24
Peak memory 206704 kb
Host smart-f592aa68-ed1c-4ecf-9c1e-814fdd777604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010879177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1010879177
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1465222601
Short name T181
Test name
Test status
Simulation time 1564103420 ps
CPU time 14.94 seconds
Started Aug 05 04:34:18 PM PDT 24
Finished Aug 05 04:34:33 PM PDT 24
Peak memory 222044 kb
Host smart-7de57c41-286f-4142-b3af-9f467fe10b1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465222601 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1465222601
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3935575021
Short name T831
Test name
Test status
Simulation time 586319036 ps
CPU time 7.03 seconds
Started Aug 05 04:34:10 PM PDT 24
Finished Aug 05 04:34:17 PM PDT 24
Peak memory 209296 kb
Host smart-422d7c2e-5477-48ea-a015-d9c2449d745c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935575021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3935575021
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.545394671
Short name T174
Test name
Test status
Simulation time 950235558 ps
CPU time 4.51 seconds
Started Aug 05 04:34:06 PM PDT 24
Finished Aug 05 04:34:10 PM PDT 24
Peak memory 210396 kb
Host smart-f425f35f-09e2-4717-a84a-1f204f4b4e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545394671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.545394671
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3436532739
Short name T572
Test name
Test status
Simulation time 16353198 ps
CPU time 1.01 seconds
Started Aug 05 04:34:22 PM PDT 24
Finished Aug 05 04:34:23 PM PDT 24
Peak memory 206044 kb
Host smart-6c0bdf96-1aad-440b-a985-90a5f3a8daa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436532739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3436532739
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.271080563
Short name T34
Test name
Test status
Simulation time 485408228 ps
CPU time 4.26 seconds
Started Aug 05 04:34:17 PM PDT 24
Finished Aug 05 04:34:21 PM PDT 24
Peak memory 215280 kb
Host smart-7d55d996-2a34-48df-a0bb-25ab5e57c53e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271080563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.271080563
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1007605010
Short name T881
Test name
Test status
Simulation time 72816171 ps
CPU time 2.38 seconds
Started Aug 05 04:34:04 PM PDT 24
Finished Aug 05 04:34:07 PM PDT 24
Peak memory 214588 kb
Host smart-09236152-1e12-4cc4-8bf6-e77d55a01b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007605010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1007605010
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.949712126
Short name T262
Test name
Test status
Simulation time 1150951010 ps
CPU time 3.36 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:01 PM PDT 24
Peak memory 209640 kb
Host smart-a39ed88e-f621-4ad3-b9cb-f148d0a3f15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949712126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.949712126
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2160500393
Short name T95
Test name
Test status
Simulation time 142014950 ps
CPU time 5.78 seconds
Started Aug 05 04:34:05 PM PDT 24
Finished Aug 05 04:34:14 PM PDT 24
Peak memory 214312 kb
Host smart-c4a14f73-4375-4ca9-9c7b-e8897315dd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160500393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2160500393
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2585956750
Short name T301
Test name
Test status
Simulation time 42520786 ps
CPU time 2.75 seconds
Started Aug 05 04:34:02 PM PDT 24
Finished Aug 05 04:34:04 PM PDT 24
Peak memory 214132 kb
Host smart-d7bb6e60-b188-43f1-8c34-96bf19de7c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585956750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2585956750
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2976122423
Short name T237
Test name
Test status
Simulation time 284978247 ps
CPU time 2.42 seconds
Started Aug 05 04:34:08 PM PDT 24
Finished Aug 05 04:34:11 PM PDT 24
Peak memory 209636 kb
Host smart-7a9b2bfc-18fd-4632-91b4-5064585ec327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976122423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2976122423
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3340529590
Short name T769
Test name
Test status
Simulation time 242269334 ps
CPU time 5.86 seconds
Started Aug 05 04:34:10 PM PDT 24
Finished Aug 05 04:34:16 PM PDT 24
Peak memory 214172 kb
Host smart-0bbcec78-b0e8-4ddf-963d-2097cad5c474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340529590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3340529590
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3747207135
Short name T463
Test name
Test status
Simulation time 60029812 ps
CPU time 3.05 seconds
Started Aug 05 04:34:22 PM PDT 24
Finished Aug 05 04:34:25 PM PDT 24
Peak memory 206924 kb
Host smart-049e8f84-57e7-4ee9-bfee-e3a7c7ee065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747207135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3747207135
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3537504571
Short name T868
Test name
Test status
Simulation time 181930841 ps
CPU time 2.74 seconds
Started Aug 05 04:34:03 PM PDT 24
Finished Aug 05 04:34:06 PM PDT 24
Peak memory 208552 kb
Host smart-05708d4f-c865-445f-9d5d-7951760f0cd5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537504571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3537504571
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3810642528
Short name T738
Test name
Test status
Simulation time 64235857 ps
CPU time 3.23 seconds
Started Aug 05 04:34:21 PM PDT 24
Finished Aug 05 04:34:24 PM PDT 24
Peak memory 208328 kb
Host smart-d34b12ce-3b73-448f-a5f7-9962aa7e843e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810642528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3810642528
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3039067787
Short name T742
Test name
Test status
Simulation time 1432931183 ps
CPU time 26.45 seconds
Started Aug 05 04:34:13 PM PDT 24
Finished Aug 05 04:34:40 PM PDT 24
Peak memory 208672 kb
Host smart-23a74f03-fa8f-4352-8de2-d9aad6bc1314
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039067787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3039067787
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.364878845
Short name T289
Test name
Test status
Simulation time 179167931 ps
CPU time 2.22 seconds
Started Aug 05 04:34:13 PM PDT 24
Finished Aug 05 04:34:15 PM PDT 24
Peak memory 208392 kb
Host smart-4205e231-1c14-425a-ac0b-95a158da948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364878845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.364878845
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2646053751
Short name T588
Test name
Test status
Simulation time 553857408 ps
CPU time 16.63 seconds
Started Aug 05 04:34:00 PM PDT 24
Finished Aug 05 04:34:16 PM PDT 24
Peak memory 208628 kb
Host smart-f768645d-e13e-43b1-bf05-4982a93d6319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646053751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2646053751
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1019137016
Short name T753
Test name
Test status
Simulation time 360988810 ps
CPU time 4.21 seconds
Started Aug 05 04:34:13 PM PDT 24
Finished Aug 05 04:34:18 PM PDT 24
Peak memory 206804 kb
Host smart-29d94b87-737e-4f4f-b67a-11376d9f35b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019137016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1019137016
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2954115221
Short name T721
Test name
Test status
Simulation time 540521305 ps
CPU time 5 seconds
Started Aug 05 04:34:15 PM PDT 24
Finished Aug 05 04:34:20 PM PDT 24
Peak memory 207356 kb
Host smart-f4befc92-c906-4423-9fe5-65a48af1633d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954115221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2954115221
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2134237642
Short name T637
Test name
Test status
Simulation time 246237722 ps
CPU time 1.63 seconds
Started Aug 05 04:33:52 PM PDT 24
Finished Aug 05 04:33:54 PM PDT 24
Peak memory 208272 kb
Host smart-b4a9f6b2-bb82-417e-b577-efd412a2896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134237642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2134237642
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3375065594
Short name T477
Test name
Test status
Simulation time 15673072 ps
CPU time 0.77 seconds
Started Aug 05 04:34:22 PM PDT 24
Finished Aug 05 04:34:23 PM PDT 24
Peak memory 205860 kb
Host smart-99687410-5fce-41da-a8d9-d081d0da48f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375065594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3375065594
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2010633469
Short name T388
Test name
Test status
Simulation time 103165664 ps
CPU time 2.63 seconds
Started Aug 05 04:34:05 PM PDT 24
Finished Aug 05 04:34:08 PM PDT 24
Peak memory 207648 kb
Host smart-f468881f-0ce4-4e63-b2b6-9a436cbdeac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010633469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2010633469
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3685759117
Short name T798
Test name
Test status
Simulation time 404819689 ps
CPU time 3.81 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:20 PM PDT 24
Peak memory 208608 kb
Host smart-86ac3a9e-7385-4e4b-95f3-694672bbb787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685759117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3685759117
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3922831268
Short name T748
Test name
Test status
Simulation time 507095134 ps
CPU time 4.18 seconds
Started Aug 05 04:34:07 PM PDT 24
Finished Aug 05 04:34:11 PM PDT 24
Peak memory 205948 kb
Host smart-f55894e3-41f5-4409-b65f-75e628920a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922831268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3922831268
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2446716498
Short name T647
Test name
Test status
Simulation time 131818235 ps
CPU time 3.94 seconds
Started Aug 05 04:34:01 PM PDT 24
Finished Aug 05 04:34:05 PM PDT 24
Peak memory 214596 kb
Host smart-d3cd51af-ff97-45c4-980d-fd073715166c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446716498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2446716498
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1500106481
Short name T419
Test name
Test status
Simulation time 109462597 ps
CPU time 3.74 seconds
Started Aug 05 04:34:15 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 209860 kb
Host smart-ca1c311d-46fe-4026-b714-f28d66eaf62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500106481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1500106481
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.236336736
Short name T806
Test name
Test status
Simulation time 579802691 ps
CPU time 4.93 seconds
Started Aug 05 04:34:05 PM PDT 24
Finished Aug 05 04:34:10 PM PDT 24
Peak memory 208564 kb
Host smart-8696211c-3dae-473f-9528-4179a87721e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236336736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.236336736
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1101113284
Short name T291
Test name
Test status
Simulation time 3603365640 ps
CPU time 38.95 seconds
Started Aug 05 04:34:11 PM PDT 24
Finished Aug 05 04:34:50 PM PDT 24
Peak memory 208604 kb
Host smart-09a7b9c3-120b-4caa-bbbb-7186a91fa333
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101113284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1101113284
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1980469001
Short name T601
Test name
Test status
Simulation time 89795199 ps
CPU time 3.06 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:00 PM PDT 24
Peak memory 206656 kb
Host smart-e2a477c3-1fd4-45e9-a75a-3f8a898a20a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980469001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1980469001
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.878095872
Short name T770
Test name
Test status
Simulation time 70112487 ps
CPU time 3.36 seconds
Started Aug 05 04:34:21 PM PDT 24
Finished Aug 05 04:34:25 PM PDT 24
Peak memory 208672 kb
Host smart-3a7e1457-ac14-4b06-9efb-f41d3d4e9eba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878095872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.878095872
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.162714829
Short name T813
Test name
Test status
Simulation time 491369392 ps
CPU time 4.84 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:02 PM PDT 24
Peak memory 218264 kb
Host smart-68dc438e-2ec0-45b8-a458-7a8133f290a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162714829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.162714829
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1022189316
Short name T440
Test name
Test status
Simulation time 1574529508 ps
CPU time 10.29 seconds
Started Aug 05 04:33:51 PM PDT 24
Finished Aug 05 04:34:01 PM PDT 24
Peak memory 207868 kb
Host smart-467858a7-78e5-4309-acfd-3d7b5a3a2cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022189316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1022189316
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2914748675
Short name T533
Test name
Test status
Simulation time 547377506 ps
CPU time 7.81 seconds
Started Aug 05 04:34:03 PM PDT 24
Finished Aug 05 04:34:11 PM PDT 24
Peak memory 218256 kb
Host smart-5a96199d-3d3f-4029-b5d7-9d20b21d650c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914748675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2914748675
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.144796545
Short name T737
Test name
Test status
Simulation time 57456359 ps
CPU time 1.57 seconds
Started Aug 05 04:34:06 PM PDT 24
Finished Aug 05 04:34:07 PM PDT 24
Peak memory 209628 kb
Host smart-f70244c1-4fd9-4cb4-81a9-41709386665b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144796545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.144796545
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2047854154
Short name T825
Test name
Test status
Simulation time 14807489 ps
CPU time 0.85 seconds
Started Aug 05 04:34:14 PM PDT 24
Finished Aug 05 04:34:15 PM PDT 24
Peak memory 205964 kb
Host smart-cd41bcd1-e0d3-48e6-9cb5-02bb35859ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047854154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2047854154
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3298604737
Short name T395
Test name
Test status
Simulation time 129836349 ps
CPU time 2.77 seconds
Started Aug 05 04:34:07 PM PDT 24
Finished Aug 05 04:34:10 PM PDT 24
Peak memory 214196 kb
Host smart-e113b19c-bdba-4130-b5e2-3a95eafa8d33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298604737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3298604737
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1853730734
Short name T579
Test name
Test status
Simulation time 300881334 ps
CPU time 2.49 seconds
Started Aug 05 04:33:55 PM PDT 24
Finished Aug 05 04:33:58 PM PDT 24
Peak memory 209396 kb
Host smart-18a87110-c37c-417f-8d86-f4e9cf8dbc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853730734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1853730734
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3459778116
Short name T339
Test name
Test status
Simulation time 199192761 ps
CPU time 3.39 seconds
Started Aug 05 04:34:27 PM PDT 24
Finished Aug 05 04:34:30 PM PDT 24
Peak memory 207464 kb
Host smart-2c4bb32a-23b3-4417-9827-8adb0f69fe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459778116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3459778116
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3418607450
Short name T300
Test name
Test status
Simulation time 64726006 ps
CPU time 1.94 seconds
Started Aug 05 04:34:05 PM PDT 24
Finished Aug 05 04:34:07 PM PDT 24
Peak memory 214268 kb
Host smart-94bfca4d-2446-4cf0-bae2-464531ef8054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418607450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3418607450
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1745740350
Short name T321
Test name
Test status
Simulation time 55663164 ps
CPU time 2.09 seconds
Started Aug 05 04:34:13 PM PDT 24
Finished Aug 05 04:34:15 PM PDT 24
Peak memory 214860 kb
Host smart-aaf0f19c-bfb9-41f0-b418-f177d9bf618e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745740350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1745740350
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3035961760
Short name T65
Test name
Test status
Simulation time 43479790 ps
CPU time 3.13 seconds
Started Aug 05 04:33:57 PM PDT 24
Finished Aug 05 04:34:01 PM PDT 24
Peak memory 222500 kb
Host smart-02402a78-1260-4480-8cfc-5c3597f4538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035961760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3035961760
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3199352512
Short name T281
Test name
Test status
Simulation time 81039845 ps
CPU time 3.45 seconds
Started Aug 05 04:34:27 PM PDT 24
Finished Aug 05 04:34:30 PM PDT 24
Peak memory 209580 kb
Host smart-95384353-5433-45fa-b513-901ed8bfddaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199352512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3199352512
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3859813163
Short name T359
Test name
Test status
Simulation time 134753973 ps
CPU time 3.71 seconds
Started Aug 05 04:34:15 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 206784 kb
Host smart-9232bcd5-a644-40a8-bdd3-30240ff7d581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859813163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3859813163
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3161134930
Short name T635
Test name
Test status
Simulation time 148932381 ps
CPU time 2.82 seconds
Started Aug 05 04:34:23 PM PDT 24
Finished Aug 05 04:34:26 PM PDT 24
Peak memory 206660 kb
Host smart-ccecc3ce-8624-4fe0-aa45-af35f020a3ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161134930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3161134930
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1643252261
Short name T205
Test name
Test status
Simulation time 136111444 ps
CPU time 5.26 seconds
Started Aug 05 04:34:13 PM PDT 24
Finished Aug 05 04:34:18 PM PDT 24
Peak memory 208740 kb
Host smart-69612f82-a4f7-437b-9233-e38974a4759a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643252261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1643252261
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.546126293
Short name T279
Test name
Test status
Simulation time 63685979 ps
CPU time 2.8 seconds
Started Aug 05 04:34:05 PM PDT 24
Finished Aug 05 04:34:08 PM PDT 24
Peak memory 209008 kb
Host smart-aa78682d-d798-4406-87a7-4d4a0dd43586
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546126293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.546126293
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3541097828
Short name T803
Test name
Test status
Simulation time 73429063 ps
CPU time 2.42 seconds
Started Aug 05 04:34:26 PM PDT 24
Finished Aug 05 04:34:29 PM PDT 24
Peak memory 208944 kb
Host smart-b0d5cce7-505e-4aeb-a073-fd35effab4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541097828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3541097828
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3835703615
Short name T758
Test name
Test status
Simulation time 85851113 ps
CPU time 2.29 seconds
Started Aug 05 04:34:09 PM PDT 24
Finished Aug 05 04:34:11 PM PDT 24
Peak memory 206704 kb
Host smart-b72fb0dc-d861-44fa-963f-57e9e192bacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835703615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3835703615
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.541555660
Short name T851
Test name
Test status
Simulation time 35730894 ps
CPU time 0.96 seconds
Started Aug 05 04:34:18 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 205980 kb
Host smart-4482b828-a76b-4669-9206-8b4db48b2215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541555660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.541555660
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.4284616775
Short name T883
Test name
Test status
Simulation time 2027017297 ps
CPU time 6.12 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:22 PM PDT 24
Peak memory 208352 kb
Host smart-8f16847e-e1e1-44c0-8095-01b34b8462e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284616775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.4284616775
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.4233283821
Short name T453
Test name
Test status
Simulation time 15811906 ps
CPU time 0.77 seconds
Started Aug 05 04:34:08 PM PDT 24
Finished Aug 05 04:34:09 PM PDT 24
Peak memory 205824 kb
Host smart-b60d8088-f77a-4aef-9501-ebc655b14781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233283821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.4233283821
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3973235267
Short name T415
Test name
Test status
Simulation time 154512051 ps
CPU time 3.53 seconds
Started Aug 05 04:34:23 PM PDT 24
Finished Aug 05 04:34:26 PM PDT 24
Peak memory 215080 kb
Host smart-835db084-f2fd-4c8e-9856-dce0c8a0fcf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3973235267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3973235267
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3307420919
Short name T846
Test name
Test status
Simulation time 314073041 ps
CPU time 3.63 seconds
Started Aug 05 04:34:04 PM PDT 24
Finished Aug 05 04:34:13 PM PDT 24
Peak memory 214160 kb
Host smart-3675e8f3-6d6a-4d82-ba5c-ff6472c7bae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307420919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3307420919
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2043914155
Short name T103
Test name
Test status
Simulation time 1456323984 ps
CPU time 9.06 seconds
Started Aug 05 04:34:05 PM PDT 24
Finished Aug 05 04:34:14 PM PDT 24
Peak memory 214184 kb
Host smart-ccce0cb5-aacb-4cee-80a9-fff3b24a2cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043914155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2043914155
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3557554159
Short name T510
Test name
Test status
Simulation time 574775505 ps
CPU time 4.21 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:20 PM PDT 24
Peak memory 214316 kb
Host smart-e459c7f6-3fa9-4298-9280-807892585750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557554159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3557554159
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2897966185
Short name T618
Test name
Test status
Simulation time 122901493 ps
CPU time 3.26 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 216768 kb
Host smart-79b4db9c-d24c-4263-964c-dbb25924bd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897966185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2897966185
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2873126703
Short name T357
Test name
Test status
Simulation time 333551981 ps
CPU time 4.29 seconds
Started Aug 05 04:34:14 PM PDT 24
Finished Aug 05 04:34:29 PM PDT 24
Peak memory 208168 kb
Host smart-4e9c2593-2eea-4f20-ae44-d07220a3094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873126703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2873126703
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3434683013
Short name T2
Test name
Test status
Simulation time 662188170 ps
CPU time 9.16 seconds
Started Aug 05 04:34:13 PM PDT 24
Finished Aug 05 04:34:23 PM PDT 24
Peak memory 208660 kb
Host smart-c857611d-f5fa-4dba-b732-3e1933cd8d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434683013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3434683013
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2325480000
Short name T787
Test name
Test status
Simulation time 637718244 ps
CPU time 4.11 seconds
Started Aug 05 04:34:14 PM PDT 24
Finished Aug 05 04:34:18 PM PDT 24
Peak memory 207816 kb
Host smart-edad29d6-4769-4ba6-a237-e5c7bbc7c050
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325480000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2325480000
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3747835216
Short name T717
Test name
Test status
Simulation time 135416850 ps
CPU time 5.23 seconds
Started Aug 05 04:34:15 PM PDT 24
Finished Aug 05 04:34:21 PM PDT 24
Peak memory 209080 kb
Host smart-8186417a-335b-4fd4-bb44-11d53c9d087c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747835216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3747835216
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2213640830
Short name T540
Test name
Test status
Simulation time 358070471 ps
CPU time 3.25 seconds
Started Aug 05 04:34:07 PM PDT 24
Finished Aug 05 04:34:10 PM PDT 24
Peak memory 206876 kb
Host smart-5dd830ee-ec91-4303-a08d-32d6510219fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213640830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2213640830
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2995735537
Short name T880
Test name
Test status
Simulation time 381671411 ps
CPU time 7.83 seconds
Started Aug 05 04:34:15 PM PDT 24
Finished Aug 05 04:34:23 PM PDT 24
Peak memory 208484 kb
Host smart-ae6e31a5-9445-4722-8e40-24e7ece2040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995735537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2995735537
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1331231884
Short name T833
Test name
Test status
Simulation time 401752138 ps
CPU time 4.91 seconds
Started Aug 05 04:34:22 PM PDT 24
Finished Aug 05 04:34:27 PM PDT 24
Peak memory 207796 kb
Host smart-2ce91ef8-944b-4b7c-adb4-1a14a40ff52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331231884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1331231884
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3685722632
Short name T708
Test name
Test status
Simulation time 604524296 ps
CPU time 5.1 seconds
Started Aug 05 04:34:23 PM PDT 24
Finished Aug 05 04:34:28 PM PDT 24
Peak memory 218204 kb
Host smart-329a239f-5e7e-40bc-9ef0-9eab7ea74a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685722632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3685722632
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.263310965
Short name T345
Test name
Test status
Simulation time 2347895481 ps
CPU time 28.58 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:44 PM PDT 24
Peak memory 222572 kb
Host smart-dcd561bd-e779-49e7-9f1f-420dff275e7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263310965 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.263310965
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2949504568
Short name T470
Test name
Test status
Simulation time 5048354407 ps
CPU time 91.73 seconds
Started Aug 05 04:34:05 PM PDT 24
Finished Aug 05 04:35:37 PM PDT 24
Peak memory 222332 kb
Host smart-bba1c42d-a0be-46e0-abf4-9b6bc48d20e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949504568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2949504568
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1064583471
Short name T154
Test name
Test status
Simulation time 131265237 ps
CPU time 3.07 seconds
Started Aug 05 04:34:18 PM PDT 24
Finished Aug 05 04:34:21 PM PDT 24
Peak memory 210044 kb
Host smart-fa27ced2-0347-40f0-9a72-36b2a24b185e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064583471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1064583471
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.377579800
Short name T757
Test name
Test status
Simulation time 41621509 ps
CPU time 0.75 seconds
Started Aug 05 04:34:18 PM PDT 24
Finished Aug 05 04:34:18 PM PDT 24
Peak memory 205808 kb
Host smart-ea1ab62c-be9d-4d21-a58e-2514db7943e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377579800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.377579800
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3719926369
Short name T28
Test name
Test status
Simulation time 225405238 ps
CPU time 2.78 seconds
Started Aug 05 04:34:22 PM PDT 24
Finished Aug 05 04:34:25 PM PDT 24
Peak memory 214448 kb
Host smart-a7cf7a54-86f6-4ec3-a3f3-4a7c031e0266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719926369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3719926369
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.713825189
Short name T240
Test name
Test status
Simulation time 222379682 ps
CPU time 2.02 seconds
Started Aug 05 04:34:21 PM PDT 24
Finished Aug 05 04:34:23 PM PDT 24
Peak memory 207508 kb
Host smart-774e7cf7-c67f-4312-9eff-4bd4ff329289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713825189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.713825189
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.647444991
Short name T25
Test name
Test status
Simulation time 227402326 ps
CPU time 3.8 seconds
Started Aug 05 04:34:14 PM PDT 24
Finished Aug 05 04:34:18 PM PDT 24
Peak memory 208840 kb
Host smart-679dd847-4183-46ab-afa9-2ebd769a5e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647444991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.647444991
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2011521541
Short name T27
Test name
Test status
Simulation time 360876332 ps
CPU time 3.5 seconds
Started Aug 05 04:34:14 PM PDT 24
Finished Aug 05 04:34:17 PM PDT 24
Peak memory 222208 kb
Host smart-0e78d3b6-557f-4217-a770-50086d98367f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011521541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2011521541
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3592184172
Short name T209
Test name
Test status
Simulation time 224539016 ps
CPU time 2.37 seconds
Started Aug 05 04:34:15 PM PDT 24
Finished Aug 05 04:34:18 PM PDT 24
Peak memory 208496 kb
Host smart-e96601a7-4f11-4fea-a676-40b62d979410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592184172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3592184172
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.767865292
Short name T381
Test name
Test status
Simulation time 9776580299 ps
CPU time 86.74 seconds
Started Aug 05 04:34:12 PM PDT 24
Finished Aug 05 04:35:39 PM PDT 24
Peak memory 209280 kb
Host smart-f8f7802c-7fae-4900-bff5-cd289f4cc68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767865292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.767865292
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1377304391
Short name T317
Test name
Test status
Simulation time 58098619 ps
CPU time 2.81 seconds
Started Aug 05 04:34:09 PM PDT 24
Finished Aug 05 04:34:12 PM PDT 24
Peak memory 208564 kb
Host smart-22ff99c0-99a7-443c-8509-bd199584293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377304391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1377304391
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3889771235
Short name T355
Test name
Test status
Simulation time 150546198 ps
CPU time 4.67 seconds
Started Aug 05 04:34:17 PM PDT 24
Finished Aug 05 04:34:21 PM PDT 24
Peak memory 206820 kb
Host smart-491b5a83-d87c-4fc7-bf61-20add740304a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889771235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3889771235
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3977471019
Short name T739
Test name
Test status
Simulation time 1411157175 ps
CPU time 26.9 seconds
Started Aug 05 04:33:55 PM PDT 24
Finished Aug 05 04:34:22 PM PDT 24
Peak memory 209008 kb
Host smart-023b4fbe-b51d-4d52-9eee-181145ece8e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977471019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3977471019
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3588026461
Short name T603
Test name
Test status
Simulation time 224131926 ps
CPU time 2.83 seconds
Started Aug 05 04:34:09 PM PDT 24
Finished Aug 05 04:34:12 PM PDT 24
Peak memory 208632 kb
Host smart-a7f341dd-34be-4260-813d-341c4bb1fb76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588026461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3588026461
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1113995086
Short name T499
Test name
Test status
Simulation time 148956959 ps
CPU time 2.26 seconds
Started Aug 05 04:34:28 PM PDT 24
Finished Aug 05 04:34:31 PM PDT 24
Peak memory 214188 kb
Host smart-37c8de3e-11c7-4ceb-a990-8d28fefdaeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113995086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1113995086
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.700795866
Short name T875
Test name
Test status
Simulation time 6316021606 ps
CPU time 29.77 seconds
Started Aug 05 04:34:27 PM PDT 24
Finished Aug 05 04:34:56 PM PDT 24
Peak memory 208336 kb
Host smart-b16f9209-5881-406a-9f26-2947935d3c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700795866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.700795866
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.38932299
Short name T218
Test name
Test status
Simulation time 445072906 ps
CPU time 23.43 seconds
Started Aug 05 04:34:31 PM PDT 24
Finished Aug 05 04:34:55 PM PDT 24
Peak memory 222484 kb
Host smart-3be2e617-bfef-4ad8-ad34-c1a5a4ac972f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38932299 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.38932299
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.973713359
Short name T760
Test name
Test status
Simulation time 2092445835 ps
CPU time 5.75 seconds
Started Aug 05 04:34:27 PM PDT 24
Finished Aug 05 04:34:32 PM PDT 24
Peak memory 210240 kb
Host smart-7117c42c-3810-4cf6-81c1-edd98e6ea293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973713359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.973713359
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2693075283
Short name T893
Test name
Test status
Simulation time 184190588 ps
CPU time 3.13 seconds
Started Aug 05 04:34:23 PM PDT 24
Finished Aug 05 04:34:26 PM PDT 24
Peak memory 210116 kb
Host smart-6b8487b1-a3eb-4310-acf5-6bc7c76b9456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693075283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2693075283
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2075609435
Short name T505
Test name
Test status
Simulation time 12233285 ps
CPU time 0.88 seconds
Started Aug 05 04:34:06 PM PDT 24
Finished Aug 05 04:34:07 PM PDT 24
Peak memory 205968 kb
Host smart-382e01c1-29b9-4a47-828c-a94a03ae093c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075609435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2075609435
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2065157128
Short name T413
Test name
Test status
Simulation time 135668712 ps
CPU time 7.13 seconds
Started Aug 05 04:34:20 PM PDT 24
Finished Aug 05 04:34:29 PM PDT 24
Peak memory 214172 kb
Host smart-265ea22b-87b2-42f2-91b5-166c10456f26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065157128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2065157128
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.958704773
Short name T30
Test name
Test status
Simulation time 65118340 ps
CPU time 3.22 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 217564 kb
Host smart-9a88480a-027b-4b9b-968d-944680744441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958704773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.958704773
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.210657472
Short name T525
Test name
Test status
Simulation time 74335137 ps
CPU time 1.72 seconds
Started Aug 05 04:34:18 PM PDT 24
Finished Aug 05 04:34:20 PM PDT 24
Peak memory 209272 kb
Host smart-f9eec79b-da47-43a3-971a-22bff7366ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210657472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.210657472
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2650072378
Short name T715
Test name
Test status
Simulation time 465696917 ps
CPU time 11.68 seconds
Started Aug 05 04:34:15 PM PDT 24
Finished Aug 05 04:34:27 PM PDT 24
Peak memory 221948 kb
Host smart-ac7a1d7a-db63-4ffc-b78b-b7e8604ba478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650072378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2650072378
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2271507999
Short name T4
Test name
Test status
Simulation time 126387378 ps
CPU time 2.76 seconds
Started Aug 05 04:34:24 PM PDT 24
Finished Aug 05 04:34:26 PM PDT 24
Peak memory 219228 kb
Host smart-9ad015ce-7ddb-42fa-865b-9acbd6402aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271507999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2271507999
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3056752656
Short name T716
Test name
Test status
Simulation time 3174872015 ps
CPU time 32.57 seconds
Started Aug 05 04:34:19 PM PDT 24
Finished Aug 05 04:34:52 PM PDT 24
Peak memory 214252 kb
Host smart-7d397e6b-fb13-4cb9-b347-04779af5e705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056752656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3056752656
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2180795495
Short name T778
Test name
Test status
Simulation time 38162612 ps
CPU time 2.28 seconds
Started Aug 05 04:34:20 PM PDT 24
Finished Aug 05 04:34:29 PM PDT 24
Peak memory 206888 kb
Host smart-a13867af-cd4a-4770-a668-e411a8b1ea58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180795495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2180795495
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.521343503
Short name T482
Test name
Test status
Simulation time 237963058 ps
CPU time 5.98 seconds
Started Aug 05 04:34:41 PM PDT 24
Finished Aug 05 04:34:52 PM PDT 24
Peak memory 207888 kb
Host smart-48e42c04-ca2b-433e-b64a-2e6ea1745b1f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521343503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.521343503
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2095664878
Short name T450
Test name
Test status
Simulation time 64783607 ps
CPU time 3.21 seconds
Started Aug 05 04:34:17 PM PDT 24
Finished Aug 05 04:34:21 PM PDT 24
Peak memory 208996 kb
Host smart-999b1331-90aa-445b-a1a9-176e7dfcc92a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095664878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2095664878
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3034685482
Short name T526
Test name
Test status
Simulation time 196594938 ps
CPU time 3.62 seconds
Started Aug 05 04:33:59 PM PDT 24
Finished Aug 05 04:34:03 PM PDT 24
Peak memory 208728 kb
Host smart-76b4d50d-649b-42a0-9b9e-94381943fde2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034685482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3034685482
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.577180217
Short name T45
Test name
Test status
Simulation time 117976807 ps
CPU time 1.68 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 206904 kb
Host smart-96dc6b9d-57a3-4245-98f3-5c406b4c0f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577180217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.577180217
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1179916143
Short name T434
Test name
Test status
Simulation time 29156299 ps
CPU time 1.95 seconds
Started Aug 05 04:34:34 PM PDT 24
Finished Aug 05 04:34:36 PM PDT 24
Peak memory 208780 kb
Host smart-12d38555-e447-4644-a0ff-ed7d0c30c6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179916143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1179916143
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2411478839
Short name T856
Test name
Test status
Simulation time 78079947 ps
CPU time 2.77 seconds
Started Aug 05 04:34:14 PM PDT 24
Finished Aug 05 04:34:17 PM PDT 24
Peak memory 207912 kb
Host smart-e60f4a77-e592-4a74-919d-0e0e6fe7cc49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411478839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2411478839
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3744538304
Short name T326
Test name
Test status
Simulation time 186445291 ps
CPU time 3.12 seconds
Started Aug 05 04:34:32 PM PDT 24
Finished Aug 05 04:34:35 PM PDT 24
Peak memory 222248 kb
Host smart-9b0e895c-979c-410f-a1fe-831ecdcdc498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744538304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3744538304
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2799444991
Short name T903
Test name
Test status
Simulation time 35586425 ps
CPU time 1.73 seconds
Started Aug 05 04:34:17 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 209952 kb
Host smart-1cff72c8-7e57-4b2e-87b0-8022e705237e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799444991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2799444991
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2290859691
Short name T436
Test name
Test status
Simulation time 46147132 ps
CPU time 0.73 seconds
Started Aug 05 04:33:13 PM PDT 24
Finished Aug 05 04:33:14 PM PDT 24
Peak memory 205784 kb
Host smart-63372209-c3ea-4a4a-b904-8f6bce44802c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290859691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2290859691
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1319345155
Short name T414
Test name
Test status
Simulation time 36116923 ps
CPU time 2.46 seconds
Started Aug 05 04:32:54 PM PDT 24
Finished Aug 05 04:32:57 PM PDT 24
Peak memory 214208 kb
Host smart-64bea6c3-99ea-4098-8785-1c0526def09d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319345155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1319345155
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3482390315
Short name T177
Test name
Test status
Simulation time 376870798 ps
CPU time 1.65 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 208680 kb
Host smart-8d269fb4-d6c5-48d4-ab4d-a76e39bfbf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482390315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3482390315
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4205119715
Short name T857
Test name
Test status
Simulation time 226513110 ps
CPU time 2.99 seconds
Started Aug 05 04:33:38 PM PDT 24
Finished Aug 05 04:33:42 PM PDT 24
Peak memory 209328 kb
Host smart-aef18fb0-3ccb-4d34-9a0b-3d1f0cc0b5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205119715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4205119715
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1958638326
Short name T100
Test name
Test status
Simulation time 30950069 ps
CPU time 2.44 seconds
Started Aug 05 04:33:18 PM PDT 24
Finished Aug 05 04:33:21 PM PDT 24
Peak memory 208984 kb
Host smart-7b32297f-8dc0-41b6-ba57-37e3c9181155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958638326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1958638326
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.945979803
Short name T208
Test name
Test status
Simulation time 164891929 ps
CPU time 2.35 seconds
Started Aug 05 04:33:02 PM PDT 24
Finished Aug 05 04:33:05 PM PDT 24
Peak memory 215060 kb
Host smart-bd50d000-2967-40f3-8821-2aa15b8da427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945979803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.945979803
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3927758710
Short name T305
Test name
Test status
Simulation time 157279939 ps
CPU time 6.2 seconds
Started Aug 05 04:32:57 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 214400 kb
Host smart-01d5cbfa-a58f-4f0d-b0a1-8c881b88f368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927758710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3927758710
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.715538795
Short name T44
Test name
Test status
Simulation time 922909128 ps
CPU time 5.39 seconds
Started Aug 05 04:32:58 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 233140 kb
Host smart-5d279cc9-2e90-4a56-a494-171bff857a47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715538795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.715538795
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2961190869
Short name T847
Test name
Test status
Simulation time 249804941 ps
CPU time 2.97 seconds
Started Aug 05 04:33:00 PM PDT 24
Finished Aug 05 04:33:08 PM PDT 24
Peak memory 206824 kb
Host smart-0fe79640-cc83-4482-a035-7e114d2e6027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961190869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2961190869
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3498854421
Short name T562
Test name
Test status
Simulation time 56851535 ps
CPU time 2.79 seconds
Started Aug 05 04:33:06 PM PDT 24
Finished Aug 05 04:33:09 PM PDT 24
Peak memory 208404 kb
Host smart-7a401151-93a2-4702-a7d0-65a7c975f8cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498854421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3498854421
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3306376166
Short name T384
Test name
Test status
Simulation time 10671194801 ps
CPU time 36.43 seconds
Started Aug 05 04:33:05 PM PDT 24
Finished Aug 05 04:33:42 PM PDT 24
Peak memory 207252 kb
Host smart-af05b38c-5246-4f41-a78f-6223f4894a97
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306376166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3306376166
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.349742185
Short name T818
Test name
Test status
Simulation time 155402584 ps
CPU time 2.38 seconds
Started Aug 05 04:32:48 PM PDT 24
Finished Aug 05 04:32:51 PM PDT 24
Peak memory 215552 kb
Host smart-a70421df-b953-42e6-a24e-231a35917061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349742185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.349742185
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.529520234
Short name T592
Test name
Test status
Simulation time 37691369 ps
CPU time 2.15 seconds
Started Aug 05 04:33:02 PM PDT 24
Finished Aug 05 04:33:04 PM PDT 24
Peak memory 206672 kb
Host smart-5a411758-ff03-44ad-a3c2-116460ea0dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529520234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.529520234
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.883010260
Short name T107
Test name
Test status
Simulation time 1038097659 ps
CPU time 16.3 seconds
Started Aug 05 04:33:16 PM PDT 24
Finished Aug 05 04:33:32 PM PDT 24
Peak memory 218756 kb
Host smart-b71df5af-13b0-4c5d-8258-7883cd264b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883010260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.883010260
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2601538961
Short name T333
Test name
Test status
Simulation time 85084477 ps
CPU time 4.03 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:33:00 PM PDT 24
Peak memory 218416 kb
Host smart-90db2303-da16-40ff-96fc-5d006ce345e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601538961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2601538961
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3909110733
Short name T861
Test name
Test status
Simulation time 26490141 ps
CPU time 0.93 seconds
Started Aug 05 04:34:20 PM PDT 24
Finished Aug 05 04:34:23 PM PDT 24
Peak memory 206016 kb
Host smart-ba08c92e-7c11-4182-b183-e35993cbfd33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909110733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3909110733
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1479862837
Short name T595
Test name
Test status
Simulation time 937745106 ps
CPU time 7.95 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:24 PM PDT 24
Peak memory 218392 kb
Host smart-9c0d4e1f-3ce4-4ddb-923d-7ce4f1b08a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479862837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1479862837
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2586031264
Short name T252
Test name
Test status
Simulation time 176477904 ps
CPU time 2.86 seconds
Started Aug 05 04:34:24 PM PDT 24
Finished Aug 05 04:34:27 PM PDT 24
Peak memory 207432 kb
Host smart-7f217d76-06bd-4d59-b7f5-d84e564122a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586031264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2586031264
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3020966154
Short name T786
Test name
Test status
Simulation time 172967624 ps
CPU time 3.47 seconds
Started Aug 05 04:34:32 PM PDT 24
Finished Aug 05 04:34:35 PM PDT 24
Peak memory 214280 kb
Host smart-cec5b2b2-8bc8-4636-96eb-8eb3bbd95c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020966154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3020966154
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3488434096
Short name T905
Test name
Test status
Simulation time 367721557 ps
CPU time 2.73 seconds
Started Aug 05 04:34:30 PM PDT 24
Finished Aug 05 04:34:33 PM PDT 24
Peak memory 220996 kb
Host smart-40148621-168b-4ce2-b2c2-45a119ea0817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488434096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3488434096
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.731539031
Short name T247
Test name
Test status
Simulation time 78895914 ps
CPU time 2.68 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 210468 kb
Host smart-4ba2b921-1d06-4181-9fe4-8dee60539bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731539031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.731539031
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1477304700
Short name T796
Test name
Test status
Simulation time 8846874875 ps
CPU time 88.8 seconds
Started Aug 05 04:34:22 PM PDT 24
Finished Aug 05 04:35:51 PM PDT 24
Peak memory 208464 kb
Host smart-a1b1d838-963f-42fa-9fba-878b06685aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477304700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1477304700
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1578391032
Short name T83
Test name
Test status
Simulation time 39831769 ps
CPU time 2.14 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:18 PM PDT 24
Peak memory 206732 kb
Host smart-741e60e1-1549-4c74-913d-f9225c5c24c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578391032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1578391032
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3616949982
Short name T836
Test name
Test status
Simulation time 105555995 ps
CPU time 3.33 seconds
Started Aug 05 04:34:19 PM PDT 24
Finished Aug 05 04:34:22 PM PDT 24
Peak memory 208028 kb
Host smart-61f83922-8ae5-4a7b-9a86-42e96ce305e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616949982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3616949982
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.213431107
Short name T254
Test name
Test status
Simulation time 104481472 ps
CPU time 2.18 seconds
Started Aug 05 04:34:05 PM PDT 24
Finished Aug 05 04:34:07 PM PDT 24
Peak memory 208900 kb
Host smart-45636bf7-103a-4d4e-89b3-bd1b053e9be7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213431107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.213431107
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2645131895
Short name T723
Test name
Test status
Simulation time 87294892 ps
CPU time 1.86 seconds
Started Aug 05 04:34:21 PM PDT 24
Finished Aug 05 04:34:23 PM PDT 24
Peak memory 206860 kb
Host smart-0acd3abe-aef4-488e-a745-473c6610d087
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645131895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2645131895
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1238562403
Short name T328
Test name
Test status
Simulation time 102078696 ps
CPU time 3.57 seconds
Started Aug 05 04:34:10 PM PDT 24
Finished Aug 05 04:34:13 PM PDT 24
Peak memory 208528 kb
Host smart-568fdd8a-9f60-4a22-acf3-901d585d3851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238562403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1238562403
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2062632670
Short name T512
Test name
Test status
Simulation time 210137622 ps
CPU time 2.91 seconds
Started Aug 05 04:34:20 PM PDT 24
Finished Aug 05 04:34:23 PM PDT 24
Peak memory 207984 kb
Host smart-ae3a170d-5e86-4c2c-9a05-d2c17f1cd6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062632670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2062632670
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1797275778
Short name T845
Test name
Test status
Simulation time 315106973 ps
CPU time 4.98 seconds
Started Aug 05 04:34:22 PM PDT 24
Finished Aug 05 04:34:27 PM PDT 24
Peak memory 207192 kb
Host smart-a0167ff9-28f8-4177-99bf-b3874bd91bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797275778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1797275778
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.4189970634
Short name T178
Test name
Test status
Simulation time 1235489907 ps
CPU time 21.07 seconds
Started Aug 05 04:34:20 PM PDT 24
Finished Aug 05 04:34:42 PM PDT 24
Peak memory 222304 kb
Host smart-921b7d38-b197-4d27-b5ba-e0cfc9c5e22d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189970634 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.4189970634
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1852817843
Short name T187
Test name
Test status
Simulation time 226279964 ps
CPU time 3.09 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 207452 kb
Host smart-0c89b63d-b490-46ea-8c48-2ba736b3a58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852817843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1852817843
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.830767777
Short name T718
Test name
Test status
Simulation time 166256347 ps
CPU time 2.11 seconds
Started Aug 05 04:34:25 PM PDT 24
Finished Aug 05 04:34:27 PM PDT 24
Peak memory 210204 kb
Host smart-fdda6362-b8b3-4249-b20b-3d103399905a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830767777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.830767777
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3265266270
Short name T842
Test name
Test status
Simulation time 68071179 ps
CPU time 0.75 seconds
Started Aug 05 04:34:18 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 205820 kb
Host smart-1a1b079e-5e09-4f27-b766-7e3514092a71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265266270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3265266270
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.266793957
Short name T411
Test name
Test status
Simulation time 273502647 ps
CPU time 12.96 seconds
Started Aug 05 04:34:26 PM PDT 24
Finished Aug 05 04:34:39 PM PDT 24
Peak memory 215636 kb
Host smart-46fde997-1887-43bb-8b96-04742966760b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=266793957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.266793957
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.4034219416
Short name T189
Test name
Test status
Simulation time 82372026 ps
CPU time 2.02 seconds
Started Aug 05 04:34:21 PM PDT 24
Finished Aug 05 04:34:23 PM PDT 24
Peak memory 207392 kb
Host smart-a7871c9f-2035-4811-9a7b-a069935acead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034219416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.4034219416
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3798144830
Short name T68
Test name
Test status
Simulation time 150815991 ps
CPU time 2.25 seconds
Started Aug 05 04:34:31 PM PDT 24
Finished Aug 05 04:34:34 PM PDT 24
Peak memory 209036 kb
Host smart-da172cb5-eed9-40e1-9205-5720490f4782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798144830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3798144830
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1038663711
Short name T302
Test name
Test status
Simulation time 310931847 ps
CPU time 3.95 seconds
Started Aug 05 04:34:18 PM PDT 24
Finished Aug 05 04:34:22 PM PDT 24
Peak memory 214220 kb
Host smart-532dd0d1-d9f1-47d1-877a-8730c28906ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038663711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1038663711
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2084451598
Short name T759
Test name
Test status
Simulation time 298717132 ps
CPU time 3.76 seconds
Started Aug 05 04:34:31 PM PDT 24
Finished Aug 05 04:34:34 PM PDT 24
Peak memory 220464 kb
Host smart-892f1e30-3925-4dc1-a320-0431173ffaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084451598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2084451598
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1682190997
Short name T372
Test name
Test status
Simulation time 338127552 ps
CPU time 4.31 seconds
Started Aug 05 04:34:40 PM PDT 24
Finished Aug 05 04:34:45 PM PDT 24
Peak memory 209176 kb
Host smart-994ee438-1ced-440a-a260-7a8019085f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682190997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1682190997
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2418087724
Short name T565
Test name
Test status
Simulation time 60877072 ps
CPU time 3.02 seconds
Started Aug 05 04:34:13 PM PDT 24
Finished Aug 05 04:34:17 PM PDT 24
Peak memory 208640 kb
Host smart-7197a51c-17bc-4ee7-8ddb-4e8cdbfcb9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418087724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2418087724
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.265002820
Short name T650
Test name
Test status
Simulation time 3472940112 ps
CPU time 22.93 seconds
Started Aug 05 04:34:35 PM PDT 24
Finished Aug 05 04:34:58 PM PDT 24
Peak memory 208768 kb
Host smart-d675332f-6302-45bf-8c5c-1bacf22c902f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265002820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.265002820
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3796250858
Short name T834
Test name
Test status
Simulation time 534816451 ps
CPU time 6.76 seconds
Started Aug 05 04:34:27 PM PDT 24
Finished Aug 05 04:34:34 PM PDT 24
Peak memory 206836 kb
Host smart-3fb5c4a5-9ea0-40fa-8a69-930fcd6d84df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796250858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3796250858
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.905917518
Short name T294
Test name
Test status
Simulation time 35274696 ps
CPU time 2.31 seconds
Started Aug 05 04:34:31 PM PDT 24
Finished Aug 05 04:34:33 PM PDT 24
Peak memory 206820 kb
Host smart-b2f02b98-3298-4042-b541-c2be1ca70665
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905917518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.905917518
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1614379226
Short name T457
Test name
Test status
Simulation time 63640836 ps
CPU time 3.17 seconds
Started Aug 05 04:34:16 PM PDT 24
Finished Aug 05 04:34:20 PM PDT 24
Peak memory 215368 kb
Host smart-8f241fd5-e3a6-4231-8604-0f9df5549f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614379226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1614379226
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4254910306
Short name T785
Test name
Test status
Simulation time 119198776 ps
CPU time 2.2 seconds
Started Aug 05 04:34:20 PM PDT 24
Finished Aug 05 04:34:22 PM PDT 24
Peak memory 206696 kb
Host smart-4e82de9b-fc44-491f-8444-a00119231157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254910306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4254910306
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3325625754
Short name T611
Test name
Test status
Simulation time 1633785747 ps
CPU time 5.43 seconds
Started Aug 05 04:34:32 PM PDT 24
Finished Aug 05 04:34:38 PM PDT 24
Peak memory 207200 kb
Host smart-c04956ce-c531-451f-8537-c6a0f9e925b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325625754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3325625754
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3902633975
Short name T762
Test name
Test status
Simulation time 280220683 ps
CPU time 2.89 seconds
Started Aug 05 04:34:42 PM PDT 24
Finished Aug 05 04:34:45 PM PDT 24
Peak memory 209784 kb
Host smart-74e4aa20-0906-4dd9-a3f2-37e30a13cac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902633975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3902633975
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3436828922
Short name T106
Test name
Test status
Simulation time 15967533 ps
CPU time 0.78 seconds
Started Aug 05 04:34:32 PM PDT 24
Finished Aug 05 04:34:33 PM PDT 24
Peak memory 205796 kb
Host smart-03f695cf-640f-4021-80c4-a91739da8a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436828922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3436828922
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3635045135
Short name T57
Test name
Test status
Simulation time 112894257 ps
CPU time 3.92 seconds
Started Aug 05 04:34:18 PM PDT 24
Finished Aug 05 04:34:22 PM PDT 24
Peak memory 208128 kb
Host smart-02def07f-abf4-49d8-b827-9f7edff3ac35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635045135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3635045135
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.676077456
Short name T896
Test name
Test status
Simulation time 228221484 ps
CPU time 5.07 seconds
Started Aug 05 04:34:20 PM PDT 24
Finished Aug 05 04:34:25 PM PDT 24
Peak memory 217164 kb
Host smart-ef911379-5dde-4a97-8a14-9345f91b40cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676077456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.676077456
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.899862298
Short name T24
Test name
Test status
Simulation time 371881305 ps
CPU time 4.62 seconds
Started Aug 05 04:34:29 PM PDT 24
Finished Aug 05 04:34:34 PM PDT 24
Peak memory 222300 kb
Host smart-421de99b-8385-4b26-b0de-50567eca4810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899862298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.899862298
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1358628199
Short name T638
Test name
Test status
Simulation time 110370511 ps
CPU time 3.29 seconds
Started Aug 05 04:34:25 PM PDT 24
Finished Aug 05 04:34:28 PM PDT 24
Peak memory 218708 kb
Host smart-51889c42-176c-4d65-8450-0edfd058eb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358628199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1358628199
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1570015607
Short name T631
Test name
Test status
Simulation time 128378004 ps
CPU time 4.41 seconds
Started Aug 05 04:34:31 PM PDT 24
Finished Aug 05 04:34:35 PM PDT 24
Peak memory 217592 kb
Host smart-2c11682a-53e2-408d-8a94-bc245f6f472b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570015607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1570015607
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.4133790069
Short name T800
Test name
Test status
Simulation time 446341820 ps
CPU time 3.71 seconds
Started Aug 05 04:34:35 PM PDT 24
Finished Aug 05 04:34:39 PM PDT 24
Peak memory 207864 kb
Host smart-b3673f4b-112c-4731-869a-eb726f512a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133790069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.4133790069
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.301682692
Short name T332
Test name
Test status
Simulation time 228137884 ps
CPU time 2.92 seconds
Started Aug 05 04:34:21 PM PDT 24
Finished Aug 05 04:34:24 PM PDT 24
Peak memory 208088 kb
Host smart-f453daef-4f52-4135-98fc-78d4365dd4ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301682692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.301682692
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3359747464
Short name T642
Test name
Test status
Simulation time 127827343 ps
CPU time 3.13 seconds
Started Aug 05 04:34:23 PM PDT 24
Finished Aug 05 04:34:26 PM PDT 24
Peak memory 207232 kb
Host smart-019683fd-88fa-4a81-ab46-dbfd67c33d9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359747464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3359747464
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.739161988
Short name T909
Test name
Test status
Simulation time 990994478 ps
CPU time 3.03 seconds
Started Aug 05 04:34:11 PM PDT 24
Finished Aug 05 04:34:14 PM PDT 24
Peak memory 206644 kb
Host smart-c523cc8b-9619-438f-83f6-f6d39257964a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739161988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.739161988
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1950487405
Short name T897
Test name
Test status
Simulation time 42511567 ps
CPU time 1.99 seconds
Started Aug 05 04:34:35 PM PDT 24
Finished Aug 05 04:34:38 PM PDT 24
Peak memory 215796 kb
Host smart-16a7dc30-29ec-4b24-8e3f-dc39ff6bc3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950487405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1950487405
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1954004972
Short name T79
Test name
Test status
Simulation time 252597171 ps
CPU time 5.14 seconds
Started Aug 05 04:34:28 PM PDT 24
Finished Aug 05 04:34:33 PM PDT 24
Peak memory 207856 kb
Host smart-281b8dcd-30ef-4ada-85a7-bc30c3903934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954004972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1954004972
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2921146928
Short name T643
Test name
Test status
Simulation time 902775834 ps
CPU time 12.72 seconds
Started Aug 05 04:34:24 PM PDT 24
Finished Aug 05 04:34:37 PM PDT 24
Peak memory 215616 kb
Host smart-930d2f8d-ec8c-434f-a90b-91adf553941e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921146928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2921146928
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3921476061
Short name T576
Test name
Test status
Simulation time 285161652 ps
CPU time 4.26 seconds
Started Aug 05 04:34:19 PM PDT 24
Finished Aug 05 04:34:24 PM PDT 24
Peak memory 207488 kb
Host smart-0b781899-a182-48c6-9a89-cb404cb7db6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921476061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3921476061
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2371125479
Short name T590
Test name
Test status
Simulation time 42661550 ps
CPU time 1.93 seconds
Started Aug 05 04:34:37 PM PDT 24
Finished Aug 05 04:34:39 PM PDT 24
Peak memory 209636 kb
Host smart-ca755564-17de-49ce-8761-c9b1d1430510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371125479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2371125479
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3591269262
Short name T645
Test name
Test status
Simulation time 17116152 ps
CPU time 0.95 seconds
Started Aug 05 04:34:26 PM PDT 24
Finished Aug 05 04:34:27 PM PDT 24
Peak memory 205984 kb
Host smart-3a065d39-0133-4435-b725-b90cc3f186d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591269262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3591269262
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1235760288
Short name T900
Test name
Test status
Simulation time 1820886211 ps
CPU time 79.4 seconds
Started Aug 05 04:34:38 PM PDT 24
Finished Aug 05 04:35:58 PM PDT 24
Peak memory 214260 kb
Host smart-0a1a3214-ef27-476c-88b8-10bcad974fa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235760288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1235760288
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2990778578
Short name T29
Test name
Test status
Simulation time 147884282 ps
CPU time 3.16 seconds
Started Aug 05 04:34:32 PM PDT 24
Finished Aug 05 04:34:36 PM PDT 24
Peak memory 217560 kb
Host smart-818aa0f0-4180-4ac5-8029-c32e6f8fc084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990778578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2990778578
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.149584781
Short name T877
Test name
Test status
Simulation time 466356424 ps
CPU time 2.28 seconds
Started Aug 05 04:34:27 PM PDT 24
Finished Aug 05 04:34:30 PM PDT 24
Peak memory 206880 kb
Host smart-ff6d6c53-e723-449a-ba62-b14348b67c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149584781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.149584781
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1083736858
Short name T92
Test name
Test status
Simulation time 235929612 ps
CPU time 7.73 seconds
Started Aug 05 04:34:32 PM PDT 24
Finished Aug 05 04:34:40 PM PDT 24
Peak memory 209172 kb
Host smart-3c6edbb8-3e73-4110-9989-95054bc6d1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083736858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1083736858
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1649365883
Short name T534
Test name
Test status
Simulation time 1330053117 ps
CPU time 4.39 seconds
Started Aug 05 04:34:36 PM PDT 24
Finished Aug 05 04:34:41 PM PDT 24
Peak memory 222296 kb
Host smart-48be96a0-e20e-4f93-aecd-53b90b75a759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649365883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1649365883
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.311198307
Short name T423
Test name
Test status
Simulation time 88716010 ps
CPU time 2.71 seconds
Started Aug 05 04:34:37 PM PDT 24
Finished Aug 05 04:34:40 PM PDT 24
Peak memory 219680 kb
Host smart-6775165b-0290-4e97-8774-f8bc98ec7feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311198307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.311198307
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3472750581
Short name T827
Test name
Test status
Simulation time 699438108 ps
CPU time 5.4 seconds
Started Aug 05 04:34:51 PM PDT 24
Finished Aug 05 04:34:56 PM PDT 24
Peak memory 208612 kb
Host smart-d792c8f5-657b-40bc-b0fe-5a1ec6dc9da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472750581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3472750581
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1596770732
Short name T330
Test name
Test status
Simulation time 510919873 ps
CPU time 2.52 seconds
Started Aug 05 04:34:28 PM PDT 24
Finished Aug 05 04:34:31 PM PDT 24
Peak memory 206576 kb
Host smart-d7946c51-b37a-41ce-b343-3f2947dec4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596770732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1596770732
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.382691150
Short name T514
Test name
Test status
Simulation time 3022280977 ps
CPU time 30.13 seconds
Started Aug 05 04:34:30 PM PDT 24
Finished Aug 05 04:35:05 PM PDT 24
Peak memory 208684 kb
Host smart-8def4413-347b-4ad4-93af-6151a492f8b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382691150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.382691150
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1513500327
Short name T621
Test name
Test status
Simulation time 92757572 ps
CPU time 1.84 seconds
Started Aug 05 04:34:37 PM PDT 24
Finished Aug 05 04:34:39 PM PDT 24
Peak memory 206760 kb
Host smart-90248180-2243-4850-8ff9-b50aaf56fc8f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513500327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1513500327
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3073433198
Short name T886
Test name
Test status
Simulation time 67246450 ps
CPU time 3.13 seconds
Started Aug 05 04:34:34 PM PDT 24
Finished Aug 05 04:34:38 PM PDT 24
Peak memory 208940 kb
Host smart-0404f2ad-fe11-417f-bb2e-43c567259a90
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073433198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3073433198
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1947124283
Short name T729
Test name
Test status
Simulation time 49392623 ps
CPU time 1.57 seconds
Started Aug 05 04:34:17 PM PDT 24
Finished Aug 05 04:34:19 PM PDT 24
Peak memory 207824 kb
Host smart-e96be6d0-0d8a-437a-81b8-8abfd1d6e6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947124283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1947124283
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3011177845
Short name T536
Test name
Test status
Simulation time 1802871284 ps
CPU time 4.34 seconds
Started Aug 05 04:34:32 PM PDT 24
Finished Aug 05 04:34:36 PM PDT 24
Peak memory 208756 kb
Host smart-c2766c79-8789-4a18-904d-1d2b31e2abfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011177845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3011177845
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3451619243
Short name T288
Test name
Test status
Simulation time 997695186 ps
CPU time 15.61 seconds
Started Aug 05 04:34:27 PM PDT 24
Finished Aug 05 04:34:43 PM PDT 24
Peak memory 221332 kb
Host smart-cc85fa5c-1604-4365-b611-90a8d334f529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451619243 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3451619243
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.734604090
Short name T872
Test name
Test status
Simulation time 545235932 ps
CPU time 12.79 seconds
Started Aug 05 04:34:29 PM PDT 24
Finished Aug 05 04:34:42 PM PDT 24
Peak memory 214188 kb
Host smart-fe7a35d6-b1d4-4997-936c-889a5e73c89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734604090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.734604090
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1992356087
Short name T124
Test name
Test status
Simulation time 65150167 ps
CPU time 1.91 seconds
Started Aug 05 04:34:20 PM PDT 24
Finished Aug 05 04:34:22 PM PDT 24
Peak memory 209352 kb
Host smart-f6ba2b4c-588d-42b3-8dd3-b1b18b46d8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992356087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1992356087
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.321554807
Short name T578
Test name
Test status
Simulation time 42202358 ps
CPU time 0.74 seconds
Started Aug 05 04:34:45 PM PDT 24
Finished Aug 05 04:34:46 PM PDT 24
Peak memory 205848 kb
Host smart-a9d229a0-092b-482f-a90c-29eeceed95c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321554807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.321554807
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2026765423
Short name T292
Test name
Test status
Simulation time 1004335919 ps
CPU time 12.99 seconds
Started Aug 05 04:34:30 PM PDT 24
Finished Aug 05 04:34:43 PM PDT 24
Peak memory 215428 kb
Host smart-1ea19220-7f71-41e4-94c2-8b9d7288c991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2026765423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2026765423
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1744821792
Short name T141
Test name
Test status
Simulation time 729261926 ps
CPU time 2 seconds
Started Aug 05 04:34:30 PM PDT 24
Finished Aug 05 04:34:32 PM PDT 24
Peak memory 217704 kb
Host smart-d8076c45-8548-40a0-aa33-8ef916079ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744821792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1744821792
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2553247240
Short name T185
Test name
Test status
Simulation time 737544270 ps
CPU time 6.68 seconds
Started Aug 05 04:34:33 PM PDT 24
Finished Aug 05 04:34:40 PM PDT 24
Peak memory 214240 kb
Host smart-a00c07f9-895f-499b-a026-e6236e0509ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553247240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2553247240
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.115444311
Short name T539
Test name
Test status
Simulation time 46196783 ps
CPU time 1.89 seconds
Started Aug 05 04:34:35 PM PDT 24
Finished Aug 05 04:34:37 PM PDT 24
Peak memory 214180 kb
Host smart-edb544bc-bfcb-4664-b8c4-7a99cac96aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115444311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.115444311
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1100254875
Short name T78
Test name
Test status
Simulation time 506171784 ps
CPU time 4.29 seconds
Started Aug 05 04:34:28 PM PDT 24
Finished Aug 05 04:34:32 PM PDT 24
Peak memory 214128 kb
Host smart-fd3c4f35-a867-40fe-939f-ecee57f76dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100254875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1100254875
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1179681874
Short name T801
Test name
Test status
Simulation time 163994498 ps
CPU time 6.57 seconds
Started Aug 05 04:34:22 PM PDT 24
Finished Aug 05 04:34:29 PM PDT 24
Peak memory 222356 kb
Host smart-0e8ee217-513d-4393-af15-34f94fd5af8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179681874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1179681874
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.73211571
Short name T280
Test name
Test status
Simulation time 886493436 ps
CPU time 6.19 seconds
Started Aug 05 04:34:22 PM PDT 24
Finished Aug 05 04:34:28 PM PDT 24
Peak memory 209824 kb
Host smart-0471875c-005f-42cf-8bc9-208ae5bfaaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73211571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.73211571
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3075941632
Short name T865
Test name
Test status
Simulation time 55188928 ps
CPU time 2.88 seconds
Started Aug 05 04:34:30 PM PDT 24
Finished Aug 05 04:34:33 PM PDT 24
Peak memory 206860 kb
Host smart-8452c278-3413-453d-a741-7cdb6f32f374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075941632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3075941632
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1201529110
Short name T110
Test name
Test status
Simulation time 196738848 ps
CPU time 3.02 seconds
Started Aug 05 04:34:38 PM PDT 24
Finished Aug 05 04:34:41 PM PDT 24
Peak memory 206836 kb
Host smart-8df1b9cc-7316-4caf-8fc9-ba2c234841a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201529110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1201529110
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2341582586
Short name T472
Test name
Test status
Simulation time 193525475 ps
CPU time 2.72 seconds
Started Aug 05 04:34:31 PM PDT 24
Finished Aug 05 04:34:33 PM PDT 24
Peak memory 207532 kb
Host smart-49335fd4-2c72-4fd6-b6b4-6e83949cd35e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341582586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2341582586
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1734132573
Short name T714
Test name
Test status
Simulation time 107892504 ps
CPU time 2.89 seconds
Started Aug 05 04:34:29 PM PDT 24
Finished Aug 05 04:34:32 PM PDT 24
Peak memory 208528 kb
Host smart-02f3394c-0b03-4625-9858-6cba3030d2ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734132573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1734132573
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3842976506
Short name T869
Test name
Test status
Simulation time 114567336 ps
CPU time 2.43 seconds
Started Aug 05 04:34:35 PM PDT 24
Finished Aug 05 04:34:37 PM PDT 24
Peak memory 209572 kb
Host smart-6c9da65f-30d7-456f-8e15-46f5d733879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842976506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3842976506
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1243935838
Short name T685
Test name
Test status
Simulation time 1340548287 ps
CPU time 7.22 seconds
Started Aug 05 04:34:34 PM PDT 24
Finished Aug 05 04:34:41 PM PDT 24
Peak memory 208692 kb
Host smart-b365dbe0-d995-4fb9-b373-bef2ad9d6d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243935838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1243935838
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2967989886
Short name T5
Test name
Test status
Simulation time 4259552736 ps
CPU time 21.39 seconds
Started Aug 05 04:34:46 PM PDT 24
Finished Aug 05 04:35:08 PM PDT 24
Peak memory 222416 kb
Host smart-f506b46a-50c3-4839-a7bd-76ffbc921390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967989886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2967989886
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2743185968
Short name T338
Test name
Test status
Simulation time 146186460 ps
CPU time 6.34 seconds
Started Aug 05 04:34:23 PM PDT 24
Finished Aug 05 04:34:29 PM PDT 24
Peak memory 207208 kb
Host smart-7491301f-45aa-4531-ba9d-d193fdc12263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743185968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2743185968
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3740468574
Short name T39
Test name
Test status
Simulation time 37815139 ps
CPU time 1.45 seconds
Started Aug 05 04:34:33 PM PDT 24
Finished Aug 05 04:34:35 PM PDT 24
Peak memory 209804 kb
Host smart-9d8e357e-3de7-4079-9966-151348d0b7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740468574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3740468574
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3306140087
Short name T804
Test name
Test status
Simulation time 62639110 ps
CPU time 0.76 seconds
Started Aug 05 04:34:38 PM PDT 24
Finished Aug 05 04:34:38 PM PDT 24
Peak memory 205848 kb
Host smart-8734a22a-1652-45aa-94a2-2d619d41b878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306140087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3306140087
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.900290042
Short name T884
Test name
Test status
Simulation time 96914295 ps
CPU time 3.66 seconds
Started Aug 05 04:34:30 PM PDT 24
Finished Aug 05 04:34:34 PM PDT 24
Peak memory 214184 kb
Host smart-24e9af9d-86bd-4a24-8638-eeda42c137c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900290042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.900290042
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3639888274
Short name T764
Test name
Test status
Simulation time 312912821 ps
CPU time 11.5 seconds
Started Aug 05 04:34:41 PM PDT 24
Finished Aug 05 04:34:52 PM PDT 24
Peak memory 216880 kb
Host smart-b4c41b10-af9b-4873-8daa-31cb69d802cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639888274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3639888274
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3091694887
Short name T344
Test name
Test status
Simulation time 109037585 ps
CPU time 2.12 seconds
Started Aug 05 04:34:28 PM PDT 24
Finished Aug 05 04:34:30 PM PDT 24
Peak memory 209736 kb
Host smart-7583e07a-abb6-490d-8932-309d5bef975c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091694887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3091694887
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2317857683
Short name T198
Test name
Test status
Simulation time 92336556 ps
CPU time 3.2 seconds
Started Aug 05 04:34:36 PM PDT 24
Finished Aug 05 04:34:40 PM PDT 24
Peak memory 214128 kb
Host smart-91080194-2252-436a-8200-47cc8bfcd714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317857683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2317857683
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3926686734
Short name T234
Test name
Test status
Simulation time 58892309 ps
CPU time 3.13 seconds
Started Aug 05 04:34:50 PM PDT 24
Finished Aug 05 04:34:54 PM PDT 24
Peak memory 208648 kb
Host smart-c0b9f3a4-ae86-429d-9d67-f828ea02bcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926686734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3926686734
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3680681350
Short name T853
Test name
Test status
Simulation time 634093216 ps
CPU time 4.49 seconds
Started Aug 05 04:34:30 PM PDT 24
Finished Aug 05 04:34:35 PM PDT 24
Peak memory 207988 kb
Host smart-c9c8b83c-223b-4ca2-88c5-5a623024b885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680681350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3680681350
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1001115777
Short name T259
Test name
Test status
Simulation time 220115360 ps
CPU time 7.88 seconds
Started Aug 05 04:34:30 PM PDT 24
Finished Aug 05 04:34:38 PM PDT 24
Peak memory 207236 kb
Host smart-2e9d2dff-9499-4fb7-9ffd-165d8530a581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001115777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1001115777
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.61242918
Short name T495
Test name
Test status
Simulation time 460968895 ps
CPU time 4.04 seconds
Started Aug 05 04:34:29 PM PDT 24
Finished Aug 05 04:34:33 PM PDT 24
Peak memory 208492 kb
Host smart-958e3be4-11d8-4056-86a4-cf35a747f16a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61242918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.61242918
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3608636868
Short name T610
Test name
Test status
Simulation time 1189535986 ps
CPU time 6.97 seconds
Started Aug 05 04:34:36 PM PDT 24
Finished Aug 05 04:34:43 PM PDT 24
Peak memory 208724 kb
Host smart-62d4ffd6-9c73-4ddc-ba0b-682092bf8b7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608636868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3608636868
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.888401478
Short name T515
Test name
Test status
Simulation time 114297916 ps
CPU time 4.28 seconds
Started Aug 05 04:34:33 PM PDT 24
Finished Aug 05 04:34:37 PM PDT 24
Peak memory 208688 kb
Host smart-7a5ee1a5-81bc-48cf-abb2-0419fca38614
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888401478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.888401478
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3922392255
Short name T417
Test name
Test status
Simulation time 3098474779 ps
CPU time 10.47 seconds
Started Aug 05 04:34:23 PM PDT 24
Finished Aug 05 04:34:33 PM PDT 24
Peak memory 214276 kb
Host smart-e50ba52a-5d2f-43aa-a5b7-32c6a6d34b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922392255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3922392255
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1259632201
Short name T816
Test name
Test status
Simulation time 215780323 ps
CPU time 3.11 seconds
Started Aug 05 04:34:21 PM PDT 24
Finished Aug 05 04:34:25 PM PDT 24
Peak memory 208376 kb
Host smart-4adadd00-3b97-4c03-83d0-bf296efcc4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259632201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1259632201
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.485086780
Short name T382
Test name
Test status
Simulation time 170691708 ps
CPU time 4.14 seconds
Started Aug 05 04:34:34 PM PDT 24
Finished Aug 05 04:34:39 PM PDT 24
Peak memory 209092 kb
Host smart-e54de0c8-5829-4ee3-bea0-f51beec72f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485086780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.485086780
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2399495851
Short name T168
Test name
Test status
Simulation time 176486756 ps
CPU time 2.76 seconds
Started Aug 05 04:34:42 PM PDT 24
Finished Aug 05 04:34:45 PM PDT 24
Peak memory 209876 kb
Host smart-107c4937-7413-44b6-bfc4-f003a35fed24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399495851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2399495851
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.18383851
Short name T439
Test name
Test status
Simulation time 45539108 ps
CPU time 0.77 seconds
Started Aug 05 04:34:52 PM PDT 24
Finished Aug 05 04:34:53 PM PDT 24
Peak memory 205820 kb
Host smart-b5a85ef3-e1eb-4c8f-9764-bf2b80468d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18383851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.18383851
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1387370899
Short name T273
Test name
Test status
Simulation time 78188404 ps
CPU time 3.3 seconds
Started Aug 05 04:34:44 PM PDT 24
Finished Aug 05 04:34:47 PM PDT 24
Peak memory 215152 kb
Host smart-c6ce09c0-9e0a-4f4c-a261-a78070fe9ee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1387370899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1387370899
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1469098531
Short name T220
Test name
Test status
Simulation time 182520873 ps
CPU time 6.87 seconds
Started Aug 05 04:34:30 PM PDT 24
Finished Aug 05 04:34:37 PM PDT 24
Peak memory 222616 kb
Host smart-b51eddde-03f4-4ef6-ab04-6adce5e52c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469098531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1469098531
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.168564857
Short name T568
Test name
Test status
Simulation time 94449987 ps
CPU time 2.57 seconds
Started Aug 05 04:34:29 PM PDT 24
Finished Aug 05 04:34:31 PM PDT 24
Peak memory 207460 kb
Host smart-8f38df5e-e54e-49a6-9827-94d84e2c27c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168564857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.168564857
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1965372375
Short name T87
Test name
Test status
Simulation time 175842176 ps
CPU time 3.25 seconds
Started Aug 05 04:34:36 PM PDT 24
Finished Aug 05 04:34:40 PM PDT 24
Peak memory 214444 kb
Host smart-27579753-efda-462c-9eea-0ba6708f91ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965372375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1965372375
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1223644739
Short name T366
Test name
Test status
Simulation time 379316280 ps
CPU time 1.93 seconds
Started Aug 05 04:34:32 PM PDT 24
Finished Aug 05 04:34:34 PM PDT 24
Peak memory 205948 kb
Host smart-98f7ca24-efcf-4b66-946a-17c26474d80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223644739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1223644739
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3782468776
Short name T876
Test name
Test status
Simulation time 49016072 ps
CPU time 3.18 seconds
Started Aug 05 04:34:36 PM PDT 24
Finished Aug 05 04:34:39 PM PDT 24
Peak memory 220564 kb
Host smart-0fc1c060-9be3-42a7-aa22-7a5a1be42b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782468776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3782468776
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3071018213
Short name T201
Test name
Test status
Simulation time 36891458 ps
CPU time 2.38 seconds
Started Aug 05 04:34:33 PM PDT 24
Finished Aug 05 04:34:36 PM PDT 24
Peak memory 214268 kb
Host smart-268db797-ff3c-4e1d-a824-1e4e0670c63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071018213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3071018213
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2634601115
Short name T862
Test name
Test status
Simulation time 57602282 ps
CPU time 2.92 seconds
Started Aug 05 04:34:28 PM PDT 24
Finished Aug 05 04:34:31 PM PDT 24
Peak memory 208680 kb
Host smart-c68b5c52-5627-4312-9cb0-53caf917a610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634601115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2634601115
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.746678574
Short name T908
Test name
Test status
Simulation time 21168309 ps
CPU time 1.8 seconds
Started Aug 05 04:34:36 PM PDT 24
Finished Aug 05 04:34:38 PM PDT 24
Peak memory 206836 kb
Host smart-a4769cbf-d434-42c2-a4a1-c10cda9965b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746678574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.746678574
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3913750544
Short name T84
Test name
Test status
Simulation time 610695148 ps
CPU time 6.03 seconds
Started Aug 05 04:34:35 PM PDT 24
Finished Aug 05 04:34:41 PM PDT 24
Peak memory 209052 kb
Host smart-6b616742-921a-41b8-9f89-247a9daa37b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913750544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3913750544
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1290625442
Short name T850
Test name
Test status
Simulation time 72059287 ps
CPU time 3.18 seconds
Started Aug 05 04:34:22 PM PDT 24
Finished Aug 05 04:34:25 PM PDT 24
Peak memory 208744 kb
Host smart-b0295913-404a-4641-8abd-7ef39f2f9c80
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290625442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1290625442
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1576964729
Short name T244
Test name
Test status
Simulation time 36752819 ps
CPU time 2.19 seconds
Started Aug 05 04:34:36 PM PDT 24
Finished Aug 05 04:34:38 PM PDT 24
Peak memory 218328 kb
Host smart-68f10a04-85af-4f15-8082-63111c75a287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576964729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1576964729
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.295616645
Short name T15
Test name
Test status
Simulation time 228687317 ps
CPU time 2.96 seconds
Started Aug 05 04:34:47 PM PDT 24
Finished Aug 05 04:34:50 PM PDT 24
Peak memory 208508 kb
Host smart-3c5630f6-b2a6-41c1-8daa-cac3694f3247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295616645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.295616645
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2207017394
Short name T69
Test name
Test status
Simulation time 1071885964 ps
CPU time 10.13 seconds
Started Aug 05 04:34:36 PM PDT 24
Finished Aug 05 04:34:47 PM PDT 24
Peak memory 219776 kb
Host smart-5a0d6b18-156b-4558-a3c0-5f06ef1c2323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207017394 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2207017394
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2358474425
Short name T271
Test name
Test status
Simulation time 2131717337 ps
CPU time 5.74 seconds
Started Aug 05 04:34:50 PM PDT 24
Finished Aug 05 04:34:56 PM PDT 24
Peak memory 207644 kb
Host smart-4228714f-9980-4bd0-b3b6-bad1ee864be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358474425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2358474425
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1853278556
Short name T852
Test name
Test status
Simulation time 38781610 ps
CPU time 1.42 seconds
Started Aug 05 04:34:30 PM PDT 24
Finished Aug 05 04:34:32 PM PDT 24
Peak memory 208512 kb
Host smart-b3072350-365c-4d66-9134-831669b78650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853278556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1853278556
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2726076419
Short name T455
Test name
Test status
Simulation time 51230438 ps
CPU time 0.76 seconds
Started Aug 05 04:34:40 PM PDT 24
Finished Aug 05 04:34:41 PM PDT 24
Peak memory 205812 kb
Host smart-34fa9f6e-fe01-4915-a3f7-ecc64289a3a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726076419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2726076419
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.898255674
Short name T232
Test name
Test status
Simulation time 131124998 ps
CPU time 2.8 seconds
Started Aug 05 04:34:48 PM PDT 24
Finished Aug 05 04:34:50 PM PDT 24
Peak memory 214296 kb
Host smart-874a2906-ac67-4d33-bd56-0635104ac714
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=898255674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.898255674
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.863480393
Short name T33
Test name
Test status
Simulation time 413794899 ps
CPU time 2.89 seconds
Started Aug 05 04:34:29 PM PDT 24
Finished Aug 05 04:34:32 PM PDT 24
Peak memory 220324 kb
Host smart-04660a91-4a05-4b36-80b7-13ca4b68738c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863480393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.863480393
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1734162332
Short name T556
Test name
Test status
Simulation time 47898776 ps
CPU time 2.57 seconds
Started Aug 05 04:34:49 PM PDT 24
Finished Aug 05 04:34:52 PM PDT 24
Peak memory 208568 kb
Host smart-566c4da5-30e7-4977-b149-3818b20df501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734162332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1734162332
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3933794182
Short name T90
Test name
Test status
Simulation time 152413899 ps
CPU time 5.67 seconds
Started Aug 05 04:34:39 PM PDT 24
Finished Aug 05 04:34:45 PM PDT 24
Peak memory 214200 kb
Host smart-6bb7b17b-b373-4c06-bc23-391fed3d11b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933794182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3933794182
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1376634791
Short name T518
Test name
Test status
Simulation time 320798928 ps
CPU time 2.62 seconds
Started Aug 05 04:34:29 PM PDT 24
Finished Aug 05 04:34:31 PM PDT 24
Peak memory 214328 kb
Host smart-61ba2c58-b6e6-42d5-b9a8-734a862fe066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376634791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1376634791
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2711454788
Short name T206
Test name
Test status
Simulation time 932562236 ps
CPU time 4.05 seconds
Started Aug 05 04:34:25 PM PDT 24
Finished Aug 05 04:34:30 PM PDT 24
Peak memory 214256 kb
Host smart-ea1ebe3e-eb35-430d-b866-681750828670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711454788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2711454788
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1182172438
Short name T658
Test name
Test status
Simulation time 136977921 ps
CPU time 3.93 seconds
Started Aug 05 04:34:36 PM PDT 24
Finished Aug 05 04:34:41 PM PDT 24
Peak memory 207520 kb
Host smart-bc924455-b75c-451e-8239-ea2194826954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182172438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1182172438
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2778889480
Short name T329
Test name
Test status
Simulation time 45339932 ps
CPU time 2.57 seconds
Started Aug 05 04:34:40 PM PDT 24
Finished Aug 05 04:34:43 PM PDT 24
Peak memory 206672 kb
Host smart-3564cae2-cbbc-4186-88bd-27694bd4a065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778889480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2778889480
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1409953008
Short name T466
Test name
Test status
Simulation time 3153111443 ps
CPU time 55.99 seconds
Started Aug 05 04:34:33 PM PDT 24
Finished Aug 05 04:35:29 PM PDT 24
Peak memory 208072 kb
Host smart-fcc25045-898e-48d4-b823-391ca51ae3f1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409953008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1409953008
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3476559769
Short name T353
Test name
Test status
Simulation time 54377436 ps
CPU time 2.96 seconds
Started Aug 05 04:34:44 PM PDT 24
Finished Aug 05 04:34:47 PM PDT 24
Peak memory 206804 kb
Host smart-12ef6e97-dd9b-4a34-8995-f9b7fa2ba9cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476559769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3476559769
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2701382260
Short name T740
Test name
Test status
Simulation time 350411585 ps
CPU time 5.42 seconds
Started Aug 05 04:34:36 PM PDT 24
Finished Aug 05 04:34:42 PM PDT 24
Peak memory 208912 kb
Host smart-b597b3fc-8fc6-477f-96eb-e3d1f3ef3514
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701382260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2701382260
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.4149232333
Short name T898
Test name
Test status
Simulation time 152688305 ps
CPU time 3.38 seconds
Started Aug 05 04:34:47 PM PDT 24
Finished Aug 05 04:34:51 PM PDT 24
Peak memory 214148 kb
Host smart-0c0a8bae-f442-411c-bd67-e7c458f36c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149232333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.4149232333
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2001052624
Short name T397
Test name
Test status
Simulation time 86571403 ps
CPU time 2.62 seconds
Started Aug 05 04:34:33 PM PDT 24
Finished Aug 05 04:34:36 PM PDT 24
Peak memory 208828 kb
Host smart-94823f96-0bf9-459d-aa7e-ab4ec7a49fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001052624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2001052624
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1785766420
Short name T749
Test name
Test status
Simulation time 1597058483 ps
CPU time 15.86 seconds
Started Aug 05 04:34:32 PM PDT 24
Finished Aug 05 04:34:47 PM PDT 24
Peak memory 222488 kb
Host smart-ff29be82-0083-4c0e-bbc5-180c0c2c39e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785766420 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1785766420
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2592401892
Short name T196
Test name
Test status
Simulation time 123787029 ps
CPU time 2.54 seconds
Started Aug 05 04:34:36 PM PDT 24
Finished Aug 05 04:34:39 PM PDT 24
Peak memory 207960 kb
Host smart-5155e7e9-6ade-4f35-b49d-ea9ae416b2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592401892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2592401892
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3369352722
Short name T766
Test name
Test status
Simulation time 38624022 ps
CPU time 2.05 seconds
Started Aug 05 04:34:36 PM PDT 24
Finished Aug 05 04:34:38 PM PDT 24
Peak memory 209720 kb
Host smart-dbde1419-b083-4ebc-ac2b-7317a15bd439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369352722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3369352722
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.649134679
Short name T580
Test name
Test status
Simulation time 14996427 ps
CPU time 0.76 seconds
Started Aug 05 04:34:25 PM PDT 24
Finished Aug 05 04:34:26 PM PDT 24
Peak memory 205844 kb
Host smart-17a5a5a6-b3d2-4ed2-9b44-777e57754763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649134679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.649134679
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.4101941429
Short name T420
Test name
Test status
Simulation time 1046943747 ps
CPU time 12.62 seconds
Started Aug 05 04:34:37 PM PDT 24
Finished Aug 05 04:34:50 PM PDT 24
Peak memory 214156 kb
Host smart-00cf6354-a0cc-4a09-b092-309d09a627b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101941429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.4101941429
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1913551594
Short name T693
Test name
Test status
Simulation time 251723167 ps
CPU time 3.12 seconds
Started Aug 05 04:34:46 PM PDT 24
Finished Aug 05 04:34:49 PM PDT 24
Peak memory 209120 kb
Host smart-81da4873-c75a-413d-8060-2b14713e4b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913551594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1913551594
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.902447228
Short name T261
Test name
Test status
Simulation time 125232281 ps
CPU time 2.42 seconds
Started Aug 05 04:34:41 PM PDT 24
Finished Aug 05 04:34:44 PM PDT 24
Peak memory 207716 kb
Host smart-6515d055-6472-45de-a7cf-de09beca6233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902447228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.902447228
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2573303581
Short name T89
Test name
Test status
Simulation time 44784084 ps
CPU time 2.33 seconds
Started Aug 05 04:34:58 PM PDT 24
Finished Aug 05 04:35:05 PM PDT 24
Peak memory 214280 kb
Host smart-2cabe055-deed-419b-bf73-479a2f2ab6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573303581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2573303581
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.111234323
Short name T285
Test name
Test status
Simulation time 166689607 ps
CPU time 6.46 seconds
Started Aug 05 04:34:51 PM PDT 24
Finished Aug 05 04:34:57 PM PDT 24
Peak memory 214304 kb
Host smart-13269cdd-0d15-40d1-8f78-66dae9c17a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111234323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.111234323
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1423612589
Short name T108
Test name
Test status
Simulation time 712087118 ps
CPU time 34.84 seconds
Started Aug 05 04:34:35 PM PDT 24
Finished Aug 05 04:35:10 PM PDT 24
Peak memory 220364 kb
Host smart-8a6fdc05-295e-4518-a0dc-2f65fddfbc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423612589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1423612589
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.418549748
Short name T81
Test name
Test status
Simulation time 67980047 ps
CPU time 3.94 seconds
Started Aug 05 04:34:29 PM PDT 24
Finished Aug 05 04:34:38 PM PDT 24
Peak memory 207600 kb
Host smart-d82ce8da-faea-4267-bbdc-2459b541195d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418549748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.418549748
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2436244698
Short name T904
Test name
Test status
Simulation time 829528212 ps
CPU time 15.24 seconds
Started Aug 05 04:35:02 PM PDT 24
Finished Aug 05 04:35:17 PM PDT 24
Peak memory 208488 kb
Host smart-a05b8d50-f5a8-4442-a633-1a0083cc9565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436244698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2436244698
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.922504963
Short name T467
Test name
Test status
Simulation time 112047736 ps
CPU time 3.36 seconds
Started Aug 05 04:34:30 PM PDT 24
Finished Aug 05 04:34:34 PM PDT 24
Peak memory 206740 kb
Host smart-1e8b2843-6f96-4f8e-a5fd-f6da1f02451f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922504963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.922504963
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3241577493
Short name T404
Test name
Test status
Simulation time 69499161 ps
CPU time 3 seconds
Started Aug 05 04:34:40 PM PDT 24
Finished Aug 05 04:34:43 PM PDT 24
Peak memory 206684 kb
Host smart-05a40419-9f64-454b-a2d2-de6443ca28a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241577493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3241577493
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3620257134
Short name T530
Test name
Test status
Simulation time 35810665 ps
CPU time 2.51 seconds
Started Aug 05 04:34:40 PM PDT 24
Finished Aug 05 04:34:43 PM PDT 24
Peak memory 207040 kb
Host smart-e3932977-19da-423b-a5e0-61e5b0a63690
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620257134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3620257134
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1475079378
Short name T859
Test name
Test status
Simulation time 2319235907 ps
CPU time 13.98 seconds
Started Aug 05 04:34:37 PM PDT 24
Finished Aug 05 04:34:51 PM PDT 24
Peak memory 218192 kb
Host smart-8b75f584-def8-4c6e-92fd-9cdb6017b82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475079378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1475079378
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2629708339
Short name T567
Test name
Test status
Simulation time 244272131 ps
CPU time 4.56 seconds
Started Aug 05 04:34:39 PM PDT 24
Finished Aug 05 04:34:44 PM PDT 24
Peak memory 206840 kb
Host smart-d5180942-3f87-4d9f-b18d-503b3fb770c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629708339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2629708339
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2207704816
Short name T496
Test name
Test status
Simulation time 1266710142 ps
CPU time 9 seconds
Started Aug 05 04:34:55 PM PDT 24
Finished Aug 05 04:35:04 PM PDT 24
Peak memory 209240 kb
Host smart-52e82cde-946c-47f0-a611-f47811689c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207704816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2207704816
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1996133329
Short name T35
Test name
Test status
Simulation time 76610384 ps
CPU time 1.85 seconds
Started Aug 05 04:35:03 PM PDT 24
Finished Aug 05 04:35:05 PM PDT 24
Peak memory 209828 kb
Host smart-a5bba87a-c405-4c1a-aabb-5c91cd12f289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996133329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1996133329
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.999812308
Short name T752
Test name
Test status
Simulation time 56273260 ps
CPU time 0.93 seconds
Started Aug 05 04:34:49 PM PDT 24
Finished Aug 05 04:34:50 PM PDT 24
Peak memory 205984 kb
Host smart-9c6b1dce-90f2-40d3-ba3e-e29122d563db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999812308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.999812308
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1435862608
Short name T699
Test name
Test status
Simulation time 469081632 ps
CPU time 4.55 seconds
Started Aug 05 04:34:51 PM PDT 24
Finished Aug 05 04:34:55 PM PDT 24
Peak memory 220868 kb
Host smart-d55a1806-d8ee-4a75-8d46-4055f24c2ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435862608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1435862608
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1073127906
Short name T701
Test name
Test status
Simulation time 550621504 ps
CPU time 5.63 seconds
Started Aug 05 04:34:35 PM PDT 24
Finished Aug 05 04:34:41 PM PDT 24
Peak memory 208072 kb
Host smart-61e0f08a-d2aa-47a1-a494-8ab2086f4c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073127906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1073127906
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2992816148
Short name T99
Test name
Test status
Simulation time 582568402 ps
CPU time 4.95 seconds
Started Aug 05 04:34:44 PM PDT 24
Finished Aug 05 04:34:49 PM PDT 24
Peak memory 214144 kb
Host smart-4246c95f-0886-4769-99bb-8e8e815594ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992816148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2992816148
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1907207926
Short name T52
Test name
Test status
Simulation time 53740325 ps
CPU time 1.87 seconds
Started Aug 05 04:34:39 PM PDT 24
Finished Aug 05 04:34:41 PM PDT 24
Peak memory 214400 kb
Host smart-f83f87e2-614a-41fe-8c68-a2122524cd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907207926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1907207926
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.4207425080
Short name T48
Test name
Test status
Simulation time 276714356 ps
CPU time 3.6 seconds
Started Aug 05 04:35:00 PM PDT 24
Finished Aug 05 04:35:03 PM PDT 24
Peak memory 214196 kb
Host smart-00a1867c-ee6d-4015-8733-6fa135979056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207425080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.4207425080
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.374865290
Short name T810
Test name
Test status
Simulation time 63792088 ps
CPU time 3.45 seconds
Started Aug 05 04:34:41 PM PDT 24
Finished Aug 05 04:34:45 PM PDT 24
Peak memory 207704 kb
Host smart-904327ef-e8b8-482e-b123-23e428036d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374865290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.374865290
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2043703902
Short name T879
Test name
Test status
Simulation time 385211340 ps
CPU time 3.62 seconds
Started Aug 05 04:35:09 PM PDT 24
Finished Aug 05 04:35:13 PM PDT 24
Peak memory 207280 kb
Host smart-9436d588-869f-4bcd-ab20-65d87c456d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043703902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2043703902
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3642588011
Short name T202
Test name
Test status
Simulation time 239204559 ps
CPU time 3.77 seconds
Started Aug 05 04:34:50 PM PDT 24
Finished Aug 05 04:34:54 PM PDT 24
Peak memory 206744 kb
Host smart-d06aa437-cda2-4bc0-8fd7-90ac273e2c67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642588011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3642588011
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3620210623
Short name T793
Test name
Test status
Simulation time 301564411 ps
CPU time 4.53 seconds
Started Aug 05 04:34:51 PM PDT 24
Finished Aug 05 04:34:56 PM PDT 24
Peak memory 208396 kb
Host smart-50771d53-edf6-4833-aa7c-df2d3cdb19e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620210623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3620210623
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2232150578
Short name T566
Test name
Test status
Simulation time 84730442 ps
CPU time 3.23 seconds
Started Aug 05 04:34:45 PM PDT 24
Finished Aug 05 04:34:49 PM PDT 24
Peak memory 208084 kb
Host smart-8b9ec3b9-a8b0-41b7-b8c3-4d9177b5a653
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232150578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2232150578
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1041781695
Short name T80
Test name
Test status
Simulation time 229786836 ps
CPU time 1.93 seconds
Started Aug 05 04:34:38 PM PDT 24
Finished Aug 05 04:34:40 PM PDT 24
Peak memory 207508 kb
Host smart-8ff44b92-2727-429c-bbed-bc80de7d7f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041781695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1041781695
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1953849274
Short name T584
Test name
Test status
Simulation time 31604554 ps
CPU time 1.99 seconds
Started Aug 05 04:34:53 PM PDT 24
Finished Aug 05 04:34:55 PM PDT 24
Peak memory 206740 kb
Host smart-9df40c25-41b1-4e37-afae-315135071142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953849274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1953849274
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.248228139
Short name T219
Test name
Test status
Simulation time 1293005043 ps
CPU time 26.52 seconds
Started Aug 05 04:34:48 PM PDT 24
Finished Aug 05 04:35:15 PM PDT 24
Peak memory 216352 kb
Host smart-6648a2ad-af3a-4614-93fd-7437d5f2d5db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248228139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.248228139
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.2272101192
Short name T582
Test name
Test status
Simulation time 93835227 ps
CPU time 5.49 seconds
Started Aug 05 04:34:52 PM PDT 24
Finished Aug 05 04:34:57 PM PDT 24
Peak memory 219248 kb
Host smart-ffe9f685-c782-48ce-9cfe-e3bf9d4a63be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272101192 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.2272101192
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3441002042
Short name T308
Test name
Test status
Simulation time 192487578 ps
CPU time 7.01 seconds
Started Aug 05 04:34:37 PM PDT 24
Finished Aug 05 04:34:44 PM PDT 24
Peak memory 209568 kb
Host smart-87d3e3d4-7e12-41c8-b0ce-1e64997c2ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441002042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3441002042
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3135267163
Short name T538
Test name
Test status
Simulation time 145593155 ps
CPU time 3.12 seconds
Started Aug 05 04:35:04 PM PDT 24
Finished Aug 05 04:35:07 PM PDT 24
Peak memory 209964 kb
Host smart-214fe89b-fd11-47cb-bd3a-a8bf3097632b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135267163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3135267163
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1171797742
Short name T725
Test name
Test status
Simulation time 21134471 ps
CPU time 0.81 seconds
Started Aug 05 04:32:43 PM PDT 24
Finished Aug 05 04:32:44 PM PDT 24
Peak memory 205736 kb
Host smart-92fc1e76-ffb8-457e-99ff-1bf796eeb040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171797742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1171797742
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.578191351
Short name T410
Test name
Test status
Simulation time 815798877 ps
CPU time 10 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:33:05 PM PDT 24
Peak memory 214164 kb
Host smart-803bebf4-2dd1-4a82-9e3b-5204a330ed13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578191351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.578191351
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3147688184
Short name T49
Test name
Test status
Simulation time 193178418 ps
CPU time 2.33 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:32:57 PM PDT 24
Peak memory 209792 kb
Host smart-cdf80608-02f8-4e86-afc6-e6134dc896eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147688184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3147688184
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3763771378
Short name T341
Test name
Test status
Simulation time 147233247 ps
CPU time 4.12 seconds
Started Aug 05 04:32:57 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 222356 kb
Host smart-6e2c622c-3a42-4343-ad42-4d9afa74ee1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763771378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3763771378
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_random.2398262446
Short name T849
Test name
Test status
Simulation time 424531896 ps
CPU time 5.29 seconds
Started Aug 05 04:33:11 PM PDT 24
Finished Aug 05 04:33:17 PM PDT 24
Peak memory 219656 kb
Host smart-5d4c69f5-26ac-4435-9467-d9a89d1aa0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398262446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2398262446
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1861936750
Short name T277
Test name
Test status
Simulation time 140701597 ps
CPU time 4.57 seconds
Started Aug 05 04:32:58 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 206648 kb
Host smart-ee93481e-e7ad-4ae2-960b-2514cb2d4409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861936750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1861936750
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.239290935
Short name T636
Test name
Test status
Simulation time 59280053 ps
CPU time 2.46 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:02 PM PDT 24
Peak memory 206676 kb
Host smart-2f7e71ff-3bc7-4958-8f19-6b4d922fcc50
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239290935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.239290935
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1188008079
Short name T788
Test name
Test status
Simulation time 121766476 ps
CPU time 3.69 seconds
Started Aug 05 04:33:08 PM PDT 24
Finished Aug 05 04:33:12 PM PDT 24
Peak memory 207948 kb
Host smart-cc9dadb0-0210-4c3a-88c5-a80f6b603b4a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188008079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1188008079
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1216264902
Short name T354
Test name
Test status
Simulation time 192044703 ps
CPU time 6.34 seconds
Started Aug 05 04:32:49 PM PDT 24
Finished Aug 05 04:32:55 PM PDT 24
Peak memory 207972 kb
Host smart-da2f4e99-a527-444a-b880-262f50d9e0a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216264902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1216264902
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1134057183
Short name T184
Test name
Test status
Simulation time 194205106 ps
CPU time 2.36 seconds
Started Aug 05 04:32:57 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 209788 kb
Host smart-7428aaae-c7a7-4ebe-b106-f324d4269e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134057183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1134057183
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2907444277
Short name T626
Test name
Test status
Simulation time 269289530 ps
CPU time 2.7 seconds
Started Aug 05 04:32:51 PM PDT 24
Finished Aug 05 04:32:54 PM PDT 24
Peak memory 206620 kb
Host smart-75556989-b42c-4c4c-8fd6-329976919608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907444277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2907444277
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1013789022
Short name T282
Test name
Test status
Simulation time 1189051166 ps
CPU time 11.56 seconds
Started Aug 05 04:32:49 PM PDT 24
Finished Aug 05 04:33:00 PM PDT 24
Peak memory 216768 kb
Host smart-80c48fec-2251-4556-ad2e-82fd4c97e884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013789022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1013789022
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1001591915
Short name T664
Test name
Test status
Simulation time 351748485 ps
CPU time 4.42 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 210288 kb
Host smart-61ce0bac-b018-4bd5-a588-f881961e018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001591915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1001591915
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2270558161
Short name T549
Test name
Test status
Simulation time 60026182 ps
CPU time 2.57 seconds
Started Aug 05 04:33:14 PM PDT 24
Finished Aug 05 04:33:16 PM PDT 24
Peak memory 209992 kb
Host smart-a939b9ee-d2f7-491a-9e65-5a22c6879a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270558161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2270558161
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2535214050
Short name T431
Test name
Test status
Simulation time 73623145 ps
CPU time 0.88 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 205792 kb
Host smart-624c95d3-e129-4cbe-adb5-39c8f01610cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535214050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2535214050
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.212454051
Short name T824
Test name
Test status
Simulation time 627296477 ps
CPU time 3.9 seconds
Started Aug 05 04:32:57 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 215144 kb
Host smart-3eda80b2-9b5d-4d97-86e4-7230afc5d5dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212454051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.212454051
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2989953935
Short name T487
Test name
Test status
Simulation time 202390928 ps
CPU time 3.4 seconds
Started Aug 05 04:32:44 PM PDT 24
Finished Aug 05 04:32:48 PM PDT 24
Peak memory 208476 kb
Host smart-cb643ebd-dfa5-4769-952a-9e830e25cce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989953935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2989953935
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2015418190
Short name T627
Test name
Test status
Simulation time 164681139 ps
CPU time 2.21 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 208684 kb
Host smart-c72e139d-a786-4713-97de-9a7d3cb46f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015418190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2015418190
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3409437306
Short name T98
Test name
Test status
Simulation time 497188215 ps
CPU time 3.96 seconds
Started Aug 05 04:32:54 PM PDT 24
Finished Aug 05 04:32:58 PM PDT 24
Peak memory 214200 kb
Host smart-74dea483-22cd-4291-8242-28451ac97d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409437306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3409437306
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2771443184
Short name T550
Test name
Test status
Simulation time 255029968 ps
CPU time 3.8 seconds
Started Aug 05 04:33:16 PM PDT 24
Finished Aug 05 04:33:20 PM PDT 24
Peak memory 222300 kb
Host smart-f3be63a1-24e1-4717-adf2-42f5cdc695ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771443184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2771443184
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_random.2286890777
Short name T554
Test name
Test status
Simulation time 178675612 ps
CPU time 4.45 seconds
Started Aug 05 04:33:06 PM PDT 24
Finished Aug 05 04:33:10 PM PDT 24
Peak memory 207852 kb
Host smart-6aa347fc-f8f8-4793-82cb-e26c62deb4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286890777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2286890777
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3917697838
Short name T671
Test name
Test status
Simulation time 437286129 ps
CPU time 3.72 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 206720 kb
Host smart-5fda7d06-3cd9-471d-9747-766bcec73453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917697838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3917697838
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1763713793
Short name T882
Test name
Test status
Simulation time 304133935 ps
CPU time 6.72 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:06 PM PDT 24
Peak memory 208684 kb
Host smart-e667922b-383b-4db1-a33b-96e46ad20179
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763713793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1763713793
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2809889971
Short name T253
Test name
Test status
Simulation time 244908249 ps
CPU time 2.74 seconds
Started Aug 05 04:33:09 PM PDT 24
Finished Aug 05 04:33:12 PM PDT 24
Peak memory 206732 kb
Host smart-68cac7d9-0338-472f-8c77-f89f09e9b6a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809889971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2809889971
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2461647870
Short name T519
Test name
Test status
Simulation time 197840422 ps
CPU time 2.95 seconds
Started Aug 05 04:33:06 PM PDT 24
Finished Aug 05 04:33:09 PM PDT 24
Peak memory 206772 kb
Host smart-99a6959d-9e4c-40cc-aeda-b4c60ec7b41f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461647870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2461647870
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1288312007
Short name T791
Test name
Test status
Simulation time 158023886 ps
CPU time 3.55 seconds
Started Aug 05 04:33:05 PM PDT 24
Finished Aug 05 04:33:08 PM PDT 24
Peak memory 208996 kb
Host smart-80725f7c-ebdd-4f0a-ada2-d209f7dbbc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288312007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1288312007
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2734374755
Short name T673
Test name
Test status
Simulation time 72910905 ps
CPU time 1.56 seconds
Started Aug 05 04:32:49 PM PDT 24
Finished Aug 05 04:32:51 PM PDT 24
Peak memory 206712 kb
Host smart-73199e96-6533-4434-a72e-dc45e61a543b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734374755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2734374755
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.406035569
Short name T835
Test name
Test status
Simulation time 750360341 ps
CPU time 14.71 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:33:10 PM PDT 24
Peak memory 220520 kb
Host smart-5369a23b-6235-4a52-8ac3-1181a0503883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406035569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.406035569
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2228494455
Short name T808
Test name
Test status
Simulation time 617077741 ps
CPU time 4.35 seconds
Started Aug 05 04:32:56 PM PDT 24
Finished Aug 05 04:33:00 PM PDT 24
Peak memory 207880 kb
Host smart-d654f787-f3c7-4a56-8c07-d8a928272ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228494455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2228494455
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2305824232
Short name T401
Test name
Test status
Simulation time 110419291 ps
CPU time 2.87 seconds
Started Aug 05 04:32:58 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 209724 kb
Host smart-8ecd48bc-79f6-490c-b9b7-320431278f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305824232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2305824232
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3653708221
Short name T743
Test name
Test status
Simulation time 25208216 ps
CPU time 0.75 seconds
Started Aug 05 04:33:13 PM PDT 24
Finished Aug 05 04:33:14 PM PDT 24
Peak memory 205784 kb
Host smart-c61a0c6c-ffa5-4605-bc0c-c22d02b6f2ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653708221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3653708221
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1134196582
Short name T248
Test name
Test status
Simulation time 186230361 ps
CPU time 2.32 seconds
Started Aug 05 04:33:10 PM PDT 24
Finished Aug 05 04:33:12 PM PDT 24
Peak memory 214184 kb
Host smart-122108c2-cfb2-4630-a5f3-4892bda8d6fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1134196582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1134196582
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2859861023
Short name T901
Test name
Test status
Simulation time 127399638 ps
CPU time 1.98 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 207116 kb
Host smart-14a41cdb-330c-40ff-ad34-43376a39f5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859861023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2859861023
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.821681043
Short name T362
Test name
Test status
Simulation time 164797071 ps
CPU time 2.96 seconds
Started Aug 05 04:33:02 PM PDT 24
Finished Aug 05 04:33:06 PM PDT 24
Peak memory 209396 kb
Host smart-3472e532-ee0a-4944-b438-6b44da8c7e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821681043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.821681043
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1369137161
Short name T767
Test name
Test status
Simulation time 404880486 ps
CPU time 3.55 seconds
Started Aug 05 04:32:54 PM PDT 24
Finished Aug 05 04:32:58 PM PDT 24
Peak memory 220064 kb
Host smart-506dfd5e-a9a7-4ba1-882e-000cfddbf38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369137161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1369137161
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2001245698
Short name T375
Test name
Test status
Simulation time 969385328 ps
CPU time 3.72 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:32:59 PM PDT 24
Peak memory 218584 kb
Host smart-4f75481d-92e6-4ed4-9e37-f567435116e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001245698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2001245698
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3048997068
Short name T620
Test name
Test status
Simulation time 410594759 ps
CPU time 4.23 seconds
Started Aug 05 04:32:54 PM PDT 24
Finished Aug 05 04:32:59 PM PDT 24
Peak memory 210172 kb
Host smart-2175ba0b-e09c-4ffe-9e35-5c53251ed4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048997068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3048997068
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.4114168001
Short name T617
Test name
Test status
Simulation time 143729457 ps
CPU time 2.8 seconds
Started Aug 05 04:33:10 PM PDT 24
Finished Aug 05 04:33:13 PM PDT 24
Peak memory 206796 kb
Host smart-13829bc3-5a16-436d-9e73-e4c8812ef189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114168001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4114168001
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1241243546
Short name T309
Test name
Test status
Simulation time 90110879 ps
CPU time 3.28 seconds
Started Aug 05 04:33:05 PM PDT 24
Finished Aug 05 04:33:08 PM PDT 24
Peak memory 207300 kb
Host smart-465afbfc-6afa-421b-ad89-a2cbab2724ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241243546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1241243546
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.4282440718
Short name T521
Test name
Test status
Simulation time 63104385 ps
CPU time 2.21 seconds
Started Aug 05 04:32:49 PM PDT 24
Finished Aug 05 04:32:56 PM PDT 24
Peak memory 206836 kb
Host smart-03cad23f-5b90-453f-951c-c486521fb044
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282440718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.4282440718
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.4187877264
Short name T843
Test name
Test status
Simulation time 78726264 ps
CPU time 1.82 seconds
Started Aug 05 04:32:54 PM PDT 24
Finished Aug 05 04:32:56 PM PDT 24
Peak memory 206792 kb
Host smart-4dbf543a-1393-4750-957e-d81a5ca4f866
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187877264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.4187877264
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3371016463
Short name T13
Test name
Test status
Simulation time 96872892 ps
CPU time 1.79 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:03 PM PDT 24
Peak memory 207044 kb
Host smart-04e05a59-8763-4546-ade8-8787a420cb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371016463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3371016463
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3409164415
Short name T612
Test name
Test status
Simulation time 779731023 ps
CPU time 5.08 seconds
Started Aug 05 04:33:00 PM PDT 24
Finished Aug 05 04:33:05 PM PDT 24
Peak memory 208464 kb
Host smart-419efc50-b594-4a30-a4bd-4429cb193a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409164415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3409164415
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2617907902
Short name T797
Test name
Test status
Simulation time 1024520301 ps
CPU time 23.15 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:24 PM PDT 24
Peak memory 215048 kb
Host smart-b4dbf91a-6e2e-4592-bf5d-a76126f48ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617907902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2617907902
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3397107317
Short name T561
Test name
Test status
Simulation time 184602010 ps
CPU time 3.1 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:32:58 PM PDT 24
Peak memory 208016 kb
Host smart-9974d6f4-069b-41e0-b420-d9513e1cbc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397107317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3397107317
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1803758610
Short name T171
Test name
Test status
Simulation time 29364158 ps
CPU time 2.04 seconds
Started Aug 05 04:33:26 PM PDT 24
Finished Aug 05 04:33:28 PM PDT 24
Peak memory 209968 kb
Host smart-404d8d35-4ef7-4302-9f13-461a47418a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803758610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1803758610
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2345353840
Short name T105
Test name
Test status
Simulation time 29329898 ps
CPU time 0.85 seconds
Started Aug 05 04:33:04 PM PDT 24
Finished Aug 05 04:33:05 PM PDT 24
Peak memory 205760 kb
Host smart-febfea1b-4f4c-49b2-a769-4cfbf1320da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345353840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2345353840
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4106329068
Short name T399
Test name
Test status
Simulation time 121260124 ps
CPU time 3.85 seconds
Started Aug 05 04:33:00 PM PDT 24
Finished Aug 05 04:33:04 PM PDT 24
Peak memory 208584 kb
Host smart-2c79ff76-bcb4-41f4-bf7b-62bc0d855f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106329068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4106329068
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.937759514
Short name T691
Test name
Test status
Simulation time 35625040 ps
CPU time 2.56 seconds
Started Aug 05 04:33:10 PM PDT 24
Finished Aug 05 04:33:13 PM PDT 24
Peak memory 214168 kb
Host smart-70b3145f-77c7-4c7b-8aec-e9394970d5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937759514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.937759514
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3325033299
Short name T727
Test name
Test status
Simulation time 62712695 ps
CPU time 3.12 seconds
Started Aug 05 04:33:14 PM PDT 24
Finished Aug 05 04:33:17 PM PDT 24
Peak memory 214128 kb
Host smart-1f51f4b0-77de-463d-96f0-a7c6dd98c2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325033299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3325033299
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3470663349
Short name T551
Test name
Test status
Simulation time 96245137 ps
CPU time 2.62 seconds
Started Aug 05 04:32:51 PM PDT 24
Finished Aug 05 04:32:53 PM PDT 24
Peak memory 209492 kb
Host smart-d0f7e9d9-7c71-4ac1-8184-c61022a373e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470663349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3470663349
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.422610250
Short name T82
Test name
Test status
Simulation time 6821866134 ps
CPU time 69.46 seconds
Started Aug 05 04:33:14 PM PDT 24
Finished Aug 05 04:34:24 PM PDT 24
Peak memory 220640 kb
Host smart-1fb31137-a368-4f5b-93d9-d2d58798dc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422610250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.422610250
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1996990415
Short name T552
Test name
Test status
Simulation time 2573625789 ps
CPU time 46.36 seconds
Started Aug 05 04:32:52 PM PDT 24
Finished Aug 05 04:33:38 PM PDT 24
Peak memory 208328 kb
Host smart-b8556947-29e4-4a98-93d6-126c3f1ad3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996990415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1996990415
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1917535758
Short name T569
Test name
Test status
Simulation time 17386837757 ps
CPU time 45.17 seconds
Started Aug 05 04:32:55 PM PDT 24
Finished Aug 05 04:33:41 PM PDT 24
Peak memory 208284 kb
Host smart-2e07ed84-b41c-4684-851f-9af431658f67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917535758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1917535758
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2092833204
Short name T511
Test name
Test status
Simulation time 64930900 ps
CPU time 3.1 seconds
Started Aug 05 04:33:13 PM PDT 24
Finished Aug 05 04:33:16 PM PDT 24
Peak memory 208664 kb
Host smart-43e6b656-5a49-4ce3-9336-3efcacf96026
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092833204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2092833204
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1266898354
Short name T692
Test name
Test status
Simulation time 103474739 ps
CPU time 2.66 seconds
Started Aug 05 04:32:59 PM PDT 24
Finished Aug 05 04:33:01 PM PDT 24
Peak memory 206872 kb
Host smart-64d35c7e-04e3-4d2d-a88b-86873c41e6de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266898354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1266898354
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.128326896
Short name T376
Test name
Test status
Simulation time 71570737 ps
CPU time 2.42 seconds
Started Aug 05 04:33:15 PM PDT 24
Finished Aug 05 04:33:17 PM PDT 24
Peak memory 208332 kb
Host smart-89acc5f9-92cf-43a2-a595-1ed751c28d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128326896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.128326896
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3024869707
Short name T484
Test name
Test status
Simulation time 926861088 ps
CPU time 3.1 seconds
Started Aug 05 04:33:14 PM PDT 24
Finished Aug 05 04:33:17 PM PDT 24
Peak memory 208276 kb
Host smart-4840c75e-092c-4584-82ca-3378d2034be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024869707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3024869707
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1441091792
Short name T191
Test name
Test status
Simulation time 144881616 ps
CPU time 3.92 seconds
Started Aug 05 04:33:07 PM PDT 24
Finished Aug 05 04:33:16 PM PDT 24
Peak memory 209216 kb
Host smart-14ca1309-1033-4bbd-8276-88ba1d7e0862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441091792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1441091792
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.17391718
Short name T368
Test name
Test status
Simulation time 556359698 ps
CPU time 7.48 seconds
Started Aug 05 04:32:58 PM PDT 24
Finished Aug 05 04:33:06 PM PDT 24
Peak memory 214192 kb
Host smart-3b817c17-5179-4894-b48e-8f01747d7b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17391718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.17391718
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2931110686
Short name T537
Test name
Test status
Simulation time 47183091 ps
CPU time 2.63 seconds
Started Aug 05 04:33:20 PM PDT 24
Finished Aug 05 04:33:23 PM PDT 24
Peak memory 209964 kb
Host smart-94fa290f-b291-4a51-a063-038526169977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931110686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2931110686
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1485959531
Short name T911
Test name
Test status
Simulation time 26967716 ps
CPU time 0.97 seconds
Started Aug 05 04:33:04 PM PDT 24
Finished Aug 05 04:33:05 PM PDT 24
Peak memory 205992 kb
Host smart-8d009894-3bc0-4648-9b43-1577deec2387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485959531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1485959531
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3197002075
Short name T242
Test name
Test status
Simulation time 45384238 ps
CPU time 2.91 seconds
Started Aug 05 04:33:56 PM PDT 24
Finished Aug 05 04:34:00 PM PDT 24
Peak memory 213424 kb
Host smart-4088253b-fc7f-4727-9fea-544c63f3cc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197002075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3197002075
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3325661239
Short name T606
Test name
Test status
Simulation time 77882660 ps
CPU time 3.69 seconds
Started Aug 05 04:33:20 PM PDT 24
Finished Aug 05 04:33:24 PM PDT 24
Peak memory 214304 kb
Host smart-a3e4d90f-6c98-4aa3-86be-e41f90c8b0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325661239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3325661239
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2543829704
Short name T648
Test name
Test status
Simulation time 842299660 ps
CPU time 3.5 seconds
Started Aug 05 04:33:03 PM PDT 24
Finished Aug 05 04:33:07 PM PDT 24
Peak memory 222184 kb
Host smart-e36d08b2-d45e-411b-bca9-beeeffa608f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543829704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2543829704
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2371852484
Short name T527
Test name
Test status
Simulation time 52324703 ps
CPU time 2.61 seconds
Started Aug 05 04:33:12 PM PDT 24
Finished Aug 05 04:33:15 PM PDT 24
Peak memory 214176 kb
Host smart-15d72977-6495-418b-bfe1-1f05b9336e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371852484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2371852484
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.856813465
Short name T820
Test name
Test status
Simulation time 86186825 ps
CPU time 3.79 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:05 PM PDT 24
Peak memory 209168 kb
Host smart-9e15bc00-16b0-4a6d-8ebe-810445cef3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856813465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.856813465
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1462575805
Short name T720
Test name
Test status
Simulation time 263426370 ps
CPU time 3.6 seconds
Started Aug 05 04:33:17 PM PDT 24
Finished Aug 05 04:33:21 PM PDT 24
Peak memory 208224 kb
Host smart-450783f2-b0df-4011-aa2a-e17f2c4d3e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462575805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1462575805
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1211863132
Short name T672
Test name
Test status
Simulation time 475525045 ps
CPU time 5.54 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:07 PM PDT 24
Peak memory 208528 kb
Host smart-b53040f0-82a3-4b5a-a6dc-52961cce4842
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211863132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1211863132
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1818214953
Short name T654
Test name
Test status
Simulation time 359759573 ps
CPU time 4.27 seconds
Started Aug 05 04:33:04 PM PDT 24
Finished Aug 05 04:33:09 PM PDT 24
Peak memory 206764 kb
Host smart-54eff44c-52b0-4012-8099-46fe5a7fbbfa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818214953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1818214953
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1774481307
Short name T587
Test name
Test status
Simulation time 9647151944 ps
CPU time 48.75 seconds
Started Aug 05 04:33:00 PM PDT 24
Finished Aug 05 04:33:54 PM PDT 24
Peak memory 208236 kb
Host smart-ecb30160-39dc-4c24-af2d-89b52b4b9eba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774481307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1774481307
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2205703082
Short name T902
Test name
Test status
Simulation time 54547250 ps
CPU time 2.43 seconds
Started Aug 05 04:33:01 PM PDT 24
Finished Aug 05 04:33:04 PM PDT 24
Peak memory 209120 kb
Host smart-2f921a8f-d92d-4346-b3b7-2c21a1a4aad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205703082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2205703082
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.202510532
Short name T823
Test name
Test status
Simulation time 714414813 ps
CPU time 3.7 seconds
Started Aug 05 04:33:02 PM PDT 24
Finished Aug 05 04:33:06 PM PDT 24
Peak memory 206668 kb
Host smart-98baba4c-3969-4e8a-8d55-50ec9ab904a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202510532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.202510532
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1687448578
Short name T373
Test name
Test status
Simulation time 4960424738 ps
CPU time 39.58 seconds
Started Aug 05 04:33:02 PM PDT 24
Finished Aug 05 04:33:42 PM PDT 24
Peak memory 219748 kb
Host smart-d68821f7-1fa0-45a2-a3af-11946076f22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687448578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1687448578
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3083700282
Short name T677
Test name
Test status
Simulation time 370307297 ps
CPU time 4.03 seconds
Started Aug 05 04:33:22 PM PDT 24
Finished Aug 05 04:33:26 PM PDT 24
Peak memory 210156 kb
Host smart-cf2be705-1453-4c39-983f-eb29c0db4d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083700282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3083700282
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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