Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	13	36	73.47

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	12	23	65.71	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	49	1			T44	1		T6	1		T45	2
auto[OpGenId]	17	1			T27	1		T46	1		T161	1
auto[OpGenSwOut]	29	1			T52	1		T54	1		T57	1
auto[OpGenHwOut]	22	1			T6	1		T7	1		T46	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1922	1			T1	1		T4	2		T11	180
auto[StInit]	81	1			T33	1		T105	1		T20	1
auto[StCreatorRootKey]	62	1			T4	1		T55	1		T7	1
auto[StOwnerIntKey]	53	1			T5	1		T44	1		T21	1
auto[StOwnerKey]	32	1			T34	1		T37	1		T52	2
auto[StDisabled]	469	1			T1	3		T4	2		T105	5
auto[StInvalid]	50	1			T14	1		T18	1		T35	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3633

1

T1

5

T2

1

T3

1

auto[1]

117

1

T44

1

T27

1

T6

2

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1916	1			T1	1		T4	2		T11	180
auto[StReset]	auto[1]	6	1			T161	1		T48	1		T39	1
auto[StInit]	auto[0]	40	1			T33	1		T105	1		T20	1
auto[StInit]	auto[1]	41	1			T6	2		T54	1		T46	2
auto[StCreatorRootKey]	auto[0]	39	1			T4	1		T55	1		T64	1
auto[StCreatorRootKey]	auto[1]	23	1			T7	1		T45	2		T46	2
auto[StOwnerIntKey]	auto[0]	34	1			T5	1		T21	1		T57	1
auto[StOwnerIntKey]	auto[1]	19	1			T44	1		T46	2		T66	1
auto[StOwnerKey]	auto[0]	19	1			T34	1		T37	1		T52	1
auto[StOwnerKey]	auto[1]	13	1			T52	1		T57	1		T61	1
auto[StDisabled]	auto[0]	454	1			T1	3		T4	2		T105	5
auto[StDisabled]	auto[1]	15	1			T27	1		T46	1		T185	1
auto[StInvalid]	auto[0]	50	1			T14	1		T18	1		T35	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	12	23	65.71	12

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	5

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	4	1			T48	1		T186	1		T49	1
auto[StReset]	auto[OpGenId]	1	1			T161	1		-	-		-	-
auto[StReset]	auto[OpGenSwOut]	1	1			T39	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	17	1			T6	1		T46	2		T187	1
auto[StInit]	auto[OpGenId]	5	1			T9	1		T70	1		T188	1
auto[StInit]	auto[OpGenSwOut]	11	1			T54	1		T189	1		T190	1
auto[StInit]	auto[OpGenHwOut]	8	1			T6	1		T191	1		T190	1
auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T45	2		T46	1		T70	1
auto[StCreatorRootKey]	auto[OpGenId]	4	1			T46	1		T192	1		T193	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T194	1		T73	1		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	6	1			T7	1		T190	1		T195	1
auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T44	1		T66	1		T196	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T190	1		T197	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T46	1		T198	3		T190	2
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T46	1		T199	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	7	1			T61	1		T200	1		T201	1
auto[StOwnerKey]	auto[OpGenId]	2	1			T32	1		T166	1		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T52	1		T57	1		T202	1
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T203	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	5	1			T46	1		T185	1		T204	1
auto[StDisabled]	auto[OpGenId]	3	1			T27	1		T205	1		T206	1
auto[StDisabled]	auto[OpGenSwOut]	2	1			T207	1		T187	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	5	1			T74	1		T208	1		T209	1