Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4824

1

T1

13

T2

2

T4

7

auto[1]

561

1

T1

1

T2

1

T109

11

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4824

1

T1

13

T2

2

T4

7

auto[1]

561

1

T1

1

T2

1

T109

11

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4791

1

T1

10

T2

3

T4

7

auto[1]

594

1

T1

4

T17

1

T19

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4791

1

T1

10

T2

3

T4

7

auto[1]

594

1

T1

4

T17

1

T19

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	421	1			T14	1		T15	1		T17	1
auto[OpGenId]	1178	1			T1	3		T4	3		T15	1
auto[OpGenSwOut]	1138	1			T1	5		T2	2		T4	3
auto[OpGenHwOut]	2573	1			T1	6		T2	1		T4	1
auto[OpDisable]	75	1			T6	1		T51	1		T52	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	421	1			T14	1		T15	1		T17	1
auto[OpGenId]	1178	1			T1	3		T4	3		T15	1
auto[OpGenSwOut]	1138	1			T1	5		T2	2		T4	3
auto[OpGenHwOut]	2573	1			T1	6		T2	1		T4	1
auto[OpDisable]	75	1			T6	1		T51	1		T52	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4807

1

T1

13

T2

3

T4

7

auto[1]

578

1

T1

1

T19

2

T87

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4807

1

T1

13

T2

3

T4

7

auto[1]

578

1

T1

1

T19

2

T87

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5114

1

T1

14

T2

3

T4

7

auto[1]

271

1

T86

4

T109

10

T124

6

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1863	1			T1	5		T2	1		T4	5
auto[1]	724	1			T1	3		T4	2		T15	1
auto[2]	730	1			T17	1		T36	3		T87	2
auto[3]	700	1			T1	4		T2	1		T14	1
auto[4]	325	1			T18	1		T36	1		T86	1
auto[5]	356	1			T1	1		T2	1		T18	1
auto[6]	324	1			T1	1		T15	1		T17	1
auto[7]	363	1			T18	1		T35	1		T105	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1368	1			T1	2		T2	1		T15	1
clear_one[1]	724	1			T1	3		T4	2		T15	1
clear_one[2]	730	1			T17	1		T36	3		T87	2
clear_one[3]	700	1			T1	4		T2	1		T14	1
clear_none	1863	1			T1	5		T2	1		T4	5

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1040	1			T1	2		T4	1		T18	5
auto[StInit]	652	1			T1	2		T4	2		T17	1
auto[StCreatorRootKey]	575	1			T1	2		T17	1		T19	1
auto[StOwnerIntKey]	513	1			T1	3		T2	1		T4	1
auto[StOwnerKey]	470	1			T1	1		T17	1		T19	1
auto[StDisabled]	1830	1			T1	4		T2	2		T4	3
auto[StInvalid]	305	1			T14	2		T15	3		T18	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1040	1			T1	2		T4	1		T18	5
auto[StInit]	652	1			T1	2		T4	2		T17	1
auto[StCreatorRootKey]	575	1			T1	2		T17	1		T19	1
auto[StOwnerIntKey]	513	1			T1	3		T2	1		T4	1
auto[StOwnerKey]	470	1			T1	1		T17	1		T19	1
auto[StDisabled]	1830	1			T1	4		T2	2		T4	3
auto[StInvalid]	305	1			T14	2		T15	3		T18	1

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[2]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[2]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[3] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[3] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[3] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T210	1		T211	1		T212	1
auto[0]	auto[StReset]	auto[OpGenId]	165	1			T4	1		T18	1		T105	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	157	1			T18	1		T27	1		T47	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	274	1			T1	1		T36	1		T105	1
auto[0]	auto[StInit]	auto[OpAdvance]	37	1			T213	1		T62	1		T214	1
auto[0]	auto[StInit]	auto[OpGenId]	99	1			T1	1		T4	1		T86	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	99	1			T1	1		T4	1		T17	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	188	1			T19	1		T87	1		T121	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	18	1			T125	1		T214	1		T46	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	43	1			T1	1		T17	1		T35	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	59	1			T177	1		T6	1		T178	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	65	1			T122	1		T215	1		T6	2
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	19	1			T5	1		T57	1		T204	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	23	1			T105	1		T45	1		T216	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	25	1			T178	1		T217	1		T218	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	63	1			T2	1		T105	1		T182	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	15	1			T35	1		T45	1		T219	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	23	1			T109	1		T63	1		T220	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T19	1		T45	2		T46	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	54	1			T1	1		T121	1		T6	3
auto[0]	auto[StDisabled]	auto[OpAdvance]	33	1			T109	1		T125	2		T46	1
auto[0]	auto[StDisabled]	auto[OpGenId]	58	1			T109	2		T180	1		T221	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T4	1		T86	1		T105	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T4	1		T109	1		T182	1
auto[0]	auto[StDisabled]	auto[OpDisable]	16	1			T45	1		T54	1		T46	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	14	1			T15	1		T222	1		T223	1
auto[0]	auto[StInvalid]	auto[OpGenId]	25	1			T90	1		T53	1		T224	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	29	1			T106	1		T225	1		T94	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T14	1		T88	2		T85	1
auto[1]	auto[StReset]	auto[OpGenId]	17	1			T46	1		T61	1		T174	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	23	1			T18	1		T105	1		T45	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	39	1			T122	2		T179	1		T62	1
auto[1]	auto[StInit]	auto[OpAdvance]	7	1			T226	1		T227	1		T228	2
auto[1]	auto[StInit]	auto[OpGenId]	12	1			T105	1		T109	1		T229	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	6	1			T25	1		T230	1		T231	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	18	1			T45	1		T214	1		T61	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T232	1		T233	1		T234	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T6	1		T52	1		T235	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	25	1			T6	3		T45	1		T46	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T47	1		T236	1		T237	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T109	1		T124	1		T127	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T6	1		T214	1		T238	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T4	1		T7	1		T214	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T19	1		T121	1		T215	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T57	1		T81	1		T239	2
auto[1]	auto[StOwnerKey]	auto[OpGenId]	17	1			T6	1		T124	1		T214	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T17	1		T7	1		T45	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	46	1			T123	1		T6	1		T184	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	23	1			T124	1		T45	1		T214	1
auto[1]	auto[StDisabled]	auto[OpGenId]	60	1			T4	1		T6	1		T240	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T1	1		T6	2		T7	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	164	1			T1	2		T36	2		T87	2
auto[1]	auto[StDisabled]	auto[OpDisable]	9	1			T241	1		T73	1		T190	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	7	1			T242	1		T243	1		T244	1
auto[1]	auto[StInvalid]	auto[OpGenId]	13	1			T106	1		T245	1		T222	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T94	1		T85	1		T89	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T15	1		T106	2		T225	1
auto[2]	auto[StReset]	auto[OpGenId]	16	1			T214	1		T229	1		T246	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	17	1			T180	1		T247	1		T248	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	48	1			T6	1		T63	1		T214	1
auto[2]	auto[StInit]	auto[OpGenId]	10	1			T183	1		T214	1		T46	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	8	1			T249	1		T54	1		T190	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	24	1			T36	1		T7	1		T179	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T95	1		T118	1		T250	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	24	1			T179	1		T21	1		T183	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T45	1		T240	1		T57	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T36	1		T182	1		T45	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T251	2		T252	1		T253	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T6	1		T54	1		T61	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T54	1		T254	1		T255	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	36	1			T87	1		T7	1		T256	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T255	1		T118	1		T257	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T105	1		T61	1		T258	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T70	1		T208	1		T171	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T182	1		T259	1		T57	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	23	1			T109	1		T6	1		T260	1
auto[2]	auto[StDisabled]	auto[OpGenId]	67	1			T105	1		T109	1		T6	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T17	1		T6	2		T45	2
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	163	1			T36	1		T87	1		T105	1
auto[2]	auto[StDisabled]	auto[OpDisable]	12	1			T52	1		T70	1		T248	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T261	1		T262	1		T263	1
auto[2]	auto[StInvalid]	auto[OpGenId]	22	1			T91	1		T225	1		T94	3
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T91	1		T89	1		T264	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	18	1			T265	1		T225	1		T93	2
auto[3]	auto[StReset]	auto[OpGenId]	21	1			T214	1		T46	1		T9	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	28	1			T1	1		T105	1		T225	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	45	1			T121	1		T122	1		T47	1
auto[3]	auto[StInit]	auto[OpAdvance]	6	1			T31	1		T266	1		T267	1
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T7	1		T240	1		T268	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	11	1			T45	1		T128	2		T46	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	25	1			T51	1		T181	1		T24	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T128	2		T269	1		T76	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T27	1		T270	3		T174	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T1	1		T45	1		T128	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T87	1		T271	1		T62	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T86	1		T6	1		T272	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	19	1			T6	1		T48	1		T273	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T6	2		T204	1		T274	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	47	1			T1	1		T35	1		T36	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T275	1		T276	1		T277	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	16	1			T6	1		T179	1		T178	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T86	1		T7	1		T235	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T36	1		T87	1		T215	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	25	1			T17	1		T177	1		T180	1
auto[3]	auto[StDisabled]	auto[OpGenId]	47	1			T105	1		T6	1		T7	2
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T2	1		T105	1		T6	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T1	1		T87	1		T105	1
auto[3]	auto[StDisabled]	auto[OpDisable]	14	1			T6	1		T61	1		T73	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	10	1			T14	1		T90	1		T91	1
auto[3]	auto[StInvalid]	auto[OpGenId]	11	1			T53	1		T92	1		T222	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T265	1		T278	1		T93	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T265	1		T279	1		T280	1
auto[4]	auto[StReset]	auto[OpGenId]	12	1			T6	1		T180	1		T76	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T47	1		T62	1		T281	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	21	1			T36	1		T7	1		T237	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T198	1		T74	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	6	1			T70	1		T282	1		T190	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	8	1			T105	1		T52	1		T187	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T122	1		T283	1		T284	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T285	1		-	-		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T46	1		T204	1		T76	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T7	1		T119	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T123	1		T259	1		T286	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T7	1		T32	1		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T214	1		T204	1		T287	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T46	1		T285	1		T199	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T184	1		T237	1		T288	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T101	1		T289	2		T290	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	3	1			T291	1		T199	1		T292	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T293	1		T294	1		T295	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T122	1		T54	1		T296	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T6	1		T61	1		T297	1
auto[4]	auto[StDisabled]	auto[OpGenId]	27	1			T124	2		T214	1		T204	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T177	1		T124	1		T7	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	52	1			T86	1		T105	1		T123	2
auto[4]	auto[StDisabled]	auto[OpDisable]	7	1			T214	1		T298	1		T190	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	9	1			T224	1		T299	1		T263	1
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T18	1		T278	1		T300	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T92	1		T280	1		T301	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T279	1		T302	1		T303	1
auto[5]	auto[StReset]	auto[OpGenId]	6	1			T18	1		T204	1		T304	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	11	1			T124	1		T249	1		T46	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	24	1			T122	1		T45	1		T305	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T119	1		T49	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	10	1			T70	1		T297	1		T190	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T306	1		T307	1		T149	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T6	1		T259	1		T308	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T19	1		T309	1		T310	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T66	1		T311	1		T190	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T124	1		T312	1		T71	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T7	1		T45	1		T313	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T214	1		-	-		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T1	1		T6	1		T185	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T221	1		T187	1		T314	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T214	1		T308	1		T284	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T48	1		T315	3		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	8	1			T46	1		T187	1		T297	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T180	1		T45	1		T316	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T204	1		T317	1		T318	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	11	1			T57	1		T289	4		T319	1
auto[5]	auto[StDisabled]	auto[OpGenId]	28	1			T6	3		T214	1		T229	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T2	1		T6	2		T7	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T121	2		T123	1		T215	1
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T320	1		T175	1		T170	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T242	1		T321	1		T303	1
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T88	1		T280	1		T264	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T91	1		T85	1		T247	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T224	1		T262	1		T322	1
auto[6]	auto[StReset]	auto[OpGenId]	13	1			T57	1		T76	1		T255	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	14	1			T61	1		T190	1		T118	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	22	1			T45	1		T323	1		T9	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T324	1		T325	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	3	1			T174	1		T326	1		T327	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	1	1			T96	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	10	1			T27	1		T24	1		T82	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T86	1		T164	1		T328	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T61	3		T67	1		T119	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T105	1		T45	1		T268	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T329	1		T330	1		T198	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T6	1		T331	1		T325	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T86	1		T46	1		T241	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T1	1		T7	1		T246	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T86	1		T181	1		T305	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T272	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	8	1			T6	1		T125	2		T229	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T105	1		T29	1		T332	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T323	1		T82	1		T333	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	8	1			T214	1		T239	2		T204	1
auto[6]	auto[StDisabled]	auto[OpGenId]	25	1			T124	2		T334	1		T46	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	18	1			T62	1		T238	1		T258	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	82	1			T17	1		T36	1		T121	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T51	1		T71	1		T76	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	1	1			T223	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	10	1			T15	1		T94	1		T299	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T223	1		T247	1		T322	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T90	1		T91	1		T265	1
auto[7]	auto[StReset]	auto[OpGenId]	14	1			T18	1		T51	1		T7	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	10	1			T63	1		T240	1		T62	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	31	1			T27	1		T312	1		T308	1
auto[7]	auto[StInit]	auto[OpAdvance]	5	1			T26	1		T292	2		T335	1
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T214	1		T46	1		T72	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	3	1			T48	1		T208	1		T336	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	6	1			T180	1		T24	1		T255	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T198	1		T337	1		T266	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T275	1		T338	1		T339	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T340	1		T341	1		T255	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T121	1		T184	1		T256	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T269	1		T342	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T179	1		T45	1		T343	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T214	1		T174	1		T344	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T345	1		T271	1		T198	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T210	1		T346	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	5	1			T7	1		T216	1		T347	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T105	2		T45	1		T187	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T256	1		T348	1		T349	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	12	1			T6	1		T179	1		T306	2
auto[7]	auto[StDisabled]	auto[OpGenId]	31	1			T35	1		T204	1		T350	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T45	1		T219	1		T46	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	90	1			T6	1		T184	1		T7	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T216	1		T73	1		T76	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T222	1		T223	1		T242	1
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T264	1		T301	1		T321	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T88	1		T53	1		T106	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T265	1		T261	1		T301	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1368

1

T1

2

T2

1

T15

1

clear_one[1]

auto[0]

auto[0]

auto[0]

425

1

T1

1

T4

2

T15

1

clear_one[1]

auto[0]

auto[0]

auto[1]

128

1

T87

2

T109

1

T215

1

clear_one[1]

auto[0]

auto[1]

auto[0]

138

1

T1

1

T17

1

T36

2

clear_one[1]

auto[0]

auto[1]

auto[1]

33

1

T1

1

T19

1

T6

3

clear_one[2]

auto[0]

auto[0]

auto[0]

427

1

T17

1

T36

3

T105

3

clear_one[2]

auto[0]

auto[0]

auto[1]

127

1

T87

2

T122

4

T6

1

clear_one[2]

auto[1]

auto[0]

auto[0]

114

1

T121

1

T6

1

T181

2

clear_one[2]

auto[1]

auto[0]

auto[1]

62

1

T109

5

T6

1

T45

2

clear_one[3]

auto[0]

auto[0]

auto[0]

420

1

T1

3

T2

1

T14

1

clear_one[3]

auto[0]

auto[1]

auto[0]

121

1

T36

2

T123

2

T177

1

clear_one[3]

auto[1]

auto[0]

auto[0]

111

1

T6

2

T45

3

T219

1

clear_one[3]

auto[1]

auto[1]

auto[0]

48

1

T1

1

T178

1

T126

1

clear_none

auto[0]

auto[0]

auto[0]

1320

1

T1

4

T4

5

T14

1

clear_none

auto[0]

auto[0]

auto[1]

132

1

T105

1

T109

1

T5

1

clear_none

auto[0]

auto[1]

auto[0]

154

1

T1

1

T105

1

T182

2

clear_none

auto[0]

auto[1]

auto[1]

31

1

T19

1

T6

1

T52

1

clear_none

auto[1]

auto[0]

auto[0]

117

1

T2

1

T121

1

T6

2

clear_none

auto[1]

auto[0]

auto[1]

40

1

T109

4

T6

2

T351

1

clear_none

auto[1]

auto[1]

auto[0]

44

1

T6

1

T125

1

T345

1

clear_none

auto[1]

auto[1]

auto[1]

25

1

T109

2

T219

1

T46

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1308	1			T1	2		T2	1		T15	1
clear_all	auto[1]	60	1			T86	2		T124	4		T125	1
clear_one[1]	auto[0]	691	1			T1	3		T4	2		T15	1
clear_one[1]	auto[1]	33	1			T124	2		T127	4		T239	2
clear_one[2]	auto[0]	689	1			T17	1		T36	3		T87	2
clear_one[2]	auto[1]	41	1			T109	4		T126	3		T128	2
clear_one[3]	auto[0]	652	1			T1	4		T2	1		T14	1
clear_one[3]	auto[1]	48	1			T86	1		T126	1		T127	1
clear_none	auto[0]	1774	1			T1	5		T2	1		T4	5
clear_none	auto[1]	89	1			T86	1		T109	6		T125	6