Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11452

1

T1

37

T2

6

T4

20

auto[Attestation]

7596

1

T1

20

T2

3

T4

16

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2764	1			T1	10		T2	2		T4	4
auto[Aes]	3337	1			T1	11		T2	2		T4	8
auto[Kmac]	3475	1			T1	9		T2	1		T4	8
auto[Otbn]	3391	1			T1	6		T2	1		T4	5

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7632	1			T1	26		T2	8		T4	16
auto[OpGenId]	6081	1			T1	21		T2	3		T4	11
auto[OpGenSwOut]	5916	1			T1	17		T2	4		T4	16
auto[OpGenHwOut]	7051	1			T1	19		T2	2		T4	9
auto[OpDisable]	148	1			T1	1		T47	1		T6	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10772

1

T1

31

T2

8

T4

23

auto[OpDoneFail]

16056

1

T1

53

T2

9

T4

29

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6665	1			T1	16		T2	2		T4	7
auto[StInit]	3783	1			T1	14		T2	2		T4	10
auto[StCreatorRootKey]	3246	1			T1	11		T2	2		T4	6
auto[StOwnerIntKey]	2795	1			T1	6		T2	2		T4	5
auto[StOwnerKey]	2479	1			T1	8		T2	2		T4	8
auto[StDisabled]	7860	1			T1	29		T2	7		T4	16

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	365	1			T1	2		T18	2		T34	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	97	1			T52	1		T63	1		T64	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T107	1		T177	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	60	1			T4	1		T177	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T19	1		T86	1		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	214	1			T1	1		T2	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	301	1			T1	1		T18	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	90	1			T4	1		T16	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	84	1			T44	1		T177	1		T6	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	77	1			T177	1		T178	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	76	1			T4	1		T105	2		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	212	1			T1	1		T2	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	343	1			T33	2		T105	1		T107	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	115	1			T1	1		T44	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T17	1		T105	3		T6	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T1	1		T6	1		T7	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	74	1			T34	2		T105	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	224	1			T4	1		T105	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	324	1			T4	1		T18	3		T33	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	110	1			T17	1		T55	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	93	1			T1	1		T124	2		T179	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	71	1			T180	1		T45	2		T46	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	67	1			T6	1		T7	2		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	229	1			T86	1		T109	1		T177	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T6	2		T45	2		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	105	1			T1	1		T17	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T1	2		T179	1		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	72	1			T16	1		T86	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	73	1			T1	1		T105	1		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	209	1			T2	1		T4	1		T105	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	76	1			T105	1		T6	5		T7	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	95	1			T4	2		T124	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	74	1			T6	1		T124	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	80	1			T17	1		T105	1		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	49	1			T1	1		T4	2		T105	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	208	1			T19	1		T105	1		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	74	1			T105	2		T6	4		T7	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	106	1			T1	1		T35	1		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	86	1			T2	1		T4	1		T105	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T4	2		T17	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	69	1			T16	1		T17	1		T180	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	199	1			T1	1		T4	1		T105	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	83	1			T6	5		T7	1		T45	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	98	1			T105	1		T107	1		T177	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T1	1		T16	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T27	1		T6	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	61	1			T7	1		T179	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	204	1			T1	1		T105	1		T6	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	308	1			T1	1		T18	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	93	1			T34	1		T6	2		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	86	1			T37	1		T6	2		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	76	1			T34	1		T105	2		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	44	1			T1	1		T19	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	173	1			T1	1		T35	2		T105	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	484	1			T1	1		T18	2		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	109	1			T1	2		T121	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	105	1			T55	1		T121	1		T6	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	115	1			T2	1		T34	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	88	1			T7	1		T181	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	271	1			T1	3		T17	1		T109	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	486	1			T1	1		T33	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	118	1			T4	1		T123	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	113	1			T123	1		T44	1		T182	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	113	1			T36	1		T37	1		T123	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	92	1			T1	1		T37	1		T123	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	271	1			T1	1		T4	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	515	1			T1	1		T4	2		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	108	1			T2	1		T19	2		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	90	1			T4	1		T105	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	102	1			T35	1		T87	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	98	1			T4	1		T87	1		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	262	1			T87	3		T105	3		T122	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T105	1		T6	5		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	95	1			T7	1		T52	1		T45	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	80	1			T109	1		T6	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	50	1			T34	1		T6	1		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T34	1		T6	1		T180	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	192	1			T4	2		T17	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	65	1			T105	1		T6	3		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	123	1			T5	1		T6	4		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	115	1			T34	1		T47	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	88	1			T121	1		T6	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	70	1			T1	1		T121	1		T183	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	282	1			T1	1		T17	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	53	1			T6	2		T45	2		T62	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	134	1			T4	1		T33	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T36	1		T105	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	97	1			T17	1		T19	1		T105	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	87	1			T36	1		T6	1		T184	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	282	1			T1	2		T17	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	48	1			T105	1		T6	4		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	110	1			T105	1		T6	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T87	1		T109	1		T122	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	87	1			T1	1		T19	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	82	1			T105	1		T109	1		T6	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	275	1			T1	1		T87	1		T109	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	170	1			T4	1		T86	1		T107	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	694	1			T1	3		T2	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	217	1			T4	1		T105	2		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	623	1			T1	2		T2	1		T4	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	233	1			T1	1		T17	1		T34	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	693	1			T1	1		T4	1		T33	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	215	1			T6	1		T124	2		T7	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	679	1			T1	1		T4	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	206	1			T1	3		T16	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	388	1			T1	1		T2	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	190	1			T1	1		T4	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	392	1			T4	3		T19	1		T105	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	208	1			T2	1		T4	3		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	392	1			T1	2		T4	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	212	1			T16	1		T86	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	404	1			T1	2		T105	2		T107	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	191	1			T1	1		T19	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	589	1			T1	2		T18	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	290	1			T2	1		T34	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	882	1			T1	6		T17	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	306	1			T1	1		T36	1		T37	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	887	1			T1	2		T4	2		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	279	1			T4	1		T35	1		T87	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	896	1			T1	1		T2	1		T4	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	161	1			T34	2		T109	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	365	1			T4	2		T17	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	258	1			T1	1		T34	1		T121	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	485	1			T1	1		T17	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	277	1			T17	1		T19	1		T36	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	479	1			T1	2		T4	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	260	1			T1	1		T19	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	446	1			T1	1		T87	1		T105	2