Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33013

1

T1

100

T2

21

T4

57

auto[1]

308

1

T86

6

T109

4

T124

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33024	1			T1	100		T2	21		T4	57
auto[134217728:268435455]	12	1			T86	1		T124	1		T358	1
auto[268435456:402653183]	8	1			T128	1		T315	1		T289	1
auto[402653184:536870911]	9	1			T128	1		T239	1		T306	1
auto[536870912:671088639]	12	1			T125	1		T128	2		T373	1
auto[671088640:805306367]	11	1			T109	1		T125	1		T270	1
auto[805306368:939524095]	13	1			T128	3		T374	2		T375	1
auto[939524096:1073741823]	11	1			T315	1		T376	1		T285	1
auto[1073741824:1207959551]	9	1			T239	2		T331	1		T377	2
auto[1207959552:1342177279]	7	1			T239	1		T311	1		T378	1
auto[1342177280:1476395007]	13	1			T86	1		T124	2		T126	1
auto[1476395008:1610612735]	7	1			T124	1		T359	1		T285	1
auto[1610612736:1744830463]	16	1			T126	2		T128	1		T359	1
auto[1744830464:1879048191]	12	1			T86	1		T124	2		T239	1
auto[1879048192:2013265919]	15	1			T347	1		T315	2		T311	2
auto[2013265920:2147483647]	7	1			T124	1		T128	2		T270	1
auto[2147483648:2281701375]	11	1			T239	1		T270	1		T376	1
auto[2281701376:2415919103]	11	1			T124	1		T127	1		T128	1
auto[2415919104:2550136831]	10	1			T128	1		T289	1		T376	1
auto[2550136832:2684354559]	10	1			T315	1		T289	1		T378	1
auto[2684354560:2818572287]	8	1			T124	1		T373	1		T292	1
auto[2818572288:2952790015]	7	1			T285	1		T361	1		T210	1
auto[2952790016:3087007743]	10	1			T86	1		T109	1		T128	1
auto[3087007744:3221225471]	6	1			T125	1		T311	1		T379	1
auto[3221225472:3355443199]	4	1			T127	1		T360	1		T380	1
auto[3355443200:3489660927]	9	1			T128	3		T315	1		T359	1
auto[3489660928:3623878655]	5	1			T289	1		T311	1		T377	1
auto[3623878656:3758096383]	8	1			T124	1		T285	1		T378	1
auto[3758096384:3892314111]	10	1			T109	1		T239	1		T315	1
auto[3892314112:4026531839]	9	1			T86	1		T109	1		T128	1
auto[4026531840:4160749567]	11	1			T86	1		T373	2		T381	1
auto[4160749568:4294967295]	6	1			T127	1		T311	1		T378	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33013	1			T1	100		T2	21		T4	57
auto[0:134217727]	auto[1]	11	1			T125	2		T311	1		T359	1
auto[134217728:268435455]	auto[1]	12	1			T86	1		T124	1		T358	1
auto[268435456:402653183]	auto[1]	8	1			T128	1		T315	1		T289	1
auto[402653184:536870911]	auto[1]	9	1			T128	1		T239	1		T306	1
auto[536870912:671088639]	auto[1]	12	1			T125	1		T128	2		T373	1
auto[671088640:805306367]	auto[1]	11	1			T109	1		T125	1		T270	1
auto[805306368:939524095]	auto[1]	13	1			T128	3		T374	2		T375	1
auto[939524096:1073741823]	auto[1]	11	1			T315	1		T376	1		T285	1
auto[1073741824:1207959551]	auto[1]	9	1			T239	2		T331	1		T377	2
auto[1207959552:1342177279]	auto[1]	7	1			T239	1		T311	1		T378	1
auto[1342177280:1476395007]	auto[1]	13	1			T86	1		T124	2		T126	1
auto[1476395008:1610612735]	auto[1]	7	1			T124	1		T359	1		T285	1
auto[1610612736:1744830463]	auto[1]	16	1			T126	2		T128	1		T359	1
auto[1744830464:1879048191]	auto[1]	12	1			T86	1		T124	2		T239	1
auto[1879048192:2013265919]	auto[1]	15	1			T347	1		T315	2		T311	2
auto[2013265920:2147483647]	auto[1]	7	1			T124	1		T128	2		T270	1
auto[2147483648:2281701375]	auto[1]	11	1			T239	1		T270	1		T376	1
auto[2281701376:2415919103]	auto[1]	11	1			T124	1		T127	1		T128	1
auto[2415919104:2550136831]	auto[1]	10	1			T128	1		T289	1		T376	1
auto[2550136832:2684354559]	auto[1]	10	1			T315	1		T289	1		T378	1
auto[2684354560:2818572287]	auto[1]	8	1			T124	1		T373	1		T292	1
auto[2818572288:2952790015]	auto[1]	7	1			T285	1		T361	1		T210	1
auto[2952790016:3087007743]	auto[1]	10	1			T86	1		T109	1		T128	1
auto[3087007744:3221225471]	auto[1]	6	1			T125	1		T311	1		T379	1
auto[3221225472:3355443199]	auto[1]	4	1			T127	1		T360	1		T380	1
auto[3355443200:3489660927]	auto[1]	9	1			T128	3		T315	1		T359	1
auto[3489660928:3623878655]	auto[1]	5	1			T289	1		T311	1		T377	1
auto[3623878656:3758096383]	auto[1]	8	1			T124	1		T285	1		T378	1
auto[3758096384:3892314111]	auto[1]	10	1			T109	1		T239	1		T315	1
auto[3892314112:4026531839]	auto[1]	9	1			T86	1		T109	1		T128	1
auto[4026531840:4160749567]	auto[1]	11	1			T86	1		T373	2		T381	1
auto[4160749568:4294967295]	auto[1]	6	1			T127	1		T311	1		T378	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1621

1

T1

3

T4

2

T14

6

auto[1]

1841

1

T1

4

T4

5

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T17	1		T18	1		T35	1
auto[134217728:268435455]	115	1			T1	1		T14	1		T17	1
auto[268435456:402653183]	110	1			T1	1		T20	1		T6	2
auto[402653184:536870911]	107	1			T19	1		T105	2		T109	1
auto[536870912:671088639]	101	1			T1	1		T86	1		T90	1
auto[671088640:805306367]	109	1			T19	1		T105	1		T44	1
auto[805306368:939524095]	129	1			T18	1		T19	1		T35	1
auto[939524096:1073741823]	115	1			T105	1		T90	1		T20	1
auto[1073741824:1207959551]	107	1			T224	1		T52	2		T180	1
auto[1207959552:1342177279]	107	1			T6	2		T179	1		T180	1
auto[1342177280:1476395007]	93	1			T15	1		T35	1		T105	2
auto[1476395008:1610612735]	101	1			T109	1		T6	2		T52	1
auto[1610612736:1744830463]	115	1			T4	1		T105	1		T88	1
auto[1744830464:1879048191]	84	1			T105	1		T177	1		T6	3
auto[1879048192:2013265919]	109	1			T14	1		T47	1		T6	1
auto[2013265920:2147483647]	114	1			T1	1		T4	1		T18	1
auto[2147483648:2281701375]	99	1			T1	1		T18	1		T86	1
auto[2281701376:2415919103]	110	1			T4	1		T14	1		T5	1
auto[2415919104:2550136831]	111	1			T18	1		T6	2		T7	1
auto[2550136832:2684354559]	108	1			T14	1		T18	1		T105	1
auto[2684354560:2818572287]	125	1			T18	1		T6	1		T224	1
auto[2818572288:2952790015]	115	1			T4	1		T177	1		T6	2
auto[2952790016:3087007743]	102	1			T4	1		T14	2		T90	1
auto[3087007744:3221225471]	113	1			T109	2		T27	1		T6	3
auto[3221225472:3355443199]	123	1			T4	1		T19	1		T44	1
auto[3355443200:3489660927]	114	1			T1	1		T105	1		T88	1
auto[3489660928:3623878655]	106	1			T15	1		T44	1		T88	1
auto[3623878656:3758096383]	117	1			T14	1		T17	1		T6	4
auto[3758096384:3892314111]	96	1			T17	1		T105	1		T6	4
auto[3892314112:4026531839]	98	1			T15	1		T86	1		T109	1
auto[4026531840:4160749567]	103	1			T1	1		T17	1		T105	3
auto[4160749568:4294967295]	106	1			T4	1		T124	1		T7	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T18	1		T47	1		T179	1
auto[0:134217727]	auto[1]	53	1			T17	1		T35	1		T6	2
auto[134217728:268435455]	auto[0]	52	1			T14	1		T18	1		T6	1
auto[134217728:268435455]	auto[1]	63	1			T1	1		T17	1		T6	2
auto[268435456:402653183]	auto[0]	43	1			T1	1		T20	1		T45	2
auto[268435456:402653183]	auto[1]	67	1			T6	2		T7	1		T45	2
auto[402653184:536870911]	auto[0]	52	1			T105	2		T109	1		T51	1
auto[402653184:536870911]	auto[1]	55	1			T19	1		T6	2		T179	1
auto[536870912:671088639]	auto[0]	41	1			T6	1		T214	1		T46	1
auto[536870912:671088639]	auto[1]	60	1			T1	1		T86	1		T90	1
auto[671088640:805306367]	auto[0]	49	1			T105	1		T6	1		T52	1
auto[671088640:805306367]	auto[1]	60	1			T19	1		T44	1		T7	1
auto[805306368:939524095]	auto[0]	59	1			T19	1		T224	1		T180	1
auto[805306368:939524095]	auto[1]	70	1			T18	1		T35	1		T7	1
auto[939524096:1073741823]	auto[0]	57	1			T20	1		T44	1		T53	1
auto[939524096:1073741823]	auto[1]	58	1			T105	1		T90	1		T6	1
auto[1073741824:1207959551]	auto[0]	40	1			T52	1		T260	1		T222	1
auto[1073741824:1207959551]	auto[1]	67	1			T224	1		T52	1		T180	1
auto[1207959552:1342177279]	auto[0]	45	1			T179	1		T351	1		T222	1
auto[1207959552:1342177279]	auto[1]	62	1			T6	2		T180	1		T45	1
auto[1342177280:1476395007]	auto[0]	48	1			T35	1		T105	2		T260	1
auto[1342177280:1476395007]	auto[1]	45	1			T15	1		T27	1		T178	1
auto[1476395008:1610612735]	auto[0]	41	1			T54	1		T127	1		T214	2
auto[1476395008:1610612735]	auto[1]	60	1			T109	1		T6	2		T52	1
auto[1610612736:1744830463]	auto[0]	55	1			T88	1		T6	1		T51	1
auto[1610612736:1744830463]	auto[1]	60	1			T4	1		T105	1		T7	1
auto[1744830464:1879048191]	auto[0]	42	1			T6	2		T53	1		T179	1
auto[1744830464:1879048191]	auto[1]	42	1			T105	1		T177	1		T6	1
auto[1879048192:2013265919]	auto[0]	56	1			T14	1		T6	1		T45	2
auto[1879048192:2013265919]	auto[1]	53	1			T47	1		T7	2		T221	1
auto[2013265920:2147483647]	auto[0]	53	1			T1	1		T4	1		T6	3
auto[2013265920:2147483647]	auto[1]	61	1			T18	1		T105	1		T45	2
auto[2147483648:2281701375]	auto[0]	46	1			T1	1		T6	1		T46	3
auto[2147483648:2281701375]	auto[1]	53	1			T18	1		T86	1		T105	2
auto[2281701376:2415919103]	auto[0]	58	1			T6	1		T124	1		T45	1
auto[2281701376:2415919103]	auto[1]	52	1			T4	1		T14	1		T5	1
auto[2415919104:2550136831]	auto[0]	48	1			T6	1		T52	1		T91	1
auto[2415919104:2550136831]	auto[1]	63	1			T18	1		T6	1		T7	1
auto[2550136832:2684354559]	auto[0]	56	1			T14	1		T105	1		T177	1
auto[2550136832:2684354559]	auto[1]	52	1			T18	1		T179	1		T125	1
auto[2684354560:2818572287]	auto[0]	64	1			T18	1		T179	1		T260	1
auto[2684354560:2818572287]	auto[1]	61	1			T6	1		T224	1		T124	1
auto[2818572288:2952790015]	auto[0]	58	1			T177	1		T6	1		T7	1
auto[2818572288:2952790015]	auto[1]	57	1			T4	1		T6	1		T7	1
auto[2952790016:3087007743]	auto[0]	49	1			T4	1		T14	2		T6	1
auto[2952790016:3087007743]	auto[1]	53	1			T90	1		T7	1		T45	1
auto[3087007744:3221225471]	auto[0]	49	1			T27	1		T6	2		T180	1
auto[3087007744:3221225471]	auto[1]	64	1			T109	2		T6	1		T124	2
auto[3221225472:3355443199]	auto[0]	61	1			T47	1		T6	1		T178	1
auto[3221225472:3355443199]	auto[1]	62	1			T4	1		T19	1		T44	1
auto[3355443200:3489660927]	auto[0]	55	1			T105	1		T88	1		T180	1
auto[3355443200:3489660927]	auto[1]	59	1			T1	1		T27	1		T224	1
auto[3489660928:3623878655]	auto[0]	52	1			T15	1		T6	3		T51	1
auto[3489660928:3623878655]	auto[1]	54	1			T44	1		T88	1		T47	1
auto[3623878656:3758096383]	auto[0]	61	1			T14	1		T6	3		T53	1
auto[3623878656:3758096383]	auto[1]	56	1			T17	1		T6	1		T224	1
auto[3758096384:3892314111]	auto[0]	45	1			T17	1		T6	2		T51	1
auto[3758096384:3892314111]	auto[1]	51	1			T105	1		T6	2		T52	1
auto[3892314112:4026531839]	auto[0]	48	1			T15	1		T6	3		T53	1
auto[3892314112:4026531839]	auto[1]	50	1			T86	1		T109	1		T7	1
auto[4026531840:4160749567]	auto[0]	46	1			T105	1		T6	1		T51	1
auto[4026531840:4160749567]	auto[1]	57	1			T1	1		T17	1		T105	2
auto[4160749568:4294967295]	auto[0]	45	1			T124	1		T45	1		T63	1
auto[4160749568:4294967295]	auto[1]	61	1			T4	1		T7	1		T249	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1642

1

T1

2

T4

3

T14

6

auto[1]

1820

1

T1

5

T4

4

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	117	1			T86	1		T105	1		T44	1
auto[134217728:268435455]	105	1			T1	1		T18	1		T35	1
auto[268435456:402653183]	102	1			T35	1		T109	1		T27	1
auto[402653184:536870911]	97	1			T1	1		T18	1		T47	1
auto[536870912:671088639]	97	1			T4	1		T18	1		T105	1
auto[671088640:805306367]	125	1			T5	1		T6	4		T45	1
auto[805306368:939524095]	106	1			T14	2		T17	1		T109	1
auto[939524096:1073741823]	131	1			T15	1		T88	1		T6	1
auto[1073741824:1207959551]	104	1			T17	1		T105	1		T177	1
auto[1207959552:1342177279]	100	1			T1	1		T20	1		T6	3
auto[1342177280:1476395007]	113	1			T1	1		T86	1		T109	1
auto[1476395008:1610612735]	117	1			T105	1		T44	1		T47	1
auto[1610612736:1744830463]	115	1			T15	1		T17	1		T19	1
auto[1744830464:1879048191]	108	1			T18	1		T6	1		T7	1
auto[1879048192:2013265919]	117	1			T1	1		T105	1		T47	2
auto[2013265920:2147483647]	107	1			T35	1		T86	1		T105	1
auto[2147483648:2281701375]	95	1			T105	1		T6	1		T45	2
auto[2281701376:2415919103]	111	1			T4	1		T14	1		T18	1
auto[2415919104:2550136831]	103	1			T1	1		T4	1		T14	2
auto[2550136832:2684354559]	104	1			T27	1		T6	4		T7	2
auto[2684354560:2818572287]	108	1			T4	1		T14	1		T105	1
auto[2818572288:2952790015]	98	1			T27	1		T47	1		T6	1
auto[2952790016:3087007743]	116	1			T6	1		T224	1		T124	1
auto[3087007744:3221225471]	117	1			T19	2		T90	1		T6	1
auto[3221225472:3355443199]	107	1			T18	1		T19	1		T105	1
auto[3355443200:3489660927]	95	1			T1	1		T14	1		T6	2
auto[3489660928:3623878655]	114	1			T105	1		T109	1		T90	1
auto[3623878656:3758096383]	118	1			T18	2		T105	2		T90	1
auto[3758096384:3892314111]	99	1			T4	2		T15	1		T17	1
auto[3892314112:4026531839]	108	1			T44	1		T177	1		T6	1
auto[4026531840:4160749567]	99	1			T4	1		T44	1		T6	2
auto[4160749568:4294967295]	109	1			T6	1		T7	1		T45	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T6	1		T45	1		T125	1
auto[0:134217727]	auto[1]	61	1			T86	1		T105	1		T44	1
auto[134217728:268435455]	auto[0]	48	1			T105	1		T20	1		T88	1
auto[134217728:268435455]	auto[1]	57	1			T1	1		T18	1		T35	1
auto[268435456:402653183]	auto[0]	44	1			T6	1		T54	1		T222	1
auto[268435456:402653183]	auto[1]	58	1			T35	1		T109	1		T27	1
auto[402653184:536870911]	auto[0]	44	1			T18	1		T179	1		T63	1
auto[402653184:536870911]	auto[1]	53	1			T1	1		T47	1		T6	2
auto[536870912:671088639]	auto[0]	55	1			T124	1		T265	1		T214	1
auto[536870912:671088639]	auto[1]	42	1			T4	1		T18	1		T105	1
auto[671088640:805306367]	auto[0]	52	1			T6	2		T260	1		T214	2
auto[671088640:805306367]	auto[1]	73	1			T5	1		T6	2		T45	1
auto[805306368:939524095]	auto[0]	48	1			T14	1		T6	2		T7	1
auto[805306368:939524095]	auto[1]	58	1			T14	1		T17	1		T109	1
auto[939524096:1073741823]	auto[0]	75	1			T88	1		T6	1		T51	1
auto[939524096:1073741823]	auto[1]	56	1			T15	1		T7	1		T214	1
auto[1073741824:1207959551]	auto[0]	48	1			T177	1		T45	1		T54	1
auto[1073741824:1207959551]	auto[1]	56	1			T17	1		T105	1		T6	2
auto[1207959552:1342177279]	auto[0]	46	1			T1	1		T20	1		T6	2
auto[1207959552:1342177279]	auto[1]	54	1			T6	1		T7	1		T45	2
auto[1342177280:1476395007]	auto[0]	55	1			T6	1		T179	1		T63	1
auto[1342177280:1476395007]	auto[1]	58	1			T1	1		T86	1		T109	1
auto[1476395008:1610612735]	auto[0]	55	1			T105	1		T44	1		T6	1
auto[1476395008:1610612735]	auto[1]	62	1			T47	1		T6	1		T53	1
auto[1610612736:1744830463]	auto[0]	52	1			T15	1		T19	1		T54	1
auto[1610612736:1744830463]	auto[1]	63	1			T17	1		T177	1		T6	1
auto[1744830464:1879048191]	auto[0]	49	1			T18	1		T52	1		T45	1
auto[1744830464:1879048191]	auto[1]	59	1			T6	1		T7	1		T63	1
auto[1879048192:2013265919]	auto[0]	60	1			T105	1		T47	1		T7	1
auto[1879048192:2013265919]	auto[1]	57	1			T1	1		T47	1		T52	1
auto[2013265920:2147483647]	auto[0]	47	1			T35	1		T6	1		T224	2
auto[2013265920:2147483647]	auto[1]	60	1			T86	1		T105	1		T178	1
auto[2147483648:2281701375]	auto[0]	50	1			T105	1		T45	1		T54	1
auto[2147483648:2281701375]	auto[1]	45	1			T6	1		T45	1		T64	1
auto[2281701376:2415919103]	auto[0]	54	1			T14	1		T109	1		T6	1
auto[2281701376:2415919103]	auto[1]	57	1			T4	1		T18	1		T105	2
auto[2415919104:2550136831]	auto[0]	44	1			T14	2		T51	1		T224	1
auto[2415919104:2550136831]	auto[1]	59	1			T1	1		T4	1		T17	1
auto[2550136832:2684354559]	auto[0]	49	1			T6	1		T180	1		T45	2
auto[2550136832:2684354559]	auto[1]	55	1			T27	1		T6	3		T7	2
auto[2684354560:2818572287]	auto[0]	50	1			T4	1		T14	1		T54	1
auto[2684354560:2818572287]	auto[1]	58	1			T105	1		T6	2		T124	1
auto[2818572288:2952790015]	auto[0]	45	1			T47	1		T178	1		T214	1
auto[2818572288:2952790015]	auto[1]	53	1			T27	1		T6	1		T45	2
auto[2952790016:3087007743]	auto[0]	49	1			T124	1		T45	2		T260	2
auto[2952790016:3087007743]	auto[1]	67	1			T6	1		T224	1		T7	1
auto[3087007744:3221225471]	auto[0]	56	1			T6	1		T45	1		T345	1
auto[3087007744:3221225471]	auto[1]	61	1			T19	2		T90	1		T7	1
auto[3221225472:3355443199]	auto[0]	47	1			T18	1		T105	1		T52	1
auto[3221225472:3355443199]	auto[1]	60	1			T19	1		T6	2		T7	1
auto[3355443200:3489660927]	auto[0]	47	1			T1	1		T14	1		T6	2
auto[3355443200:3489660927]	auto[1]	48	1			T7	1		T61	1		T241	1
auto[3489660928:3623878655]	auto[0]	63	1			T105	1		T6	2		T180	1
auto[3489660928:3623878655]	auto[1]	51	1			T109	1		T90	1		T6	1
auto[3623878656:3758096383]	auto[0]	57	1			T105	1		T6	1		T51	1
auto[3623878656:3758096383]	auto[1]	61	1			T18	2		T105	1		T90	1
auto[3758096384:3892314111]	auto[0]	48	1			T4	1		T15	1		T105	1
auto[3758096384:3892314111]	auto[1]	51	1			T4	1		T17	1		T45	1
auto[3892314112:4026531839]	auto[0]	56	1			T177	1		T6	1		T125	1
auto[3892314112:4026531839]	auto[1]	52	1			T44	1		T45	1		T24	1
auto[4026531840:4160749567]	auto[0]	46	1			T4	1		T44	1		T6	1
auto[4026531840:4160749567]	auto[1]	53	1			T6	1		T53	1		T124	1
auto[4160749568:4294967295]	auto[0]	47	1			T6	1		T45	2		T128	1
auto[4160749568:4294967295]	auto[1]	62	1			T7	1		T221	1		T92	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1654

1

T1

3

T4

2

T14

7

auto[1]

1808

1

T1

4

T4

5

T17

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T1	3		T15	1		T6	2
auto[134217728:268435455]	121	1			T1	1		T4	1		T35	1
auto[268435456:402653183]	102	1			T18	1		T20	1		T6	2
auto[402653184:536870911]	102	1			T4	1		T18	1		T19	1
auto[536870912:671088639]	118	1			T19	1		T88	1		T177	1
auto[671088640:805306367]	107	1			T1	1		T105	2		T20	1
auto[805306368:939524095]	135	1			T18	2		T105	1		T6	2
auto[939524096:1073741823]	104	1			T86	1		T105	1		T44	1
auto[1073741824:1207959551]	98	1			T15	1		T105	1		T109	1
auto[1207959552:1342177279]	122	1			T14	3		T18	1		T90	1
auto[1342177280:1476395007]	123	1			T4	1		T105	1		T27	1
auto[1476395008:1610612735]	103	1			T15	1		T86	1		T6	1
auto[1610612736:1744830463]	114	1			T1	1		T35	1		T86	1
auto[1744830464:1879048191]	100	1			T35	1		T105	1		T124	1
auto[1879048192:2013265919]	107	1			T17	2		T105	1		T44	1
auto[2013265920:2147483647]	94	1			T4	1		T105	2		T224	1
auto[2147483648:2281701375]	113	1			T90	1		T177	1		T6	1
auto[2281701376:2415919103]	112	1			T105	1		T109	1		T6	2
auto[2415919104:2550136831]	109	1			T18	1		T105	1		T6	2
auto[2550136832:2684354559]	96	1			T6	1		T7	1		T178	1
auto[2684354560:2818572287]	91	1			T1	1		T44	1		T47	1
auto[2818572288:2952790015]	94	1			T88	1		T27	1		T6	2
auto[2952790016:3087007743]	106	1			T14	1		T105	1		T6	1
auto[3087007744:3221225471]	110	1			T4	1		T14	1		T17	1
auto[3221225472:3355443199]	100	1			T14	1		T105	1		T177	1
auto[3355443200:3489660927]	106	1			T4	1		T19	1		T105	1
auto[3489660928:3623878655]	106	1			T47	1		T6	3		T124	1
auto[3623878656:3758096383]	105	1			T14	1		T17	1		T6	3
auto[3758096384:3892314111]	119	1			T4	1		T109	1		T6	2
auto[3892314112:4026531839]	100	1			T17	1		T90	1		T44	1
auto[4026531840:4160749567]	119	1			T19	1		T105	1		T53	1
auto[4160749568:4294967295]	128	1			T105	1		T109	1		T6	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T1	1		T15	1		T6	1
auto[0:134217727]	auto[1]	54	1			T1	2		T6	1		T63	1
auto[134217728:268435455]	auto[0]	50	1			T1	1		T35	1		T91	1
auto[134217728:268435455]	auto[1]	71	1			T4	1		T88	1		T27	1
auto[268435456:402653183]	auto[0]	46	1			T18	1		T20	1		T6	1
auto[268435456:402653183]	auto[1]	56	1			T6	1		T219	1		T64	1
auto[402653184:536870911]	auto[0]	52	1			T19	1		T6	1		T224	1
auto[402653184:536870911]	auto[1]	50	1			T4	1		T18	1		T45	1
auto[536870912:671088639]	auto[0]	55	1			T88	1		T177	1		T6	2
auto[536870912:671088639]	auto[1]	63	1			T19	1		T6	1		T124	1
auto[671088640:805306367]	auto[0]	55	1			T6	2		T224	1		T45	1
auto[671088640:805306367]	auto[1]	52	1			T1	1		T105	2		T20	1
auto[805306368:939524095]	auto[0]	72	1			T18	1		T6	2		T51	1
auto[805306368:939524095]	auto[1]	63	1			T18	1		T105	1		T7	1
auto[939524096:1073741823]	auto[0]	49	1			T86	1		T105	1		T44	1
auto[939524096:1073741823]	auto[1]	55	1			T6	1		T224	1		T7	1
auto[1073741824:1207959551]	auto[0]	40	1			T15	1		T6	1		T45	1
auto[1073741824:1207959551]	auto[1]	58	1			T105	1		T109	1		T6	2
auto[1207959552:1342177279]	auto[0]	67	1			T14	3		T6	1		T7	1
auto[1207959552:1342177279]	auto[1]	55	1			T18	1		T90	1		T5	1
auto[1342177280:1476395007]	auto[0]	57	1			T6	2		T54	1		T57	2
auto[1342177280:1476395007]	auto[1]	66	1			T4	1		T105	1		T27	1
auto[1476395008:1610612735]	auto[0]	44	1			T15	1		T6	1		T180	1
auto[1476395008:1610612735]	auto[1]	59	1			T86	1		T224	1		T7	1
auto[1610612736:1744830463]	auto[0]	56	1			T109	1		T45	2		T128	1
auto[1610612736:1744830463]	auto[1]	58	1			T1	1		T35	1		T86	1
auto[1744830464:1879048191]	auto[0]	40	1			T105	1		T124	1		T45	1
auto[1744830464:1879048191]	auto[1]	60	1			T35	1		T7	1		T52	1
auto[1879048192:2013265919]	auto[0]	52	1			T7	1		T52	1		T180	1
auto[1879048192:2013265919]	auto[1]	55	1			T17	2		T105	1		T44	1
auto[2013265920:2147483647]	auto[0]	55	1			T4	1		T105	1		T224	1
auto[2013265920:2147483647]	auto[1]	39	1			T105	1		T45	1		T63	1
auto[2147483648:2281701375]	auto[0]	62	1			T177	1		T51	1		T46	3
auto[2147483648:2281701375]	auto[1]	51	1			T90	1		T6	1		T45	1
auto[2281701376:2415919103]	auto[0]	51	1			T109	1		T6	1		T221	1
auto[2281701376:2415919103]	auto[1]	61	1			T105	1		T6	1		T214	1
auto[2415919104:2550136831]	auto[0]	47	1			T105	1		T6	1		T53	1
auto[2415919104:2550136831]	auto[1]	62	1			T18	1		T6	1		T7	1
auto[2550136832:2684354559]	auto[0]	40	1			T6	1		T178	1		T54	2
auto[2550136832:2684354559]	auto[1]	56	1			T7	1		T45	1		T245	1
auto[2684354560:2818572287]	auto[0]	44	1			T1	1		T44	1		T6	1
auto[2684354560:2818572287]	auto[1]	47	1			T47	1		T45	1		T221	1
auto[2818572288:2952790015]	auto[0]	51	1			T88	1		T27	1		T6	2
auto[2818572288:2952790015]	auto[1]	43	1			T180	1		T30	1		T128	1
auto[2952790016:3087007743]	auto[0]	47	1			T14	1		T53	1		T45	1
auto[2952790016:3087007743]	auto[1]	59	1			T105	1		T6	1		T224	1
auto[3087007744:3221225471]	auto[0]	59	1			T4	1		T14	1		T18	1
auto[3087007744:3221225471]	auto[1]	51	1			T17	1		T18	1		T6	2
auto[3221225472:3355443199]	auto[0]	43	1			T14	1		T180	1		T63	1
auto[3221225472:3355443199]	auto[1]	57	1			T105	1		T177	1		T224	1
auto[3355443200:3489660927]	auto[0]	50	1			T105	1		T47	1		T6	1
auto[3355443200:3489660927]	auto[1]	56	1			T4	1		T19	1		T47	1
auto[3489660928:3623878655]	auto[0]	56	1			T47	1		T6	3		T128	1
auto[3489660928:3623878655]	auto[1]	50	1			T124	1		T214	3		T46	2
auto[3623878656:3758096383]	auto[0]	52	1			T14	1		T6	1		T180	1
auto[3623878656:3758096383]	auto[1]	53	1			T17	1		T6	2		T124	1
auto[3758096384:3892314111]	auto[0]	59	1			T6	1		T45	2		T125	1
auto[3758096384:3892314111]	auto[1]	60	1			T4	1		T109	1		T6	1
auto[3892314112:4026531839]	auto[0]	51	1			T90	1		T6	2		T51	1
auto[3892314112:4026531839]	auto[1]	49	1			T17	1		T44	1		T178	1
auto[4026531840:4160749567]	auto[0]	48	1			T45	1		T345	1		T225	1
auto[4026531840:4160749567]	auto[1]	71	1			T19	1		T105	1		T53	1
auto[4160749568:4294967295]	auto[0]	60	1			T105	1		T6	1		T124	1
auto[4160749568:4294967295]	auto[1]	68	1			T109	1		T53	2		T7	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1642

1

T1

2

T4

1

T14

6

auto[1]

1821

1

T1

5

T4

6

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	122	1			T4	1		T18	1		T90	1
auto[134217728:268435455]	106	1			T18	1		T105	2		T7	2
auto[268435456:402653183]	101	1			T17	1		T105	1		T6	1
auto[402653184:536870911]	101	1			T18	1		T105	1		T5	1
auto[536870912:671088639]	115	1			T27	1		T47	1		T6	2
auto[671088640:805306367]	114	1			T47	1		T6	2		T224	1
auto[805306368:939524095]	104	1			T18	1		T90	1		T47	1
auto[939524096:1073741823]	89	1			T4	1		T14	2		T105	1
auto[1073741824:1207959551]	104	1			T17	1		T6	1		T7	1
auto[1207959552:1342177279]	111	1			T14	1		T18	1		T90	1
auto[1342177280:1476395007]	122	1			T1	1		T6	3		T7	1
auto[1476395008:1610612735]	111	1			T1	2		T105	1		T20	1
auto[1610612736:1744830463]	120	1			T1	1		T14	1		T105	1
auto[1744830464:1879048191]	106	1			T19	1		T105	1		T109	1
auto[1879048192:2013265919]	113	1			T14	1		T15	2		T17	1
auto[2013265920:2147483647]	87	1			T19	1		T35	1		T105	1
auto[2147483648:2281701375]	101	1			T17	1		T86	1		T105	1
auto[2281701376:2415919103]	102	1			T109	1		T178	1		T245	1
auto[2415919104:2550136831]	106	1			T19	1		T179	1		T45	1
auto[2550136832:2684354559]	106	1			T1	1		T4	2		T6	5
auto[2684354560:2818572287]	101	1			T18	1		T35	1		T51	1
auto[2818572288:2952790015]	110	1			T4	1		T86	1		T88	1
auto[2952790016:3087007743]	105	1			T6	1		T51	1		T7	1
auto[3087007744:3221225471]	115	1			T105	2		T44	1		T6	1
auto[3221225472:3355443199]	113	1			T177	1		T6	3		T178	1
auto[3355443200:3489660927]	108	1			T1	1		T4	1		T14	1
auto[3489660928:3623878655]	109	1			T14	1		T109	1		T20	1
auto[3623878656:3758096383]	114	1			T15	1		T18	1		T19	1
auto[3758096384:3892314111]	111	1			T1	1		T105	1		T6	3
auto[3892314112:4026531839]	101	1			T17	1		T18	1		T44	1
auto[4026531840:4160749567]	119	1			T105	1		T6	5		T7	1
auto[4160749568:4294967295]	116	1			T4	1		T35	1		T6	2