Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2986

1

T1

7

T4

7

T14

7

auto[1]

291

1

T86

3

T109

10

T124

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	90	1			T18	2		T7	1		T179	1
auto[134217728:268435455]	115	1			T14	1		T105	3		T109	1
auto[268435456:402653183]	94	1			T86	1		T27	1		T47	1
auto[402653184:536870911]	110	1			T86	1		T6	3		T124	1
auto[536870912:671088639]	112	1			T1	1		T109	1		T6	1
auto[671088640:805306367]	90	1			T105	1		T53	1		T124	1
auto[805306368:939524095]	95	1			T35	1		T109	1		T90	1
auto[939524096:1073741823]	84	1			T1	1		T105	1		T109	1
auto[1073741824:1207959551]	115	1			T105	1		T6	1		T7	1
auto[1207959552:1342177279]	92	1			T86	2		T109	1		T27	1
auto[1342177280:1476395007]	91	1			T177	1		T6	2		T51	2
auto[1476395008:1610612735]	85	1			T1	1		T4	1		T18	1
auto[1610612736:1744830463]	98	1			T15	1		T17	1		T19	1
auto[1744830464:1879048191]	113	1			T14	1		T17	1		T18	1
auto[1879048192:2013265919]	103	1			T14	1		T18	1		T6	2
auto[2013265920:2147483647]	109	1			T44	1		T88	1		T6	6
auto[2147483648:2281701375]	81	1			T109	1		T51	1		T124	1
auto[2281701376:2415919103]	108	1			T17	1		T18	2		T86	1
auto[2415919104:2550136831]	121	1			T14	1		T109	3		T124	1
auto[2550136832:2684354559]	96	1			T6	1		T7	2		T125	1
auto[2684354560:2818572287]	95	1			T1	1		T109	1		T6	1
auto[2818572288:2952790015]	113	1			T4	2		T14	1		T17	1
auto[2952790016:3087007743]	110	1			T18	1		T19	1		T177	1
auto[3087007744:3221225471]	98	1			T1	3		T15	1		T19	1
auto[3221225472:3355443199]	114	1			T4	2		T6	4		T224	2
auto[3355443200:3489660927]	111	1			T4	1		T19	1		T105	1
auto[3489660928:3623878655]	117	1			T35	1		T47	2		T224	2
auto[3623878656:3758096383]	98	1			T14	1		T105	2		T53	1
auto[3758096384:3892314111]	103	1			T4	1		T109	1		T20	1
auto[3892314112:4026531839]	109	1			T14	1		T6	1		T7	1
auto[4026531840:4160749567]	94	1			T109	1		T7	1		T180	1
auto[4160749568:4294967295]	113	1			T15	1		T17	1		T86	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	80	1			T18	2		T7	1		T179	1
auto[0:134217727]	auto[1]	10	1			T128	1		T357	1		T289	1
auto[134217728:268435455]	auto[0]	100	1			T14	1		T105	3		T27	1
auto[134217728:268435455]	auto[1]	15	1			T109	1		T125	1		T128	2
auto[268435456:402653183]	auto[0]	80	1			T27	1		T47	1		T6	2
auto[268435456:402653183]	auto[1]	14	1			T86	1		T124	1		T128	1
auto[402653184:536870911]	auto[0]	97	1			T86	1		T6	3		T7	1
auto[402653184:536870911]	auto[1]	13	1			T124	1		T126	1		T311	2
auto[536870912:671088639]	auto[0]	100	1			T1	1		T6	1		T124	1
auto[536870912:671088639]	auto[1]	12	1			T109	1		T124	1		T239	1
auto[671088640:805306367]	auto[0]	83	1			T105	1		T53	1		T124	1
auto[671088640:805306367]	auto[1]	7	1			T128	1		T239	1		T289	1
auto[805306368:939524095]	auto[0]	86	1			T35	1		T90	1		T6	2
auto[805306368:939524095]	auto[1]	9	1			T109	1		T125	1		T128	1
auto[939524096:1073741823]	auto[0]	77	1			T1	1		T105	1		T88	1
auto[939524096:1073741823]	auto[1]	7	1			T109	1		T124	1		T311	1
auto[1073741824:1207959551]	auto[0]	103	1			T105	1		T6	1		T7	1
auto[1073741824:1207959551]	auto[1]	12	1			T128	1		T270	1		T311	1
auto[1207959552:1342177279]	auto[0]	84	1			T86	1		T109	1		T27	1
auto[1207959552:1342177279]	auto[1]	8	1			T86	1		T342	1		T373	1
auto[1342177280:1476395007]	auto[0]	76	1			T177	1		T6	2		T51	2
auto[1342177280:1476395007]	auto[1]	15	1			T125	1		T239	1		T306	1
auto[1476395008:1610612735]	auto[0]	76	1			T1	1		T4	1		T18	1
auto[1476395008:1610612735]	auto[1]	9	1			T109	1		T358	1		T239	1
auto[1610612736:1744830463]	auto[0]	92	1			T15	1		T17	1		T19	1
auto[1610612736:1744830463]	auto[1]	6	1			T109	1		T124	1		T311	1
auto[1744830464:1879048191]	auto[0]	102	1			T14	1		T17	1		T18	1
auto[1744830464:1879048191]	auto[1]	11	1			T109	1		T124	1		T126	1
auto[1879048192:2013265919]	auto[0]	98	1			T14	1		T18	1		T6	2
auto[1879048192:2013265919]	auto[1]	5	1			T128	2		T239	1		T385	1
auto[2013265920:2147483647]	auto[0]	101	1			T44	1		T88	1		T6	6
auto[2013265920:2147483647]	auto[1]	8	1			T239	1		T270	1		T342	1
auto[2147483648:2281701375]	auto[0]	78	1			T109	1		T51	1		T45	1
auto[2147483648:2281701375]	auto[1]	3	1			T124	1		T126	1		T376	1
auto[2281701376:2415919103]	auto[0]	100	1			T17	1		T18	2		T86	1
auto[2281701376:2415919103]	auto[1]	8	1			T127	1		T128	2		T379	2
auto[2415919104:2550136831]	auto[0]	109	1			T14	1		T109	2		T124	1
auto[2415919104:2550136831]	auto[1]	12	1			T109	1		T128	1		T289	2
auto[2550136832:2684354559]	auto[0]	87	1			T6	1		T7	2		T125	1
auto[2550136832:2684354559]	auto[1]	9	1			T306	1		T359	1		T379	1
auto[2684354560:2818572287]	auto[0]	84	1			T1	1		T6	1		T179	1
auto[2684354560:2818572287]	auto[1]	11	1			T109	1		T239	3		T289	2
auto[2818572288:2952790015]	auto[0]	107	1			T4	2		T14	1		T17	1
auto[2818572288:2952790015]	auto[1]	6	1			T306	1		T373	1		T386	1
auto[2952790016:3087007743]	auto[0]	103	1			T18	1		T19	1		T177	1
auto[2952790016:3087007743]	auto[1]	7	1			T125	1		T270	1		T311	1
auto[3087007744:3221225471]	auto[0]	84	1			T1	3		T15	1		T19	1
auto[3087007744:3221225471]	auto[1]	14	1			T124	1		T127	1		T128	2
auto[3221225472:3355443199]	auto[0]	110	1			T4	2		T6	4		T224	2
auto[3221225472:3355443199]	auto[1]	4	1			T124	1		T331	1		T374	1
auto[3355443200:3489660927]	auto[0]	105	1			T4	1		T19	1		T105	1
auto[3355443200:3489660927]	auto[1]	6	1			T124	1		T239	1		T377	2
auto[3489660928:3623878655]	auto[0]	107	1			T35	1		T47	2		T224	2
auto[3489660928:3623878655]	auto[1]	10	1			T124	1		T126	1		T270	2
auto[3623878656:3758096383]	auto[0]	93	1			T14	1		T105	2		T53	1
auto[3623878656:3758096383]	auto[1]	5	1			T315	1		T374	1		T251	1
auto[3758096384:3892314111]	auto[0]	96	1			T4	1		T20	1		T47	1
auto[3758096384:3892314111]	auto[1]	7	1			T109	1		T127	1		T239	1
auto[3892314112:4026531839]	auto[0]	102	1			T14	1		T6	1		T7	1
auto[3892314112:4026531839]	auto[1]	7	1			T126	1		T128	1		T239	1
auto[4026531840:4160749567]	auto[0]	85	1			T109	1		T7	1		T180	1
auto[4026531840:4160749567]	auto[1]	9	1			T306	1		T357	1		T289	1
auto[4160749568:4294967295]	auto[0]	101	1			T15	1		T17	1		T90	1
auto[4160749568:4294967295]	auto[1]	12	1			T86	1		T128	1		T270	1