Unified Coverage Report :: Group Instance : sealing_sw_binding_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1631

1

T1

3

T4

2

T14

6

auto[1]

1832

1

T1

4

T4

5

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	91	1			T105	2		T177	2		T6	1
auto[134217728:268435455]	125	1			T4	1		T86	1		T105	1
auto[268435456:402653183]	113	1			T14	1		T35	2		T105	1
auto[402653184:536870911]	99	1			T1	1		T88	1		T27	1
auto[536870912:671088639]	104	1			T1	1		T4	1		T105	1
auto[671088640:805306367]	100	1			T14	1		T18	1		T105	1
auto[805306368:939524095]	112	1			T86	1		T105	1		T109	1
auto[939524096:1073741823]	94	1			T4	1		T6	3		T53	1
auto[1073741824:1207959551]	116	1			T44	1		T6	3		T179	1
auto[1207959552:1342177279]	108	1			T14	1		T18	1		T27	1
auto[1342177280:1476395007]	129	1			T1	1		T14	1		T6	3
auto[1476395008:1610612735]	105	1			T17	1		T18	1		T105	1
auto[1610612736:1744830463]	107	1			T4	1		T109	1		T44	1
auto[1744830464:1879048191]	92	1			T1	1		T17	1		T20	1
auto[1879048192:2013265919]	120	1			T4	1		T18	1		T109	1
auto[2013265920:2147483647]	106	1			T6	1		T53	2		T180	1
auto[2147483648:2281701375]	105	1			T18	1		T35	1		T90	1
auto[2281701376:2415919103]	119	1			T19	1		T44	1		T6	4
auto[2415919104:2550136831]	74	1			T105	1		T53	1		T7	1
auto[2550136832:2684354559]	104	1			T4	1		T15	1		T105	1
auto[2684354560:2818572287]	110	1			T18	1		T19	1		T105	1
auto[2818572288:2952790015]	96	1			T51	1		T45	1		T345	1
auto[2952790016:3087007743]	98	1			T105	1		T27	1		T6	2
auto[3087007744:3221225471]	99	1			T1	1		T4	1		T17	1
auto[3221225472:3355443199]	122	1			T1	1		T15	1		T6	2
auto[3355443200:3489660927]	119	1			T17	1		T18	1		T105	2
auto[3489660928:3623878655]	111	1			T1	1		T14	1		T19	1
auto[3623878656:3758096383]	126	1			T19	1		T109	1		T88	1
auto[3758096384:3892314111]	118	1			T105	1		T6	5		T178	1
auto[3892314112:4026531839]	114	1			T14	2		T15	1		T18	1
auto[4026531840:4160749567]	112	1			T44	1		T6	1		T224	1
auto[4160749568:4294967295]	115	1			T17	1		T86	1		T109	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	40	1			T177	1		T6	1		T178	1
auto[0:134217727]	auto[1]	51	1			T105	2		T177	1		T224	2
auto[134217728:268435455]	auto[0]	55	1			T105	1		T6	4		T179	1
auto[134217728:268435455]	auto[1]	70	1			T4	1		T86	1		T47	1
auto[268435456:402653183]	auto[0]	49	1			T35	1		T6	1		T52	1
auto[268435456:402653183]	auto[1]	64	1			T14	1		T35	1		T105	1
auto[402653184:536870911]	auto[0]	54	1			T1	1		T88	1		T27	1
auto[402653184:536870911]	auto[1]	45	1			T45	1		T24	1		T46	3
auto[536870912:671088639]	auto[0]	47	1			T20	1		T224	1		T180	1
auto[536870912:671088639]	auto[1]	57	1			T1	1		T4	1		T105	1
auto[671088640:805306367]	auto[0]	48	1			T14	1		T6	1		T45	1
auto[671088640:805306367]	auto[1]	52	1			T18	1		T105	1		T5	1
auto[805306368:939524095]	auto[0]	58	1			T105	1		T47	1		T51	2
auto[805306368:939524095]	auto[1]	54	1			T86	1		T109	1		T7	2
auto[939524096:1073741823]	auto[0]	44	1			T4	1		T6	2		T53	1
auto[939524096:1073741823]	auto[1]	50	1			T6	1		T45	2		T221	1
auto[1073741824:1207959551]	auto[0]	54	1			T179	1		T45	1		T125	1
auto[1073741824:1207959551]	auto[1]	62	1			T44	1		T6	3		T92	1
auto[1207959552:1342177279]	auto[0]	47	1			T14	1		T52	1		T54	1
auto[1207959552:1342177279]	auto[1]	61	1			T18	1		T27	1		T7	1
auto[1342177280:1476395007]	auto[0]	64	1			T1	1		T14	1		T6	2
auto[1342177280:1476395007]	auto[1]	65	1			T6	1		T7	1		T52	1
auto[1476395008:1610612735]	auto[0]	32	1			T105	1		T46	2		T225	1
auto[1476395008:1610612735]	auto[1]	73	1			T17	1		T18	1		T124	1
auto[1610612736:1744830463]	auto[0]	51	1			T6	1		T51	1		T45	1
auto[1610612736:1744830463]	auto[1]	56	1			T4	1		T109	1		T44	1
auto[1744830464:1879048191]	auto[0]	37	1			T45	3		T214	1		T46	1
auto[1744830464:1879048191]	auto[1]	55	1			T1	1		T17	1		T20	1
auto[1879048192:2013265919]	auto[0]	67	1			T4	1		T18	1		T109	1
auto[1879048192:2013265919]	auto[1]	53	1			T90	1		T178	1		T221	1
auto[2013265920:2147483647]	auto[0]	48	1			T6	1		T53	1		T180	1
auto[2013265920:2147483647]	auto[1]	58	1			T53	1		T221	1		T245	1
auto[2147483648:2281701375]	auto[0]	54	1			T18	1		T47	1		T6	1
auto[2147483648:2281701375]	auto[1]	51	1			T35	1		T90	1		T7	1
auto[2281701376:2415919103]	auto[0]	50	1			T44	1		T6	2		T224	1
auto[2281701376:2415919103]	auto[1]	69	1			T19	1		T6	2		T124	1
auto[2415919104:2550136831]	auto[0]	35	1			T53	1		T265	1		T278	1
auto[2415919104:2550136831]	auto[1]	39	1			T105	1		T7	1		T62	1
auto[2550136832:2684354559]	auto[0]	47	1			T15	1		T179	1		T45	1
auto[2550136832:2684354559]	auto[1]	57	1			T4	1		T105	1		T90	1
auto[2684354560:2818572287]	auto[0]	49	1			T19	1		T6	1		T179	1
auto[2684354560:2818572287]	auto[1]	61	1			T18	1		T105	1		T90	1
auto[2818572288:2952790015]	auto[0]	46	1			T51	1		T345	1		T106	1
auto[2818572288:2952790015]	auto[1]	50	1			T45	1		T46	2		T61	1
auto[2952790016:3087007743]	auto[0]	43	1			T105	1		T124	1		T180	1
auto[2952790016:3087007743]	auto[1]	55	1			T27	1		T6	2		T7	1
auto[3087007744:3221225471]	auto[0]	46	1			T105	1		T6	2		T222	1
auto[3087007744:3221225471]	auto[1]	53	1			T1	1		T4	1		T17	1
auto[3221225472:3355443199]	auto[0]	68	1			T1	1		T15	1		T6	1
auto[3221225472:3355443199]	auto[1]	54	1			T6	1		T124	2		T45	1
auto[3355443200:3489660927]	auto[0]	60	1			T18	1		T105	1		T6	1
auto[3355443200:3489660927]	auto[1]	59	1			T17	1		T105	1		T125	1
auto[3489660928:3623878655]	auto[0]	64	1			T14	1		T19	1		T105	1
auto[3489660928:3623878655]	auto[1]	47	1			T1	1		T6	1		T7	1
auto[3623878656:3758096383]	auto[0]	58	1			T46	1		T61	1		T223	1
auto[3623878656:3758096383]	auto[1]	68	1			T19	1		T109	1		T88	1
auto[3758096384:3892314111]	auto[0]	60	1			T6	2		T45	1		T219	1
auto[3758096384:3892314111]	auto[1]	58	1			T105	1		T6	3		T178	1
auto[3892314112:4026531839]	auto[0]	50	1			T14	2		T6	2		T124	1
auto[3892314112:4026531839]	auto[1]	64	1			T15	1		T18	1		T47	1
auto[4026531840:4160749567]	auto[0]	52	1			T224	1		T124	1		T7	1
auto[4026531840:4160749567]	auto[1]	60	1			T44	1		T6	1		T45	2
auto[4160749568:4294967295]	auto[0]	54	1			T86	1		T177	1		T6	2
auto[4160749568:4294967295]	auto[1]	61	1			T17	1		T109	1		T7	1