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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.88 99.04 98.19 99.29 100.00 99.02 98.41 91.24


Total test records in report: 1081
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T1005 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2828608047 Aug 06 05:52:08 PM PDT 24 Aug 06 05:52:10 PM PDT 24 51702250 ps
T1006 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2731120192 Aug 06 05:51:54 PM PDT 24 Aug 06 05:51:55 PM PDT 24 107315939 ps
T1007 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2011450684 Aug 06 05:52:47 PM PDT 24 Aug 06 05:52:48 PM PDT 24 45252763 ps
T1008 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.270093069 Aug 06 05:52:29 PM PDT 24 Aug 06 05:52:31 PM PDT 24 57170157 ps
T1009 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3234444592 Aug 06 05:52:13 PM PDT 24 Aug 06 05:52:14 PM PDT 24 43505935 ps
T1010 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.414421373 Aug 06 05:52:13 PM PDT 24 Aug 06 05:52:28 PM PDT 24 1005978885 ps
T1011 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3456583162 Aug 06 05:52:09 PM PDT 24 Aug 06 05:52:17 PM PDT 24 272699632 ps
T1012 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.635675772 Aug 06 05:52:07 PM PDT 24 Aug 06 05:52:11 PM PDT 24 123299974 ps
T1013 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2592622669 Aug 06 05:51:51 PM PDT 24 Aug 06 05:51:56 PM PDT 24 157456238 ps
T1014 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.244543125 Aug 06 05:52:46 PM PDT 24 Aug 06 05:52:48 PM PDT 24 65867351 ps
T1015 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.287274608 Aug 06 05:52:44 PM PDT 24 Aug 06 05:52:45 PM PDT 24 34470669 ps
T1016 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2011787046 Aug 06 05:52:27 PM PDT 24 Aug 06 05:52:29 PM PDT 24 191036355 ps
T1017 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.201318954 Aug 06 05:52:46 PM PDT 24 Aug 06 05:52:49 PM PDT 24 824761714 ps
T1018 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.913329713 Aug 06 05:52:43 PM PDT 24 Aug 06 05:52:47 PM PDT 24 519162847 ps
T1019 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.197357191 Aug 06 05:52:26 PM PDT 24 Aug 06 05:52:28 PM PDT 24 126536406 ps
T1020 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3835547652 Aug 06 05:52:27 PM PDT 24 Aug 06 05:52:28 PM PDT 24 72623401 ps
T1021 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1407659327 Aug 06 05:52:46 PM PDT 24 Aug 06 05:52:47 PM PDT 24 9087248 ps
T1022 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.572119241 Aug 06 05:52:27 PM PDT 24 Aug 06 05:52:28 PM PDT 24 51503416 ps
T1023 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.682350667 Aug 06 05:52:10 PM PDT 24 Aug 06 05:52:12 PM PDT 24 44656529 ps
T1024 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1863200047 Aug 06 05:52:05 PM PDT 24 Aug 06 05:52:14 PM PDT 24 127481174 ps
T1025 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2778818329 Aug 06 05:52:10 PM PDT 24 Aug 06 05:52:10 PM PDT 24 22266215 ps
T1026 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.393327408 Aug 06 05:52:29 PM PDT 24 Aug 06 05:52:30 PM PDT 24 7550802 ps
T1027 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1858510309 Aug 06 05:52:45 PM PDT 24 Aug 06 05:52:46 PM PDT 24 30764477 ps
T1028 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3884525177 Aug 06 05:52:45 PM PDT 24 Aug 06 05:52:48 PM PDT 24 139267666 ps
T1029 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1094400756 Aug 06 05:52:27 PM PDT 24 Aug 06 05:52:31 PM PDT 24 308246335 ps
T1030 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2914127448 Aug 06 05:52:44 PM PDT 24 Aug 06 05:52:47 PM PDT 24 1251667530 ps
T1031 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2854899361 Aug 06 05:52:55 PM PDT 24 Aug 06 05:52:56 PM PDT 24 25065648 ps
T148 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.96764780 Aug 06 05:52:31 PM PDT 24 Aug 06 05:52:40 PM PDT 24 215768819 ps
T1032 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4115081496 Aug 06 05:52:48 PM PDT 24 Aug 06 05:52:49 PM PDT 24 46870221 ps
T145 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3722711264 Aug 06 05:52:28 PM PDT 24 Aug 06 05:52:35 PM PDT 24 497730030 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2339294792 Aug 06 05:52:43 PM PDT 24 Aug 06 05:52:45 PM PDT 24 35530977 ps
T1034 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3227245636 Aug 06 05:52:26 PM PDT 24 Aug 06 05:52:35 PM PDT 24 401804381 ps
T1035 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4238628018 Aug 06 05:52:44 PM PDT 24 Aug 06 05:52:46 PM PDT 24 45626863 ps
T1036 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.496853418 Aug 06 05:52:06 PM PDT 24 Aug 06 05:52:08 PM PDT 24 555472302 ps
T1037 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2291319156 Aug 06 05:52:13 PM PDT 24 Aug 06 05:52:17 PM PDT 24 93360428 ps
T1038 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1184252817 Aug 06 05:52:07 PM PDT 24 Aug 06 05:52:08 PM PDT 24 22138566 ps
T1039 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.233529913 Aug 06 05:52:55 PM PDT 24 Aug 06 05:52:56 PM PDT 24 12194130 ps
T1040 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.282015307 Aug 06 05:53:07 PM PDT 24 Aug 06 05:53:08 PM PDT 24 61762291 ps
T1041 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2810030720 Aug 06 05:52:04 PM PDT 24 Aug 06 05:52:24 PM PDT 24 2303231198 ps
T1042 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2843871124 Aug 06 05:52:49 PM PDT 24 Aug 06 05:52:50 PM PDT 24 10165386 ps
T1043 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.739018557 Aug 06 05:52:46 PM PDT 24 Aug 06 05:52:49 PM PDT 24 424698559 ps
T1044 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3210826517 Aug 06 05:52:24 PM PDT 24 Aug 06 05:52:27 PM PDT 24 50654562 ps
T1045 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.362585260 Aug 06 05:52:44 PM PDT 24 Aug 06 05:52:46 PM PDT 24 68572023 ps
T1046 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3653733540 Aug 06 05:52:49 PM PDT 24 Aug 06 05:52:50 PM PDT 24 19282747 ps
T1047 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.920234796 Aug 06 05:52:09 PM PDT 24 Aug 06 05:52:10 PM PDT 24 10292588 ps
T1048 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1793643347 Aug 06 05:51:54 PM PDT 24 Aug 06 05:51:55 PM PDT 24 13859178 ps
T1049 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1802587972 Aug 06 05:52:07 PM PDT 24 Aug 06 05:52:12 PM PDT 24 197390606 ps
T1050 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2744846754 Aug 06 05:52:07 PM PDT 24 Aug 06 05:52:09 PM PDT 24 69415575 ps
T1051 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4284940454 Aug 06 05:52:49 PM PDT 24 Aug 06 05:52:51 PM PDT 24 197282367 ps
T1052 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.556141771 Aug 06 05:52:48 PM PDT 24 Aug 06 05:52:49 PM PDT 24 24070488 ps
T1053 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.169613579 Aug 06 05:52:50 PM PDT 24 Aug 06 05:52:51 PM PDT 24 18703730 ps
T1054 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2098905121 Aug 06 05:52:27 PM PDT 24 Aug 06 05:52:30 PM PDT 24 190549844 ps
T1055 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4290588522 Aug 06 05:52:45 PM PDT 24 Aug 06 05:52:50 PM PDT 24 250314926 ps
T1056 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2156222599 Aug 06 05:52:47 PM PDT 24 Aug 06 05:52:58 PM PDT 24 1829461524 ps
T1057 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1633180268 Aug 06 05:53:11 PM PDT 24 Aug 06 05:53:12 PM PDT 24 12372886 ps
T1058 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3484088774 Aug 06 05:52:48 PM PDT 24 Aug 06 05:52:51 PM PDT 24 142375335 ps
T1059 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.75820829 Aug 06 05:52:44 PM PDT 24 Aug 06 05:52:46 PM PDT 24 49245275 ps
T1060 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2924029332 Aug 06 05:52:06 PM PDT 24 Aug 06 05:52:09 PM PDT 24 291643589 ps
T140 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3626177540 Aug 06 05:52:28 PM PDT 24 Aug 06 05:52:31 PM PDT 24 76536301 ps
T1061 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4032175559 Aug 06 05:52:27 PM PDT 24 Aug 06 05:52:28 PM PDT 24 46852001 ps
T1062 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1064840906 Aug 06 05:52:26 PM PDT 24 Aug 06 05:52:28 PM PDT 24 27686268 ps
T1063 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.995931445 Aug 06 05:53:05 PM PDT 24 Aug 06 05:53:06 PM PDT 24 10235882 ps
T1064 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.319257044 Aug 06 05:52:07 PM PDT 24 Aug 06 05:52:14 PM PDT 24 167096029 ps
T1065 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.4260861254 Aug 06 05:52:31 PM PDT 24 Aug 06 05:52:35 PM PDT 24 324133101 ps
T1066 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1380284703 Aug 06 05:52:45 PM PDT 24 Aug 06 05:52:50 PM PDT 24 227987724 ps
T1067 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3205966023 Aug 06 05:52:55 PM PDT 24 Aug 06 05:52:56 PM PDT 24 28105424 ps
T1068 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1322570 Aug 06 05:52:26 PM PDT 24 Aug 06 05:52:28 PM PDT 24 254286595 ps
T1069 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2509996398 Aug 06 05:52:50 PM PDT 24 Aug 06 05:52:51 PM PDT 24 8366511 ps
T1070 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.193196067 Aug 06 05:52:49 PM PDT 24 Aug 06 05:52:49 PM PDT 24 21102412 ps
T1071 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.168625086 Aug 06 05:53:08 PM PDT 24 Aug 06 05:53:09 PM PDT 24 42032868 ps
T1072 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.979306498 Aug 06 05:52:26 PM PDT 24 Aug 06 05:52:29 PM PDT 24 401325684 ps
T1073 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.716681554 Aug 06 05:52:09 PM PDT 24 Aug 06 05:52:12 PM PDT 24 148979927 ps
T1074 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3786305717 Aug 06 05:52:06 PM PDT 24 Aug 06 05:52:08 PM PDT 24 63254505 ps
T1075 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2776881507 Aug 06 05:52:28 PM PDT 24 Aug 06 05:52:32 PM PDT 24 586616537 ps
T1076 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.644928156 Aug 06 05:52:49 PM PDT 24 Aug 06 05:52:50 PM PDT 24 136599775 ps
T154 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.4173389970 Aug 06 05:52:10 PM PDT 24 Aug 06 05:52:16 PM PDT 24 405077313 ps
T1077 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.489648800 Aug 06 05:52:29 PM PDT 24 Aug 06 05:52:30 PM PDT 24 11394218 ps
T1078 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.435021198 Aug 06 05:52:08 PM PDT 24 Aug 06 05:52:12 PM PDT 24 270774254 ps
T1079 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.247807134 Aug 06 05:52:13 PM PDT 24 Aug 06 05:52:16 PM PDT 24 509846267 ps
T1080 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3473284614 Aug 06 05:52:08 PM PDT 24 Aug 06 05:52:08 PM PDT 24 17447869 ps
T1081 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3211450855 Aug 06 05:52:48 PM PDT 24 Aug 06 05:52:49 PM PDT 24 10823724 ps

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2708514662
Short name T4
Test name
Test status
Simulation time 306896807 ps
CPU time 7.94 seconds
Started Aug 06 05:25:37 PM PDT 24
Finished Aug 06 05:25:45 PM PDT 24
Peak memory 222652 kb
Host smart-6a7850be-7d06-40bf-babc-d753a61ed323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708514662 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2708514662
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1359627547
Short name T6
Test name
Test status
Simulation time 20152350057 ps
CPU time 355.11 seconds
Started Aug 06 05:25:31 PM PDT 24
Finished Aug 06 05:31:26 PM PDT 24
Peak memory 222488 kb
Host smart-c7268db2-c65e-442d-b8cc-9af141546a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359627547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1359627547
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3893478637
Short name T46
Test name
Test status
Simulation time 8471359689 ps
CPU time 87.81 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:28:52 PM PDT 24
Peak memory 222240 kb
Host smart-7c559a14-644f-4763-9d4d-ff2b24a4b8e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893478637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3893478637
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.597086713
Short name T11
Test name
Test status
Simulation time 1420270027 ps
CPU time 9.73 seconds
Started Aug 06 05:24:43 PM PDT 24
Finished Aug 06 05:24:53 PM PDT 24
Peak memory 234008 kb
Host smart-ade881d9-1d5b-4227-a33c-e51da0065812
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597086713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.597086713
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1759475641
Short name T14
Test name
Test status
Simulation time 88167296 ps
CPU time 3.94 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:47 PM PDT 24
Peak memory 214220 kb
Host smart-50d88139-3dbd-4c1c-9c51-76e25a0a7412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759475641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1759475641
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3998802118
Short name T105
Test name
Test status
Simulation time 671129115 ps
CPU time 22.11 seconds
Started Aug 06 05:27:03 PM PDT 24
Finished Aug 06 05:27:25 PM PDT 24
Peak memory 220368 kb
Host smart-fda410db-710c-43c1-b79f-6c9797c78e59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998802118 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3998802118
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.411001885
Short name T8
Test name
Test status
Simulation time 338122083 ps
CPU time 3.31 seconds
Started Aug 06 05:26:18 PM PDT 24
Finished Aug 06 05:26:21 PM PDT 24
Peak memory 222596 kb
Host smart-808f5813-5cab-492d-b182-c161b647b025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411001885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.411001885
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2038430555
Short name T128
Test name
Test status
Simulation time 1612105052 ps
CPU time 20.02 seconds
Started Aug 06 05:26:58 PM PDT 24
Finished Aug 06 05:27:19 PM PDT 24
Peak memory 215972 kb
Host smart-e57ab12a-a219-41da-96b1-adf361356341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038430555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2038430555
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3296623614
Short name T110
Test name
Test status
Simulation time 1264444698 ps
CPU time 7.95 seconds
Started Aug 06 05:52:26 PM PDT 24
Finished Aug 06 05:52:35 PM PDT 24
Peak memory 214696 kb
Host smart-068b3a4a-eee0-48d6-bccd-641f810e35ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296623614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3296623614
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.798666151
Short name T109
Test name
Test status
Simulation time 214697953 ps
CPU time 11.59 seconds
Started Aug 06 05:25:24 PM PDT 24
Finished Aug 06 05:25:35 PM PDT 24
Peak memory 215620 kb
Host smart-8401acc2-22f3-4dbb-9eea-8b841fba0274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798666151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.798666151
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1903993101
Short name T214
Test name
Test status
Simulation time 1519749449 ps
CPU time 24.37 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:49 PM PDT 24
Peak memory 216396 kb
Host smart-cf37eeb0-4d3a-4c07-b17c-5d20c26297a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903993101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1903993101
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3179407420
Short name T124
Test name
Test status
Simulation time 1468453902 ps
CPU time 74.9 seconds
Started Aug 06 05:26:34 PM PDT 24
Finished Aug 06 05:27:49 PM PDT 24
Peak memory 215264 kb
Host smart-e748fc52-a9aa-4c66-957f-a48acbaece9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179407420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3179407420
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1635416340
Short name T161
Test name
Test status
Simulation time 87768568 ps
CPU time 1.53 seconds
Started Aug 06 05:26:57 PM PDT 24
Finished Aug 06 05:26:58 PM PDT 24
Peak memory 215696 kb
Host smart-2f5a2ef3-aece-4191-9a78-a893ee02e136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635416340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1635416340
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3325217842
Short name T98
Test name
Test status
Simulation time 83913137 ps
CPU time 3.4 seconds
Started Aug 06 05:26:50 PM PDT 24
Finished Aug 06 05:26:54 PM PDT 24
Peak memory 218796 kb
Host smart-9260a17c-dbcb-49ce-85d0-24c89e286bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325217842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3325217842
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3867387554
Short name T34
Test name
Test status
Simulation time 111886397 ps
CPU time 3.26 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:06 PM PDT 24
Peak memory 210332 kb
Host smart-2460fb4f-b0bb-4768-b290-9fee7b936d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867387554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3867387554
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1409624471
Short name T239
Test name
Test status
Simulation time 618264740 ps
CPU time 29.79 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:27:16 PM PDT 24
Peak memory 214228 kb
Host smart-217a60e9-e175-4fc8-ba14-e7570e4c724b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1409624471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1409624471
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.586974556
Short name T45
Test name
Test status
Simulation time 2081433376 ps
CPU time 48.91 seconds
Started Aug 06 05:26:44 PM PDT 24
Finished Aug 06 05:27:33 PM PDT 24
Peak memory 216884 kb
Host smart-79e146fc-97b7-4a93-a9da-9bf969d45b55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586974556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.586974556
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.1705446271
Short name T62
Test name
Test status
Simulation time 920244905 ps
CPU time 13.24 seconds
Started Aug 06 05:24:42 PM PDT 24
Finished Aug 06 05:24:55 PM PDT 24
Peak memory 222532 kb
Host smart-c73b9e1b-f7c5-4eb0-b928-8e080f2805ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705446271 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.1705446271
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1451712146
Short name T327
Test name
Test status
Simulation time 2481852209 ps
CPU time 122.53 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:27:01 PM PDT 24
Peak memory 214812 kb
Host smart-a1b9a193-f2fa-4fbc-a699-9e4b79eae280
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451712146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1451712146
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3023199003
Short name T22
Test name
Test status
Simulation time 272098166 ps
CPU time 3.64 seconds
Started Aug 06 05:25:03 PM PDT 24
Finished Aug 06 05:25:07 PM PDT 24
Peak memory 217508 kb
Host smart-84d23726-e227-4fad-87fc-65613d915ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023199003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3023199003
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3572122937
Short name T315
Test name
Test status
Simulation time 134875185 ps
CPU time 7.63 seconds
Started Aug 06 05:26:14 PM PDT 24
Finished Aug 06 05:26:22 PM PDT 24
Peak memory 214316 kb
Host smart-c0534bad-2f82-4e7e-a771-2a7a7d977960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572122937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3572122937
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1623381008
Short name T39
Test name
Test status
Simulation time 1647868906 ps
CPU time 45.22 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 222332 kb
Host smart-3dc9a795-1aee-4273-a608-045c9766b07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623381008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1623381008
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.212267956
Short name T76
Test name
Test status
Simulation time 3174124542 ps
CPU time 30.73 seconds
Started Aug 06 05:25:12 PM PDT 24
Finished Aug 06 05:25:43 PM PDT 24
Peak memory 221968 kb
Host smart-d50a0428-c368-4658-b577-896b1548af1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212267956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.212267956
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3545423258
Short name T7
Test name
Test status
Simulation time 1335910921 ps
CPU time 24.23 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:51 PM PDT 24
Peak memory 214140 kb
Host smart-08601130-44b2-4060-8471-800dfab8d57a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545423258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3545423258
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2584382763
Short name T32
Test name
Test status
Simulation time 91430885 ps
CPU time 4.32 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:25:18 PM PDT 24
Peak memory 218524 kb
Host smart-d05f345e-e1d0-45c4-bb60-027287992c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584382763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2584382763
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1248761942
Short name T388
Test name
Test status
Simulation time 253331081 ps
CPU time 7.15 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:31 PM PDT 24
Peak memory 222420 kb
Host smart-5b1e4e5a-2d0b-4e36-9471-597d09310a9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248761942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1248761942
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.122135633
Short name T190
Test name
Test status
Simulation time 1834962334 ps
CPU time 33.06 seconds
Started Aug 06 05:24:34 PM PDT 24
Finished Aug 06 05:25:07 PM PDT 24
Peak memory 216324 kb
Host smart-0faef29d-913d-4797-9c69-f76ae17f1d8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122135633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.122135633
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.4058089700
Short name T331
Test name
Test status
Simulation time 201740389 ps
CPU time 10.91 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:40 PM PDT 24
Peak memory 215308 kb
Host smart-2dd9957f-f05d-4b30-bdb5-b694e5ab4a5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4058089700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.4058089700
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2372640105
Short name T136
Test name
Test status
Simulation time 842234068 ps
CPU time 8.54 seconds
Started Aug 06 05:52:08 PM PDT 24
Finished Aug 06 05:52:16 PM PDT 24
Peak memory 214356 kb
Host smart-31fecc65-f6e7-457e-8729-e7c044a5a719
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372640105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2372640105
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3953753633
Short name T61
Test name
Test status
Simulation time 523827050 ps
CPU time 25.65 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:27:02 PM PDT 24
Peak memory 221756 kb
Host smart-350c5e60-d123-4718-bbf6-8353801a1246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953753633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3953753633
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2236420474
Short name T93
Test name
Test status
Simulation time 57210813 ps
CPU time 2.86 seconds
Started Aug 06 05:27:03 PM PDT 24
Finished Aug 06 05:27:06 PM PDT 24
Peak memory 222516 kb
Host smart-08bad45a-2cbf-4b25-b7b5-a4eb6326d052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236420474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2236420474
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1653588238
Short name T935
Test name
Test status
Simulation time 375815428 ps
CPU time 2.44 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:08 PM PDT 24
Peak memory 214628 kb
Host smart-b6d26420-c08e-4cfa-9276-caef26e09d4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653588238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1653588238
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3347047724
Short name T394
Test name
Test status
Simulation time 26760614 ps
CPU time 0.76 seconds
Started Aug 06 05:25:28 PM PDT 24
Finished Aug 06 05:25:29 PM PDT 24
Peak memory 205984 kb
Host smart-4436e869-fa0c-4c9b-99af-07a7125307d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347047724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3347047724
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.955424673
Short name T95
Test name
Test status
Simulation time 168910599 ps
CPU time 3.35 seconds
Started Aug 06 05:26:34 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 221860 kb
Host smart-f8413d11-e2ec-4aae-8e45-05d7e042c194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955424673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.955424673
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.791147431
Short name T204
Test name
Test status
Simulation time 2065664437 ps
CPU time 28.92 seconds
Started Aug 06 05:25:04 PM PDT 24
Finished Aug 06 05:25:33 PM PDT 24
Peak memory 216448 kb
Host smart-28a555bf-b430-45da-a47b-bc6fb771d595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791147431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.791147431
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1283174438
Short name T139
Test name
Test status
Simulation time 269513255 ps
CPU time 6.61 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:13 PM PDT 24
Peak memory 216668 kb
Host smart-44b195c3-9767-4ee0-93c0-80b3513eb7e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283174438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1283174438
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.534745836
Short name T143
Test name
Test status
Simulation time 1154939529 ps
CPU time 7.21 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:53 PM PDT 24
Peak memory 214424 kb
Host smart-9717e8c1-4a9d-4796-aeef-9fcca163efa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534745836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.534745836
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3924798885
Short name T48
Test name
Test status
Simulation time 1518378535 ps
CPU time 14.82 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:50 PM PDT 24
Peak memory 222400 kb
Host smart-37c8e05c-10ba-4c22-97a9-87f8d1c5a892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924798885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3924798885
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1885621112
Short name T264
Test name
Test status
Simulation time 90292167 ps
CPU time 2.46 seconds
Started Aug 06 05:27:52 PM PDT 24
Finished Aug 06 05:27:54 PM PDT 24
Peak memory 214192 kb
Host smart-7bde2e3b-31e3-4d30-9cf2-47b9a579eb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885621112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1885621112
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1287714553
Short name T24
Test name
Test status
Simulation time 90717357 ps
CPU time 4.18 seconds
Started Aug 06 05:26:14 PM PDT 24
Finished Aug 06 05:26:19 PM PDT 24
Peak memory 208980 kb
Host smart-cb78754c-e162-4040-a16c-a5b663340982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287714553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1287714553
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2700520147
Short name T228
Test name
Test status
Simulation time 113608237 ps
CPU time 5.94 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:36 PM PDT 24
Peak memory 215352 kb
Host smart-b6c46420-e36b-4f89-bd79-c69358f6602a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2700520147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2700520147
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1161052628
Short name T247
Test name
Test status
Simulation time 355706769 ps
CPU time 3.39 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:38 PM PDT 24
Peak memory 214312 kb
Host smart-33f1d5c5-6047-429f-b9ac-00b9a6f3a958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161052628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1161052628
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.4245208686
Short name T556
Test name
Test status
Simulation time 68573680 ps
CPU time 2.43 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:27 PM PDT 24
Peak memory 209956 kb
Host smart-37b28d45-b80d-49fc-889e-e296928f106e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245208686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.4245208686
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3834701012
Short name T285
Test name
Test status
Simulation time 135618354 ps
CPU time 5.57 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:33 PM PDT 24
Peak memory 214408 kb
Host smart-1c8d2160-8f0f-4d3a-b345-48f28daaeeef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3834701012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3834701012
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.673367748
Short name T59
Test name
Test status
Simulation time 265612976 ps
CPU time 2.78 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:40 PM PDT 24
Peak memory 222564 kb
Host smart-7fe3de7d-8331-4111-89a8-627e96b6c9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673367748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.673367748
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3005367774
Short name T898
Test name
Test status
Simulation time 690435840 ps
CPU time 30.07 seconds
Started Aug 06 05:24:26 PM PDT 24
Finished Aug 06 05:24:56 PM PDT 24
Peak memory 221368 kb
Host smart-26489b33-b946-4f94-8ea7-16ae585bc0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005367774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3005367774
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2392394291
Short name T621
Test name
Test status
Simulation time 476059609 ps
CPU time 4.08 seconds
Started Aug 06 05:25:17 PM PDT 24
Finished Aug 06 05:25:21 PM PDT 24
Peak memory 214120 kb
Host smart-13028c8a-b69b-45c3-aed7-f6876be1960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392394291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2392394291
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2910107496
Short name T389
Test name
Test status
Simulation time 161039687 ps
CPU time 8.8 seconds
Started Aug 06 05:25:44 PM PDT 24
Finished Aug 06 05:25:53 PM PDT 24
Peak memory 215268 kb
Host smart-80066ab4-89e8-48d7-b8ce-979c25af8929
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2910107496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2910107496
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1218588945
Short name T299
Test name
Test status
Simulation time 163596419 ps
CPU time 2.5 seconds
Started Aug 06 05:24:42 PM PDT 24
Finished Aug 06 05:24:45 PM PDT 24
Peak memory 222372 kb
Host smart-809c5f81-ddea-4be3-98b5-811f63e2e764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218588945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1218588945
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.617879003
Short name T223
Test name
Test status
Simulation time 52185595 ps
CPU time 2.8 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:26 PM PDT 24
Peak memory 214316 kb
Host smart-b12ee963-0462-4edf-b288-2923e36ecdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617879003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.617879003
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1905965302
Short name T325
Test name
Test status
Simulation time 1354196290 ps
CPU time 47.54 seconds
Started Aug 06 05:27:21 PM PDT 24
Finished Aug 06 05:28:09 PM PDT 24
Peak memory 222400 kb
Host smart-c7aef6b8-fad1-400b-a4c8-bde9d482557c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905965302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1905965302
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.559568726
Short name T328
Test name
Test status
Simulation time 2985253282 ps
CPU time 23.25 seconds
Started Aug 06 05:27:27 PM PDT 24
Finished Aug 06 05:27:50 PM PDT 24
Peak memory 220876 kb
Host smart-a82cbcad-8bfe-4f22-92a2-cda90faa8eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559568726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.559568726
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4159598915
Short name T146
Test name
Test status
Simulation time 979944112 ps
CPU time 6.94 seconds
Started Aug 06 05:52:47 PM PDT 24
Finished Aug 06 05:52:54 PM PDT 24
Peak memory 206260 kb
Host smart-0d47d8da-d422-4e4d-b897-c463ed71a913
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159598915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4159598915
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.4173389970
Short name T154
Test name
Test status
Simulation time 405077313 ps
CPU time 6.44 seconds
Started Aug 06 05:52:10 PM PDT 24
Finished Aug 06 05:52:16 PM PDT 24
Peak memory 206124 kb
Host smart-c04db6a0-489a-409a-9d46-45c86e39505c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173389970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.4173389970
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3722711264
Short name T145
Test name
Test status
Simulation time 497730030 ps
CPU time 6.87 seconds
Started Aug 06 05:52:28 PM PDT 24
Finished Aug 06 05:52:35 PM PDT 24
Peak memory 214188 kb
Host smart-fc799ff5-ec4c-4269-9d9e-e300db28e99a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722711264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3722711264
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3175405933
Short name T380
Test name
Test status
Simulation time 257616391 ps
CPU time 4.75 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:26:02 PM PDT 24
Peak memory 214244 kb
Host smart-7c74382d-35fd-486f-b7d3-a282f90854e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175405933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3175405933
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.681796741
Short name T122
Test name
Test status
Simulation time 330358771 ps
CPU time 3.51 seconds
Started Aug 06 05:26:40 PM PDT 24
Finished Aug 06 05:26:43 PM PDT 24
Peak memory 208616 kb
Host smart-1e9f6ad1-e212-4327-a31c-aef2000bd627
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681796741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.681796741
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1595652658
Short name T295
Test name
Test status
Simulation time 2406585741 ps
CPU time 78.49 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:28:04 PM PDT 24
Peak memory 221596 kb
Host smart-72a9e81c-df57-4236-aa92-535534819b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595652658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1595652658
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3928860045
Short name T210
Test name
Test status
Simulation time 154187993 ps
CPU time 4.14 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:28 PM PDT 24
Peak memory 214416 kb
Host smart-71fae193-ed12-422f-a1cb-611316d54dd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3928860045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3928860045
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.453983738
Short name T368
Test name
Test status
Simulation time 59747315 ps
CPU time 1.61 seconds
Started Aug 06 05:25:04 PM PDT 24
Finished Aug 06 05:25:06 PM PDT 24
Peak memory 210236 kb
Host smart-9e620a07-1af1-47a8-ab1b-9b7c1fe79065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453983738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.453983738
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1569534921
Short name T226
Test name
Test status
Simulation time 300016164 ps
CPU time 5.12 seconds
Started Aug 06 05:25:55 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 220092 kb
Host smart-3c1a55df-5e53-47d0-ba3b-422179c9f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569534921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1569534921
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2433558588
Short name T162
Test name
Test status
Simulation time 37436810 ps
CPU time 2.32 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 216880 kb
Host smart-8a95ee85-04c1-483e-99da-b426499f5c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433558588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2433558588
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2992220621
Short name T91
Test name
Test status
Simulation time 34946685 ps
CPU time 2.46 seconds
Started Aug 06 05:25:24 PM PDT 24
Finished Aug 06 05:25:26 PM PDT 24
Peak memory 214284 kb
Host smart-688ab5b3-0c91-410b-b809-2dc8cc8b3dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992220621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2992220621
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2966502535
Short name T236
Test name
Test status
Simulation time 141092857 ps
CPU time 2.26 seconds
Started Aug 06 05:25:31 PM PDT 24
Finished Aug 06 05:25:33 PM PDT 24
Peak memory 206924 kb
Host smart-0ef74ed2-253c-4a97-a483-7d857305f065
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966502535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2966502535
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2210753149
Short name T125
Test name
Test status
Simulation time 1250407404 ps
CPU time 6.37 seconds
Started Aug 06 05:25:55 PM PDT 24
Finished Aug 06 05:26:01 PM PDT 24
Peak memory 214272 kb
Host smart-e0fd7dfa-b524-4092-a306-5c4b386f2392
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2210753149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2210753149
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1249606995
Short name T242
Test name
Test status
Simulation time 238716476 ps
CPU time 3.69 seconds
Started Aug 06 05:26:13 PM PDT 24
Finished Aug 06 05:26:16 PM PDT 24
Peak memory 215040 kb
Host smart-60763a49-e31a-4ae8-871b-0fb3c7399a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249606995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1249606995
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2740409372
Short name T548
Test name
Test status
Simulation time 129523167 ps
CPU time 3.32 seconds
Started Aug 06 05:24:43 PM PDT 24
Finished Aug 06 05:24:47 PM PDT 24
Peak memory 208928 kb
Host smart-85b17887-26a8-4675-87b8-00a00c1e7006
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740409372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2740409372
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2121431639
Short name T153
Test name
Test status
Simulation time 816862160 ps
CPU time 6.58 seconds
Started Aug 06 05:52:51 PM PDT 24
Finished Aug 06 05:52:58 PM PDT 24
Peak memory 216700 kb
Host smart-ba007af6-f3f1-4351-8a64-a0189503c5b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121431639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2121431639
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1837299151
Short name T150
Test name
Test status
Simulation time 346295441 ps
CPU time 4.63 seconds
Started Aug 06 05:52:28 PM PDT 24
Finished Aug 06 05:52:33 PM PDT 24
Peak memory 215524 kb
Host smart-72da5f93-332a-44ca-98ed-8c5d30828906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837299151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1837299151
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1007862392
Short name T13
Test name
Test status
Simulation time 832961987 ps
CPU time 13.09 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:42 PM PDT 24
Peak memory 230596 kb
Host smart-a9c3142c-d4e1-4cb0-b9d2-d09d2d7b8bbd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007862392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1007862392
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.4052427563
Short name T43
Test name
Test status
Simulation time 4990586173 ps
CPU time 17.68 seconds
Started Aug 06 05:24:35 PM PDT 24
Finished Aug 06 05:24:53 PM PDT 24
Peak memory 235164 kb
Host smart-826fdb6d-84b0-44e8-8bb2-c8e72fe667f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052427563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.4052427563
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.249764706
Short name T164
Test name
Test status
Simulation time 781717825 ps
CPU time 3.39 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:25:18 PM PDT 24
Peak memory 217960 kb
Host smart-7a3da729-ef54-45d3-b491-5bf768c27f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249764706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.249764706
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2978122925
Short name T163
Test name
Test status
Simulation time 69651124 ps
CPU time 3.17 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:28 PM PDT 24
Peak memory 216860 kb
Host smart-3fb509b4-6571-4fd0-b50d-e3065499213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978122925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2978122925
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2139531500
Short name T68
Test name
Test status
Simulation time 233170813 ps
CPU time 3.84 seconds
Started Aug 06 05:24:58 PM PDT 24
Finished Aug 06 05:25:02 PM PDT 24
Peak memory 215608 kb
Host smart-81c89ca5-0e0a-469e-ac0b-c452610e464e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139531500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2139531500
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2081853551
Short name T166
Test name
Test status
Simulation time 1499612014 ps
CPU time 12.56 seconds
Started Aug 06 05:24:35 PM PDT 24
Finished Aug 06 05:24:48 PM PDT 24
Peak memory 222596 kb
Host smart-67ae64a8-2702-4b82-813b-e0e50dde7200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081853551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2081853551
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_random.352915782
Short name T275
Test name
Test status
Simulation time 293823744 ps
CPU time 3.9 seconds
Started Aug 06 05:24:37 PM PDT 24
Finished Aug 06 05:24:41 PM PDT 24
Peak memory 214244 kb
Host smart-cd966500-8147-42ab-ba9c-33cbf44b62f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352915782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.352915782
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.4015179102
Short name T218
Test name
Test status
Simulation time 288512916 ps
CPU time 2.41 seconds
Started Aug 06 05:24:35 PM PDT 24
Finished Aug 06 05:24:37 PM PDT 24
Peak memory 214296 kb
Host smart-6b324937-e15a-4b6e-9f22-d125ca5417c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015179102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4015179102
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1504373029
Short name T281
Test name
Test status
Simulation time 113881287 ps
CPU time 2.93 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:32 PM PDT 24
Peak memory 214592 kb
Host smart-78b08c99-5111-4651-9ad6-f224f3c5e304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504373029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1504373029
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.245093261
Short name T574
Test name
Test status
Simulation time 1900141757 ps
CPU time 23.89 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:53 PM PDT 24
Peak memory 210628 kb
Host smart-a040ceda-cd5e-4f1c-87b0-8484ac051e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245093261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.245093261
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2137956908
Short name T302
Test name
Test status
Simulation time 716081369 ps
CPU time 2.56 seconds
Started Aug 06 05:25:17 PM PDT 24
Finished Aug 06 05:25:19 PM PDT 24
Peak memory 214304 kb
Host smart-4e2dc2e4-ef4a-4b02-96f5-48c401b0c0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137956908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2137956908
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_smoke.451012120
Short name T369
Test name
Test status
Simulation time 3038497240 ps
CPU time 6.45 seconds
Started Aug 06 05:25:12 PM PDT 24
Finished Aug 06 05:25:19 PM PDT 24
Peak memory 206792 kb
Host smart-a97ee6f3-eb4b-4dd3-941d-5332751698af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451012120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.451012120
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1048781396
Short name T74
Test name
Test status
Simulation time 334099072 ps
CPU time 14.64 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:25:28 PM PDT 24
Peak memory 222368 kb
Host smart-8a1d9f52-b06e-4a4d-bc07-b8e937f78590
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048781396 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1048781396
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2833697149
Short name T373
Test name
Test status
Simulation time 421300072 ps
CPU time 11.8 seconds
Started Aug 06 05:25:15 PM PDT 24
Finished Aug 06 05:25:27 PM PDT 24
Peak memory 214328 kb
Host smart-b694beb0-ed54-4264-8afe-c1276228a145
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2833697149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2833697149
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1007543165
Short name T276
Test name
Test status
Simulation time 762466086 ps
CPU time 7.5 seconds
Started Aug 06 05:25:16 PM PDT 24
Finished Aug 06 05:25:24 PM PDT 24
Peak memory 214268 kb
Host smart-ae7ab2a9-a5f8-4b21-8129-49d0d47933e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007543165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1007543165
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1682295719
Short name T309
Test name
Test status
Simulation time 316172707 ps
CPU time 2.53 seconds
Started Aug 06 05:25:12 PM PDT 24
Finished Aug 06 05:25:14 PM PDT 24
Peak memory 208412 kb
Host smart-c8bd77b1-69ef-42be-bc06-c79d4cf67734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682295719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1682295719
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2495549819
Short name T49
Test name
Test status
Simulation time 576318887 ps
CPU time 17.03 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:30 PM PDT 24
Peak memory 222516 kb
Host smart-08edb8bc-4f5a-461b-9313-39e355a31996
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495549819 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2495549819
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3287280922
Short name T261
Test name
Test status
Simulation time 63774819 ps
CPU time 3.24 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 222408 kb
Host smart-083d610d-64e0-4775-a2aa-6b2cc6921b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287280922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3287280922
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3420684696
Short name T207
Test name
Test status
Simulation time 63542182 ps
CPU time 3.78 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 209600 kb
Host smart-c78f975d-8d1d-4536-8d24-7ef4e577cefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420684696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3420684696
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1882831815
Short name T253
Test name
Test status
Simulation time 776562075 ps
CPU time 4.84 seconds
Started Aug 06 05:25:31 PM PDT 24
Finished Aug 06 05:25:36 PM PDT 24
Peak memory 207748 kb
Host smart-869549bc-85d6-45d7-a299-06cf94bfcb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882831815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1882831815
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2428897017
Short name T798
Test name
Test status
Simulation time 106247855 ps
CPU time 2.59 seconds
Started Aug 06 05:25:41 PM PDT 24
Finished Aug 06 05:25:43 PM PDT 24
Peak memory 214452 kb
Host smart-fcc588c3-563d-4b26-ab54-c736e56bb492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428897017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2428897017
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3748494155
Short name T27
Test name
Test status
Simulation time 494673001 ps
CPU time 4.05 seconds
Started Aug 06 05:26:00 PM PDT 24
Finished Aug 06 05:26:04 PM PDT 24
Peak memory 221592 kb
Host smart-4d5ee078-3b1e-4474-89ed-8bc57ec27c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748494155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3748494155
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2220871863
Short name T203
Test name
Test status
Simulation time 3470676936 ps
CPU time 33.12 seconds
Started Aug 06 05:25:54 PM PDT 24
Finished Aug 06 05:26:28 PM PDT 24
Peak memory 215340 kb
Host smart-cfff244c-4bdd-47d0-8115-ea3ec90ea231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220871863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2220871863
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2382237373
Short name T199
Test name
Test status
Simulation time 41578607964 ps
CPU time 263.33 seconds
Started Aug 06 05:25:53 PM PDT 24
Finished Aug 06 05:30:17 PM PDT 24
Peak memory 218196 kb
Host smart-46a713ff-5f04-4e88-af27-e475c25678ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382237373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2382237373
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.401687757
Short name T57
Test name
Test status
Simulation time 1985487613 ps
CPU time 22.32 seconds
Started Aug 06 05:25:54 PM PDT 24
Finished Aug 06 05:26:16 PM PDT 24
Peak memory 216792 kb
Host smart-58ff8f46-5d3c-4d94-9aae-7dc1aad2fbb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401687757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.401687757
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2126747179
Short name T73
Test name
Test status
Simulation time 1839122368 ps
CPU time 22.47 seconds
Started Aug 06 05:26:13 PM PDT 24
Finished Aug 06 05:26:35 PM PDT 24
Peak memory 216380 kb
Host smart-8064591b-6507-4df7-a327-05941e062d61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126747179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2126747179
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3243592237
Short name T262
Test name
Test status
Simulation time 189884319 ps
CPU time 2.1 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 214176 kb
Host smart-dbf24b9b-bb3a-4284-8c2b-c7ae0a5a65cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243592237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3243592237
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_random.324511148
Short name T269
Test name
Test status
Simulation time 920694566 ps
CPU time 8.22 seconds
Started Aug 06 05:26:38 PM PDT 24
Finished Aug 06 05:26:46 PM PDT 24
Peak memory 209704 kb
Host smart-94e4d6a9-2fae-4cde-b973-5ec7a9978703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324511148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.324511148
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.4118931920
Short name T96
Test name
Test status
Simulation time 619318657 ps
CPU time 8.38 seconds
Started Aug 06 05:26:58 PM PDT 24
Finished Aug 06 05:27:06 PM PDT 24
Peak memory 209632 kb
Host smart-bc0fe6da-5531-4b44-8b20-98151cd527e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118931920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.4118931920
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.627941267
Short name T272
Test name
Test status
Simulation time 246086133 ps
CPU time 3.19 seconds
Started Aug 06 05:25:04 PM PDT 24
Finished Aug 06 05:25:08 PM PDT 24
Peak memory 222140 kb
Host smart-32cd521d-4329-420c-8a77-019b87e43dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627941267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.627941267
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.898555883
Short name T165
Test name
Test status
Simulation time 107391621 ps
CPU time 5.17 seconds
Started Aug 06 05:26:56 PM PDT 24
Finished Aug 06 05:27:01 PM PDT 24
Peak memory 217796 kb
Host smart-5126626a-81f6-4d53-8d4a-51df17ac33b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898555883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.898555883
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2233017811
Short name T986
Test name
Test status
Simulation time 137583699 ps
CPU time 4.1 seconds
Started Aug 06 05:52:03 PM PDT 24
Finished Aug 06 05:52:07 PM PDT 24
Peak memory 206192 kb
Host smart-c2c05d79-8b7d-441a-b393-9a0294edbd62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233017811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
233017811
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.191995123
Short name T910
Test name
Test status
Simulation time 1357299085 ps
CPU time 16.49 seconds
Started Aug 06 05:51:56 PM PDT 24
Finished Aug 06 05:52:12 PM PDT 24
Peak memory 206176 kb
Host smart-572ad29e-3cd4-4cf0-82a7-74994aa00544
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191995123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.191995123
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2731120192
Short name T1006
Test name
Test status
Simulation time 107315939 ps
CPU time 1.11 seconds
Started Aug 06 05:51:54 PM PDT 24
Finished Aug 06 05:51:55 PM PDT 24
Peak memory 206108 kb
Host smart-83bc38ba-e581-4e41-b069-4bf5b778ed37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731120192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
731120192
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3055986524
Short name T972
Test name
Test status
Simulation time 111623540 ps
CPU time 1.83 seconds
Started Aug 06 05:52:05 PM PDT 24
Finished Aug 06 05:52:07 PM PDT 24
Peak memory 214552 kb
Host smart-8ed7f360-054f-4316-b74c-1a075777bfe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055986524 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3055986524
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.986232728
Short name T144
Test name
Test status
Simulation time 93337910 ps
CPU time 1.13 seconds
Started Aug 06 05:51:55 PM PDT 24
Finished Aug 06 05:51:56 PM PDT 24
Peak memory 206188 kb
Host smart-688084e1-0f13-41e8-ac1a-bb4ae4cd2212
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986232728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.986232728
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1793643347
Short name T1048
Test name
Test status
Simulation time 13859178 ps
CPU time 0.77 seconds
Started Aug 06 05:51:54 PM PDT 24
Finished Aug 06 05:51:55 PM PDT 24
Peak memory 205868 kb
Host smart-aba0a68c-706e-46ad-9a80-b1a65e5e6998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793643347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1793643347
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3786305717
Short name T1074
Test name
Test status
Simulation time 63254505 ps
CPU time 2.35 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:08 PM PDT 24
Peak memory 206108 kb
Host smart-6789d8f9-52d2-4eee-a50d-018134265588
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786305717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3786305717
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2984680640
Short name T937
Test name
Test status
Simulation time 197077645 ps
CPU time 1.88 seconds
Started Aug 06 05:51:53 PM PDT 24
Finished Aug 06 05:51:55 PM PDT 24
Peak memory 214588 kb
Host smart-4fee7538-b1fc-495c-b416-0e8c4a395e78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984680640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2984680640
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1586993594
Short name T132
Test name
Test status
Simulation time 212939157 ps
CPU time 5.47 seconds
Started Aug 06 05:51:59 PM PDT 24
Finished Aug 06 05:52:05 PM PDT 24
Peak memory 220476 kb
Host smart-d39e3363-4fbb-4e0c-8abe-8fbb5e534008
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586993594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1586993594
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3242311131
Short name T975
Test name
Test status
Simulation time 580576067 ps
CPU time 2.06 seconds
Started Aug 06 05:51:55 PM PDT 24
Finished Aug 06 05:51:57 PM PDT 24
Peak memory 214412 kb
Host smart-6953381a-dbd7-47cb-8194-47fe9f2cde08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242311131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3242311131
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2592622669
Short name T1013
Test name
Test status
Simulation time 157456238 ps
CPU time 5.28 seconds
Started Aug 06 05:51:51 PM PDT 24
Finished Aug 06 05:51:56 PM PDT 24
Peak memory 206532 kb
Host smart-23dea7d5-38d7-476f-b26f-cc0feb60ac94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592622669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2592622669
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2446689310
Short name T991
Test name
Test status
Simulation time 69213513 ps
CPU time 4.68 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:10 PM PDT 24
Peak memory 206140 kb
Host smart-44ecbf73-09be-41c4-ba1d-14db3dd15263
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446689310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
446689310
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3681735022
Short name T137
Test name
Test status
Simulation time 1282416308 ps
CPU time 17.82 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:24 PM PDT 24
Peak memory 206212 kb
Host smart-03da4576-2d4a-4a97-9216-d0c2353546b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681735022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
681735022
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.790813791
Short name T951
Test name
Test status
Simulation time 17279214 ps
CPU time 1.22 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:07 PM PDT 24
Peak memory 206088 kb
Host smart-b4f9bfa0-5978-4229-b43f-7eab92704078
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790813791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.790813791
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2488836340
Short name T964
Test name
Test status
Simulation time 123938977 ps
CPU time 2.24 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:08 PM PDT 24
Peak memory 214472 kb
Host smart-b2a25f95-3fbf-4989-a47f-764f714f725d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488836340 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2488836340
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2237496603
Short name T947
Test name
Test status
Simulation time 11830119 ps
CPU time 1.01 seconds
Started Aug 06 05:52:08 PM PDT 24
Finished Aug 06 05:52:09 PM PDT 24
Peak memory 206168 kb
Host smart-e13bb81e-25b1-4e2b-accc-48b024d0fe9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237496603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2237496603
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.920234796
Short name T1047
Test name
Test status
Simulation time 10292588 ps
CPU time 0.72 seconds
Started Aug 06 05:52:09 PM PDT 24
Finished Aug 06 05:52:10 PM PDT 24
Peak memory 205992 kb
Host smart-91ecbf26-5fca-4127-b6e5-42f6addd8d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920234796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.920234796
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.823883551
Short name T1002
Test name
Test status
Simulation time 416911681 ps
CPU time 1.63 seconds
Started Aug 06 05:52:08 PM PDT 24
Finished Aug 06 05:52:10 PM PDT 24
Peak memory 206200 kb
Host smart-673873ee-576b-43e5-80c5-f4e320942e87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823883551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.823883551
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3456583162
Short name T1011
Test name
Test status
Simulation time 272699632 ps
CPU time 8.05 seconds
Started Aug 06 05:52:09 PM PDT 24
Finished Aug 06 05:52:17 PM PDT 24
Peak memory 214652 kb
Host smart-c1571b10-636f-4f80-8b08-ea26f170f712
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456583162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3456583162
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.635675772
Short name T1012
Test name
Test status
Simulation time 123299974 ps
CPU time 3.65 seconds
Started Aug 06 05:52:07 PM PDT 24
Finished Aug 06 05:52:11 PM PDT 24
Peak memory 214484 kb
Host smart-e3710ab2-5cd7-44d5-a2bc-6b6ef6775550
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635675772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.635675772
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.270093069
Short name T1008
Test name
Test status
Simulation time 57170157 ps
CPU time 1.91 seconds
Started Aug 06 05:52:29 PM PDT 24
Finished Aug 06 05:52:31 PM PDT 24
Peak memory 214508 kb
Host smart-4c2b61b3-ad60-4547-8eed-f01024439bc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270093069 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.270093069
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1164047310
Short name T963
Test name
Test status
Simulation time 12311146 ps
CPU time 0.99 seconds
Started Aug 06 05:52:26 PM PDT 24
Finished Aug 06 05:52:28 PM PDT 24
Peak memory 205948 kb
Host smart-dd5d3acf-8e8d-4857-bd40-48f978ffb78a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164047310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1164047310
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.489648800
Short name T1077
Test name
Test status
Simulation time 11394218 ps
CPU time 0.73 seconds
Started Aug 06 05:52:29 PM PDT 24
Finished Aug 06 05:52:30 PM PDT 24
Peak memory 206040 kb
Host smart-84da306d-2160-419d-b20d-dc923d77fa05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489648800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.489648800
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2582202363
Short name T129
Test name
Test status
Simulation time 92898667 ps
CPU time 2.16 seconds
Started Aug 06 05:52:29 PM PDT 24
Finished Aug 06 05:52:31 PM PDT 24
Peak memory 206172 kb
Host smart-c9526f4a-7bdf-4e5b-a436-daaa7d1cf3ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582202363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2582202363
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2189050540
Short name T926
Test name
Test status
Simulation time 37828276 ps
CPU time 1.39 seconds
Started Aug 06 05:52:26 PM PDT 24
Finished Aug 06 05:52:28 PM PDT 24
Peak memory 214652 kb
Host smart-d42168ea-8e27-4b1f-9ebf-a19ccf62589c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189050540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2189050540
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3487096011
Short name T971
Test name
Test status
Simulation time 356815193 ps
CPU time 13.55 seconds
Started Aug 06 05:52:29 PM PDT 24
Finished Aug 06 05:52:42 PM PDT 24
Peak memory 214736 kb
Host smart-adb4382c-3a33-47ef-beaa-399f3f88550a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487096011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3487096011
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.344521137
Short name T908
Test name
Test status
Simulation time 41102518 ps
CPU time 3.09 seconds
Started Aug 06 05:52:31 PM PDT 24
Finished Aug 06 05:52:34 PM PDT 24
Peak memory 217500 kb
Host smart-c372b169-1a0b-4dae-9be1-c5c4a50b0b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344521137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.344521137
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.979306498
Short name T1072
Test name
Test status
Simulation time 401325684 ps
CPU time 3.48 seconds
Started Aug 06 05:52:26 PM PDT 24
Finished Aug 06 05:52:29 PM PDT 24
Peak memory 214396 kb
Host smart-969848fa-36fa-4b9a-b801-be20efe6091f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979306498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.979306498
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3678245625
Short name T936
Test name
Test status
Simulation time 55952390 ps
CPU time 1.63 seconds
Started Aug 06 05:52:29 PM PDT 24
Finished Aug 06 05:52:30 PM PDT 24
Peak memory 217404 kb
Host smart-f3d5d02e-296f-47d4-b1b9-287d6c49acaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678245625 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3678245625
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.674866811
Short name T997
Test name
Test status
Simulation time 26468901 ps
CPU time 1.15 seconds
Started Aug 06 05:52:27 PM PDT 24
Finished Aug 06 05:52:29 PM PDT 24
Peak memory 206080 kb
Host smart-6cc0f24f-00f7-4558-a12c-dfea0ef22e6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674866811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.674866811
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.393327408
Short name T1026
Test name
Test status
Simulation time 7550802 ps
CPU time 0.7 seconds
Started Aug 06 05:52:29 PM PDT 24
Finished Aug 06 05:52:30 PM PDT 24
Peak memory 205944 kb
Host smart-ea877be7-640d-471f-b1c4-77f6ca550026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393327408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.393327408
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1064265822
Short name T1000
Test name
Test status
Simulation time 46987044 ps
CPU time 1.5 seconds
Started Aug 06 05:52:29 PM PDT 24
Finished Aug 06 05:52:31 PM PDT 24
Peak memory 206080 kb
Host smart-e42e487e-6ed9-42ab-8eac-717f1d567aca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064265822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1064265822
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1094400756
Short name T1029
Test name
Test status
Simulation time 308246335 ps
CPU time 3.54 seconds
Started Aug 06 05:52:27 PM PDT 24
Finished Aug 06 05:52:31 PM PDT 24
Peak memory 214696 kb
Host smart-7de88783-2efb-451e-9fb5-e13aa7b747c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094400756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1094400756
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.4260861254
Short name T1065
Test name
Test status
Simulation time 324133101 ps
CPU time 3.88 seconds
Started Aug 06 05:52:31 PM PDT 24
Finished Aug 06 05:52:35 PM PDT 24
Peak memory 220832 kb
Host smart-97fc2ff5-63f9-46b8-9a5c-f14eaae19e10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260861254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.4260861254
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2011787046
Short name T1016
Test name
Test status
Simulation time 191036355 ps
CPU time 2.1 seconds
Started Aug 06 05:52:27 PM PDT 24
Finished Aug 06 05:52:29 PM PDT 24
Peak memory 216496 kb
Host smart-acad6cdf-0284-4551-96c7-29b60cb87f34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011787046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2011787046
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2098905121
Short name T1054
Test name
Test status
Simulation time 190549844 ps
CPU time 2.59 seconds
Started Aug 06 05:52:27 PM PDT 24
Finished Aug 06 05:52:30 PM PDT 24
Peak memory 214408 kb
Host smart-ff7d0621-4484-4b0b-aceb-c033cd3dff02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098905121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2098905121
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2742832727
Short name T934
Test name
Test status
Simulation time 203784028 ps
CPU time 1.69 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:47 PM PDT 24
Peak memory 214484 kb
Host smart-1b51fa0a-50ff-4d25-a9b5-ce86be003f91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742832727 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2742832727
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1537787832
Short name T945
Test name
Test status
Simulation time 86603319 ps
CPU time 1.28 seconds
Started Aug 06 05:52:44 PM PDT 24
Finished Aug 06 05:52:45 PM PDT 24
Peak memory 206312 kb
Host smart-a3379e15-1b54-4d83-9f67-d218af794ae1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537787832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1537787832
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3555226375
Short name T911
Test name
Test status
Simulation time 46056925 ps
CPU time 0.85 seconds
Started Aug 06 05:52:24 PM PDT 24
Finished Aug 06 05:52:25 PM PDT 24
Peak memory 205924 kb
Host smart-241466d1-9062-4d3d-8677-8fbded87be58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555226375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3555226375
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3884525177
Short name T1028
Test name
Test status
Simulation time 139267666 ps
CPU time 2.81 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:48 PM PDT 24
Peak memory 206276 kb
Host smart-ce372439-c8c6-42b0-b577-66b185296698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884525177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3884525177
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3240899495
Short name T973
Test name
Test status
Simulation time 92494725 ps
CPU time 2.89 seconds
Started Aug 06 05:52:30 PM PDT 24
Finished Aug 06 05:52:33 PM PDT 24
Peak memory 222820 kb
Host smart-ca209d79-ed59-4fad-af23-fb8c0ed368b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240899495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3240899495
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.403921975
Short name T133
Test name
Test status
Simulation time 1293734639 ps
CPU time 9.05 seconds
Started Aug 06 05:52:31 PM PDT 24
Finished Aug 06 05:52:40 PM PDT 24
Peak memory 220804 kb
Host smart-cb4423d0-d5a2-4348-9708-5acc5f4e0b52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403921975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.403921975
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1322570
Short name T1068
Test name
Test status
Simulation time 254286595 ps
CPU time 2.37 seconds
Started Aug 06 05:52:26 PM PDT 24
Finished Aug 06 05:52:28 PM PDT 24
Peak memory 214504 kb
Host smart-16cc6cff-71e6-4900-8282-ffec0f98598f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1322570
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.96764780
Short name T148
Test name
Test status
Simulation time 215768819 ps
CPU time 8.88 seconds
Started Aug 06 05:52:31 PM PDT 24
Finished Aug 06 05:52:40 PM PDT 24
Peak memory 214432 kb
Host smart-b5e34a2d-15a8-4b42-ac87-3e78a61ed752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96764780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.96764780
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2339294792
Short name T1033
Test name
Test status
Simulation time 35530977 ps
CPU time 1.73 seconds
Started Aug 06 05:52:43 PM PDT 24
Finished Aug 06 05:52:45 PM PDT 24
Peak memory 206188 kb
Host smart-45f2af1f-3981-404b-a402-384bb5b7b6aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339294792 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2339294792
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1858510309
Short name T1027
Test name
Test status
Simulation time 30764477 ps
CPU time 0.94 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:46 PM PDT 24
Peak memory 206064 kb
Host smart-d39611de-9787-44ce-90ac-2860d3640840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858510309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1858510309
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.287274608
Short name T1015
Test name
Test status
Simulation time 34470669 ps
CPU time 0.71 seconds
Started Aug 06 05:52:44 PM PDT 24
Finished Aug 06 05:52:45 PM PDT 24
Peak memory 205996 kb
Host smart-010bcc43-7cdc-42dd-bd6d-d4673e046b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287274608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.287274608
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3494689732
Short name T969
Test name
Test status
Simulation time 457571609 ps
CPU time 3.08 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:52 PM PDT 24
Peak memory 206272 kb
Host smart-2a0b5b45-108d-4394-b247-af4d214144fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494689732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3494689732
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.739018557
Short name T1043
Test name
Test status
Simulation time 424698559 ps
CPU time 3.17 seconds
Started Aug 06 05:52:46 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 214588 kb
Host smart-28904db1-d86a-42c8-9cec-40930cdc1948
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739018557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.739018557
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1195173127
Short name T932
Test name
Test status
Simulation time 263669870 ps
CPU time 7.37 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:53 PM PDT 24
Peak memory 214664 kb
Host smart-ae591574-dd7b-42ce-a98e-2461c19ba5b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195173127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1195173127
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.75820829
Short name T1059
Test name
Test status
Simulation time 49245275 ps
CPU time 2.27 seconds
Started Aug 06 05:52:44 PM PDT 24
Finished Aug 06 05:52:46 PM PDT 24
Peak memory 214392 kb
Host smart-7969bfc4-6ad0-4c60-a4fb-770c8c43b797
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75820829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.75820829
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2324497612
Short name T160
Test name
Test status
Simulation time 165899812 ps
CPU time 4.68 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:53 PM PDT 24
Peak memory 214376 kb
Host smart-76c2c0e1-fc96-4329-9d53-643e94b98f27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324497612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2324497612
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4238628018
Short name T1035
Test name
Test status
Simulation time 45626863 ps
CPU time 1.8 seconds
Started Aug 06 05:52:44 PM PDT 24
Finished Aug 06 05:52:46 PM PDT 24
Peak memory 214476 kb
Host smart-93704b8a-c46c-474f-abb9-0fbf14988a1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238628018 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.4238628018
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.169613579
Short name T1053
Test name
Test status
Simulation time 18703730 ps
CPU time 0.91 seconds
Started Aug 06 05:52:50 PM PDT 24
Finished Aug 06 05:52:51 PM PDT 24
Peak memory 205952 kb
Host smart-f997c31c-b812-4221-951d-9d1fe0b0c4a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169613579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.169613579
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2224763385
Short name T952
Test name
Test status
Simulation time 24638609 ps
CPU time 0.87 seconds
Started Aug 06 05:52:46 PM PDT 24
Finished Aug 06 05:52:47 PM PDT 24
Peak memory 205976 kb
Host smart-d57aaea5-9bd0-4804-b927-2f1ce56a6ee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224763385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2224763385
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.913329713
Short name T1018
Test name
Test status
Simulation time 519162847 ps
CPU time 4 seconds
Started Aug 06 05:52:43 PM PDT 24
Finished Aug 06 05:52:47 PM PDT 24
Peak memory 206176 kb
Host smart-c0e642a3-9b97-4d48-8e6d-1c903d2dcac6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913329713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.913329713
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3484088774
Short name T1058
Test name
Test status
Simulation time 142375335 ps
CPU time 2.58 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:51 PM PDT 24
Peak memory 214688 kb
Host smart-5ec19b4a-a9fb-4f60-a21d-0f110244baf3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484088774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3484088774
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2156222599
Short name T1056
Test name
Test status
Simulation time 1829461524 ps
CPU time 10.2 seconds
Started Aug 06 05:52:47 PM PDT 24
Finished Aug 06 05:52:58 PM PDT 24
Peak memory 214692 kb
Host smart-acab2560-ef74-4b3d-ac3f-18f447571057
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156222599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2156222599
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2914127448
Short name T1030
Test name
Test status
Simulation time 1251667530 ps
CPU time 3.05 seconds
Started Aug 06 05:52:44 PM PDT 24
Finished Aug 06 05:52:47 PM PDT 24
Peak memory 214296 kb
Host smart-f7f40a95-adfc-4a9a-9c54-4b6dedb24000
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914127448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2914127448
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2519396683
Short name T138
Test name
Test status
Simulation time 854422818 ps
CPU time 7.39 seconds
Started Aug 06 05:52:44 PM PDT 24
Finished Aug 06 05:52:51 PM PDT 24
Peak memory 214396 kb
Host smart-5411b767-0a0d-44ab-8d4c-631722e6f5c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519396683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2519396683
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1475208015
Short name T957
Test name
Test status
Simulation time 101917521 ps
CPU time 1.9 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:47 PM PDT 24
Peak memory 214460 kb
Host smart-0e14be03-6bf2-4421-a3b1-e0a694d9dbfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475208015 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1475208015
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1221092219
Short name T965
Test name
Test status
Simulation time 18998168 ps
CPU time 0.93 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:46 PM PDT 24
Peak memory 205980 kb
Host smart-0ccc4cdd-30e2-4752-aebe-9a60f1c56d99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221092219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1221092219
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2011450684
Short name T1007
Test name
Test status
Simulation time 45252763 ps
CPU time 0.79 seconds
Started Aug 06 05:52:47 PM PDT 24
Finished Aug 06 05:52:48 PM PDT 24
Peak memory 205984 kb
Host smart-7e3742df-e4aa-434f-976a-1bebf4758956
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011450684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2011450684
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.117815629
Short name T931
Test name
Test status
Simulation time 174964976 ps
CPU time 2.58 seconds
Started Aug 06 05:52:47 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 206168 kb
Host smart-4b69c6a3-055f-4a6d-9e45-3fa6d8105e94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117815629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.117815629
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.201318954
Short name T1017
Test name
Test status
Simulation time 824761714 ps
CPU time 2.59 seconds
Started Aug 06 05:52:46 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 214720 kb
Host smart-d6c8fe77-498a-4521-bd6c-7fe783099e6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201318954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.201318954
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1380284703
Short name T1066
Test name
Test status
Simulation time 227987724 ps
CPU time 5.24 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:50 PM PDT 24
Peak memory 220636 kb
Host smart-cf4c9bb1-e0d0-4618-9224-9df768c7c958
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380284703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1380284703
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.929679607
Short name T959
Test name
Test status
Simulation time 618153548 ps
CPU time 4.66 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:50 PM PDT 24
Peak memory 216856 kb
Host smart-059e25d4-2a4b-4565-bae4-b12cb584f85c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929679607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.929679607
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1320433868
Short name T981
Test name
Test status
Simulation time 102513446 ps
CPU time 2.49 seconds
Started Aug 06 05:52:55 PM PDT 24
Finished Aug 06 05:52:58 PM PDT 24
Peak memory 214436 kb
Host smart-d36692ce-f6b9-4a22-853b-b8787f2aeb66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320433868 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1320433868
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2202298219
Short name T917
Test name
Test status
Simulation time 24058026 ps
CPU time 1.04 seconds
Started Aug 06 05:52:50 PM PDT 24
Finished Aug 06 05:52:51 PM PDT 24
Peak memory 206184 kb
Host smart-869af016-dea0-4461-af01-af631b007106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202298219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2202298219
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1407659327
Short name T1021
Test name
Test status
Simulation time 9087248 ps
CPU time 0.78 seconds
Started Aug 06 05:52:46 PM PDT 24
Finished Aug 06 05:52:47 PM PDT 24
Peak memory 205952 kb
Host smart-078f1f56-6e3c-4383-b7c6-a5992ca51d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407659327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1407659327
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.244543125
Short name T1014
Test name
Test status
Simulation time 65867351 ps
CPU time 1.87 seconds
Started Aug 06 05:52:46 PM PDT 24
Finished Aug 06 05:52:48 PM PDT 24
Peak memory 206080 kb
Host smart-872c024c-3ba2-4eae-8198-8ae7d3dba56f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244543125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.244543125
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.257480523
Short name T114
Test name
Test status
Simulation time 131229186 ps
CPU time 2.15 seconds
Started Aug 06 05:52:50 PM PDT 24
Finished Aug 06 05:52:52 PM PDT 24
Peak memory 214768 kb
Host smart-38cf354a-aed4-496d-b9dc-b694410c628a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257480523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.257480523
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.193275166
Short name T996
Test name
Test status
Simulation time 545807520 ps
CPU time 6.61 seconds
Started Aug 06 05:52:47 PM PDT 24
Finished Aug 06 05:52:54 PM PDT 24
Peak memory 214648 kb
Host smart-f86697d2-670b-48af-b605-e535ac73f66f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193275166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.193275166
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4290588522
Short name T1055
Test name
Test status
Simulation time 250314926 ps
CPU time 4.35 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:50 PM PDT 24
Peak memory 217504 kb
Host smart-209284b8-f176-4d47-804c-9b3c68260cc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290588522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4290588522
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4115081496
Short name T1032
Test name
Test status
Simulation time 46870221 ps
CPU time 1.35 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 206188 kb
Host smart-8552c042-29d6-4fd6-bd3e-5822c695a7f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115081496 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.4115081496
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2284493729
Short name T992
Test name
Test status
Simulation time 144042562 ps
CPU time 1.54 seconds
Started Aug 06 05:52:47 PM PDT 24
Finished Aug 06 05:52:48 PM PDT 24
Peak memory 206156 kb
Host smart-799a98c0-0cc7-4a92-a391-d658219f7888
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284493729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2284493729
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2969956088
Short name T919
Test name
Test status
Simulation time 32691037 ps
CPU time 0.69 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 206008 kb
Host smart-536d584e-0245-4029-ac60-fc4a6858fd19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969956088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2969956088
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.487852565
Short name T953
Test name
Test status
Simulation time 80271755 ps
CPU time 1.62 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:47 PM PDT 24
Peak memory 206248 kb
Host smart-3a3f892c-fe64-4be1-bb66-246ab94f38e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487852565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.487852565
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3334677666
Short name T983
Test name
Test status
Simulation time 337684999 ps
CPU time 2.63 seconds
Started Aug 06 05:52:44 PM PDT 24
Finished Aug 06 05:52:47 PM PDT 24
Peak memory 214532 kb
Host smart-e4ff581b-a43f-4522-8248-14af4bad3d69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334677666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3334677666
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3368312095
Short name T976
Test name
Test status
Simulation time 195840158 ps
CPU time 5.72 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:51 PM PDT 24
Peak memory 214696 kb
Host smart-2fc502eb-5501-4084-852b-ee5d854998ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368312095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3368312095
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4284940454
Short name T1051
Test name
Test status
Simulation time 197282367 ps
CPU time 2.38 seconds
Started Aug 06 05:52:49 PM PDT 24
Finished Aug 06 05:52:51 PM PDT 24
Peak memory 217588 kb
Host smart-c6f032c1-42f5-47a0-97a8-c7f7588f8bd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284940454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4284940454
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1297243594
Short name T998
Test name
Test status
Simulation time 233764436 ps
CPU time 3.85 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 215284 kb
Host smart-ed49acbf-bb35-4955-b00e-1d77034b819c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297243594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1297243594
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1877757669
Short name T928
Test name
Test status
Simulation time 57820223 ps
CPU time 2.11 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:50 PM PDT 24
Peak memory 214492 kb
Host smart-8321e941-ec80-410f-abd1-f25e481eb29c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877757669 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1877757669
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.50693109
Short name T948
Test name
Test status
Simulation time 11422618 ps
CPU time 1.04 seconds
Started Aug 06 05:52:50 PM PDT 24
Finished Aug 06 05:52:51 PM PDT 24
Peak memory 206176 kb
Host smart-510949fb-6ba1-4d84-831d-84d12c4cf41c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50693109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.50693109
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2509996398
Short name T1069
Test name
Test status
Simulation time 8366511 ps
CPU time 0.82 seconds
Started Aug 06 05:52:50 PM PDT 24
Finished Aug 06 05:52:51 PM PDT 24
Peak memory 205944 kb
Host smart-91f610f9-7411-4b95-981f-b52ac17575bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509996398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2509996398
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2787029506
Short name T960
Test name
Test status
Simulation time 115778278 ps
CPU time 1.95 seconds
Started Aug 06 05:52:50 PM PDT 24
Finished Aug 06 05:52:52 PM PDT 24
Peak memory 206272 kb
Host smart-a602aa75-003f-4ac7-bd54-34c94df4bf0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787029506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2787029506
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1323137894
Short name T940
Test name
Test status
Simulation time 46263715 ps
CPU time 1.7 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:50 PM PDT 24
Peak memory 214736 kb
Host smart-6b5458d5-1771-41c7-b578-9c951c423b00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323137894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1323137894
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.203382831
Short name T115
Test name
Test status
Simulation time 1543803609 ps
CPU time 8.08 seconds
Started Aug 06 05:52:46 PM PDT 24
Finished Aug 06 05:52:55 PM PDT 24
Peak memory 214760 kb
Host smart-71fdd493-31f4-41cb-b903-78183a5f6ff8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203382831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.203382831
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1105604389
Short name T1004
Test name
Test status
Simulation time 268164163 ps
CPU time 2.98 seconds
Started Aug 06 05:52:51 PM PDT 24
Finished Aug 06 05:52:54 PM PDT 24
Peak memory 215556 kb
Host smart-2fde4045-1ed4-4ac0-8e3e-803510b8a017
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105604389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1105604389
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2456755028
Short name T962
Test name
Test status
Simulation time 50305738 ps
CPU time 1.16 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:50 PM PDT 24
Peak memory 206328 kb
Host smart-73a38626-bc84-467a-ad5c-8118d777b291
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456755028 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2456755028
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.473946387
Short name T939
Test name
Test status
Simulation time 26077289 ps
CPU time 1.29 seconds
Started Aug 06 05:52:47 PM PDT 24
Finished Aug 06 05:52:48 PM PDT 24
Peak memory 206160 kb
Host smart-28d59cab-1e54-437a-bdba-3680e9f723c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473946387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.473946387
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2673377014
Short name T944
Test name
Test status
Simulation time 45762630 ps
CPU time 0.85 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 205964 kb
Host smart-e4747801-4047-4ec6-9590-68c62c9d2bc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673377014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2673377014
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.556141771
Short name T1052
Test name
Test status
Simulation time 24070488 ps
CPU time 1.47 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 206132 kb
Host smart-33886405-9a58-4f1b-b93a-56fb174c1dda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556141771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.556141771
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.362585260
Short name T1045
Test name
Test status
Simulation time 68572023 ps
CPU time 1.71 seconds
Started Aug 06 05:52:44 PM PDT 24
Finished Aug 06 05:52:46 PM PDT 24
Peak memory 214600 kb
Host smart-8c98a740-dda3-4dbd-a21c-14b906486fe3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362585260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.362585260
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1928364229
Short name T967
Test name
Test status
Simulation time 1657370910 ps
CPU time 14.94 seconds
Started Aug 06 05:52:43 PM PDT 24
Finished Aug 06 05:52:58 PM PDT 24
Peak memory 214700 kb
Host smart-49fc54d7-d2ef-4d59-bc5b-0fb47662f2fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928364229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1928364229
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3295190593
Short name T968
Test name
Test status
Simulation time 286829190 ps
CPU time 2.03 seconds
Started Aug 06 05:52:49 PM PDT 24
Finished Aug 06 05:52:51 PM PDT 24
Peak memory 214564 kb
Host smart-3d02df90-06d1-468b-985b-80930530eebd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295190593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3295190593
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.760234077
Short name T142
Test name
Test status
Simulation time 1007455151 ps
CPU time 6.66 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:55 PM PDT 24
Peak memory 206156 kb
Host smart-6e91905d-29e7-4709-b8e4-f2929f8629af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760234077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.760234077
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1802587972
Short name T1049
Test name
Test status
Simulation time 197390606 ps
CPU time 4.63 seconds
Started Aug 06 05:52:07 PM PDT 24
Finished Aug 06 05:52:12 PM PDT 24
Peak memory 206172 kb
Host smart-7867f65b-2da2-47e8-a0ee-230bd700a26b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802587972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
802587972
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2810030720
Short name T1041
Test name
Test status
Simulation time 2303231198 ps
CPU time 19.08 seconds
Started Aug 06 05:52:04 PM PDT 24
Finished Aug 06 05:52:24 PM PDT 24
Peak memory 206284 kb
Host smart-f9e2b14e-20fb-45a8-9efd-cf071ac20d4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810030720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
810030720
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2744846754
Short name T1050
Test name
Test status
Simulation time 69415575 ps
CPU time 1.11 seconds
Started Aug 06 05:52:07 PM PDT 24
Finished Aug 06 05:52:09 PM PDT 24
Peak memory 206180 kb
Host smart-5563601c-ca4c-4337-98d9-aa926458b280
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744846754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
744846754
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1184131843
Short name T930
Test name
Test status
Simulation time 168235554 ps
CPU time 1.52 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:08 PM PDT 24
Peak memory 206260 kb
Host smart-46648f52-d151-4a30-a8c2-70f8652ff045
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184131843 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1184131843
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.206507404
Short name T131
Test name
Test status
Simulation time 138328293 ps
CPU time 1.23 seconds
Started Aug 06 05:52:05 PM PDT 24
Finished Aug 06 05:52:07 PM PDT 24
Peak memory 206292 kb
Host smart-523c4c44-8a14-447f-87f3-5022f22bbaf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206507404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.206507404
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1237231687
Short name T925
Test name
Test status
Simulation time 10777921 ps
CPU time 0.71 seconds
Started Aug 06 05:52:05 PM PDT 24
Finished Aug 06 05:52:06 PM PDT 24
Peak memory 205888 kb
Host smart-c669a160-39c6-4b08-af16-d0ada619bc00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237231687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1237231687
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3350699213
Short name T954
Test name
Test status
Simulation time 73274016 ps
CPU time 2 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:08 PM PDT 24
Peak memory 206164 kb
Host smart-486be308-09e1-4883-9a5d-b5eea16e857e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350699213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3350699213
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1877408228
Short name T113
Test name
Test status
Simulation time 101681730 ps
CPU time 2.09 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:08 PM PDT 24
Peak memory 214600 kb
Host smart-c9546ab5-f68f-471f-9975-26dd6b4876a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877408228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1877408228
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.319257044
Short name T1064
Test name
Test status
Simulation time 167096029 ps
CPU time 7.4 seconds
Started Aug 06 05:52:07 PM PDT 24
Finished Aug 06 05:52:14 PM PDT 24
Peak memory 220908 kb
Host smart-81abb504-32cb-4ba7-9f6b-1e4f7be1984f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319257044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.319257044
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1338358312
Short name T988
Test name
Test status
Simulation time 50755161 ps
CPU time 1.52 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:08 PM PDT 24
Peak memory 214596 kb
Host smart-7388b2c3-526c-48f0-92a0-f01a7f397c6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338358312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1338358312
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1507364953
Short name T989
Test name
Test status
Simulation time 39597069 ps
CPU time 0.68 seconds
Started Aug 06 05:52:49 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 205944 kb
Host smart-8889c27b-caf4-4ce1-a82c-5b4935bf1df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507364953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1507364953
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3059401259
Short name T913
Test name
Test status
Simulation time 16195190 ps
CPU time 0.68 seconds
Started Aug 06 05:52:50 PM PDT 24
Finished Aug 06 05:52:50 PM PDT 24
Peak memory 205868 kb
Host smart-b6d6c9d4-b4d0-4787-b92a-1acf6c7fa20b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059401259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3059401259
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3706323479
Short name T912
Test name
Test status
Simulation time 22332134 ps
CPU time 0.74 seconds
Started Aug 06 05:52:50 PM PDT 24
Finished Aug 06 05:52:51 PM PDT 24
Peak memory 205980 kb
Host smart-e1a0736c-2b65-4f4b-90e9-7b3382eb8461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706323479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3706323479
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.402648856
Short name T941
Test name
Test status
Simulation time 47048718 ps
CPU time 0.73 seconds
Started Aug 06 05:52:47 PM PDT 24
Finished Aug 06 05:52:48 PM PDT 24
Peak memory 205880 kb
Host smart-d85e5401-4613-4e98-a76c-891d7227eacf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402648856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.402648856
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.193196067
Short name T1070
Test name
Test status
Simulation time 21102412 ps
CPU time 0.8 seconds
Started Aug 06 05:52:49 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 205872 kb
Host smart-7305e4f7-dba6-48c7-baae-c9cbe5c0f29b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193196067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.193196067
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3420086827
Short name T942
Test name
Test status
Simulation time 11830491 ps
CPU time 0.85 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 205992 kb
Host smart-7c40bb59-96f7-45b1-a4e6-639dc1226fe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420086827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3420086827
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2905823566
Short name T924
Test name
Test status
Simulation time 17372720 ps
CPU time 0.69 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:48 PM PDT 24
Peak memory 205908 kb
Host smart-2793535c-a239-473d-8e2d-96a0bc5ab3a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905823566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2905823566
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3211450855
Short name T1081
Test name
Test status
Simulation time 10823724 ps
CPU time 0.77 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 205968 kb
Host smart-a8be5518-6de0-48f7-a398-69140f4c9ea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211450855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3211450855
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1598102601
Short name T950
Test name
Test status
Simulation time 42543978 ps
CPU time 0.73 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:46 PM PDT 24
Peak memory 205908 kb
Host smart-5e044701-d38b-445e-98ae-5667325abde4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598102601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1598102601
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1083465652
Short name T920
Test name
Test status
Simulation time 24216882 ps
CPU time 0.79 seconds
Started Aug 06 05:52:55 PM PDT 24
Finished Aug 06 05:52:56 PM PDT 24
Peak memory 205940 kb
Host smart-19d54252-dea6-4c77-993c-4affbf8d3fa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083465652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1083465652
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1863200047
Short name T1024
Test name
Test status
Simulation time 127481174 ps
CPU time 8.02 seconds
Started Aug 06 05:52:05 PM PDT 24
Finished Aug 06 05:52:14 PM PDT 24
Peak memory 206108 kb
Host smart-f5f5ec02-044d-4415-98fd-a9b8ab0d6bad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863200047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
863200047
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3679651929
Short name T999
Test name
Test status
Simulation time 960566974 ps
CPU time 14.09 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:20 PM PDT 24
Peak memory 206280 kb
Host smart-fa2ffa29-5df4-4f49-93cf-a56410416ee6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679651929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
679651929
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1184252817
Short name T1038
Test name
Test status
Simulation time 22138566 ps
CPU time 1 seconds
Started Aug 06 05:52:07 PM PDT 24
Finished Aug 06 05:52:08 PM PDT 24
Peak memory 206184 kb
Host smart-75cf8a69-e8a4-4590-b8e1-3881b0c48cba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184252817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
184252817
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.682350667
Short name T1023
Test name
Test status
Simulation time 44656529 ps
CPU time 1.53 seconds
Started Aug 06 05:52:10 PM PDT 24
Finished Aug 06 05:52:12 PM PDT 24
Peak memory 214492 kb
Host smart-00b8885c-da89-4c2a-a87e-67ce2f647efb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682350667 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.682350667
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2345794342
Short name T1003
Test name
Test status
Simulation time 13281111 ps
CPU time 1.04 seconds
Started Aug 06 05:52:08 PM PDT 24
Finished Aug 06 05:52:09 PM PDT 24
Peak memory 206212 kb
Host smart-a2f009ea-1dea-4da4-a857-46dc9b62b0b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345794342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2345794342
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.117930537
Short name T916
Test name
Test status
Simulation time 22949052 ps
CPU time 0.68 seconds
Started Aug 06 05:52:08 PM PDT 24
Finished Aug 06 05:52:09 PM PDT 24
Peak memory 205912 kb
Host smart-0814dfb5-7780-4322-9fc6-8bd8d3da7849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117930537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.117930537
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4282618914
Short name T134
Test name
Test status
Simulation time 232154917 ps
CPU time 3.77 seconds
Started Aug 06 05:52:08 PM PDT 24
Finished Aug 06 05:52:11 PM PDT 24
Peak memory 206172 kb
Host smart-639f7bbc-5d52-4bc0-a45b-fa1d34a067e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282618914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.4282618914
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.496853418
Short name T1036
Test name
Test status
Simulation time 555472302 ps
CPU time 2.24 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:08 PM PDT 24
Peak memory 214696 kb
Host smart-cb2df02e-fd9d-44a0-9c57-f3244428586f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496853418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.496853418
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1992711337
Short name T977
Test name
Test status
Simulation time 1564330536 ps
CPU time 14.56 seconds
Started Aug 06 05:52:08 PM PDT 24
Finished Aug 06 05:52:23 PM PDT 24
Peak memory 214668 kb
Host smart-0b093719-33c9-40b2-8247-a927f9231b13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992711337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1992711337
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2924029332
Short name T1060
Test name
Test status
Simulation time 291643589 ps
CPU time 2.63 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:09 PM PDT 24
Peak memory 214444 kb
Host smart-23fa941b-22c1-4e6e-a64f-f1be9dc9a5c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924029332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2924029332
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.435021198
Short name T1078
Test name
Test status
Simulation time 270774254 ps
CPU time 4.13 seconds
Started Aug 06 05:52:08 PM PDT 24
Finished Aug 06 05:52:12 PM PDT 24
Peak memory 214408 kb
Host smart-722f09fe-a5c2-47dc-881c-7e6db9947b62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435021198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
435021198
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3205966023
Short name T1067
Test name
Test status
Simulation time 28105424 ps
CPU time 0.71 seconds
Started Aug 06 05:52:55 PM PDT 24
Finished Aug 06 05:52:56 PM PDT 24
Peak memory 205940 kb
Host smart-5efec0dc-2883-46fc-89ba-eb8d9ae426ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205966023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3205966023
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.644928156
Short name T1076
Test name
Test status
Simulation time 136599775 ps
CPU time 0.73 seconds
Started Aug 06 05:52:49 PM PDT 24
Finished Aug 06 05:52:50 PM PDT 24
Peak memory 205964 kb
Host smart-e5a9c9b4-5d09-4018-9c56-6b9613436246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644928156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.644928156
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3889236467
Short name T921
Test name
Test status
Simulation time 17790884 ps
CPU time 0.71 seconds
Started Aug 06 05:52:48 PM PDT 24
Finished Aug 06 05:52:49 PM PDT 24
Peak memory 205968 kb
Host smart-4648ff98-e279-4e79-93bf-2afb17901dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889236467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3889236467
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3653733540
Short name T1046
Test name
Test status
Simulation time 19282747 ps
CPU time 0.94 seconds
Started Aug 06 05:52:49 PM PDT 24
Finished Aug 06 05:52:50 PM PDT 24
Peak memory 206088 kb
Host smart-74ff8912-8d77-42ea-a587-0b89210c5632
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653733540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3653733540
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2843871124
Short name T1042
Test name
Test status
Simulation time 10165386 ps
CPU time 0.74 seconds
Started Aug 06 05:52:49 PM PDT 24
Finished Aug 06 05:52:50 PM PDT 24
Peak memory 205996 kb
Host smart-e0b38661-4387-4377-850e-d7f73f59e92b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843871124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2843871124
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.233529913
Short name T1039
Test name
Test status
Simulation time 12194130 ps
CPU time 0.89 seconds
Started Aug 06 05:52:55 PM PDT 24
Finished Aug 06 05:52:56 PM PDT 24
Peak memory 205944 kb
Host smart-573f94fc-53f4-4de8-aacc-06aa737d3fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233529913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.233529913
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2854899361
Short name T1031
Test name
Test status
Simulation time 25065648 ps
CPU time 0.75 seconds
Started Aug 06 05:52:55 PM PDT 24
Finished Aug 06 05:52:56 PM PDT 24
Peak memory 205864 kb
Host smart-7f2b9423-a1a8-41e9-bb02-74f5a39f2a45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854899361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2854899361
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2791171665
Short name T927
Test name
Test status
Simulation time 17669718 ps
CPU time 0.91 seconds
Started Aug 06 05:52:45 PM PDT 24
Finished Aug 06 05:52:46 PM PDT 24
Peak memory 206056 kb
Host smart-fc09f50e-b0ae-42f9-b37b-d5dc9b13082e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791171665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2791171665
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2152270511
Short name T974
Test name
Test status
Simulation time 9853378 ps
CPU time 0.86 seconds
Started Aug 06 05:52:49 PM PDT 24
Finished Aug 06 05:52:50 PM PDT 24
Peak memory 205968 kb
Host smart-8e451189-2420-444d-9b00-b1334fce0cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152270511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2152270511
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.282015307
Short name T1040
Test name
Test status
Simulation time 61762291 ps
CPU time 0.73 seconds
Started Aug 06 05:53:07 PM PDT 24
Finished Aug 06 05:53:08 PM PDT 24
Peak memory 205924 kb
Host smart-405d0276-dc3c-4f64-9e68-ea81927f8fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282015307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.282015307
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2013011036
Short name T978
Test name
Test status
Simulation time 2043158890 ps
CPU time 12.99 seconds
Started Aug 06 05:52:10 PM PDT 24
Finished Aug 06 05:52:23 PM PDT 24
Peak memory 206228 kb
Host smart-7ec19ff1-952d-4f23-a3fa-a9e55bb04b5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013011036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
013011036
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.414421373
Short name T1010
Test name
Test status
Simulation time 1005978885 ps
CPU time 14.82 seconds
Started Aug 06 05:52:13 PM PDT 24
Finished Aug 06 05:52:28 PM PDT 24
Peak memory 206208 kb
Host smart-ef7cb1c6-3211-4581-aee3-c153fb5b2eff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414421373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.414421373
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2203514357
Short name T929
Test name
Test status
Simulation time 69791410 ps
CPU time 0.91 seconds
Started Aug 06 05:52:09 PM PDT 24
Finished Aug 06 05:52:10 PM PDT 24
Peak memory 206032 kb
Host smart-86dfe73d-51f1-4fcc-afb5-27cfc578efac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203514357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
203514357
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3048153899
Short name T982
Test name
Test status
Simulation time 56824386 ps
CPU time 1.42 seconds
Started Aug 06 05:52:10 PM PDT 24
Finished Aug 06 05:52:12 PM PDT 24
Peak memory 206280 kb
Host smart-81490d2d-8478-42de-98f4-c675d78ec40c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048153899 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3048153899
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.69912497
Short name T961
Test name
Test status
Simulation time 56939025 ps
CPU time 1.11 seconds
Started Aug 06 05:52:10 PM PDT 24
Finished Aug 06 05:52:11 PM PDT 24
Peak memory 206104 kb
Host smart-a4cfa87d-fecd-44ed-8902-bd211aeed680
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69912497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.69912497
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3473284614
Short name T1080
Test name
Test status
Simulation time 17447869 ps
CPU time 0.71 seconds
Started Aug 06 05:52:08 PM PDT 24
Finished Aug 06 05:52:08 PM PDT 24
Peak memory 205876 kb
Host smart-8028a20f-2fb4-4e41-8da8-fac0b6851f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473284614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3473284614
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2828608047
Short name T1005
Test name
Test status
Simulation time 51702250 ps
CPU time 2.09 seconds
Started Aug 06 05:52:08 PM PDT 24
Finished Aug 06 05:52:10 PM PDT 24
Peak memory 206140 kb
Host smart-2f400a10-0e4d-4f19-9b9f-8e2f439de9b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828608047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2828608047
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2059420406
Short name T111
Test name
Test status
Simulation time 209420206 ps
CPU time 3.21 seconds
Started Aug 06 05:52:06 PM PDT 24
Finished Aug 06 05:52:09 PM PDT 24
Peak memory 214592 kb
Host smart-b1e68871-6d6e-4563-b506-489e9c54089a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059420406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2059420406
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3282067299
Short name T970
Test name
Test status
Simulation time 1363709955 ps
CPU time 12.87 seconds
Started Aug 06 05:52:10 PM PDT 24
Finished Aug 06 05:52:23 PM PDT 24
Peak memory 214724 kb
Host smart-4262f0cd-6606-4b86-ac1d-8d9290ad6d7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282067299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3282067299
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.716681554
Short name T1073
Test name
Test status
Simulation time 148979927 ps
CPU time 2.79 seconds
Started Aug 06 05:52:09 PM PDT 24
Finished Aug 06 05:52:12 PM PDT 24
Peak memory 214444 kb
Host smart-4569f138-5697-4865-837b-07bb35b21f08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716681554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.716681554
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1766259450
Short name T918
Test name
Test status
Simulation time 172501614 ps
CPU time 0.79 seconds
Started Aug 06 05:53:05 PM PDT 24
Finished Aug 06 05:53:06 PM PDT 24
Peak memory 205996 kb
Host smart-b7852f06-6b97-4172-b51d-806937cddecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766259450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1766259450
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.378665183
Short name T980
Test name
Test status
Simulation time 69236227 ps
CPU time 0.78 seconds
Started Aug 06 05:53:06 PM PDT 24
Finished Aug 06 05:53:07 PM PDT 24
Peak memory 205952 kb
Host smart-5a079277-fb21-48b3-bb45-d03374dc9666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378665183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.378665183
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.995931445
Short name T1063
Test name
Test status
Simulation time 10235882 ps
CPU time 0.83 seconds
Started Aug 06 05:53:05 PM PDT 24
Finished Aug 06 05:53:06 PM PDT 24
Peak memory 205804 kb
Host smart-05d77196-5b82-4606-9a2a-87ef78f93339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995931445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.995931445
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.168625086
Short name T1071
Test name
Test status
Simulation time 42032868 ps
CPU time 0.81 seconds
Started Aug 06 05:53:08 PM PDT 24
Finished Aug 06 05:53:09 PM PDT 24
Peak memory 205900 kb
Host smart-a60e68f3-0b8e-4db9-95a4-4444c41bc51c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168625086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.168625086
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.870210523
Short name T995
Test name
Test status
Simulation time 18021465 ps
CPU time 0.74 seconds
Started Aug 06 05:53:08 PM PDT 24
Finished Aug 06 05:53:09 PM PDT 24
Peak memory 205956 kb
Host smart-85dcb2a2-1b0a-43a4-965b-0dd2848e832c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870210523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.870210523
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1358865614
Short name T933
Test name
Test status
Simulation time 25981021 ps
CPU time 0.68 seconds
Started Aug 06 05:53:06 PM PDT 24
Finished Aug 06 05:53:07 PM PDT 24
Peak memory 205780 kb
Host smart-acdad5df-4379-4908-85fc-3ac02f608612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358865614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1358865614
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1633180268
Short name T1057
Test name
Test status
Simulation time 12372886 ps
CPU time 0.72 seconds
Started Aug 06 05:53:11 PM PDT 24
Finished Aug 06 05:53:12 PM PDT 24
Peak memory 205976 kb
Host smart-97f9576f-6adb-4321-b5a0-9fb06e6346cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633180268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1633180268
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1882505085
Short name T914
Test name
Test status
Simulation time 12782524 ps
CPU time 0.85 seconds
Started Aug 06 05:53:07 PM PDT 24
Finished Aug 06 05:53:08 PM PDT 24
Peak memory 205944 kb
Host smart-d25ea7a2-835c-4558-8b8c-c9c81bc6be37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882505085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1882505085
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3569588008
Short name T985
Test name
Test status
Simulation time 11457374 ps
CPU time 0.87 seconds
Started Aug 06 05:53:10 PM PDT 24
Finished Aug 06 05:53:11 PM PDT 24
Peak memory 205932 kb
Host smart-3ea28241-d3ef-44ea-b776-f9b90bdfadb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569588008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3569588008
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1571031857
Short name T956
Test name
Test status
Simulation time 8649348 ps
CPU time 0.78 seconds
Started Aug 06 05:53:05 PM PDT 24
Finished Aug 06 05:53:06 PM PDT 24
Peak memory 205952 kb
Host smart-292e17fb-2898-4047-bdbc-a21ac17128c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571031857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1571031857
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3234444592
Short name T1009
Test name
Test status
Simulation time 43505935 ps
CPU time 1.38 seconds
Started Aug 06 05:52:13 PM PDT 24
Finished Aug 06 05:52:14 PM PDT 24
Peak memory 214424 kb
Host smart-940137dc-3e5e-4013-afb6-284b86f49911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234444592 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3234444592
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1084078249
Short name T987
Test name
Test status
Simulation time 12922370 ps
CPU time 1.12 seconds
Started Aug 06 05:52:11 PM PDT 24
Finished Aug 06 05:52:12 PM PDT 24
Peak memory 206108 kb
Host smart-84674d23-86dc-41c2-9eb5-9acd68b4f416
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084078249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1084078249
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2778818329
Short name T1025
Test name
Test status
Simulation time 22266215 ps
CPU time 0.73 seconds
Started Aug 06 05:52:10 PM PDT 24
Finished Aug 06 05:52:10 PM PDT 24
Peak memory 206016 kb
Host smart-20b93e6f-aac4-448b-941e-eb6e5355336e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778818329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2778818329
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4194081925
Short name T946
Test name
Test status
Simulation time 43856311 ps
CPU time 1.74 seconds
Started Aug 06 05:52:13 PM PDT 24
Finished Aug 06 05:52:15 PM PDT 24
Peak memory 206260 kb
Host smart-dc471ed3-54c5-45af-b291-8e75d4048ff8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194081925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4194081925
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.247807134
Short name T1079
Test name
Test status
Simulation time 509846267 ps
CPU time 3.14 seconds
Started Aug 06 05:52:13 PM PDT 24
Finished Aug 06 05:52:16 PM PDT 24
Peak memory 214732 kb
Host smart-5cc673cd-6c3d-4896-bf12-56724137da0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247807134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.247807134
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2291319156
Short name T1037
Test name
Test status
Simulation time 93360428 ps
CPU time 3.96 seconds
Started Aug 06 05:52:13 PM PDT 24
Finished Aug 06 05:52:17 PM PDT 24
Peak memory 214692 kb
Host smart-332d12ac-1a93-4906-8d92-48d556a458a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291319156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2291319156
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1495215745
Short name T909
Test name
Test status
Simulation time 394548680 ps
CPU time 3.35 seconds
Started Aug 06 05:52:12 PM PDT 24
Finished Aug 06 05:52:15 PM PDT 24
Peak memory 215328 kb
Host smart-55c1acaa-4fcf-4201-8e26-29333ea08db2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495215745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1495215745
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1281056589
Short name T151
Test name
Test status
Simulation time 260726894 ps
CPU time 5.91 seconds
Started Aug 06 05:52:11 PM PDT 24
Finished Aug 06 05:52:17 PM PDT 24
Peak memory 214392 kb
Host smart-da6af950-df4a-4684-9f84-d0983d7201ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281056589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1281056589
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.197357191
Short name T1019
Test name
Test status
Simulation time 126536406 ps
CPU time 1.1 seconds
Started Aug 06 05:52:26 PM PDT 24
Finished Aug 06 05:52:28 PM PDT 24
Peak memory 206036 kb
Host smart-ae8a9183-57fc-4c22-99d0-c15b50688dff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197357191 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.197357191
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3835547652
Short name T1020
Test name
Test status
Simulation time 72623401 ps
CPU time 0.92 seconds
Started Aug 06 05:52:27 PM PDT 24
Finished Aug 06 05:52:28 PM PDT 24
Peak memory 205948 kb
Host smart-32b607c3-7e47-42ca-931d-035fd5fa3b40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835547652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3835547652
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3998132737
Short name T923
Test name
Test status
Simulation time 26994475 ps
CPU time 0.69 seconds
Started Aug 06 05:52:26 PM PDT 24
Finished Aug 06 05:52:27 PM PDT 24
Peak memory 205896 kb
Host smart-80e51625-c686-4f01-9c74-d81561f18648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998132737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3998132737
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.879832161
Short name T990
Test name
Test status
Simulation time 22692186 ps
CPU time 1.45 seconds
Started Aug 06 05:52:31 PM PDT 24
Finished Aug 06 05:52:32 PM PDT 24
Peak memory 206052 kb
Host smart-d20e8cb8-453e-44b8-adb5-42a5c4ac58cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879832161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.879832161
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2053196552
Short name T984
Test name
Test status
Simulation time 228273922 ps
CPU time 4.15 seconds
Started Aug 06 05:52:10 PM PDT 24
Finished Aug 06 05:52:14 PM PDT 24
Peak memory 214700 kb
Host smart-b7f1d4c4-f854-492e-830d-9f8f74a6ede3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053196552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2053196552
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1811440780
Short name T112
Test name
Test status
Simulation time 505292509 ps
CPU time 6.8 seconds
Started Aug 06 05:52:09 PM PDT 24
Finished Aug 06 05:52:16 PM PDT 24
Peak memory 214692 kb
Host smart-7040757d-b179-4bd1-8caf-100cbb8c5f96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811440780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1811440780
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2422017061
Short name T955
Test name
Test status
Simulation time 92930473 ps
CPU time 2.74 seconds
Started Aug 06 05:52:29 PM PDT 24
Finished Aug 06 05:52:31 PM PDT 24
Peak memory 214480 kb
Host smart-6e6c6dd3-5505-4f73-a321-2a69af540801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422017061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2422017061
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1064840906
Short name T1062
Test name
Test status
Simulation time 27686268 ps
CPU time 1.46 seconds
Started Aug 06 05:52:26 PM PDT 24
Finished Aug 06 05:52:28 PM PDT 24
Peak memory 206300 kb
Host smart-c64e3a8c-864f-41b5-9d3e-1759f3e2ec9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064840906 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1064840906
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3766790418
Short name T949
Test name
Test status
Simulation time 103866299 ps
CPU time 1.03 seconds
Started Aug 06 05:52:26 PM PDT 24
Finished Aug 06 05:52:27 PM PDT 24
Peak memory 206200 kb
Host smart-95d7cc0d-51c8-4587-8b93-622ab9a73ad8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766790418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3766790418
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3997674901
Short name T958
Test name
Test status
Simulation time 39171571 ps
CPU time 0.81 seconds
Started Aug 06 05:52:28 PM PDT 24
Finished Aug 06 05:52:29 PM PDT 24
Peak memory 205896 kb
Host smart-822a74dd-8a88-4856-a2c3-09691e5f2660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997674901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3997674901
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1860581499
Short name T1001
Test name
Test status
Simulation time 316817500 ps
CPU time 2.39 seconds
Started Aug 06 05:52:29 PM PDT 24
Finished Aug 06 05:52:31 PM PDT 24
Peak memory 206152 kb
Host smart-fa433735-41e8-478b-9c3d-2651abd6674a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860581499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1860581499
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3897536287
Short name T116
Test name
Test status
Simulation time 80723644 ps
CPU time 2.02 seconds
Started Aug 06 05:52:28 PM PDT 24
Finished Aug 06 05:52:30 PM PDT 24
Peak memory 214752 kb
Host smart-5e64637b-0eb3-484e-8754-5445d10c5fe6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897536287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3897536287
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3210826517
Short name T1044
Test name
Test status
Simulation time 50654562 ps
CPU time 3.24 seconds
Started Aug 06 05:52:24 PM PDT 24
Finished Aug 06 05:52:27 PM PDT 24
Peak memory 214504 kb
Host smart-6d951e0e-a35b-4c0d-8d68-405f40838f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210826517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3210826517
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1367825548
Short name T979
Test name
Test status
Simulation time 67993122 ps
CPU time 1.12 seconds
Started Aug 06 05:52:28 PM PDT 24
Finished Aug 06 05:52:29 PM PDT 24
Peak memory 206264 kb
Host smart-e5a16bed-6dd8-4945-a881-b49a47e81fd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367825548 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1367825548
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3143637137
Short name T135
Test name
Test status
Simulation time 13836831 ps
CPU time 1.07 seconds
Started Aug 06 05:52:26 PM PDT 24
Finished Aug 06 05:52:28 PM PDT 24
Peak memory 206092 kb
Host smart-96893bfc-c2e4-4d79-9339-e076c855813a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143637137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3143637137
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4032175559
Short name T1061
Test name
Test status
Simulation time 46852001 ps
CPU time 0.73 seconds
Started Aug 06 05:52:27 PM PDT 24
Finished Aug 06 05:52:28 PM PDT 24
Peak memory 205904 kb
Host smart-0a4ef68d-ecea-41f2-b4e7-0e18bb55165f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032175559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4032175559
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3405086634
Short name T994
Test name
Test status
Simulation time 93598713 ps
CPU time 2.05 seconds
Started Aug 06 05:52:30 PM PDT 24
Finished Aug 06 05:52:32 PM PDT 24
Peak memory 206164 kb
Host smart-f5c3ac66-e018-4f70-94fd-fbb57e505765
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405086634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3405086634
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2776881507
Short name T1075
Test name
Test status
Simulation time 586616537 ps
CPU time 4.08 seconds
Started Aug 06 05:52:28 PM PDT 24
Finished Aug 06 05:52:32 PM PDT 24
Peak memory 222876 kb
Host smart-443240a7-21b0-4be9-814f-4d1c261ffb05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776881507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2776881507
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3227245636
Short name T1034
Test name
Test status
Simulation time 401804381 ps
CPU time 8.79 seconds
Started Aug 06 05:52:26 PM PDT 24
Finished Aug 06 05:52:35 PM PDT 24
Peak memory 214708 kb
Host smart-cdcb05a3-5705-4c8b-aa7e-841e17f877ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227245636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3227245636
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1758831060
Short name T966
Test name
Test status
Simulation time 1896460549 ps
CPU time 3.96 seconds
Started Aug 06 05:52:27 PM PDT 24
Finished Aug 06 05:52:31 PM PDT 24
Peak memory 214436 kb
Host smart-849e74eb-7126-470b-a279-7f2b5efb0d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758831060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1758831060
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.163213275
Short name T147
Test name
Test status
Simulation time 187166355 ps
CPU time 2.52 seconds
Started Aug 06 05:52:28 PM PDT 24
Finished Aug 06 05:52:31 PM PDT 24
Peak memory 214368 kb
Host smart-009c7caf-154f-4850-92dc-e0bbf62c3d53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163213275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
163213275
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2376887172
Short name T922
Test name
Test status
Simulation time 43087007 ps
CPU time 2.01 seconds
Started Aug 06 05:52:29 PM PDT 24
Finished Aug 06 05:52:32 PM PDT 24
Peak memory 214200 kb
Host smart-b43f2e96-64e2-4fd7-9d43-8ebda8592286
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376887172 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2376887172
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4196210741
Short name T130
Test name
Test status
Simulation time 32220123 ps
CPU time 0.92 seconds
Started Aug 06 05:52:31 PM PDT 24
Finished Aug 06 05:52:32 PM PDT 24
Peak memory 205684 kb
Host smart-cec4c49f-3525-4908-aa0c-e69293068264
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196210741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.4196210741
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.101080038
Short name T915
Test name
Test status
Simulation time 46774287 ps
CPU time 0.88 seconds
Started Aug 06 05:52:24 PM PDT 24
Finished Aug 06 05:52:25 PM PDT 24
Peak memory 205924 kb
Host smart-5bf7a122-5bbf-408c-80ed-d1e24f26ab3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101080038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.101080038
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.572119241
Short name T1022
Test name
Test status
Simulation time 51503416 ps
CPU time 1.55 seconds
Started Aug 06 05:52:27 PM PDT 24
Finished Aug 06 05:52:28 PM PDT 24
Peak memory 206224 kb
Host smart-14053891-640a-43db-87a7-d0d1bfea09df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572119241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.572119241
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.311479717
Short name T938
Test name
Test status
Simulation time 96898381 ps
CPU time 3.55 seconds
Started Aug 06 05:52:27 PM PDT 24
Finished Aug 06 05:52:31 PM PDT 24
Peak memory 214664 kb
Host smart-e6115047-679c-4e00-add1-15c56de8ea28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311479717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.311479717
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1225663390
Short name T993
Test name
Test status
Simulation time 187414845 ps
CPU time 8.52 seconds
Started Aug 06 05:52:26 PM PDT 24
Finished Aug 06 05:52:35 PM PDT 24
Peak memory 220796 kb
Host smart-a03c08ad-e6cc-4feb-a0ae-1f6ec1596e49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225663390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1225663390
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3200145720
Short name T943
Test name
Test status
Simulation time 654111435 ps
CPU time 3.57 seconds
Started Aug 06 05:52:29 PM PDT 24
Finished Aug 06 05:52:33 PM PDT 24
Peak memory 214388 kb
Host smart-aa126990-46c8-4d58-9fc2-dd7e7b1e229f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200145720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3200145720
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3626177540
Short name T140
Test name
Test status
Simulation time 76536301 ps
CPU time 2.58 seconds
Started Aug 06 05:52:28 PM PDT 24
Finished Aug 06 05:52:31 PM PDT 24
Peak memory 206196 kb
Host smart-3ebe3855-0b95-4671-8634-298bc2495721
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626177540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3626177540
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3920577029
Short name T857
Test name
Test status
Simulation time 12364311 ps
CPU time 0.89 seconds
Started Aug 06 05:24:30 PM PDT 24
Finished Aug 06 05:24:31 PM PDT 24
Peak memory 205940 kb
Host smart-5bae4dbc-dbc1-45c8-af2f-dab75b0893b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920577029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3920577029
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.24305690
Short name T211
Test name
Test status
Simulation time 259349198 ps
CPU time 4.36 seconds
Started Aug 06 05:24:34 PM PDT 24
Finished Aug 06 05:24:39 PM PDT 24
Peak memory 214360 kb
Host smart-cd87675d-0dba-4177-9bd6-ae0c1ba48d84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24305690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.24305690
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.221328727
Short name T575
Test name
Test status
Simulation time 72514459 ps
CPU time 1.59 seconds
Started Aug 06 05:24:36 PM PDT 24
Finished Aug 06 05:24:37 PM PDT 24
Peak memory 207116 kb
Host smart-1601f265-5801-44ce-a574-16d26451da0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221328727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.221328727
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.463614407
Short name T477
Test name
Test status
Simulation time 1724449353 ps
CPU time 5.52 seconds
Started Aug 06 05:24:35 PM PDT 24
Finished Aug 06 05:24:41 PM PDT 24
Peak memory 221176 kb
Host smart-897fdbf6-a16f-4f03-a6b4-8ebc93340754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463614407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.463614407
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3024228204
Short name T35
Test name
Test status
Simulation time 2973934984 ps
CPU time 32.9 seconds
Started Aug 06 05:24:35 PM PDT 24
Finished Aug 06 05:25:08 PM PDT 24
Peak memory 221052 kb
Host smart-c8d7d4c5-21ce-4771-a98a-ffbaeda3fdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024228204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3024228204
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2107561190
Short name T44
Test name
Test status
Simulation time 52917583 ps
CPU time 2.49 seconds
Started Aug 06 05:24:36 PM PDT 24
Finished Aug 06 05:24:38 PM PDT 24
Peak memory 218504 kb
Host smart-87cd65d5-b981-4f04-871e-3f4ec99d4309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107561190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2107561190
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3196644175
Short name T791
Test name
Test status
Simulation time 3166380076 ps
CPU time 37.23 seconds
Started Aug 06 05:24:36 PM PDT 24
Finished Aug 06 05:25:14 PM PDT 24
Peak memory 208216 kb
Host smart-c7169e41-1cdc-43dd-ace7-275aff360bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196644175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3196644175
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3001966570
Short name T546
Test name
Test status
Simulation time 138625670 ps
CPU time 4.68 seconds
Started Aug 06 05:24:34 PM PDT 24
Finished Aug 06 05:24:39 PM PDT 24
Peak memory 208732 kb
Host smart-8f37f876-b8ea-4ea2-a42c-af19636667dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001966570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3001966570
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.752663610
Short name T422
Test name
Test status
Simulation time 62003912 ps
CPU time 3.17 seconds
Started Aug 06 05:24:36 PM PDT 24
Finished Aug 06 05:24:40 PM PDT 24
Peak memory 206748 kb
Host smart-1db6d352-abf6-4c78-942b-aca8bed30f65
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752663610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.752663610
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2318274348
Short name T866
Test name
Test status
Simulation time 61993425 ps
CPU time 2.33 seconds
Started Aug 06 05:24:30 PM PDT 24
Finished Aug 06 05:24:33 PM PDT 24
Peak memory 206056 kb
Host smart-8128487f-355c-4c67-b304-34b66f86a70a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318274348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2318274348
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1546592649
Short name T424
Test name
Test status
Simulation time 68283616 ps
CPU time 2.78 seconds
Started Aug 06 05:24:37 PM PDT 24
Finished Aug 06 05:24:39 PM PDT 24
Peak memory 206728 kb
Host smart-d3dd2157-2bf1-46ae-809d-54720407cf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546592649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1546592649
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2925806167
Short name T335
Test name
Test status
Simulation time 857664453 ps
CPU time 19.03 seconds
Started Aug 06 05:24:27 PM PDT 24
Finished Aug 06 05:24:46 PM PDT 24
Peak memory 222488 kb
Host smart-0d600625-7bef-42c2-83a8-923deddf4bf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925806167 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2925806167
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.610695779
Short name T882
Test name
Test status
Simulation time 338739884 ps
CPU time 6.32 seconds
Started Aug 06 05:24:37 PM PDT 24
Finished Aug 06 05:24:43 PM PDT 24
Peak memory 207364 kb
Host smart-1a33dcec-aec2-4914-8d14-681d3e97484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610695779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.610695779
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.688366725
Short name T513
Test name
Test status
Simulation time 299773718 ps
CPU time 3.1 seconds
Started Aug 06 05:24:36 PM PDT 24
Finished Aug 06 05:24:39 PM PDT 24
Peak memory 210380 kb
Host smart-9bb79737-2126-4653-a5ff-8fdfce4d8fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688366725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.688366725
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2560686067
Short name T641
Test name
Test status
Simulation time 33921518 ps
CPU time 0.85 seconds
Started Aug 06 05:24:28 PM PDT 24
Finished Aug 06 05:24:29 PM PDT 24
Peak memory 205864 kb
Host smart-d9cc2308-4cac-4b19-b252-6bedcb698eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560686067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2560686067
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.506071204
Short name T553
Test name
Test status
Simulation time 8216443624 ps
CPU time 11.81 seconds
Started Aug 06 05:24:28 PM PDT 24
Finished Aug 06 05:24:40 PM PDT 24
Peak memory 209624 kb
Host smart-d3a3d094-09ed-4d5a-b4fe-68a0c1250090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506071204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.506071204
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.4261821948
Short name T94
Test name
Test status
Simulation time 26280840 ps
CPU time 1.81 seconds
Started Aug 06 05:24:28 PM PDT 24
Finished Aug 06 05:24:30 PM PDT 24
Peak memory 214380 kb
Host smart-4301b162-ff7b-4428-83ab-c6c931a99748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261821948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.4261821948
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1476126898
Short name T748
Test name
Test status
Simulation time 534941078 ps
CPU time 2.54 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:32 PM PDT 24
Peak memory 214336 kb
Host smart-b6d96ee2-dd00-4706-b779-8f0e53c6a234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476126898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1476126898
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2630151736
Short name T629
Test name
Test status
Simulation time 384759613 ps
CPU time 3.73 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:33 PM PDT 24
Peak memory 209628 kb
Host smart-6107abed-0a78-474b-838c-318808db8772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630151736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2630151736
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.224569808
Short name T307
Test name
Test status
Simulation time 213809611 ps
CPU time 5.21 seconds
Started Aug 06 05:24:28 PM PDT 24
Finished Aug 06 05:24:33 PM PDT 24
Peak memory 218260 kb
Host smart-65940032-98db-4d2c-95df-243d842ad994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224569808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.224569808
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3918181699
Short name T42
Test name
Test status
Simulation time 1736347369 ps
CPU time 5.84 seconds
Started Aug 06 05:24:28 PM PDT 24
Finished Aug 06 05:24:33 PM PDT 24
Peak memory 229160 kb
Host smart-c250aadb-8157-4feb-8827-229e71f73ecd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918181699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3918181699
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2776521801
Short name T605
Test name
Test status
Simulation time 416858794 ps
CPU time 3.25 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:32 PM PDT 24
Peak memory 208360 kb
Host smart-d54eac8e-a6d0-4e9b-b291-3874ef9be8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776521801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2776521801
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.979796236
Short name T470
Test name
Test status
Simulation time 64712606 ps
CPU time 2.94 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:32 PM PDT 24
Peak memory 207952 kb
Host smart-619f8913-cf1b-4b88-8c4d-da384d26ce63
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979796236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.979796236
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2900380806
Short name T731
Test name
Test status
Simulation time 37362628 ps
CPU time 2.78 seconds
Started Aug 06 05:24:28 PM PDT 24
Finished Aug 06 05:24:31 PM PDT 24
Peak memory 208676 kb
Host smart-fd35c100-7f51-434b-8247-a6eb9c09a1b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900380806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2900380806
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1290029696
Short name T215
Test name
Test status
Simulation time 77369450 ps
CPU time 2.55 seconds
Started Aug 06 05:24:28 PM PDT 24
Finished Aug 06 05:24:30 PM PDT 24
Peak memory 206800 kb
Host smart-571a3c29-550b-430c-a156-2727974bf797
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290029696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1290029696
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.440120766
Short name T213
Test name
Test status
Simulation time 114320557 ps
CPU time 1.99 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:31 PM PDT 24
Peak memory 207284 kb
Host smart-79bd9c66-0b98-46f5-a885-5a11f9742c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440120766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.440120766
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2366269721
Short name T754
Test name
Test status
Simulation time 311898698 ps
CPU time 2.07 seconds
Started Aug 06 05:24:29 PM PDT 24
Finished Aug 06 05:24:31 PM PDT 24
Peak memory 206856 kb
Host smart-c401e099-ddc8-4992-8725-4a43d80d94f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366269721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2366269721
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3217397850
Short name T691
Test name
Test status
Simulation time 339012456 ps
CPU time 14.98 seconds
Started Aug 06 05:24:32 PM PDT 24
Finished Aug 06 05:24:47 PM PDT 24
Peak memory 222492 kb
Host smart-51492571-ada3-4b6e-b11c-2170cf710b07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217397850 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3217397850
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3247405649
Short name T453
Test name
Test status
Simulation time 229587441 ps
CPU time 7.3 seconds
Started Aug 06 05:24:28 PM PDT 24
Finished Aug 06 05:24:36 PM PDT 24
Peak memory 209400 kb
Host smart-d1c4c9e4-6518-4aa4-8dc1-a856b2db0bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247405649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3247405649
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2190543765
Short name T512
Test name
Test status
Simulation time 44324029 ps
CPU time 0.78 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:25:15 PM PDT 24
Peak memory 205976 kb
Host smart-7967c191-dfdd-4157-8255-10e27eddd405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190543765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2190543765
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3393251967
Short name T311
Test name
Test status
Simulation time 669415441 ps
CPU time 35.55 seconds
Started Aug 06 05:25:15 PM PDT 24
Finished Aug 06 05:25:50 PM PDT 24
Peak memory 222436 kb
Host smart-c7d75355-ae64-4957-b57e-b020a532f9c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393251967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3393251967
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3915790873
Short name T75
Test name
Test status
Simulation time 318525336 ps
CPU time 6.1 seconds
Started Aug 06 05:25:15 PM PDT 24
Finished Aug 06 05:25:22 PM PDT 24
Peak memory 208280 kb
Host smart-57f31139-ade0-436e-b5f7-a8a3a2166777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915790873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3915790873
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.215773821
Short name T717
Test name
Test status
Simulation time 364061050 ps
CPU time 2.4 seconds
Started Aug 06 05:25:20 PM PDT 24
Finished Aug 06 05:25:23 PM PDT 24
Peak memory 222048 kb
Host smart-9bda012a-3816-46da-894d-00e6ce252e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215773821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.215773821
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1511689247
Short name T227
Test name
Test status
Simulation time 165209815 ps
CPU time 3.79 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:17 PM PDT 24
Peak memory 210208 kb
Host smart-92539bdc-a590-48a8-bc95-ab262b948788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511689247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1511689247
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2571727128
Short name T764
Test name
Test status
Simulation time 100050136 ps
CPU time 3.27 seconds
Started Aug 06 05:25:12 PM PDT 24
Finished Aug 06 05:25:15 PM PDT 24
Peak memory 208740 kb
Host smart-63eadb3c-b835-4106-8a7e-1c05b52258a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571727128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2571727128
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3620036396
Short name T561
Test name
Test status
Simulation time 131717009 ps
CPU time 2.46 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:25:16 PM PDT 24
Peak memory 208540 kb
Host smart-857abd1e-c180-4fdb-8f90-04b42660b778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620036396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3620036396
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1495850592
Short name T793
Test name
Test status
Simulation time 42934402 ps
CPU time 1.85 seconds
Started Aug 06 05:25:16 PM PDT 24
Finished Aug 06 05:25:18 PM PDT 24
Peak memory 206996 kb
Host smart-16aacde0-2ea5-4880-8f04-dd4041680f97
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495850592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1495850592
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2736268469
Short name T904
Test name
Test status
Simulation time 87367739 ps
CPU time 1.98 seconds
Started Aug 06 05:25:09 PM PDT 24
Finished Aug 06 05:25:12 PM PDT 24
Peak memory 208752 kb
Host smart-01f9acee-d435-47de-91d0-6febadb403d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736268469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2736268469
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.326067305
Short name T416
Test name
Test status
Simulation time 620724198 ps
CPU time 22.23 seconds
Started Aug 06 05:25:11 PM PDT 24
Finished Aug 06 05:25:33 PM PDT 24
Peak memory 208828 kb
Host smart-622fb5d8-3a65-47da-bab7-85a7a39f7fe9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326067305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.326067305
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.785833924
Short name T725
Test name
Test status
Simulation time 270083385 ps
CPU time 5.96 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:20 PM PDT 24
Peak memory 209408 kb
Host smart-8fc14ba5-9248-4b11-a3c5-6bed62529890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785833924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.785833924
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.222035738
Short name T859
Test name
Test status
Simulation time 2868552856 ps
CPU time 12.99 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:27 PM PDT 24
Peak memory 222464 kb
Host smart-9f13a80e-1c99-412c-ad80-5e03642fff1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222035738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.222035738
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.578391601
Short name T805
Test name
Test status
Simulation time 388214457 ps
CPU time 4.59 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:25:19 PM PDT 24
Peak memory 209832 kb
Host smart-bd5cd30e-2417-4a69-a477-c4a03ff67d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578391601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.578391601
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3335856359
Short name T623
Test name
Test status
Simulation time 111530759 ps
CPU time 2.43 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:25:17 PM PDT 24
Peak memory 210100 kb
Host smart-a6ab3ee7-3f8c-4622-bb6e-d4a2db156334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335856359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3335856359
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1086637832
Short name T844
Test name
Test status
Simulation time 49695769 ps
CPU time 0.75 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:25:14 PM PDT 24
Peak memory 205976 kb
Host smart-83f392dc-a187-4593-81ce-fb5a9cae9f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086637832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1086637832
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2341364752
Short name T51
Test name
Test status
Simulation time 52299764 ps
CPU time 2.59 seconds
Started Aug 06 05:25:15 PM PDT 24
Finished Aug 06 05:25:18 PM PDT 24
Peak memory 219720 kb
Host smart-aa32ad33-b69a-4c7e-adfa-d94f56996e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341364752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2341364752
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2339743050
Short name T756
Test name
Test status
Simulation time 281217868 ps
CPU time 4.14 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:18 PM PDT 24
Peak memory 214312 kb
Host smart-6f4b8747-ba3c-4a3b-bc0d-e33cc7d83310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339743050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2339743050
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2357584678
Short name T645
Test name
Test status
Simulation time 207697995 ps
CPU time 5.87 seconds
Started Aug 06 05:25:16 PM PDT 24
Finished Aug 06 05:25:22 PM PDT 24
Peak memory 209244 kb
Host smart-c3bbb31e-97bf-4184-a16d-1956bae55003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357584678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2357584678
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1751461673
Short name T79
Test name
Test status
Simulation time 145832542 ps
CPU time 4.02 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:18 PM PDT 24
Peak memory 206696 kb
Host smart-e5c1a8cc-f460-4972-9edf-f034867e4a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751461673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1751461673
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.676921952
Short name T413
Test name
Test status
Simulation time 65353857 ps
CPU time 3.22 seconds
Started Aug 06 05:25:17 PM PDT 24
Finished Aug 06 05:25:20 PM PDT 24
Peak memory 208128 kb
Host smart-f7b843aa-d5c4-4c46-800c-41d208034c7b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676921952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.676921952
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3011263405
Short name T729
Test name
Test status
Simulation time 392185119 ps
CPU time 10.32 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:23 PM PDT 24
Peak memory 208028 kb
Host smart-d10a39e0-7077-4844-abc5-47ce29b615a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011263405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3011263405
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1114068323
Short name T625
Test name
Test status
Simulation time 512726722 ps
CPU time 3.9 seconds
Started Aug 06 05:25:12 PM PDT 24
Finished Aug 06 05:25:16 PM PDT 24
Peak memory 206888 kb
Host smart-8fbb0670-bb94-43db-94a7-447887b58aaf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114068323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1114068323
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1837523368
Short name T780
Test name
Test status
Simulation time 323915492 ps
CPU time 2.87 seconds
Started Aug 06 05:25:16 PM PDT 24
Finished Aug 06 05:25:18 PM PDT 24
Peak memory 208488 kb
Host smart-5e648373-76ea-439a-a8f2-e7a8e774776b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837523368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1837523368
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1426205723
Short name T634
Test name
Test status
Simulation time 2081689111 ps
CPU time 64.11 seconds
Started Aug 06 05:25:15 PM PDT 24
Finished Aug 06 05:26:19 PM PDT 24
Peak memory 214332 kb
Host smart-9036f922-519c-4c44-a206-c93d8484c54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426205723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1426205723
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.537251614
Short name T755
Test name
Test status
Simulation time 142793442 ps
CPU time 2.2 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:16 PM PDT 24
Peak memory 209644 kb
Host smart-78f8c83f-e787-4a29-952b-738427fc3974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537251614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.537251614
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3372692969
Short name T765
Test name
Test status
Simulation time 73017180 ps
CPU time 3.04 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:28 PM PDT 24
Peak memory 209492 kb
Host smart-3c7ef548-cbbe-4535-b8e3-b08f567d1627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372692969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3372692969
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3880552987
Short name T669
Test name
Test status
Simulation time 59272464 ps
CPU time 2.12 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:30 PM PDT 24
Peak memory 208776 kb
Host smart-8a9e6014-97c3-4046-a08c-40eb36836aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880552987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3880552987
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3839920810
Short name T820
Test name
Test status
Simulation time 53441457 ps
CPU time 3.32 seconds
Started Aug 06 05:25:24 PM PDT 24
Finished Aug 06 05:25:27 PM PDT 24
Peak memory 209820 kb
Host smart-36f8b8fc-de0b-48da-a041-be8d9633c2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839920810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3839920810
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1548955318
Short name T597
Test name
Test status
Simulation time 98305221 ps
CPU time 3.22 seconds
Started Aug 06 05:25:29 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 209104 kb
Host smart-f0b7640b-6ef5-4116-af7c-6a5035390492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548955318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1548955318
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2004488345
Short name T17
Test name
Test status
Simulation time 321556392 ps
CPU time 7.66 seconds
Started Aug 06 05:25:26 PM PDT 24
Finished Aug 06 05:25:34 PM PDT 24
Peak memory 207880 kb
Host smart-09e4bcca-a6eb-4d25-87d6-060c359f23b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004488345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2004488345
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.878761900
Short name T440
Test name
Test status
Simulation time 264149738 ps
CPU time 2.54 seconds
Started Aug 06 05:25:17 PM PDT 24
Finished Aug 06 05:25:20 PM PDT 24
Peak memory 206788 kb
Host smart-c23fa21b-ca08-46dd-919b-b786aaace231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878761900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.878761900
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1933389818
Short name T860
Test name
Test status
Simulation time 115622301 ps
CPU time 2.94 seconds
Started Aug 06 05:25:12 PM PDT 24
Finished Aug 06 05:25:15 PM PDT 24
Peak memory 207044 kb
Host smart-7cd03427-e779-45e5-ab1e-621c676b470a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933389818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1933389818
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2696835499
Short name T855
Test name
Test status
Simulation time 130481721 ps
CPU time 3.51 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:25:17 PM PDT 24
Peak memory 208556 kb
Host smart-bce93dc3-4aa1-4dbb-a51d-39ffed8ca287
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696835499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2696835499
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3394751855
Short name T684
Test name
Test status
Simulation time 285853502 ps
CPU time 2.67 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:25:16 PM PDT 24
Peak memory 206816 kb
Host smart-b60eb2f8-a14b-423f-93e1-0c32223ee31d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394751855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3394751855
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3006773186
Short name T439
Test name
Test status
Simulation time 274132131 ps
CPU time 3.58 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 214300 kb
Host smart-60d80366-2a84-4946-a674-358c9a360048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006773186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3006773186
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1442895088
Short name T847
Test name
Test status
Simulation time 55734099 ps
CPU time 2.75 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:16 PM PDT 24
Peak memory 206836 kb
Host smart-5f502d79-109f-4d4f-bede-a98aafba513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442895088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1442895088
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3291783698
Short name T234
Test name
Test status
Simulation time 1982304359 ps
CPU time 27.57 seconds
Started Aug 06 05:25:24 PM PDT 24
Finished Aug 06 05:25:52 PM PDT 24
Peak memory 215684 kb
Host smart-a9ae3dd7-8fba-4f62-b4b7-d15520cf69ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291783698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3291783698
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.255726509
Short name T435
Test name
Test status
Simulation time 94814291 ps
CPU time 4.83 seconds
Started Aug 06 05:25:24 PM PDT 24
Finished Aug 06 05:25:29 PM PDT 24
Peak memory 207740 kb
Host smart-59cff6ef-0244-45e2-978b-77bbd49015e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255726509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.255726509
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1804151652
Short name T790
Test name
Test status
Simulation time 1831189988 ps
CPU time 16.5 seconds
Started Aug 06 05:25:26 PM PDT 24
Finished Aug 06 05:25:43 PM PDT 24
Peak memory 211084 kb
Host smart-03998934-1573-429e-9812-b89ec853b78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804151652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1804151652
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2099403070
Short name T698
Test name
Test status
Simulation time 42006092 ps
CPU time 0.74 seconds
Started Aug 06 05:25:26 PM PDT 24
Finished Aug 06 05:25:27 PM PDT 24
Peak memory 205956 kb
Host smart-021fb32c-3dc3-484e-a518-544d5621643a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099403070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2099403070
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3768695947
Short name T374
Test name
Test status
Simulation time 1439776726 ps
CPU time 37.71 seconds
Started Aug 06 05:25:23 PM PDT 24
Finished Aug 06 05:26:01 PM PDT 24
Peak memory 214596 kb
Host smart-b74f4864-ec0e-4e39-aba6-2725a41fe04e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3768695947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3768695947
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.212532133
Short name T38
Test name
Test status
Simulation time 125489533 ps
CPU time 2.45 seconds
Started Aug 06 05:25:26 PM PDT 24
Finished Aug 06 05:25:29 PM PDT 24
Peak memory 209548 kb
Host smart-46ade45b-b08b-48e7-a01f-a7a3d403e282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212532133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.212532133
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2151808308
Short name T667
Test name
Test status
Simulation time 68607044 ps
CPU time 2.74 seconds
Started Aug 06 05:25:28 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 208436 kb
Host smart-ddbbd13b-f4d9-443c-a2b4-3f4dee055a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151808308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2151808308
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.227664372
Short name T853
Test name
Test status
Simulation time 25905915 ps
CPU time 1.89 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:27 PM PDT 24
Peak memory 214352 kb
Host smart-7e2b5017-d5a3-4b34-aa77-82dcdfc905bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227664372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.227664372
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1093309118
Short name T657
Test name
Test status
Simulation time 445631330 ps
CPU time 4.61 seconds
Started Aug 06 05:25:23 PM PDT 24
Finished Aug 06 05:25:28 PM PDT 24
Peak memory 214196 kb
Host smart-e46fb6f2-d7f0-49d6-a8a8-f0bae2e9a326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093309118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1093309118
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.4136255207
Short name T316
Test name
Test status
Simulation time 674145276 ps
CPU time 10.58 seconds
Started Aug 06 05:25:24 PM PDT 24
Finished Aug 06 05:25:34 PM PDT 24
Peak memory 209388 kb
Host smart-5a0810dc-9045-4be2-974e-c3263393718f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136255207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4136255207
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2932015157
Short name T749
Test name
Test status
Simulation time 232161804 ps
CPU time 7.26 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 207380 kb
Host smart-895a8eb8-73bd-48b7-b9c6-f4f066353a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932015157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2932015157
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3490972764
Short name T343
Test name
Test status
Simulation time 56927130 ps
CPU time 2.96 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:30 PM PDT 24
Peak memory 208760 kb
Host smart-af2b9688-5b5e-493b-9d31-b17b78a0a066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490972764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3490972764
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.932458573
Short name T665
Test name
Test status
Simulation time 27249170 ps
CPU time 2.06 seconds
Started Aug 06 05:25:29 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 208756 kb
Host smart-3efe9f8e-4243-4171-9c37-19352f9cfa85
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932458573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.932458573
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1047449061
Short name T727
Test name
Test status
Simulation time 22733459 ps
CPU time 1.89 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 206964 kb
Host smart-0c754b1b-56cc-41aa-90c0-ebbc63f2d00a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047449061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1047449061
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1645026251
Short name T78
Test name
Test status
Simulation time 274274165 ps
CPU time 3.58 seconds
Started Aug 06 05:25:24 PM PDT 24
Finished Aug 06 05:25:28 PM PDT 24
Peak memory 206932 kb
Host smart-fc211d1b-2d3b-4479-b5b2-8652302e9736
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645026251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1645026251
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.4224158598
Short name T833
Test name
Test status
Simulation time 72256757 ps
CPU time 3.37 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:34 PM PDT 24
Peak memory 209308 kb
Host smart-2ab9d8e3-4d6a-4feb-8582-04b6142b0fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224158598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.4224158598
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3757248441
Short name T538
Test name
Test status
Simulation time 80543223 ps
CPU time 2.64 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:28 PM PDT 24
Peak memory 208000 kb
Host smart-696197e5-65e0-4ee9-b102-c52f8830ed48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757248441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3757248441
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1034249434
Short name T81
Test name
Test status
Simulation time 50775094 ps
CPU time 3.09 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:28 PM PDT 24
Peak memory 208880 kb
Host smart-0c6ab2a2-a5a0-43e6-bf66-fbe1c552984f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034249434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1034249434
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3226872470
Short name T372
Test name
Test status
Simulation time 8758541893 ps
CPU time 19.74 seconds
Started Aug 06 05:25:24 PM PDT 24
Finished Aug 06 05:25:44 PM PDT 24
Peak memory 211260 kb
Host smart-f240bec1-6289-4f02-a885-5ea644d788fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226872470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3226872470
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2188316913
Short name T788
Test name
Test status
Simulation time 23931294 ps
CPU time 0.84 seconds
Started Aug 06 05:25:28 PM PDT 24
Finished Aug 06 05:25:29 PM PDT 24
Peak memory 205876 kb
Host smart-6410e157-9587-4460-b927-391a989cd8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188316913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2188316913
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1811798111
Short name T126
Test name
Test status
Simulation time 423851459 ps
CPU time 4.35 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:34 PM PDT 24
Peak memory 215456 kb
Host smart-e0bab641-7b36-40b7-aafa-52d7dd035795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811798111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1811798111
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.264577468
Short name T649
Test name
Test status
Simulation time 1110985504 ps
CPU time 3.66 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:29 PM PDT 24
Peak memory 218108 kb
Host smart-9966cf68-7038-4fea-b323-a3e4861468fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264577468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.264577468
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.4203025903
Short name T101
Test name
Test status
Simulation time 31592606 ps
CPU time 2.51 seconds
Started Aug 06 05:25:26 PM PDT 24
Finished Aug 06 05:25:29 PM PDT 24
Peak memory 209000 kb
Host smart-c7bcc34f-f4db-41e1-acb7-41b71e4957b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203025903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4203025903
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.944525457
Short name T863
Test name
Test status
Simulation time 68778751 ps
CPU time 3.5 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:29 PM PDT 24
Peak memory 222392 kb
Host smart-5d2892c8-87b7-42b0-aeb6-f8187d8dc91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944525457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.944525457
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4074721199
Short name T63
Test name
Test status
Simulation time 131485195 ps
CPU time 6.78 seconds
Started Aug 06 05:25:29 PM PDT 24
Finished Aug 06 05:25:35 PM PDT 24
Peak memory 222428 kb
Host smart-c6550044-125a-44e1-b22d-a8f25da5cea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074721199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4074721199
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3691263310
Short name T906
Test name
Test status
Simulation time 152351239 ps
CPU time 3.76 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:28 PM PDT 24
Peak memory 209144 kb
Host smart-58d6a175-234e-4360-b9a0-79341b5eb538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691263310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3691263310
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1967039720
Short name T461
Test name
Test status
Simulation time 454286749 ps
CPU time 4.05 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:29 PM PDT 24
Peak memory 206844 kb
Host smart-f53802bc-44ef-4e75-b19b-edd6050c6a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967039720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1967039720
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.4079400105
Short name T819
Test name
Test status
Simulation time 185480477 ps
CPU time 3.21 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:28 PM PDT 24
Peak memory 208328 kb
Host smart-7ee66156-1011-4ab3-b5cb-eb9e333033d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079400105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.4079400105
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.445447781
Short name T683
Test name
Test status
Simulation time 169680477 ps
CPU time 4.12 seconds
Started Aug 06 05:25:25 PM PDT 24
Finished Aug 06 05:25:29 PM PDT 24
Peak memory 208132 kb
Host smart-20022b28-d5db-4e2e-a1f9-9c1a1b3f29db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445447781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.445447781
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2761063902
Short name T333
Test name
Test status
Simulation time 250921229 ps
CPU time 5.09 seconds
Started Aug 06 05:25:28 PM PDT 24
Finished Aug 06 05:25:33 PM PDT 24
Peak memory 208936 kb
Host smart-4ef75fe1-d90f-423f-8b5e-f67ae7d10893
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761063902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2761063902
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1598391943
Short name T407
Test name
Test status
Simulation time 28570086 ps
CPU time 1.87 seconds
Started Aug 06 05:25:23 PM PDT 24
Finished Aug 06 05:25:25 PM PDT 24
Peak memory 207948 kb
Host smart-a5b7f700-d53e-4725-acd8-32f66b16f997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598391943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1598391943
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3779824445
Short name T890
Test name
Test status
Simulation time 767388372 ps
CPU time 4.59 seconds
Started Aug 06 05:25:23 PM PDT 24
Finished Aug 06 05:25:28 PM PDT 24
Peak memory 208156 kb
Host smart-e7df27a8-aee3-45df-ab18-7389ca8b688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779824445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3779824445
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3831177330
Short name T704
Test name
Test status
Simulation time 427225281 ps
CPU time 6.09 seconds
Started Aug 06 05:25:24 PM PDT 24
Finished Aug 06 05:25:30 PM PDT 24
Peak memory 207956 kb
Host smart-1dc04a1e-b837-447c-9d76-0dcc7b6552ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831177330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3831177330
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2550685537
Short name T676
Test name
Test status
Simulation time 474607972 ps
CPU time 2.51 seconds
Started Aug 06 05:25:28 PM PDT 24
Finished Aug 06 05:25:30 PM PDT 24
Peak memory 209904 kb
Host smart-92e5849b-33d2-4e2d-9f40-c167e7ba5672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550685537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2550685537
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1555949263
Short name T845
Test name
Test status
Simulation time 12631016 ps
CPU time 0.86 seconds
Started Aug 06 05:25:31 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 205908 kb
Host smart-eb1feb77-e46f-4e7a-b17a-170971c0f38a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555949263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1555949263
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3770605674
Short name T30
Test name
Test status
Simulation time 1204285103 ps
CPU time 14.05 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:41 PM PDT 24
Peak memory 209240 kb
Host smart-23d6c70e-2523-4f18-bb61-f0f749b87d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770605674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3770605674
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3089359661
Short name T476
Test name
Test status
Simulation time 619585930 ps
CPU time 4.45 seconds
Started Aug 06 05:25:28 PM PDT 24
Finished Aug 06 05:25:33 PM PDT 24
Peak memory 218296 kb
Host smart-82fd267b-062e-4fb4-9f79-af5a6d5c49a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089359661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3089359661
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2701851595
Short name T300
Test name
Test status
Simulation time 180427086 ps
CPU time 4.31 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 222348 kb
Host smart-04ad80bc-6ace-4da9-89b1-35fa7fa81b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701851595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2701851595
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_random.813506198
Short name T895
Test name
Test status
Simulation time 14330241635 ps
CPU time 37.03 seconds
Started Aug 06 05:25:24 PM PDT 24
Finished Aug 06 05:26:01 PM PDT 24
Peak memory 209324 kb
Host smart-b854475e-dd04-4e60-b082-b6bba10c76b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813506198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.813506198
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1652763082
Short name T517
Test name
Test status
Simulation time 356991165 ps
CPU time 3.4 seconds
Started Aug 06 05:25:28 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 208636 kb
Host smart-39a98a07-74f5-4c13-b29e-e29582a1af01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652763082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1652763082
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1267238233
Short name T284
Test name
Test status
Simulation time 335645203 ps
CPU time 3.65 seconds
Started Aug 06 05:25:29 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 208912 kb
Host smart-b395a8f4-f919-4867-9403-0e3bffca96fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267238233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1267238233
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.426288673
Short name T426
Test name
Test status
Simulation time 50410845 ps
CPU time 2.6 seconds
Started Aug 06 05:25:26 PM PDT 24
Finished Aug 06 05:25:29 PM PDT 24
Peak memory 206912 kb
Host smart-8d27b625-5c8d-4703-9002-ea7b3d159b4c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426288673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.426288673
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2453358681
Short name T491
Test name
Test status
Simulation time 40965056 ps
CPU time 2.85 seconds
Started Aug 06 05:25:28 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 209012 kb
Host smart-0c537874-f85e-4faf-8da3-c5fb36d23371
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453358681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2453358681
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.779440050
Short name T656
Test name
Test status
Simulation time 40383315 ps
CPU time 2.04 seconds
Started Aug 06 05:25:29 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 207660 kb
Host smart-40d30a56-772f-49a6-9e67-90b95b6b2e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779440050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.779440050
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1339832328
Short name T862
Test name
Test status
Simulation time 716900005 ps
CPU time 15.87 seconds
Started Aug 06 05:25:26 PM PDT 24
Finished Aug 06 05:25:42 PM PDT 24
Peak memory 208728 kb
Host smart-9a184b6c-e5a8-46a2-b5aa-469e0e25eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339832328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1339832328
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2953398618
Short name T808
Test name
Test status
Simulation time 359808143 ps
CPU time 11.48 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:38 PM PDT 24
Peak memory 214988 kb
Host smart-36a0a68f-73c5-4a66-87da-a46dc3465fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953398618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2953398618
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.766264207
Short name T310
Test name
Test status
Simulation time 615882020 ps
CPU time 9.8 seconds
Started Aug 06 05:25:29 PM PDT 24
Finished Aug 06 05:25:39 PM PDT 24
Peak memory 222576 kb
Host smart-1d182ab7-dc41-40c1-b8e6-db24b913dcf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766264207 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.766264207
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3414723551
Short name T602
Test name
Test status
Simulation time 191753699 ps
CPU time 2.68 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:30 PM PDT 24
Peak memory 207768 kb
Host smart-dc6bdfc2-3d6b-4b78-9b8e-7f86e2efeffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414723551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3414723551
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.45148582
Short name T584
Test name
Test status
Simulation time 287675689 ps
CPU time 1.94 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:29 PM PDT 24
Peak memory 209612 kb
Host smart-a2db26c8-ad15-4e30-8f2e-905bd3714c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45148582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.45148582
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2718354845
Short name T651
Test name
Test status
Simulation time 24783249 ps
CPU time 0.7 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 205964 kb
Host smart-aa25244c-72f5-43bd-94e5-16c97d799018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718354845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2718354845
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3879503327
Short name T601
Test name
Test status
Simulation time 295955926 ps
CPU time 3.81 seconds
Started Aug 06 05:25:28 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 214416 kb
Host smart-5f5e1b6a-1944-4d2b-a4e7-347cc453e97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879503327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3879503327
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.448544571
Short name T85
Test name
Test status
Simulation time 51769907 ps
CPU time 2.66 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:33 PM PDT 24
Peak memory 214260 kb
Host smart-ba3278ae-fa96-41e1-81f7-235b6c98d26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448544571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.448544571
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3924910386
Short name T613
Test name
Test status
Simulation time 77475287 ps
CPU time 2.34 seconds
Started Aug 06 05:25:32 PM PDT 24
Finished Aug 06 05:25:34 PM PDT 24
Peak memory 214184 kb
Host smart-84c6c100-5fdf-4510-9e99-083de528e375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924910386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3924910386
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.566245838
Short name T688
Test name
Test status
Simulation time 954014333 ps
CPU time 4.28 seconds
Started Aug 06 05:25:32 PM PDT 24
Finished Aug 06 05:25:36 PM PDT 24
Peak memory 220316 kb
Host smart-a75f248d-1dc6-4d62-a667-bcbfa7ad6ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566245838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.566245838
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1115654686
Short name T703
Test name
Test status
Simulation time 2444158608 ps
CPU time 26.93 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:57 PM PDT 24
Peak memory 209048 kb
Host smart-e4e50be9-384d-4f49-8f0c-451d6fa0ad3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115654686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1115654686
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1507091507
Short name T772
Test name
Test status
Simulation time 2171242680 ps
CPU time 6.87 seconds
Started Aug 06 05:25:29 PM PDT 24
Finished Aug 06 05:25:36 PM PDT 24
Peak memory 208400 kb
Host smart-06e58389-21f6-4d7b-8b4a-e93bc84ba1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507091507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1507091507
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2243738721
Short name T495
Test name
Test status
Simulation time 38183444 ps
CPU time 2.29 seconds
Started Aug 06 05:25:29 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 208184 kb
Host smart-1292f6e4-0b87-42a4-82fb-d4c5d75d7b9e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243738721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2243738721
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.4031484185
Short name T525
Test name
Test status
Simulation time 130155734 ps
CPU time 2.67 seconds
Started Aug 06 05:25:31 PM PDT 24
Finished Aug 06 05:25:33 PM PDT 24
Peak memory 206900 kb
Host smart-ad41030f-a420-4205-b88d-500ea6e51245
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031484185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.4031484185
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3251910640
Short name T562
Test name
Test status
Simulation time 243623202 ps
CPU time 3.35 seconds
Started Aug 06 05:25:32 PM PDT 24
Finished Aug 06 05:25:35 PM PDT 24
Peak memory 216236 kb
Host smart-5d28f9c0-3ecf-4cc8-9d15-ba78b1faa940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251910640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3251910640
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3225047504
Short name T557
Test name
Test status
Simulation time 67643803 ps
CPU time 1.62 seconds
Started Aug 06 05:25:24 PM PDT 24
Finished Aug 06 05:25:26 PM PDT 24
Peak memory 206964 kb
Host smart-47c7aa7b-9e3f-4d13-8b1a-b70924dc417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225047504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3225047504
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3031066426
Short name T152
Test name
Test status
Simulation time 67793757 ps
CPU time 1.73 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 209464 kb
Host smart-5181a6b4-a5c2-4d9a-8f11-5043f7d59213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031066426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3031066426
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1997499363
Short name T405
Test name
Test status
Simulation time 29649398 ps
CPU time 0.75 seconds
Started Aug 06 05:25:41 PM PDT 24
Finished Aug 06 05:25:41 PM PDT 24
Peak memory 205644 kb
Host smart-a5ef63ea-4d65-4797-b23d-648c5eea120f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997499363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1997499363
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.4071993329
Short name T379
Test name
Test status
Simulation time 376387055 ps
CPU time 6.24 seconds
Started Aug 06 05:25:29 PM PDT 24
Finished Aug 06 05:25:36 PM PDT 24
Peak memory 214340 kb
Host smart-f75a9bb3-6b26-4ac6-a3c7-570e4b3aa8f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4071993329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.4071993329
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.298169127
Short name T186
Test name
Test status
Simulation time 163954754 ps
CPU time 1.68 seconds
Started Aug 06 05:25:28 PM PDT 24
Finished Aug 06 05:25:29 PM PDT 24
Peak memory 214532 kb
Host smart-f499f17c-012a-44ad-9271-1b5c4c0483a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298169127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.298169127
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3652950766
Short name T298
Test name
Test status
Simulation time 2541327644 ps
CPU time 20.71 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:50 PM PDT 24
Peak memory 209252 kb
Host smart-7dec1905-e114-4cce-afeb-7631b0c55785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652950766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3652950766
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2648458590
Short name T545
Test name
Test status
Simulation time 480676800 ps
CPU time 3.27 seconds
Started Aug 06 05:25:28 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 222472 kb
Host smart-5b99f23f-0af3-42a0-832b-5fbbf7922694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648458590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2648458590
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.234386763
Short name T102
Test name
Test status
Simulation time 944063530 ps
CPU time 3.86 seconds
Started Aug 06 05:25:28 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 214540 kb
Host smart-7b5d8ed1-8380-44a7-a454-e9b2ef21c311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234386763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.234386763
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3901453907
Short name T720
Test name
Test status
Simulation time 62750621 ps
CPU time 3.05 seconds
Started Aug 06 05:25:29 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 209232 kb
Host smart-efb66e53-4243-479f-8df0-3f76ad8feff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901453907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3901453907
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3894593531
Short name T689
Test name
Test status
Simulation time 69142179 ps
CPU time 4.03 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:34 PM PDT 24
Peak memory 218284 kb
Host smart-658ac3ca-235f-4585-802a-4266d7bf145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894593531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3894593531
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2848602710
Short name T650
Test name
Test status
Simulation time 37966979 ps
CPU time 2.56 seconds
Started Aug 06 05:25:31 PM PDT 24
Finished Aug 06 05:25:33 PM PDT 24
Peak memory 208632 kb
Host smart-ed35b333-ad70-4fa9-823f-7696a3979e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848602710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2848602710
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.4045645454
Short name T308
Test name
Test status
Simulation time 317846496 ps
CPU time 3.65 seconds
Started Aug 06 05:25:31 PM PDT 24
Finished Aug 06 05:25:35 PM PDT 24
Peak memory 208768 kb
Host smart-afe54420-706b-475d-a847-9e6094454240
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045645454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.4045645454
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.4173085331
Short name T783
Test name
Test status
Simulation time 123583706 ps
CPU time 1.9 seconds
Started Aug 06 05:25:31 PM PDT 24
Finished Aug 06 05:25:33 PM PDT 24
Peak memory 206812 kb
Host smart-22c3df6c-78b8-4fd3-891f-038605a2c330
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173085331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.4173085331
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.827387097
Short name T492
Test name
Test status
Simulation time 2047493321 ps
CPU time 46.4 seconds
Started Aug 06 05:25:29 PM PDT 24
Finished Aug 06 05:26:16 PM PDT 24
Peak memory 207964 kb
Host smart-e9e55fca-4b9e-4717-ba65-e011899239b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827387097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.827387097
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.382200758
Short name T884
Test name
Test status
Simulation time 195752489 ps
CPU time 1.44 seconds
Started Aug 06 05:25:27 PM PDT 24
Finished Aug 06 05:25:28 PM PDT 24
Peak memory 206672 kb
Host smart-70ceced0-4002-412a-80bf-2aa7125fbf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382200758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.382200758
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1476167701
Short name T395
Test name
Test status
Simulation time 50153326 ps
CPU time 2.13 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 206764 kb
Host smart-8022d925-67d3-41b6-b39a-6441f216af37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476167701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1476167701
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.4215547572
Short name T632
Test name
Test status
Simulation time 2126248870 ps
CPU time 21.6 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:51 PM PDT 24
Peak memory 216740 kb
Host smart-2c70a19a-4962-4db1-8f88-2d2313796e70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215547572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.4215547572
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1717840380
Short name T70
Test name
Test status
Simulation time 935868986 ps
CPU time 16.82 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:55 PM PDT 24
Peak memory 222544 kb
Host smart-a1a62fa1-e71f-40f3-9eb3-2e13a99c84ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717840380 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1717840380
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2578411549
Short name T551
Test name
Test status
Simulation time 157563535 ps
CPU time 4.35 seconds
Started Aug 06 05:25:30 PM PDT 24
Finished Aug 06 05:25:35 PM PDT 24
Peak memory 208044 kb
Host smart-bfd2fd59-a792-4ed8-a95b-79457b4e066c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578411549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2578411549
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3900013330
Short name T41
Test name
Test status
Simulation time 295635087 ps
CPU time 1.55 seconds
Started Aug 06 05:25:26 PM PDT 24
Finished Aug 06 05:25:27 PM PDT 24
Peak memory 209516 kb
Host smart-63631b1a-427e-40f0-b222-e22e008ffd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900013330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3900013330
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2129666277
Short name T787
Test name
Test status
Simulation time 45163147 ps
CPU time 0.82 seconds
Started Aug 06 05:25:35 PM PDT 24
Finished Aug 06 05:25:36 PM PDT 24
Peak memory 205948 kb
Host smart-2fc1c571-c068-4c9d-af3f-9e4a73637cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129666277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2129666277
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1947633062
Short name T359
Test name
Test status
Simulation time 350747663 ps
CPU time 9.17 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:47 PM PDT 24
Peak memory 214568 kb
Host smart-4136bb9f-11e1-4f7e-a114-7fe9008fb1b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1947633062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1947633062
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.4268281666
Short name T899
Test name
Test status
Simulation time 269191097 ps
CPU time 2.16 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:40 PM PDT 24
Peak memory 215748 kb
Host smart-b6c096f2-12af-4b92-a5d7-46a4ef25357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268281666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.4268281666
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1567179329
Short name T598
Test name
Test status
Simulation time 837925081 ps
CPU time 4.82 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:42 PM PDT 24
Peak memory 214372 kb
Host smart-8ed34e32-dff2-4393-ae56-8ed11e56bec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567179329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1567179329
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1791600019
Short name T682
Test name
Test status
Simulation time 86838675 ps
CPU time 3.1 seconds
Started Aug 06 05:25:44 PM PDT 24
Finished Aug 06 05:25:47 PM PDT 24
Peak memory 214196 kb
Host smart-c552026b-99d1-47a7-ab9f-faca6bb44237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791600019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1791600019
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3534902004
Short name T671
Test name
Test status
Simulation time 174977667 ps
CPU time 3.45 seconds
Started Aug 06 05:25:43 PM PDT 24
Finished Aug 06 05:25:46 PM PDT 24
Peak memory 208248 kb
Host smart-8a105152-bb34-46b0-a02e-7c04c9a70089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534902004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3534902004
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3928403725
Short name T564
Test name
Test status
Simulation time 403144697 ps
CPU time 4.58 seconds
Started Aug 06 05:25:43 PM PDT 24
Finished Aug 06 05:25:48 PM PDT 24
Peak memory 209424 kb
Host smart-18c28f2a-9fd5-409c-ade5-30b5996590b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928403725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3928403725
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.666641010
Short name T588
Test name
Test status
Simulation time 88375537 ps
CPU time 3.2 seconds
Started Aug 06 05:25:41 PM PDT 24
Finished Aug 06 05:25:44 PM PDT 24
Peak memory 208696 kb
Host smart-fcd065af-5f9d-4883-9865-a9276196cb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666641010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.666641010
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1304511238
Short name T181
Test name
Test status
Simulation time 37279068 ps
CPU time 2.5 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:41 PM PDT 24
Peak memory 208768 kb
Host smart-e025b714-5edc-4c4a-8a67-041ba6ecdcc6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304511238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1304511238
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.4192814984
Short name T622
Test name
Test status
Simulation time 719176348 ps
CPU time 16.25 seconds
Started Aug 06 05:25:43 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 208648 kb
Host smart-9d561a0f-0b52-4630-beff-763b49187ef7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192814984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4192814984
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2795032065
Short name T520
Test name
Test status
Simulation time 2797906165 ps
CPU time 18.27 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:57 PM PDT 24
Peak memory 209108 kb
Host smart-d414cac1-7910-482d-84c2-a1bd5cc6b487
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795032065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2795032065
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3090900307
Short name T692
Test name
Test status
Simulation time 77187663 ps
CPU time 2.64 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:40 PM PDT 24
Peak memory 216004 kb
Host smart-400f2f9c-65eb-4bc2-9948-9c98f1d95b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090900307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3090900307
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1069971685
Short name T468
Test name
Test status
Simulation time 451030036 ps
CPU time 2.6 seconds
Started Aug 06 05:25:44 PM PDT 24
Finished Aug 06 05:25:47 PM PDT 24
Peak memory 208724 kb
Host smart-4de85907-2447-4546-b74f-7b173c2d44e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069971685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1069971685
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.6608090
Short name T344
Test name
Test status
Simulation time 202998552 ps
CPU time 6.29 seconds
Started Aug 06 05:25:39 PM PDT 24
Finished Aug 06 05:25:45 PM PDT 24
Peak memory 219312 kb
Host smart-c3b88743-68d7-44f2-b403-6c941217c504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6608090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.6608090
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.83688651
Short name T149
Test name
Test status
Simulation time 434126369 ps
CPU time 16.89 seconds
Started Aug 06 05:25:37 PM PDT 24
Finished Aug 06 05:25:54 PM PDT 24
Peak memory 220960 kb
Host smart-43bd8157-2571-4931-8a29-eb94f66ae480
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83688651 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.83688651
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3021743998
Short name T229
Test name
Test status
Simulation time 197509163 ps
CPU time 4.43 seconds
Started Aug 06 05:25:40 PM PDT 24
Finished Aug 06 05:25:45 PM PDT 24
Peak memory 209944 kb
Host smart-1e224bd8-2694-48e0-a40b-045cf7fc1e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021743998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3021743998
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1737899635
Short name T354
Test name
Test status
Simulation time 54143062 ps
CPU time 2.19 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:40 PM PDT 24
Peak memory 210052 kb
Host smart-f2e93093-aa33-4370-80e6-88e418ccb2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737899635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1737899635
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1319099109
Short name T447
Test name
Test status
Simulation time 13399424 ps
CPU time 0.77 seconds
Started Aug 06 05:25:40 PM PDT 24
Finished Aug 06 05:25:41 PM PDT 24
Peak memory 205952 kb
Host smart-698088a2-f589-4fca-8f71-fad17eabed69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319099109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1319099109
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2169779396
Short name T734
Test name
Test status
Simulation time 121465594 ps
CPU time 2.75 seconds
Started Aug 06 05:25:42 PM PDT 24
Finished Aug 06 05:25:45 PM PDT 24
Peak memory 222540 kb
Host smart-fc1865b1-f6c6-4fcf-b3c1-131aff3bb0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169779396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2169779396
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.721186464
Short name T770
Test name
Test status
Simulation time 1593828218 ps
CPU time 4.17 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:43 PM PDT 24
Peak memory 208924 kb
Host smart-cfad9d57-1c7c-4d74-ab32-d6451c8d979a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721186464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.721186464
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1372004970
Short name T530
Test name
Test status
Simulation time 82377891 ps
CPU time 3.93 seconds
Started Aug 06 05:25:44 PM PDT 24
Finished Aug 06 05:25:48 PM PDT 24
Peak memory 214304 kb
Host smart-6d2333eb-bd7d-4d32-999e-a62f767ce165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372004970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1372004970
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1129716029
Short name T570
Test name
Test status
Simulation time 87484552 ps
CPU time 2.19 seconds
Started Aug 06 05:25:41 PM PDT 24
Finished Aug 06 05:25:44 PM PDT 24
Peak memory 218784 kb
Host smart-2af3d32d-6210-424c-bc27-dd642f346631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129716029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1129716029
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.423762686
Short name T591
Test name
Test status
Simulation time 958954442 ps
CPU time 3.68 seconds
Started Aug 06 05:25:43 PM PDT 24
Finished Aug 06 05:25:47 PM PDT 24
Peak memory 207620 kb
Host smart-a01d6bd5-2a8f-4dd5-a15b-c28277e38734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423762686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.423762686
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1023097016
Short name T850
Test name
Test status
Simulation time 229725082 ps
CPU time 6.36 seconds
Started Aug 06 05:25:40 PM PDT 24
Finished Aug 06 05:25:46 PM PDT 24
Peak memory 209472 kb
Host smart-485841cf-730b-4d5c-be6b-309797314b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023097016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1023097016
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1104919373
Short name T583
Test name
Test status
Simulation time 360185832 ps
CPU time 4.97 seconds
Started Aug 06 05:25:37 PM PDT 24
Finished Aug 06 05:25:42 PM PDT 24
Peak memory 208780 kb
Host smart-a3f26548-6fce-4abf-93df-615432112a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104919373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1104919373
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3248098008
Short name T399
Test name
Test status
Simulation time 1085717352 ps
CPU time 5.21 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:43 PM PDT 24
Peak memory 207964 kb
Host smart-703a1be1-2ba8-4e7a-80ae-f1887bcae5ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248098008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3248098008
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.663103551
Short name T905
Test name
Test status
Simulation time 108214022 ps
CPU time 3.83 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:42 PM PDT 24
Peak memory 208552 kb
Host smart-ea1ec5f8-d045-4b69-a7ed-2dcfbc2aa82d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663103551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.663103551
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3145538045
Short name T87
Test name
Test status
Simulation time 64178355 ps
CPU time 2.74 seconds
Started Aug 06 05:25:43 PM PDT 24
Finished Aug 06 05:25:46 PM PDT 24
Peak memory 206872 kb
Host smart-6839d1e5-3829-474f-b510-05b22ec017ab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145538045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3145538045
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1178313625
Short name T767
Test name
Test status
Simulation time 153797426 ps
CPU time 4.39 seconds
Started Aug 06 05:25:44 PM PDT 24
Finished Aug 06 05:25:49 PM PDT 24
Peak memory 209212 kb
Host smart-5a03ed20-734b-4d46-81f6-b9891ffb0b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178313625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1178313625
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.797655185
Short name T363
Test name
Test status
Simulation time 184368442 ps
CPU time 2.43 seconds
Started Aug 06 05:25:42 PM PDT 24
Finished Aug 06 05:25:44 PM PDT 24
Peak memory 206728 kb
Host smart-a83372c2-0064-4749-b9fb-32c9ba17a40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797655185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.797655185
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2736322016
Short name T736
Test name
Test status
Simulation time 178055448 ps
CPU time 9.25 seconds
Started Aug 06 05:25:39 PM PDT 24
Finished Aug 06 05:25:48 PM PDT 24
Peak memory 216300 kb
Host smart-a2cf47f8-6b66-4203-93a1-035a3aa60f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736322016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2736322016
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3922115300
Short name T341
Test name
Test status
Simulation time 706080465 ps
CPU time 4.11 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:43 PM PDT 24
Peak memory 208776 kb
Host smart-4bf46f50-f636-416d-bf92-5655af4d46f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922115300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3922115300
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1846552250
Short name T120
Test name
Test status
Simulation time 80493875 ps
CPU time 2.38 seconds
Started Aug 06 05:25:41 PM PDT 24
Finished Aug 06 05:25:43 PM PDT 24
Peak memory 209968 kb
Host smart-0be3b841-b229-487d-ab41-6967b35c6412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846552250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1846552250
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1596172235
Short name T430
Test name
Test status
Simulation time 15496340 ps
CPU time 0.76 seconds
Started Aug 06 05:24:36 PM PDT 24
Finished Aug 06 05:24:37 PM PDT 24
Peak memory 205960 kb
Host smart-a9c7716b-3fa5-4391-b339-2b92764c36d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596172235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1596172235
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2713952850
Short name T872
Test name
Test status
Simulation time 33531391 ps
CPU time 2.65 seconds
Started Aug 06 05:24:32 PM PDT 24
Finished Aug 06 05:24:35 PM PDT 24
Peak memory 214340 kb
Host smart-ba5f289e-2afd-4f1d-93fd-df5615dbed79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713952850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2713952850
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3695834792
Short name T509
Test name
Test status
Simulation time 267756491 ps
CPU time 1.88 seconds
Started Aug 06 05:24:36 PM PDT 24
Finished Aug 06 05:24:38 PM PDT 24
Peak memory 214444 kb
Host smart-27eeb97a-bf54-437f-ac47-70f7a8e0e6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695834792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3695834792
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.4129744986
Short name T456
Test name
Test status
Simulation time 30082474 ps
CPU time 1.94 seconds
Started Aug 06 05:24:33 PM PDT 24
Finished Aug 06 05:24:35 PM PDT 24
Peak memory 207652 kb
Host smart-081422a3-ae6e-4faf-bb14-ead9568c4aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129744986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.4129744986
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4288560104
Short name T100
Test name
Test status
Simulation time 177026787 ps
CPU time 5.6 seconds
Started Aug 06 05:24:34 PM PDT 24
Finished Aug 06 05:24:40 PM PDT 24
Peak memory 214324 kb
Host smart-78aa0d12-a1ad-4064-9260-ef5d8cfd8b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288560104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4288560104
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.400738741
Short name T321
Test name
Test status
Simulation time 212409339 ps
CPU time 6.4 seconds
Started Aug 06 05:24:35 PM PDT 24
Finished Aug 06 05:24:41 PM PDT 24
Peak memory 214272 kb
Host smart-4faf00d0-da74-4104-bb0e-2cc41ed49714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400738741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.400738741
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2988945664
Short name T266
Test name
Test status
Simulation time 58564691 ps
CPU time 3.24 seconds
Started Aug 06 05:24:34 PM PDT 24
Finished Aug 06 05:24:37 PM PDT 24
Peak memory 210476 kb
Host smart-645f385d-100b-479c-ab1a-5928e3beb499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988945664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2988945664
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1421712935
Short name T233
Test name
Test status
Simulation time 1923773674 ps
CPU time 14.93 seconds
Started Aug 06 05:24:31 PM PDT 24
Finished Aug 06 05:24:46 PM PDT 24
Peak memory 214344 kb
Host smart-a6fee397-63f4-4cd1-8c87-714bdfe149d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421712935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1421712935
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1108706713
Short name T705
Test name
Test status
Simulation time 61511483 ps
CPU time 2.78 seconds
Started Aug 06 05:24:33 PM PDT 24
Finished Aug 06 05:24:36 PM PDT 24
Peak memory 206884 kb
Host smart-1b15c12a-df3a-4d74-9cf3-31b482c360e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108706713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1108706713
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1361712291
Short name T80
Test name
Test status
Simulation time 543410093 ps
CPU time 6.21 seconds
Started Aug 06 05:24:33 PM PDT 24
Finished Aug 06 05:24:39 PM PDT 24
Peak memory 208740 kb
Host smart-12fe1aed-724c-4447-ad2a-b1ed530daf72
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361712291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1361712291
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2588904944
Short name T531
Test name
Test status
Simulation time 86545292 ps
CPU time 2.85 seconds
Started Aug 06 05:24:33 PM PDT 24
Finished Aug 06 05:24:36 PM PDT 24
Peak memory 208828 kb
Host smart-de31e098-793b-445c-af0e-37160a9ac231
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588904944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2588904944
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3785439271
Short name T827
Test name
Test status
Simulation time 200916277 ps
CPU time 3.09 seconds
Started Aug 06 05:24:33 PM PDT 24
Finished Aug 06 05:24:36 PM PDT 24
Peak memory 208816 kb
Host smart-443e126b-f199-4017-a894-8b2581e4eb0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785439271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3785439271
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.820112989
Short name T592
Test name
Test status
Simulation time 81154383 ps
CPU time 3.38 seconds
Started Aug 06 05:24:34 PM PDT 24
Finished Aug 06 05:24:37 PM PDT 24
Peak memory 209480 kb
Host smart-aba7f525-3ee8-4300-90ab-b17fafcbe562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820112989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.820112989
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1347473519
Short name T679
Test name
Test status
Simulation time 33138256 ps
CPU time 2.21 seconds
Started Aug 06 05:24:33 PM PDT 24
Finished Aug 06 05:24:35 PM PDT 24
Peak memory 206928 kb
Host smart-969ceee1-072e-4a5c-b92c-a47527f4bf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347473519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1347473519
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2589191448
Short name T175
Test name
Test status
Simulation time 123219594664 ps
CPU time 448.71 seconds
Started Aug 06 05:24:35 PM PDT 24
Finished Aug 06 05:32:04 PM PDT 24
Peak memory 221648 kb
Host smart-c6bdde1b-d597-41b8-ba8a-23061ead2a31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589191448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2589191448
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1739328729
Short name T238
Test name
Test status
Simulation time 395510337 ps
CPU time 5.14 seconds
Started Aug 06 05:24:36 PM PDT 24
Finished Aug 06 05:24:41 PM PDT 24
Peak memory 210228 kb
Host smart-df0c3827-4db0-4d59-9ca2-e35a503f2d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739328729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1739328729
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2743811308
Short name T587
Test name
Test status
Simulation time 189424009 ps
CPU time 2.5 seconds
Started Aug 06 05:24:35 PM PDT 24
Finished Aug 06 05:24:38 PM PDT 24
Peak memory 209700 kb
Host smart-699ee414-b063-459b-876c-3b7b5072a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743811308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2743811308
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1451310366
Short name T408
Test name
Test status
Simulation time 35434706 ps
CPU time 0.92 seconds
Started Aug 06 05:25:55 PM PDT 24
Finished Aug 06 05:25:56 PM PDT 24
Peak memory 205928 kb
Host smart-51ae8f26-eff3-4e54-9c34-293b4ccc1673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451310366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1451310366
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1969931546
Short name T289
Test name
Test status
Simulation time 188872077 ps
CPU time 10.16 seconds
Started Aug 06 05:25:43 PM PDT 24
Finished Aug 06 05:25:53 PM PDT 24
Peak memory 215892 kb
Host smart-1525f003-60d0-4099-b427-24c3aa3d13b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969931546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1969931546
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3397796220
Short name T67
Test name
Test status
Simulation time 93281920 ps
CPU time 3.82 seconds
Started Aug 06 05:25:38 PM PDT 24
Finished Aug 06 05:25:42 PM PDT 24
Peak memory 207020 kb
Host smart-f6028704-624a-4765-9a8e-3e51f210232b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397796220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3397796220
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2713788396
Short name T326
Test name
Test status
Simulation time 302318275 ps
CPU time 8.44 seconds
Started Aug 06 05:25:53 PM PDT 24
Finished Aug 06 05:26:02 PM PDT 24
Peak memory 214412 kb
Host smart-4f871dee-d3dc-4ce5-b9a1-9ee70cadff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713788396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2713788396
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3345360500
Short name T861
Test name
Test status
Simulation time 106960493 ps
CPU time 2.93 seconds
Started Aug 06 05:25:52 PM PDT 24
Finished Aug 06 05:25:55 PM PDT 24
Peak memory 214264 kb
Host smart-96f067ef-75f3-411c-bb92-641310c2b745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345360500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3345360500
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1585590550
Short name T837
Test name
Test status
Simulation time 299641454 ps
CPU time 13.15 seconds
Started Aug 06 05:25:43 PM PDT 24
Finished Aug 06 05:25:56 PM PDT 24
Peak memory 209664 kb
Host smart-ee4d2d6b-cc26-44e4-aa88-72ba49d705cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585590550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1585590550
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3032984026
Short name T260
Test name
Test status
Simulation time 88467746 ps
CPU time 4.65 seconds
Started Aug 06 05:25:40 PM PDT 24
Finished Aug 06 05:25:44 PM PDT 24
Peak memory 209284 kb
Host smart-9d704bc9-39f0-4b2b-926b-d29d9f1bae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032984026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3032984026
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1452243210
Short name T687
Test name
Test status
Simulation time 179584320 ps
CPU time 4.12 seconds
Started Aug 06 05:25:41 PM PDT 24
Finished Aug 06 05:25:46 PM PDT 24
Peak memory 208612 kb
Host smart-8c6602af-1917-4298-8a7e-bd05b738b114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452243210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1452243210
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1586830889
Short name T398
Test name
Test status
Simulation time 153383149 ps
CPU time 2.74 seconds
Started Aug 06 05:25:42 PM PDT 24
Finished Aug 06 05:25:45 PM PDT 24
Peak memory 206952 kb
Host smart-b28e0ed0-f41d-48ba-8f70-c28051ccc31e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586830889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1586830889
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4065285440
Short name T472
Test name
Test status
Simulation time 286139420 ps
CPU time 3.02 seconds
Started Aug 06 05:25:40 PM PDT 24
Finished Aug 06 05:25:43 PM PDT 24
Peak memory 208840 kb
Host smart-d2171f26-d418-44c9-9851-74c27d8f473f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065285440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4065285440
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1514620744
Short name T480
Test name
Test status
Simulation time 605335160 ps
CPU time 4.64 seconds
Started Aug 06 05:25:39 PM PDT 24
Finished Aug 06 05:25:44 PM PDT 24
Peak memory 208864 kb
Host smart-8a499049-a7e1-469a-8de9-782ebb43c098
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514620744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1514620744
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1316338588
Short name T314
Test name
Test status
Simulation time 827294604 ps
CPU time 10.03 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:26:07 PM PDT 24
Peak memory 208504 kb
Host smart-323ff443-4457-4d3c-98fe-75cbefdc7869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316338588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1316338588
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.909462256
Short name T786
Test name
Test status
Simulation time 414779995 ps
CPU time 4.39 seconds
Started Aug 06 05:25:43 PM PDT 24
Finished Aug 06 05:25:47 PM PDT 24
Peak memory 208600 kb
Host smart-a75fed62-119b-4f91-89e5-0854bae61205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909462256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.909462256
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.685769377
Short name T318
Test name
Test status
Simulation time 1685682620 ps
CPU time 17.11 seconds
Started Aug 06 05:25:53 PM PDT 24
Finished Aug 06 05:26:10 PM PDT 24
Peak memory 218356 kb
Host smart-02395a36-364e-4cb3-937e-bf8a13671735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685769377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.685769377
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3852413089
Short name T159
Test name
Test status
Simulation time 341671905 ps
CPU time 1.9 seconds
Started Aug 06 05:25:52 PM PDT 24
Finished Aug 06 05:25:54 PM PDT 24
Peak memory 209672 kb
Host smart-13d0d9c8-a006-4420-b5cc-530604a3a1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852413089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3852413089
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.910234690
Short name T612
Test name
Test status
Simulation time 34505579 ps
CPU time 0.75 seconds
Started Aug 06 05:25:55 PM PDT 24
Finished Aug 06 05:25:55 PM PDT 24
Peak memory 205780 kb
Host smart-ff36d724-5fc8-4840-9eed-3b5b43b79150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910234690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.910234690
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1691248174
Short name T387
Test name
Test status
Simulation time 53268922 ps
CPU time 3.83 seconds
Started Aug 06 05:25:55 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 214248 kb
Host smart-84a626f2-0171-4c13-98a6-ca87c6363155
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1691248174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1691248174
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1196177239
Short name T576
Test name
Test status
Simulation time 1396193763 ps
CPU time 11.7 seconds
Started Aug 06 05:25:53 PM PDT 24
Finished Aug 06 05:26:05 PM PDT 24
Peak memory 214616 kb
Host smart-39976892-474c-4660-a921-1d84262cd0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196177239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1196177239
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1354418189
Short name T518
Test name
Test status
Simulation time 50325261 ps
CPU time 2.03 seconds
Started Aug 06 05:25:56 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 214396 kb
Host smart-1fbca471-dee4-4e04-8398-3feab34c5939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354418189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1354418189
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2956230804
Short name T880
Test name
Test status
Simulation time 372899324 ps
CPU time 7.54 seconds
Started Aug 06 05:25:51 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 214220 kb
Host smart-d1e7b42f-88bb-44da-bd5d-c3a5910095c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956230804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2956230804
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2002121275
Short name T245
Test name
Test status
Simulation time 38253080 ps
CPU time 2.14 seconds
Started Aug 06 05:25:52 PM PDT 24
Finished Aug 06 05:25:54 PM PDT 24
Peak memory 214156 kb
Host smart-c4780ee0-e39c-4623-ab99-29278e0eda50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002121275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2002121275
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1510258963
Short name T640
Test name
Test status
Simulation time 169510082 ps
CPU time 3.22 seconds
Started Aug 06 05:25:51 PM PDT 24
Finished Aug 06 05:25:55 PM PDT 24
Peak memory 214328 kb
Host smart-cc366b7b-f24d-44cc-a7f8-5238d9f9e273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510258963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1510258963
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1672529629
Short name T178
Test name
Test status
Simulation time 1448301762 ps
CPU time 10.34 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:26:07 PM PDT 24
Peak memory 209436 kb
Host smart-c43869cc-3c97-4ddf-a7c0-ebe87ca8c8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672529629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1672529629
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.4053678140
Short name T867
Test name
Test status
Simulation time 83288529 ps
CPU time 1.91 seconds
Started Aug 06 05:25:53 PM PDT 24
Finished Aug 06 05:25:55 PM PDT 24
Peak memory 206804 kb
Host smart-3ec48018-43be-4486-832d-c93e29a9d975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053678140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.4053678140
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3726874388
Short name T317
Test name
Test status
Simulation time 1472526595 ps
CPU time 20.83 seconds
Started Aug 06 05:25:54 PM PDT 24
Finished Aug 06 05:26:15 PM PDT 24
Peak memory 208652 kb
Host smart-d380f567-0b0a-4d8f-b9fd-156de4b284ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726874388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3726874388
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1504114569
Short name T349
Test name
Test status
Simulation time 127664688 ps
CPU time 3.13 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 208908 kb
Host smart-573c6b22-051a-42ae-8981-5c5fbc52aa2a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504114569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1504114569
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3850920273
Short name T886
Test name
Test status
Simulation time 49875537 ps
CPU time 2.75 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 206828 kb
Host smart-e524125f-ebe3-45da-b0cc-baa7a2bd2463
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850920273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3850920273
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.4189234809
Short name T217
Test name
Test status
Simulation time 61859276 ps
CPU time 2.51 seconds
Started Aug 06 05:25:53 PM PDT 24
Finished Aug 06 05:25:56 PM PDT 24
Peak memory 215880 kb
Host smart-53d2665c-5609-4c7d-a89c-783ff1e8ed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189234809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4189234809
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.244533376
Short name T627
Test name
Test status
Simulation time 33300678 ps
CPU time 2.08 seconds
Started Aug 06 05:25:54 PM PDT 24
Finished Aug 06 05:25:56 PM PDT 24
Peak memory 206772 kb
Host smart-67cce507-cc78-4f6c-902d-607d4b25a5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244533376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.244533376
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3660724371
Short name T500
Test name
Test status
Simulation time 934441998 ps
CPU time 4.05 seconds
Started Aug 06 05:25:53 PM PDT 24
Finished Aug 06 05:25:57 PM PDT 24
Peak memory 207556 kb
Host smart-f9efc872-b365-453d-86c0-a4625706937a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660724371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3660724371
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1034423540
Short name T58
Test name
Test status
Simulation time 375439585 ps
CPU time 3.34 seconds
Started Aug 06 05:25:52 PM PDT 24
Finished Aug 06 05:25:56 PM PDT 24
Peak memory 210380 kb
Host smart-485a1561-af29-4f99-b354-7ea189e32935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034423540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1034423540
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1698496649
Short name T496
Test name
Test status
Simulation time 22965071 ps
CPU time 0.78 seconds
Started Aug 06 05:25:56 PM PDT 24
Finished Aug 06 05:25:57 PM PDT 24
Peak memory 205568 kb
Host smart-07160f89-5f25-43be-acf6-734ecffebef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698496649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1698496649
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1977829893
Short name T733
Test name
Test status
Simulation time 257832252 ps
CPU time 2.54 seconds
Started Aug 06 05:25:56 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 207612 kb
Host smart-7c419904-9433-4bb1-a03e-a59eeb2b121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977829893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1977829893
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2111089543
Short name T282
Test name
Test status
Simulation time 132096700 ps
CPU time 5.51 seconds
Started Aug 06 05:25:53 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 222356 kb
Host smart-51c21700-bf43-4eb2-aa6c-3be38b8c5c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111089543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2111089543
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2555417583
Short name T191
Test name
Test status
Simulation time 362039397 ps
CPU time 3.19 seconds
Started Aug 06 05:25:54 PM PDT 24
Finished Aug 06 05:25:57 PM PDT 24
Peak memory 214644 kb
Host smart-f4a0d36b-7deb-4391-ad91-9639b342dfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555417583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2555417583
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2530271223
Short name T831
Test name
Test status
Simulation time 258779693 ps
CPU time 4.68 seconds
Started Aug 06 05:25:52 PM PDT 24
Finished Aug 06 05:25:57 PM PDT 24
Peak memory 218096 kb
Host smart-fd1c2832-b17f-49c9-bd93-d797846cc0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530271223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2530271223
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1327237071
Short name T312
Test name
Test status
Simulation time 149726329 ps
CPU time 3.22 seconds
Started Aug 06 05:25:53 PM PDT 24
Finished Aug 06 05:25:57 PM PDT 24
Peak memory 208704 kb
Host smart-13a20884-4fdc-451f-8518-86a05177d238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327237071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1327237071
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.223753578
Short name T450
Test name
Test status
Simulation time 6513459797 ps
CPU time 46.72 seconds
Started Aug 06 05:25:54 PM PDT 24
Finished Aug 06 05:26:41 PM PDT 24
Peak memory 208456 kb
Host smart-2a2a3567-49f1-498b-81fb-d72d1c955232
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223753578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.223753578
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3674749195
Short name T642
Test name
Test status
Simulation time 422311557 ps
CPU time 5.8 seconds
Started Aug 06 05:25:56 PM PDT 24
Finished Aug 06 05:26:02 PM PDT 24
Peak memory 209088 kb
Host smart-5223a39e-b052-4f95-a7fc-3e1e12048c63
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674749195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3674749195
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3632147759
Short name T674
Test name
Test status
Simulation time 25735924 ps
CPU time 1.92 seconds
Started Aug 06 05:25:54 PM PDT 24
Finished Aug 06 05:25:56 PM PDT 24
Peak memory 208748 kb
Host smart-f24e1480-29a0-4ad1-88b8-7204fba9c113
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632147759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3632147759
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3362012327
Short name T894
Test name
Test status
Simulation time 316795263 ps
CPU time 3.27 seconds
Started Aug 06 05:26:00 PM PDT 24
Finished Aug 06 05:26:03 PM PDT 24
Peak memory 208584 kb
Host smart-db2b12c4-004d-41b1-a07a-514a4a9a28a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362012327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3362012327
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3046402744
Short name T364
Test name
Test status
Simulation time 463518815 ps
CPU time 3.24 seconds
Started Aug 06 05:25:55 PM PDT 24
Finished Aug 06 05:25:58 PM PDT 24
Peak memory 208720 kb
Host smart-25a079d4-3df3-4f4f-8649-34dee347a38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046402744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3046402744
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.777395144
Short name T738
Test name
Test status
Simulation time 203660110 ps
CPU time 6.45 seconds
Started Aug 06 05:25:54 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 210340 kb
Host smart-3e79858f-6bf5-476d-b86b-9aa5596fecfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777395144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.777395144
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1706598228
Short name T33
Test name
Test status
Simulation time 55124365 ps
CPU time 2.44 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 210312 kb
Host smart-031da865-224e-4541-ba68-6f367cba2f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706598228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1706598228
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3036617535
Short name T510
Test name
Test status
Simulation time 14190229 ps
CPU time 0.78 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:25:58 PM PDT 24
Peak memory 205952 kb
Host smart-95764e48-690c-4cd0-bc92-f420e48ee81b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036617535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3036617535
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3701535221
Short name T251
Test name
Test status
Simulation time 3484370940 ps
CPU time 13.5 seconds
Started Aug 06 05:25:55 PM PDT 24
Finished Aug 06 05:26:09 PM PDT 24
Peak memory 215652 kb
Host smart-62ee8fef-18e6-4923-a5fa-1e81172f90e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701535221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3701535221
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.28823229
Short name T9
Test name
Test status
Simulation time 141409979 ps
CPU time 3.19 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 221728 kb
Host smart-ba118cb2-ae6e-40a2-8ab1-807bf97f2b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28823229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.28823229
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1659093180
Short name T459
Test name
Test status
Simulation time 5601625972 ps
CPU time 41.32 seconds
Started Aug 06 05:25:56 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 208804 kb
Host smart-7a4aa42a-b10f-4fdb-a234-e19a9e47514b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659093180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1659093180
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1985984074
Short name T263
Test name
Test status
Simulation time 54421938 ps
CPU time 2.26 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 214396 kb
Host smart-01cdb00e-fe5f-4ec4-ab1d-d89fc239883c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985984074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1985984074
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2916885212
Short name T759
Test name
Test status
Simulation time 43918496 ps
CPU time 2.7 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 214264 kb
Host smart-a72382cc-79f4-4fdf-b83c-d1b2a1e9d37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916885212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2916885212
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2418001510
Short name T339
Test name
Test status
Simulation time 84635262 ps
CPU time 3.25 seconds
Started Aug 06 05:25:56 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 222580 kb
Host smart-a854b9f8-b3a3-401a-8a1e-cfdb094dffdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418001510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2418001510
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2514752472
Short name T448
Test name
Test status
Simulation time 106415383 ps
CPU time 3.2 seconds
Started Aug 06 05:25:55 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 218408 kb
Host smart-4c1e6534-486d-452d-bbc7-c4ca0590d238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514752472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2514752472
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2433445868
Short name T2
Test name
Test status
Simulation time 128631970 ps
CPU time 2.79 seconds
Started Aug 06 05:26:00 PM PDT 24
Finished Aug 06 05:26:03 PM PDT 24
Peak memory 208204 kb
Host smart-da5f73e0-ae85-4af2-b610-08005e41aab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433445868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2433445868
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3596277559
Short name T365
Test name
Test status
Simulation time 404837359 ps
CPU time 10.4 seconds
Started Aug 06 05:25:55 PM PDT 24
Finished Aug 06 05:26:06 PM PDT 24
Peak memory 208352 kb
Host smart-965bb3c1-e788-4223-9c3e-1058bb331c2b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596277559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3596277559
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2285111726
Short name T537
Test name
Test status
Simulation time 566878712 ps
CPU time 2.38 seconds
Started Aug 06 05:25:56 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 206572 kb
Host smart-507bf8e9-962f-41f0-8593-ba8f28812d25
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285111726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2285111726
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3545188103
Short name T330
Test name
Test status
Simulation time 206927060 ps
CPU time 5.7 seconds
Started Aug 06 05:25:55 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 207816 kb
Host smart-303430b9-2225-4341-96cd-cf9c835ac071
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545188103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3545188103
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2164538560
Short name T580
Test name
Test status
Simulation time 73808877 ps
CPU time 1.71 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 209380 kb
Host smart-53393127-7406-468c-90a8-e21f031ecb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164538560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2164538560
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1074974212
Short name T887
Test name
Test status
Simulation time 273893664 ps
CPU time 3.23 seconds
Started Aug 06 05:25:56 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 206596 kb
Host smart-131d6b97-a900-4df0-98ae-cb86351c73a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074974212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1074974212
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2997176884
Short name T206
Test name
Test status
Simulation time 2208112999 ps
CPU time 73.38 seconds
Started Aug 06 05:25:58 PM PDT 24
Finished Aug 06 05:27:11 PM PDT 24
Peak memory 215268 kb
Host smart-4505c381-d10f-4f35-8f04-63e3dab5e2ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997176884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2997176884
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.249092545
Short name T117
Test name
Test status
Simulation time 368766154 ps
CPU time 8.82 seconds
Started Aug 06 05:25:55 PM PDT 24
Finished Aug 06 05:26:04 PM PDT 24
Peak memory 222524 kb
Host smart-bce754ac-47d0-4ab0-85a9-752ca45c8425
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249092545 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.249092545
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1467745082
Short name T179
Test name
Test status
Simulation time 449071269 ps
CPU time 4.9 seconds
Started Aug 06 05:25:54 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 214324 kb
Host smart-af16309d-337d-4dbd-a8e9-efe28eb471cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467745082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1467745082
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1017065454
Short name T497
Test name
Test status
Simulation time 564243878 ps
CPU time 2.49 seconds
Started Aug 06 05:25:56 PM PDT 24
Finished Aug 06 05:25:58 PM PDT 24
Peak memory 210032 kb
Host smart-3932d0a7-e994-4834-a89b-f59e4db67483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017065454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1017065454
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2442239422
Short name T609
Test name
Test status
Simulation time 21744526 ps
CPU time 1.02 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:16 PM PDT 24
Peak memory 206000 kb
Host smart-3db246e7-6736-436f-a0c5-be9d6c2f896d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442239422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2442239422
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1837587178
Short name T10
Test name
Test status
Simulation time 74882032 ps
CPU time 1.78 seconds
Started Aug 06 05:25:58 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 209488 kb
Host smart-e7241b68-b0bc-4f1b-9933-30b7b5b8901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837587178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1837587178
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1756754949
Short name T216
Test name
Test status
Simulation time 25077759 ps
CPU time 1.78 seconds
Started Aug 06 05:25:59 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 207568 kb
Host smart-759f9c02-d80b-45ee-8cf6-64f87b6b5c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756754949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1756754949
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.198745840
Short name T458
Test name
Test status
Simulation time 92735528 ps
CPU time 1.82 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:25:59 PM PDT 24
Peak memory 214196 kb
Host smart-bfbfba96-9649-42ec-8cc9-965994bb149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198745840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.198745840
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3593721621
Short name T243
Test name
Test status
Simulation time 881794274 ps
CPU time 4.55 seconds
Started Aug 06 05:25:59 PM PDT 24
Finished Aug 06 05:26:03 PM PDT 24
Peak memory 222540 kb
Host smart-1d9c12f2-86b3-4e95-b9c0-3ead4155b84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593721621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3593721621
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2156449982
Short name T864
Test name
Test status
Simulation time 260462521 ps
CPU time 2.95 seconds
Started Aug 06 05:25:55 PM PDT 24
Finished Aug 06 05:25:58 PM PDT 24
Peak memory 214444 kb
Host smart-b50dd2e3-b10a-48b2-aeaa-b0fb2bd5b006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156449982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2156449982
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2710944794
Short name T249
Test name
Test status
Simulation time 303402951 ps
CPU time 3.92 seconds
Started Aug 06 05:26:01 PM PDT 24
Finished Aug 06 05:26:05 PM PDT 24
Peak memory 218484 kb
Host smart-60b7210f-30c5-494c-9a72-490c0bcb6c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710944794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2710944794
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.630349329
Short name T743
Test name
Test status
Simulation time 488630601 ps
CPU time 5.53 seconds
Started Aug 06 05:25:56 PM PDT 24
Finished Aug 06 05:26:02 PM PDT 24
Peak memory 208392 kb
Host smart-bad7f027-869f-4709-8b93-2cb674a2a780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630349329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.630349329
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2639393367
Short name T313
Test name
Test status
Simulation time 143056591 ps
CPU time 4.3 seconds
Started Aug 06 05:25:58 PM PDT 24
Finished Aug 06 05:26:02 PM PDT 24
Peak memory 208256 kb
Host smart-963bffe8-ab17-4bb8-86ee-9f63f69cc508
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639393367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2639393367
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3090826515
Short name T702
Test name
Test status
Simulation time 2745284276 ps
CPU time 51.41 seconds
Started Aug 06 05:25:53 PM PDT 24
Finished Aug 06 05:26:44 PM PDT 24
Peak memory 209148 kb
Host smart-1a29fed0-2d83-4c69-96d9-68eaf40469f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090826515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3090826515
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2462883291
Short name T664
Test name
Test status
Simulation time 20581735 ps
CPU time 1.69 seconds
Started Aug 06 05:26:01 PM PDT 24
Finished Aug 06 05:26:03 PM PDT 24
Peak memory 207336 kb
Host smart-f6be1adb-b40a-45cb-94aa-286c8ebed288
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462883291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2462883291
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1789166761
Short name T506
Test name
Test status
Simulation time 145051531 ps
CPU time 2.39 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 207936 kb
Host smart-bc43dcd1-6fb7-4bf6-a37e-dfa7749687f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789166761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1789166761
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2630145758
Short name T467
Test name
Test status
Simulation time 5908889655 ps
CPU time 28.8 seconds
Started Aug 06 05:25:59 PM PDT 24
Finished Aug 06 05:26:28 PM PDT 24
Peak memory 208628 kb
Host smart-84f4d611-99be-492a-8332-7d0fde425a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630145758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2630145758
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.725023898
Short name T257
Test name
Test status
Simulation time 354450847 ps
CPU time 18.38 seconds
Started Aug 06 05:26:14 PM PDT 24
Finished Aug 06 05:26:33 PM PDT 24
Peak memory 216132 kb
Host smart-7d29c2f2-8cc7-4e7d-a4b7-eb160f771688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725023898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.725023898
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2747035729
Short name T874
Test name
Test status
Simulation time 145206152 ps
CPU time 2.96 seconds
Started Aug 06 05:25:57 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 208280 kb
Host smart-c7b40a21-7732-44f9-aaf1-b93f0aee0c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747035729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2747035729
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.782838902
Short name T794
Test name
Test status
Simulation time 37519366 ps
CPU time 2.1 seconds
Started Aug 06 05:25:58 PM PDT 24
Finished Aug 06 05:26:01 PM PDT 24
Peak memory 209980 kb
Host smart-34dc042c-c3fc-4899-95cc-3ae2ffdcea08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782838902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.782838902
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3688431153
Short name T404
Test name
Test status
Simulation time 65434246 ps
CPU time 0.87 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:16 PM PDT 24
Peak memory 205884 kb
Host smart-e8d89b71-2700-4740-a240-37d75883dbd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688431153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3688431153
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3019010040
Short name T212
Test name
Test status
Simulation time 589540509 ps
CPU time 7.25 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:23 PM PDT 24
Peak memory 214412 kb
Host smart-5b63f88c-38a4-4eb0-a4ef-2768c8f6ce6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3019010040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3019010040
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1591568574
Short name T20
Test name
Test status
Simulation time 143062221 ps
CPU time 2.22 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:18 PM PDT 24
Peak memory 221096 kb
Host smart-8363f84b-4fea-4903-9f88-6374a0a8214a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591568574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1591568574
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.105787975
Short name T65
Test name
Test status
Simulation time 26825809 ps
CPU time 1.38 seconds
Started Aug 06 05:26:18 PM PDT 24
Finished Aug 06 05:26:19 PM PDT 24
Peak memory 207508 kb
Host smart-dbaa19a1-9acc-4c23-8995-b5eb3025f7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105787975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.105787975
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1089612651
Short name T856
Test name
Test status
Simulation time 636928619 ps
CPU time 4.26 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:20 PM PDT 24
Peak memory 214404 kb
Host smart-9ac4913e-d4cb-4537-9043-ce4f24a9c36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089612651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1089612651
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1117720102
Short name T205
Test name
Test status
Simulation time 1403511894 ps
CPU time 5.73 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:22 PM PDT 24
Peak memory 209192 kb
Host smart-84acb5bb-c450-45ab-b3fd-48f19c5505b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117720102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1117720102
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.4122520550
Short name T465
Test name
Test status
Simulation time 310699847 ps
CPU time 8.77 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:25 PM PDT 24
Peak memory 208116 kb
Host smart-7d302ddc-5892-49e2-ac2e-29af1eb9492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122520550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.4122520550
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.4091291666
Short name T340
Test name
Test status
Simulation time 169982804 ps
CPU time 2.73 seconds
Started Aug 06 05:26:14 PM PDT 24
Finished Aug 06 05:26:17 PM PDT 24
Peak memory 207040 kb
Host smart-dcebaae9-2e88-4035-a5db-cace2446165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091291666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4091291666
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2387673883
Short name T445
Test name
Test status
Simulation time 12301328327 ps
CPU time 35.44 seconds
Started Aug 06 05:26:13 PM PDT 24
Finished Aug 06 05:26:49 PM PDT 24
Peak memory 208016 kb
Host smart-5935f57f-69c3-4748-8343-732609e9d2fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387673883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2387673883
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1410866972
Short name T259
Test name
Test status
Simulation time 809914000 ps
CPU time 28.37 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:44 PM PDT 24
Peak memory 208920 kb
Host smart-ef10467e-8b49-4b27-a19e-c88b4e484310
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410866972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1410866972
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1291331760
Short name T411
Test name
Test status
Simulation time 191444224 ps
CPU time 2.48 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:17 PM PDT 24
Peak memory 208168 kb
Host smart-af6859d2-7847-4c00-a2be-a4b9f2d8515e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291331760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1291331760
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2334693002
Short name T250
Test name
Test status
Simulation time 266969415 ps
CPU time 4.11 seconds
Started Aug 06 05:26:18 PM PDT 24
Finished Aug 06 05:26:22 PM PDT 24
Peak memory 215672 kb
Host smart-8a10a708-047a-4f99-a265-91e5ced8b9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334693002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2334693002
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3061272133
Short name T879
Test name
Test status
Simulation time 190208237 ps
CPU time 2.66 seconds
Started Aug 06 05:26:14 PM PDT 24
Finished Aug 06 05:26:17 PM PDT 24
Peak memory 206924 kb
Host smart-3a2bca67-e291-451e-97f5-38f16d4e1339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061272133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3061272133
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2086105000
Short name T775
Test name
Test status
Simulation time 353371116 ps
CPU time 4.73 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:21 PM PDT 24
Peak memory 217840 kb
Host smart-046c7e8e-39ee-450f-a9b1-4226048627c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086105000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2086105000
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4242996932
Short name T156
Test name
Test status
Simulation time 1320201401 ps
CPU time 2.55 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:18 PM PDT 24
Peak memory 209668 kb
Host smart-074d7158-ca02-46e6-ac22-b69e8f4bd688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242996932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4242996932
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3462880363
Short name T3
Test name
Test status
Simulation time 11184872 ps
CPU time 0.71 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:16 PM PDT 24
Peak memory 205964 kb
Host smart-2a6f71a0-330f-4d7e-b27d-7d23eb9d3faa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462880363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3462880363
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.960904293
Short name T376
Test name
Test status
Simulation time 120126610 ps
CPU time 3.95 seconds
Started Aug 06 05:26:17 PM PDT 24
Finished Aug 06 05:26:21 PM PDT 24
Peak memory 214332 kb
Host smart-0dba5116-0f6e-450e-a7b5-5f2f736ea4ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960904293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.960904293
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2164514051
Short name T346
Test name
Test status
Simulation time 198521361 ps
CPU time 6.85 seconds
Started Aug 06 05:26:20 PM PDT 24
Finished Aug 06 05:26:27 PM PDT 24
Peak memory 220600 kb
Host smart-624d4eed-9a15-4887-a03e-7951cb8b28f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164514051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2164514051
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2892411739
Short name T900
Test name
Test status
Simulation time 111002918 ps
CPU time 1.86 seconds
Started Aug 06 05:26:18 PM PDT 24
Finished Aug 06 05:26:20 PM PDT 24
Peak memory 214436 kb
Host smart-1fb5075c-b532-46e0-a060-f6a311a40490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892411739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2892411739
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.882154039
Short name T828
Test name
Test status
Simulation time 228606518 ps
CPU time 2.39 seconds
Started Aug 06 05:26:19 PM PDT 24
Finished Aug 06 05:26:22 PM PDT 24
Peak memory 208524 kb
Host smart-499cda14-212e-4ebd-a532-583347260c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882154039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.882154039
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2677970964
Short name T244
Test name
Test status
Simulation time 36592215 ps
CPU time 2.17 seconds
Started Aug 06 05:26:19 PM PDT 24
Finished Aug 06 05:26:22 PM PDT 24
Peak memory 214272 kb
Host smart-f3c69880-e738-48ad-85dd-5c6ab81557df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677970964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2677970964
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.785627557
Short name T670
Test name
Test status
Simulation time 398365367 ps
CPU time 3.39 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:20 PM PDT 24
Peak memory 214220 kb
Host smart-711754e6-9f38-4cf3-b5b1-011d84bf38ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785627557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.785627557
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2729181787
Short name T350
Test name
Test status
Simulation time 757925518 ps
CPU time 7.63 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:24 PM PDT 24
Peak memory 207688 kb
Host smart-1ea38db6-434c-4656-b753-4bf5fdf5b903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729181787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2729181787
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2926217890
Short name T903
Test name
Test status
Simulation time 73902954 ps
CPU time 3.48 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:19 PM PDT 24
Peak memory 208756 kb
Host smart-7620a597-3dcc-4889-9157-ab77e96a3d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926217890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2926217890
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.4150515417
Short name T716
Test name
Test status
Simulation time 31255193 ps
CPU time 2.36 seconds
Started Aug 06 05:26:17 PM PDT 24
Finished Aug 06 05:26:20 PM PDT 24
Peak memory 206876 kb
Host smart-b1c9070e-9200-40cd-ad8d-f9ed559d9e4e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150515417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.4150515417
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2849309406
Short name T508
Test name
Test status
Simulation time 112927683 ps
CPU time 4.84 seconds
Started Aug 06 05:26:18 PM PDT 24
Finished Aug 06 05:26:23 PM PDT 24
Peak memory 207028 kb
Host smart-be46583c-85f3-4386-b56e-aca97314efef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849309406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2849309406
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1693406651
Short name T554
Test name
Test status
Simulation time 166637843 ps
CPU time 3.15 seconds
Started Aug 06 05:26:17 PM PDT 24
Finished Aug 06 05:26:20 PM PDT 24
Peak memory 206844 kb
Host smart-ec7df868-31f5-4b09-ada2-c6a5240f09e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693406651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1693406651
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4007537673
Short name T888
Test name
Test status
Simulation time 1281123003 ps
CPU time 4.54 seconds
Started Aug 06 05:26:20 PM PDT 24
Finished Aug 06 05:26:24 PM PDT 24
Peak memory 209292 kb
Host smart-34baba9a-a2ec-4774-851c-ad443b8433a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007537673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4007537673
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.4157856650
Short name T457
Test name
Test status
Simulation time 60263722 ps
CPU time 2.1 seconds
Started Aug 06 05:26:17 PM PDT 24
Finished Aug 06 05:26:19 PM PDT 24
Peak memory 206700 kb
Host smart-d72b1356-0c52-4990-97c5-d7aa62110d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157856650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.4157856650
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1831844281
Short name T174
Test name
Test status
Simulation time 10628604151 ps
CPU time 59.86 seconds
Started Aug 06 05:26:22 PM PDT 24
Finished Aug 06 05:27:22 PM PDT 24
Peak memory 216132 kb
Host smart-f81856d2-1b7b-445b-af43-2fb355b9af7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831844281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1831844281
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.806208627
Short name T818
Test name
Test status
Simulation time 2771202844 ps
CPU time 11.98 seconds
Started Aug 06 05:26:22 PM PDT 24
Finished Aug 06 05:26:34 PM PDT 24
Peak memory 222436 kb
Host smart-71c63ccf-b796-4cfe-9951-93e16225643f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806208627 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.806208627
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2134593052
Short name T277
Test name
Test status
Simulation time 2280262558 ps
CPU time 8.5 seconds
Started Aug 06 05:26:19 PM PDT 24
Finished Aug 06 05:26:28 PM PDT 24
Peak memory 218040 kb
Host smart-3c428347-4ce1-4bce-9627-c6571dc56c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134593052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2134593052
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2123799928
Short name T355
Test name
Test status
Simulation time 71817185 ps
CPU time 1.39 seconds
Started Aug 06 05:26:19 PM PDT 24
Finished Aug 06 05:26:21 PM PDT 24
Peak memory 210020 kb
Host smart-015609b2-5b2c-4f99-8474-fde3b7e5feb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123799928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2123799928
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2114621693
Short name T415
Test name
Test status
Simulation time 48488132 ps
CPU time 0.76 seconds
Started Aug 06 05:26:14 PM PDT 24
Finished Aug 06 05:26:15 PM PDT 24
Peak memory 205956 kb
Host smart-66a08319-4896-4286-b431-cdb6740f8a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114621693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2114621693
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3752298536
Short name T360
Test name
Test status
Simulation time 48900264 ps
CPU time 3.84 seconds
Started Aug 06 05:26:17 PM PDT 24
Finished Aug 06 05:26:21 PM PDT 24
Peak memory 214328 kb
Host smart-3c10b563-abe9-4588-97ff-553ce98538de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752298536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3752298536
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2991199663
Short name T614
Test name
Test status
Simulation time 384306898 ps
CPU time 4.79 seconds
Started Aug 06 05:26:13 PM PDT 24
Finished Aug 06 05:26:18 PM PDT 24
Peak memory 220120 kb
Host smart-c9627b88-f20e-4873-a030-ffe2d96c7129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991199663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2991199663
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3355553861
Short name T876
Test name
Test status
Simulation time 409323949 ps
CPU time 2.27 seconds
Started Aug 06 05:26:18 PM PDT 24
Finished Aug 06 05:26:20 PM PDT 24
Peak memory 208780 kb
Host smart-f89e8da4-9b86-42c0-b3de-8f96afa58547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355553861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3355553861
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3148855594
Short name T706
Test name
Test status
Simulation time 101692724 ps
CPU time 3.36 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:20 PM PDT 24
Peak memory 214880 kb
Host smart-9c501211-0338-4628-9f11-3e20fb6d6998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148855594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3148855594
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1310484492
Short name T779
Test name
Test status
Simulation time 446447939 ps
CPU time 2.7 seconds
Started Aug 06 05:26:18 PM PDT 24
Finished Aug 06 05:26:21 PM PDT 24
Peak memory 207800 kb
Host smart-9d7e3a23-9c26-4b45-8957-9b7ab16ea0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310484492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1310484492
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.355538869
Short name T826
Test name
Test status
Simulation time 425116126 ps
CPU time 4.98 seconds
Started Aug 06 05:26:18 PM PDT 24
Finished Aug 06 05:26:23 PM PDT 24
Peak memory 207648 kb
Host smart-477e1ec6-ccd1-4c10-9e39-3807b2e499ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355538869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.355538869
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1302980422
Short name T741
Test name
Test status
Simulation time 41553570 ps
CPU time 3.01 seconds
Started Aug 06 05:26:18 PM PDT 24
Finished Aug 06 05:26:21 PM PDT 24
Peak memory 208884 kb
Host smart-64265c02-0a69-4df6-a8c8-4734f5f35798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302980422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1302980422
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.974579289
Short name T813
Test name
Test status
Simulation time 397852605 ps
CPU time 2.42 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:17 PM PDT 24
Peak memory 207052 kb
Host smart-889b31c2-6869-4aca-a696-46508d4e1abc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974579289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.974579289
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.226737865
Short name T560
Test name
Test status
Simulation time 37062320 ps
CPU time 2.33 seconds
Started Aug 06 05:26:22 PM PDT 24
Finished Aug 06 05:26:25 PM PDT 24
Peak memory 206800 kb
Host smart-880996fe-7f68-4ea8-9e20-441bd63cdb5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226737865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.226737865
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.396577427
Short name T773
Test name
Test status
Simulation time 369475628 ps
CPU time 5.05 seconds
Started Aug 06 05:26:22 PM PDT 24
Finished Aug 06 05:26:27 PM PDT 24
Peak memory 208736 kb
Host smart-bffb3699-3ba7-49d6-bf94-c7aade22eb61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396577427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.396577427
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2611808143
Short name T423
Test name
Test status
Simulation time 855308378 ps
CPU time 3.17 seconds
Started Aug 06 05:26:12 PM PDT 24
Finished Aug 06 05:26:15 PM PDT 24
Peak memory 207900 kb
Host smart-04d55dd9-2d6b-415d-bd46-de4b7ff44f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611808143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2611808143
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3165604389
Short name T431
Test name
Test status
Simulation time 190237107 ps
CPU time 2.38 seconds
Started Aug 06 05:26:19 PM PDT 24
Finished Aug 06 05:26:22 PM PDT 24
Peak memory 206752 kb
Host smart-c187dbed-c462-4069-a485-1f23df9df77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165604389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3165604389
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.771303870
Short name T52
Test name
Test status
Simulation time 1517132091 ps
CPU time 11.49 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:27 PM PDT 24
Peak memory 222516 kb
Host smart-5d3fb993-b037-4144-b682-31e604bdba28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771303870 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.771303870
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.360009776
Short name T663
Test name
Test status
Simulation time 108086865 ps
CPU time 4.94 seconds
Started Aug 06 05:26:17 PM PDT 24
Finished Aug 06 05:26:22 PM PDT 24
Peak memory 209612 kb
Host smart-8665a0a6-53a6-442a-a0c7-964219f0e8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360009776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.360009776
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3899467234
Short name T902
Test name
Test status
Simulation time 65660956 ps
CPU time 2.01 seconds
Started Aug 06 05:26:14 PM PDT 24
Finished Aug 06 05:26:16 PM PDT 24
Peak memory 209916 kb
Host smart-67dc88bb-c75f-4dec-a9be-8578fcfbc35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899467234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3899467234
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1227887222
Short name T600
Test name
Test status
Simulation time 25555287 ps
CPU time 0.95 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:17 PM PDT 24
Peak memory 205876 kb
Host smart-048fd175-ed9f-4587-ae87-69192ba031b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227887222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1227887222
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3995636860
Short name T371
Test name
Test status
Simulation time 426952077 ps
CPU time 3.32 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:18 PM PDT 24
Peak memory 208452 kb
Host smart-68dce4b5-4f83-415f-a8d5-5a0c0cf396a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995636860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3995636860
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1812380379
Short name T697
Test name
Test status
Simulation time 576311659 ps
CPU time 2.44 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:19 PM PDT 24
Peak memory 215496 kb
Host smart-b8ec80ba-6fbb-42b1-82d9-bdfa7d194284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812380379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1812380379
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2624304827
Short name T515
Test name
Test status
Simulation time 96207634 ps
CPU time 1.86 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:17 PM PDT 24
Peak memory 214236 kb
Host smart-95673e96-94c4-490e-a945-38d77e8b05ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624304827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2624304827
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.4156706891
Short name T662
Test name
Test status
Simulation time 115326034 ps
CPU time 5.21 seconds
Started Aug 06 05:26:18 PM PDT 24
Finished Aug 06 05:26:23 PM PDT 24
Peak memory 210296 kb
Host smart-ac9919ba-58c5-4056-b93c-043c0edfa986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156706891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.4156706891
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1093190005
Short name T504
Test name
Test status
Simulation time 459078824 ps
CPU time 4.83 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:20 PM PDT 24
Peak memory 207272 kb
Host smart-9c5650fe-3a95-43f1-9900-4539a3d27e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093190005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1093190005
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.381505290
Short name T507
Test name
Test status
Simulation time 143739979 ps
CPU time 5.31 seconds
Started Aug 06 05:26:14 PM PDT 24
Finished Aug 06 05:26:19 PM PDT 24
Peak memory 208064 kb
Host smart-1363dcbf-aefe-47c3-9b34-002018d85b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381505290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.381505290
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2145216359
Short name T329
Test name
Test status
Simulation time 6958736083 ps
CPU time 54.4 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:27:09 PM PDT 24
Peak memory 208064 kb
Host smart-4cf203f0-ed66-4a20-9b3f-3c02ccc3ab6e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145216359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2145216359
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3537460600
Short name T611
Test name
Test status
Simulation time 256073071 ps
CPU time 3.59 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:19 PM PDT 24
Peak memory 206924 kb
Host smart-b79d383f-47f2-476d-9387-bd729b8c3a99
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537460600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3537460600
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1140776496
Short name T501
Test name
Test status
Simulation time 561721225 ps
CPU time 2.77 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:18 PM PDT 24
Peak memory 206924 kb
Host smart-71bff919-5f7b-4cc0-848d-14dcd3429612
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140776496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1140776496
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3117759403
Short name T514
Test name
Test status
Simulation time 56578614 ps
CPU time 2.11 seconds
Started Aug 06 05:26:18 PM PDT 24
Finished Aug 06 05:26:20 PM PDT 24
Peak memory 214412 kb
Host smart-feaf3d42-c941-41fb-9e46-c77a19d5e670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117759403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3117759403
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2420209409
Short name T455
Test name
Test status
Simulation time 715775702 ps
CPU time 6.67 seconds
Started Aug 06 05:26:13 PM PDT 24
Finished Aug 06 05:26:20 PM PDT 24
Peak memory 206820 kb
Host smart-12afb637-3af1-45ed-b01c-a1230e851fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420209409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2420209409
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.277645245
Short name T187
Test name
Test status
Simulation time 3820707845 ps
CPU time 35.1 seconds
Started Aug 06 05:26:18 PM PDT 24
Finished Aug 06 05:26:53 PM PDT 24
Peak memory 220452 kb
Host smart-0f9ceb07-96f6-4a30-aa5c-a128811ce487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277645245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.277645245
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.174907485
Short name T170
Test name
Test status
Simulation time 507651271 ps
CPU time 18.33 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:34 PM PDT 24
Peak memory 222328 kb
Host smart-9d7e06a0-2ecb-4697-80d1-de3725924382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174907485 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.174907485
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3915492036
Short name T750
Test name
Test status
Simulation time 70998458 ps
CPU time 2.78 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:19 PM PDT 24
Peak memory 207628 kb
Host smart-b779e0f5-43f6-4e49-aaf4-fa39414e3187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915492036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3915492036
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1623928539
Short name T55
Test name
Test status
Simulation time 64105072 ps
CPU time 1.5 seconds
Started Aug 06 05:26:15 PM PDT 24
Finished Aug 06 05:26:17 PM PDT 24
Peak memory 209708 kb
Host smart-2c69e214-9ca0-4553-8aeb-b81992b83ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623928539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1623928539
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1754933836
Short name T573
Test name
Test status
Simulation time 45219781 ps
CPU time 0.84 seconds
Started Aug 06 05:26:30 PM PDT 24
Finished Aug 06 05:26:31 PM PDT 24
Peak memory 205948 kb
Host smart-dc2aaee3-117f-48dd-a455-a1510b9a2672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754933836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1754933836
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1802932328
Short name T728
Test name
Test status
Simulation time 934472103 ps
CPU time 12.86 seconds
Started Aug 06 05:26:31 PM PDT 24
Finished Aug 06 05:26:44 PM PDT 24
Peak memory 215336 kb
Host smart-3c890409-9906-4df0-b226-86da4309c728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1802932328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1802932328
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1129021560
Short name T427
Test name
Test status
Simulation time 120940069 ps
CPU time 2.77 seconds
Started Aug 06 05:26:30 PM PDT 24
Finished Aug 06 05:26:33 PM PDT 24
Peak memory 220572 kb
Host smart-8bbea70b-b865-4365-a429-ecf9758e3211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129021560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1129021560
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3901140375
Short name T246
Test name
Test status
Simulation time 183523467 ps
CPU time 2.84 seconds
Started Aug 06 05:26:29 PM PDT 24
Finished Aug 06 05:26:32 PM PDT 24
Peak memory 214484 kb
Host smart-1e2a4faf-48c1-42c3-985c-246f0e1a547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901140375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3901140375
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1997973676
Short name T26
Test name
Test status
Simulation time 198552674 ps
CPU time 3.47 seconds
Started Aug 06 05:26:30 PM PDT 24
Finished Aug 06 05:26:33 PM PDT 24
Peak memory 209136 kb
Host smart-57b06e6d-fd4f-4e8a-b2b1-11d1d3cf9b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997973676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1997973676
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3090544731
Short name T462
Test name
Test status
Simulation time 85080271 ps
CPU time 3.09 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:38 PM PDT 24
Peak memory 222396 kb
Host smart-6ad86037-8d0a-46aa-a401-4123cb954a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090544731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3090544731
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1222517241
Short name T425
Test name
Test status
Simulation time 56386112 ps
CPU time 2.24 seconds
Started Aug 06 05:26:31 PM PDT 24
Finished Aug 06 05:26:33 PM PDT 24
Peak memory 214444 kb
Host smart-2901c019-cb6a-4158-9e76-c2afc512dc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222517241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1222517241
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.695951873
Short name T814
Test name
Test status
Simulation time 239894787 ps
CPU time 6.39 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:42 PM PDT 24
Peak memory 214288 kb
Host smart-d9c815e6-7dd4-4a02-b7d5-de7e14d68825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695951873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.695951873
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3873329543
Short name T291
Test name
Test status
Simulation time 36333649 ps
CPU time 2.25 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:38 PM PDT 24
Peak memory 206952 kb
Host smart-aa1a328e-7b77-42b0-85a7-6be6967db627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873329543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3873329543
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2360357770
Short name T585
Test name
Test status
Simulation time 1732234952 ps
CPU time 3.54 seconds
Started Aug 06 05:26:30 PM PDT 24
Finished Aug 06 05:26:34 PM PDT 24
Peak memory 206820 kb
Host smart-a6295b51-6c60-45b5-8c12-c2d21350bcf5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360357770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2360357770
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.636652497
Short name T184
Test name
Test status
Simulation time 47769990 ps
CPU time 2.75 seconds
Started Aug 06 05:26:31 PM PDT 24
Finished Aug 06 05:26:33 PM PDT 24
Peak memory 206640 kb
Host smart-45814a10-5a85-44c7-96a5-301339005525
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636652497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.636652497
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.629775376
Short name T478
Test name
Test status
Simulation time 205762470 ps
CPU time 2.89 seconds
Started Aug 06 05:26:28 PM PDT 24
Finished Aug 06 05:26:31 PM PDT 24
Peak memory 206904 kb
Host smart-0b4bacb5-16a1-40a9-b7b9-432b807d9ccb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629775376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.629775376
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4008533535
Short name T836
Test name
Test status
Simulation time 476176895 ps
CPU time 3.29 seconds
Started Aug 06 05:26:31 PM PDT 24
Finished Aug 06 05:26:34 PM PDT 24
Peak memory 214408 kb
Host smart-4512255c-acdf-4b69-a04c-95696d546c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008533535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4008533535
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.4070509685
Short name T16
Test name
Test status
Simulation time 415206559 ps
CPU time 4.55 seconds
Started Aug 06 05:26:16 PM PDT 24
Finished Aug 06 05:26:21 PM PDT 24
Peak memory 206732 kb
Host smart-70edbc59-19d9-42bc-a00e-2e6254abe370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070509685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.4070509685
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2667690676
Short name T362
Test name
Test status
Simulation time 419217274 ps
CPU time 6.8 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:44 PM PDT 24
Peak memory 218612 kb
Host smart-4439d324-78a1-4141-8b6f-00eb748c2bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667690676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2667690676
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3846086299
Short name T19
Test name
Test status
Simulation time 5980050189 ps
CPU time 40.76 seconds
Started Aug 06 05:26:31 PM PDT 24
Finished Aug 06 05:27:11 PM PDT 24
Peak memory 209096 kb
Host smart-ee626b62-8d83-4fb7-a89e-bd38842b6176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846086299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3846086299
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.994287204
Short name T484
Test name
Test status
Simulation time 503034261 ps
CPU time 2.76 seconds
Started Aug 06 05:26:31 PM PDT 24
Finished Aug 06 05:26:34 PM PDT 24
Peak memory 210020 kb
Host smart-c194a550-46c7-46f7-b460-196621880f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994287204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.994287204
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1177443335
Short name T746
Test name
Test status
Simulation time 41944541 ps
CPU time 0.84 seconds
Started Aug 06 05:24:43 PM PDT 24
Finished Aug 06 05:24:44 PM PDT 24
Peak memory 205888 kb
Host smart-74f67988-9ee5-4303-9528-f030cdacb829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177443335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1177443335
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.4078994620
Short name T324
Test name
Test status
Simulation time 43802804 ps
CPU time 3.24 seconds
Started Aug 06 05:24:42 PM PDT 24
Finished Aug 06 05:24:46 PM PDT 24
Peak memory 222468 kb
Host smart-22210055-2097-4e2d-b14b-efa3c4dc6a41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4078994620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.4078994620
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1844910866
Short name T709
Test name
Test status
Simulation time 164926351 ps
CPU time 4.59 seconds
Started Aug 06 05:24:44 PM PDT 24
Finished Aug 06 05:24:48 PM PDT 24
Peak memory 220252 kb
Host smart-54d40d76-54ed-47de-935d-e52c378cbb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844910866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1844910866
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2616257354
Short name T433
Test name
Test status
Simulation time 68554687 ps
CPU time 2.7 seconds
Started Aug 06 05:24:44 PM PDT 24
Finished Aug 06 05:24:47 PM PDT 24
Peak memory 208580 kb
Host smart-c9274ab7-43c4-4186-ad59-46210db1e4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616257354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2616257354
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3150595713
Short name T222
Test name
Test status
Simulation time 40109163 ps
CPU time 2.6 seconds
Started Aug 06 05:24:44 PM PDT 24
Finished Aug 06 05:24:47 PM PDT 24
Peak memory 221888 kb
Host smart-9e3c9099-9eca-42cf-8dc7-d61996b6e262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150595713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3150595713
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3530042145
Short name T290
Test name
Test status
Simulation time 761082923 ps
CPU time 4.45 seconds
Started Aug 06 05:24:42 PM PDT 24
Finished Aug 06 05:24:47 PM PDT 24
Peak memory 208552 kb
Host smart-a5b60097-9813-4f79-83f3-4f38eecf0d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530042145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3530042145
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.4285476823
Short name T875
Test name
Test status
Simulation time 360352120 ps
CPU time 4.99 seconds
Started Aug 06 05:24:44 PM PDT 24
Finished Aug 06 05:24:49 PM PDT 24
Peak memory 214312 kb
Host smart-9addb10d-3e93-40de-9aeb-2ab74ac5df87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285476823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.4285476823
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.501986110
Short name T841
Test name
Test status
Simulation time 681884080 ps
CPU time 7.36 seconds
Started Aug 06 05:24:30 PM PDT 24
Finished Aug 06 05:24:37 PM PDT 24
Peak memory 206328 kb
Host smart-3148be58-e17c-4248-93ea-596335edda34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501986110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.501986110
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1360563281
Short name T810
Test name
Test status
Simulation time 60097677 ps
CPU time 2.85 seconds
Started Aug 06 05:24:30 PM PDT 24
Finished Aug 06 05:24:33 PM PDT 24
Peak memory 207652 kb
Host smart-edae1002-5b71-4450-b19f-3bb2c88ce2c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360563281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1360563281
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2961470619
Short name T753
Test name
Test status
Simulation time 278886413 ps
CPU time 3.78 seconds
Started Aug 06 05:24:35 PM PDT 24
Finished Aug 06 05:24:39 PM PDT 24
Peak memory 206832 kb
Host smart-de0040d9-ea35-4706-8c0b-3d3263009552
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961470619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2961470619
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2368414842
Short name T648
Test name
Test status
Simulation time 144912944 ps
CPU time 3.52 seconds
Started Aug 06 05:24:44 PM PDT 24
Finished Aug 06 05:24:48 PM PDT 24
Peak memory 209512 kb
Host smart-51bc762d-bf5b-4c2d-a4b3-1dc537140cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368414842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2368414842
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1686756712
Short name T390
Test name
Test status
Simulation time 48556256 ps
CPU time 2.34 seconds
Started Aug 06 05:24:27 PM PDT 24
Finished Aug 06 05:24:30 PM PDT 24
Peak memory 206704 kb
Host smart-3fd43aac-c503-4da9-b1a6-a10f6b25330b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686756712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1686756712
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2961123429
Short name T255
Test name
Test status
Simulation time 1857841526 ps
CPU time 38.35 seconds
Started Aug 06 05:24:43 PM PDT 24
Finished Aug 06 05:25:21 PM PDT 24
Peak memory 216712 kb
Host smart-87341204-24dc-4c61-b8be-4834081a8089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961123429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2961123429
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.4254654516
Short name T643
Test name
Test status
Simulation time 222729092 ps
CPU time 3.61 seconds
Started Aug 06 05:24:44 PM PDT 24
Finished Aug 06 05:24:48 PM PDT 24
Peak memory 209464 kb
Host smart-b052610d-888d-427b-a5a7-74776c993d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254654516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.4254654516
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1101064942
Short name T356
Test name
Test status
Simulation time 157604794 ps
CPU time 2.43 seconds
Started Aug 06 05:24:43 PM PDT 24
Finished Aug 06 05:24:45 PM PDT 24
Peak memory 209840 kb
Host smart-b8a03cad-6cb4-4ca3-b698-d88075143670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101064942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1101064942
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3002978939
Short name T522
Test name
Test status
Simulation time 13057048 ps
CPU time 0.72 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:38 PM PDT 24
Peak memory 205984 kb
Host smart-92059233-6071-4abc-b6f6-7bda36a10d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002978939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3002978939
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.58010808
Short name T375
Test name
Test status
Simulation time 210984894 ps
CPU time 4.42 seconds
Started Aug 06 05:26:34 PM PDT 24
Finished Aug 06 05:26:38 PM PDT 24
Peak memory 215372 kb
Host smart-2a7279fb-5fe7-45f8-823d-a70925e2b01f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58010808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.58010808
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4111794433
Short name T28
Test name
Test status
Simulation time 212720278 ps
CPU time 4.13 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:41 PM PDT 24
Peak memory 210732 kb
Host smart-6e836e89-dce3-4e03-acf4-65e280cab28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111794433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4111794433
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.455619118
Short name T254
Test name
Test status
Simulation time 333421908 ps
CPU time 4.83 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:40 PM PDT 24
Peak memory 214312 kb
Host smart-b0b2a9eb-bfe6-4724-bfae-6f7256833805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455619118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.455619118
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.686626276
Short name T722
Test name
Test status
Simulation time 169393953 ps
CPU time 1.74 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:38 PM PDT 24
Peak memory 222252 kb
Host smart-52dfb130-b81b-4281-b071-be8aa47650b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686626276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.686626276
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1838306022
Short name T708
Test name
Test status
Simulation time 477275795 ps
CPU time 3.79 seconds
Started Aug 06 05:26:30 PM PDT 24
Finished Aug 06 05:26:34 PM PDT 24
Peak memory 210092 kb
Host smart-ed73cc32-1954-4da2-982f-a36c9cbcc719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838306022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1838306022
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.4077956952
Short name T177
Test name
Test status
Simulation time 491778437 ps
CPU time 5.56 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 208404 kb
Host smart-801ddfbe-e129-472e-beb5-6fd0e3d27031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077956952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.4077956952
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3804086225
Short name T637
Test name
Test status
Simulation time 1475986676 ps
CPU time 40.59 seconds
Started Aug 06 05:26:32 PM PDT 24
Finished Aug 06 05:27:13 PM PDT 24
Peak memory 208280 kb
Host smart-0d8a79a7-ac35-41de-b591-f74abbb74643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804086225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3804086225
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.752657880
Short name T812
Test name
Test status
Simulation time 428016785 ps
CPU time 6.03 seconds
Started Aug 06 05:26:31 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 208032 kb
Host smart-f06b710b-de3f-498c-b49b-d894acaa5fa0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752657880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.752657880
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1665945432
Short name T822
Test name
Test status
Simulation time 621079623 ps
CPU time 17.07 seconds
Started Aug 06 05:26:38 PM PDT 24
Finished Aug 06 05:26:55 PM PDT 24
Peak memory 208220 kb
Host smart-dbba6765-2fa1-4087-9a44-89d15181b708
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665945432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1665945432
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1948200861
Short name T529
Test name
Test status
Simulation time 217404445 ps
CPU time 5.17 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:41 PM PDT 24
Peak memory 207860 kb
Host smart-9cd7e104-7b26-4b60-80ab-46a547802430
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948200861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1948200861
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2290724923
Short name T824
Test name
Test status
Simulation time 461982061 ps
CPU time 3.73 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 218140 kb
Host smart-63ccc4be-649a-4cea-abde-9b8a6676f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290724923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2290724923
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.790500349
Short name T449
Test name
Test status
Simulation time 1484676945 ps
CPU time 5.4 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:43 PM PDT 24
Peak memory 208428 kb
Host smart-c3e38844-318d-485e-9d41-6abd08efb9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790500349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.790500349
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1674037349
Short name T193
Test name
Test status
Simulation time 2043771685 ps
CPU time 26.75 seconds
Started Aug 06 05:26:32 PM PDT 24
Finished Aug 06 05:26:59 PM PDT 24
Peak memory 217032 kb
Host smart-f4c62cab-10cb-4116-90fd-2479051531ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674037349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1674037349
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3556109676
Short name T840
Test name
Test status
Simulation time 329969063 ps
CPU time 18.49 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:55 PM PDT 24
Peak memory 222472 kb
Host smart-87e2644e-3ac7-43fb-92b8-783f5fd92590
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556109676 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3556109676
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2169115442
Short name T712
Test name
Test status
Simulation time 69048215 ps
CPU time 3.39 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:40 PM PDT 24
Peak memory 214304 kb
Host smart-89cee43c-3fc7-4103-be41-74db06a45cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169115442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2169115442
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1551054700
Short name T658
Test name
Test status
Simulation time 142430099 ps
CPU time 4.01 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:41 PM PDT 24
Peak memory 209708 kb
Host smart-c3b8e512-947d-4357-b63a-34fa53f371f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551054700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1551054700
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2147790885
Short name T620
Test name
Test status
Simulation time 11253053 ps
CPU time 0.87 seconds
Started Aug 06 05:26:29 PM PDT 24
Finished Aug 06 05:26:30 PM PDT 24
Peak memory 205932 kb
Host smart-dd50a6b5-0a6e-423b-9c4b-4fe8494d5384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147790885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2147790885
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3697121592
Short name T292
Test name
Test status
Simulation time 78558225 ps
CPU time 2.83 seconds
Started Aug 06 05:26:40 PM PDT 24
Finished Aug 06 05:26:43 PM PDT 24
Peak memory 214340 kb
Host smart-9354bf02-ca0e-40ed-a7d2-32786fc5369a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3697121592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3697121592
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1788396635
Short name T188
Test name
Test status
Simulation time 100877255 ps
CPU time 1.77 seconds
Started Aug 06 05:26:31 PM PDT 24
Finished Aug 06 05:26:33 PM PDT 24
Peak memory 208512 kb
Host smart-0ee95b7b-87d2-4036-8df8-4541a16d2f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788396635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1788396635
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.180767141
Short name T865
Test name
Test status
Simulation time 50183227 ps
CPU time 2.45 seconds
Started Aug 06 05:26:39 PM PDT 24
Finished Aug 06 05:26:42 PM PDT 24
Peak memory 209816 kb
Host smart-dc20afc4-85d6-45b3-bbea-1401eccf3356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180767141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.180767141
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3668809264
Short name T15
Test name
Test status
Simulation time 46177948 ps
CPU time 1.96 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 214312 kb
Host smart-06c2c8d6-89b4-418c-9456-f4dbf00ff4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668809264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3668809264
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1038420496
Short name T301
Test name
Test status
Simulation time 100788049 ps
CPU time 4.69 seconds
Started Aug 06 05:26:32 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 214276 kb
Host smart-69ebd03d-7a43-4075-ae0d-39422a9d3e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038420496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1038420496
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1567290880
Short name T200
Test name
Test status
Simulation time 283269198 ps
CPU time 3.11 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:40 PM PDT 24
Peak memory 207668 kb
Host smart-9dc6cb85-f331-411f-bc42-537d9248710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567290880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1567290880
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.413935633
Short name T893
Test name
Test status
Simulation time 195018435 ps
CPU time 3.58 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:40 PM PDT 24
Peak memory 218200 kb
Host smart-5945f028-413d-4b03-bfbf-230be6f1433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413935633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.413935633
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2009068370
Short name T535
Test name
Test status
Simulation time 310952812 ps
CPU time 1.73 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 206916 kb
Host smart-e6414af8-f236-4df8-9a16-70bd69ed25da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009068370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2009068370
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.662592165
Short name T785
Test name
Test status
Simulation time 546580237 ps
CPU time 4.24 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:40 PM PDT 24
Peak memory 208568 kb
Host smart-c93ee49b-7f48-4cb4-8ca9-08f8eb41e461
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662592165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.662592165
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1973131993
Short name T685
Test name
Test status
Simulation time 44923780 ps
CPU time 2.46 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 208060 kb
Host smart-dd6bb578-1188-4eab-9e8a-3f5be85bfb3f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973131993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1973131993
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1572582261
Short name T776
Test name
Test status
Simulation time 39263433 ps
CPU time 1.78 seconds
Started Aug 06 05:26:40 PM PDT 24
Finished Aug 06 05:26:41 PM PDT 24
Peak memory 206852 kb
Host smart-930fca80-a169-4c12-b45e-09b3f67b9cd0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572582261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1572582261
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.325170022
Short name T528
Test name
Test status
Simulation time 48682076 ps
CPU time 2.39 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 208516 kb
Host smart-aa24de74-aa16-4a90-99cb-e423e9f4dc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325170022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.325170022
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.4167565686
Short name T694
Test name
Test status
Simulation time 152867264 ps
CPU time 2.63 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 206884 kb
Host smart-23dcd526-15b7-4ffc-89ca-07df70aa9192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167565686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.4167565686
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2927628550
Short name T202
Test name
Test status
Simulation time 426036646 ps
CPU time 20.66 seconds
Started Aug 06 05:26:29 PM PDT 24
Finished Aug 06 05:26:50 PM PDT 24
Peak memory 222388 kb
Host smart-324da867-a90a-4e2e-9bc2-c8fdf08140d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927628550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2927628550
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1969483038
Short name T516
Test name
Test status
Simulation time 539666338 ps
CPU time 8.09 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:45 PM PDT 24
Peak memory 207716 kb
Host smart-00c4b4f3-9310-4016-b20e-036eb73e447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969483038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1969483038
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.600203142
Short name T353
Test name
Test status
Simulation time 124856844 ps
CPU time 2.53 seconds
Started Aug 06 05:26:32 PM PDT 24
Finished Aug 06 05:26:35 PM PDT 24
Peak memory 209788 kb
Host smart-feac3b16-f02e-45da-8e11-063a64a6546e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600203142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.600203142
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.712102775
Short name T437
Test name
Test status
Simulation time 16590707 ps
CPU time 0.77 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 205884 kb
Host smart-471efa51-dc55-4eb2-809d-cbc8220b8303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712102775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.712102775
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.993086793
Short name T758
Test name
Test status
Simulation time 204015186 ps
CPU time 4.61 seconds
Started Aug 06 05:26:29 PM PDT 24
Finished Aug 06 05:26:34 PM PDT 24
Peak memory 215380 kb
Host smart-7574f688-bbb7-42e9-af8f-4143e4bc31fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=993086793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.993086793
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4007876380
Short name T532
Test name
Test status
Simulation time 277663218 ps
CPU time 2.56 seconds
Started Aug 06 05:26:34 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 218356 kb
Host smart-94960b03-9bbc-4c11-8490-550b222462a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007876380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4007876380
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1097385342
Short name T846
Test name
Test status
Simulation time 125608377 ps
CPU time 2.96 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:36 PM PDT 24
Peak memory 208636 kb
Host smart-bbe6243f-7c9a-4aa8-82bd-5c4d5a0a8b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097385342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1097385342
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3527998468
Short name T690
Test name
Test status
Simulation time 1527810760 ps
CPU time 3.81 seconds
Started Aug 06 05:26:30 PM PDT 24
Finished Aug 06 05:26:33 PM PDT 24
Peak memory 222388 kb
Host smart-27788dd5-6101-4390-b263-bdcdb71631cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527998468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3527998468
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.169218055
Short name T197
Test name
Test status
Simulation time 136126089 ps
CPU time 4.2 seconds
Started Aug 06 05:26:30 PM PDT 24
Finished Aug 06 05:26:35 PM PDT 24
Peak memory 220156 kb
Host smart-4ddd2433-ab62-4202-8188-a720c38c001b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169218055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.169218055
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2160436199
Short name T660
Test name
Test status
Simulation time 255785214 ps
CPU time 5.28 seconds
Started Aug 06 05:26:29 PM PDT 24
Finished Aug 06 05:26:35 PM PDT 24
Peak memory 208852 kb
Host smart-82066b59-2d3d-46ac-af9e-ca89dc8fc169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160436199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2160436199
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3350687786
Short name T220
Test name
Test status
Simulation time 602464734 ps
CPU time 4.79 seconds
Started Aug 06 05:26:30 PM PDT 24
Finished Aug 06 05:26:35 PM PDT 24
Peak memory 208560 kb
Host smart-4f60c936-b050-4514-adf1-c4cc95574a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350687786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3350687786
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2310630306
Short name T288
Test name
Test status
Simulation time 76390236 ps
CPU time 1.85 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:35 PM PDT 24
Peak memory 206964 kb
Host smart-3743ddfd-65b5-45e9-a2be-5044d838a3ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310630306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2310630306
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3081320005
Short name T572
Test name
Test status
Simulation time 313474152 ps
CPU time 6.13 seconds
Started Aug 06 05:26:29 PM PDT 24
Finished Aug 06 05:26:36 PM PDT 24
Peak memory 208804 kb
Host smart-d32d57fe-e98f-4074-812e-2cbf139721f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081320005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3081320005
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.4189689608
Short name T747
Test name
Test status
Simulation time 66590596 ps
CPU time 3.71 seconds
Started Aug 06 05:26:32 PM PDT 24
Finished Aug 06 05:26:36 PM PDT 24
Peak memory 208700 kb
Host smart-6ea7752a-b883-41ef-af3e-2c2e47c5cf6a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189689608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.4189689608
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1590162815
Short name T540
Test name
Test status
Simulation time 137804628 ps
CPU time 3.34 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 209820 kb
Host smart-0a02fa67-6539-4285-b2d2-a8b359f1243d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590162815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1590162815
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.614425678
Short name T571
Test name
Test status
Simulation time 393698481 ps
CPU time 10.07 seconds
Started Aug 06 05:26:30 PM PDT 24
Finished Aug 06 05:26:40 PM PDT 24
Peak memory 207144 kb
Host smart-896166a6-ccb0-4d3d-9a62-2b9430511b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614425678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.614425678
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3858780304
Short name T168
Test name
Test status
Simulation time 1282345970 ps
CPU time 16.88 seconds
Started Aug 06 05:26:38 PM PDT 24
Finished Aug 06 05:26:55 PM PDT 24
Peak memory 222464 kb
Host smart-3866a167-54ba-4cc8-884d-f32ec4096b6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858780304 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3858780304
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.131329975
Short name T544
Test name
Test status
Simulation time 1978554277 ps
CPU time 45.59 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:27:22 PM PDT 24
Peak memory 209432 kb
Host smart-43a1085b-300c-4108-8045-ca1cf363fc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131329975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.131329975
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.186836317
Short name T487
Test name
Test status
Simulation time 809127630 ps
CPU time 5.83 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 210760 kb
Host smart-7fa0b608-91e8-4d79-a886-37c0ea1f0d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186836317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.186836317
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2076890
Short name T877
Test name
Test status
Simulation time 29446667 ps
CPU time 0.77 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 205760 kb
Host smart-cc5ea4af-33c1-40f3-9cfb-7791416e85d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2076890
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3514384697
Short name T825
Test name
Test status
Simulation time 66689426 ps
CPU time 2.91 seconds
Started Aug 06 05:26:34 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 209908 kb
Host smart-a025536a-9d25-4bad-aa45-e028dcacc5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514384697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3514384697
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.291120455
Short name T352
Test name
Test status
Simulation time 2003155391 ps
CPU time 6.15 seconds
Started Aug 06 05:26:34 PM PDT 24
Finished Aug 06 05:26:40 PM PDT 24
Peak memory 220764 kb
Host smart-6fe7c83b-a9b1-400c-b6b9-ba679767af90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291120455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.291120455
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1117798070
Short name T647
Test name
Test status
Simulation time 154570119 ps
CPU time 4.84 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:41 PM PDT 24
Peak memory 222400 kb
Host smart-a225719e-dfe2-4611-a3e9-168e83466ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117798070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1117798070
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_random.388931171
Short name T829
Test name
Test status
Simulation time 277030216 ps
CPU time 7.76 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:43 PM PDT 24
Peak memory 218280 kb
Host smart-c706295a-0afb-4f6b-aa46-933827e38f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388931171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.388931171
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1658833332
Short name T83
Test name
Test status
Simulation time 106449321 ps
CPU time 3.42 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 208472 kb
Host smart-64cce1c9-ebda-47bd-b2ac-40b5c2e44e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658833332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1658833332
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3738429141
Short name T618
Test name
Test status
Simulation time 42065701 ps
CPU time 1.84 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:38 PM PDT 24
Peak memory 206696 kb
Host smart-f26a10fc-fd2f-4365-a80f-6da6ee21bf64
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738429141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3738429141
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1304628741
Short name T511
Test name
Test status
Simulation time 1407819650 ps
CPU time 5.29 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:41 PM PDT 24
Peak memory 206836 kb
Host smart-ade7b3a9-20a4-4d6d-89e1-b9084610e7e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304628741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1304628741
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.941121424
Short name T397
Test name
Test status
Simulation time 252666865 ps
CPU time 8.2 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:43 PM PDT 24
Peak memory 208056 kb
Host smart-f54adbed-c2bf-40a2-8d86-3b3d84fe33f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941121424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.941121424
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1550103507
Short name T809
Test name
Test status
Simulation time 270247737 ps
CPU time 2.19 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 207532 kb
Host smart-28ca29f6-17d7-46c5-90b4-501e2f56e133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550103507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1550103507
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1165072843
Short name T693
Test name
Test status
Simulation time 85544617 ps
CPU time 2.1 seconds
Started Aug 06 05:26:34 PM PDT 24
Finished Aug 06 05:26:36 PM PDT 24
Peak memory 208824 kb
Host smart-2e7f4ac5-a30f-47dd-ad50-59ce1c252826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165072843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1165072843
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.11841817
Short name T604
Test name
Test status
Simulation time 247155476 ps
CPU time 7.47 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:44 PM PDT 24
Peak memory 209128 kb
Host smart-f0cd3a39-3039-4b2a-9de5-a4acbec601d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11841817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.11841817
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1605931729
Short name T66
Test name
Test status
Simulation time 359199096 ps
CPU time 12.6 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:49 PM PDT 24
Peak memory 222572 kb
Host smart-f9057251-8c13-4d6a-803c-745c3f809235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605931729 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1605931729
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.710080248
Short name T892
Test name
Test status
Simulation time 80076163 ps
CPU time 4.32 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:41 PM PDT 24
Peak memory 208004 kb
Host smart-a37079d2-046b-48b0-8816-e0d03b4f70ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710080248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.710080248
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3412437276
Short name T710
Test name
Test status
Simulation time 663570660 ps
CPU time 7.03 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:43 PM PDT 24
Peak memory 210400 kb
Host smart-2b87cdc5-b922-42f9-895e-9477e54afb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412437276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3412437276
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2638626608
Short name T104
Test name
Test status
Simulation time 12410292 ps
CPU time 0.95 seconds
Started Aug 06 05:26:31 PM PDT 24
Finished Aug 06 05:26:32 PM PDT 24
Peak memory 206108 kb
Host smart-06b69743-8da7-4103-94c3-daf3bb5391b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638626608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2638626608
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.616711532
Short name T386
Test name
Test status
Simulation time 44312329 ps
CPU time 2.61 seconds
Started Aug 06 05:26:34 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 214284 kb
Host smart-1e24ad34-e64d-4588-84df-4ccd08a9c4c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616711532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.616711532
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.490232645
Short name T797
Test name
Test status
Simulation time 56379714 ps
CPU time 1.47 seconds
Started Aug 06 05:26:30 PM PDT 24
Finished Aug 06 05:26:32 PM PDT 24
Peak memory 222756 kb
Host smart-89fd0c76-6227-4838-8409-66e568ed3975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490232645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.490232645
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.532600868
Short name T686
Test name
Test status
Simulation time 120807170 ps
CPU time 3 seconds
Started Aug 06 05:26:40 PM PDT 24
Finished Aug 06 05:26:43 PM PDT 24
Peak memory 207688 kb
Host smart-7e9a0947-37b9-4c3c-94bb-012edbc24a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532600868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.532600868
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.295409233
Short name T607
Test name
Test status
Simulation time 75448584 ps
CPU time 2.92 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:36 PM PDT 24
Peak memory 222520 kb
Host smart-7678b897-cf7b-48ff-a539-20b57d25ad30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295409233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.295409233
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1059080573
Short name T383
Test name
Test status
Simulation time 403058660 ps
CPU time 4.54 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:40 PM PDT 24
Peak memory 217980 kb
Host smart-85a7f24e-f9e2-459e-a9da-fb74e9605051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059080573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1059080573
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3275400856
Short name T655
Test name
Test status
Simulation time 337194953 ps
CPU time 7.01 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:43 PM PDT 24
Peak memory 208408 kb
Host smart-818e75bd-385b-46cb-9d51-a8ec8360d5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275400856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3275400856
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3521233205
Short name T84
Test name
Test status
Simulation time 831525581 ps
CPU time 26.58 seconds
Started Aug 06 05:26:40 PM PDT 24
Finished Aug 06 05:27:07 PM PDT 24
Peak memory 207996 kb
Host smart-b799928e-91ab-4f8e-bcfa-3aa4be36af24
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521233205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3521233205
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2977384001
Short name T256
Test name
Test status
Simulation time 2095192781 ps
CPU time 10.2 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:47 PM PDT 24
Peak memory 206988 kb
Host smart-4c7bd775-8ead-4975-8868-2cd07c6a7c94
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977384001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2977384001
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3960809145
Short name T652
Test name
Test status
Simulation time 1171463140 ps
CPU time 8.66 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:42 PM PDT 24
Peak memory 209296 kb
Host smart-defc0ae8-ec69-4f4b-a361-fe9447547904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960809145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3960809145
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2770578756
Short name T543
Test name
Test status
Simulation time 806046164 ps
CPU time 4.38 seconds
Started Aug 06 05:26:32 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 206836 kb
Host smart-1ddcfec1-1f1e-4fe6-b5b1-465d09a93f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770578756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2770578756
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3460541272
Short name T771
Test name
Test status
Simulation time 304580654 ps
CPU time 6.33 seconds
Started Aug 06 05:26:35 PM PDT 24
Finished Aug 06 05:26:41 PM PDT 24
Peak memory 207252 kb
Host smart-170140cb-ad7a-4761-9d5d-717e0381f0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460541272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3460541272
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1809430284
Short name T568
Test name
Test status
Simulation time 217226296 ps
CPU time 2.72 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:36 PM PDT 24
Peak memory 210816 kb
Host smart-92fc1181-a16d-48eb-bbe1-6fddc285d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809430284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1809430284
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1467104356
Short name T816
Test name
Test status
Simulation time 36511600 ps
CPU time 0.81 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:34 PM PDT 24
Peak memory 205940 kb
Host smart-0b7fd46f-edb1-4315-bde5-c05a803b0d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467104356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1467104356
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.105163147
Short name T347
Test name
Test status
Simulation time 121740111 ps
CPU time 3.18 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 214188 kb
Host smart-e9ee2812-85d8-4a58-915b-9714bda24f66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105163147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.105163147
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3254975083
Short name T232
Test name
Test status
Simulation time 421355252 ps
CPU time 3.23 seconds
Started Aug 06 05:26:34 PM PDT 24
Finished Aug 06 05:26:37 PM PDT 24
Peak memory 209996 kb
Host smart-2f06e418-a291-40fc-abc3-9c0aebacd0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254975083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3254975083
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1913437075
Short name T661
Test name
Test status
Simulation time 1671580647 ps
CPU time 10.34 seconds
Started Aug 06 05:26:31 PM PDT 24
Finished Aug 06 05:26:42 PM PDT 24
Peak memory 208596 kb
Host smart-fb82c550-b39a-4563-a06d-66279386ecac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913437075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1913437075
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2601187846
Short name T90
Test name
Test status
Simulation time 66294051 ps
CPU time 3.28 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 214172 kb
Host smart-e7f597c4-01b1-49d5-bc08-22572a467fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601187846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2601187846
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.4199065895
Short name T224
Test name
Test status
Simulation time 489862822 ps
CPU time 3.59 seconds
Started Aug 06 05:26:37 PM PDT 24
Finished Aug 06 05:26:40 PM PDT 24
Peak memory 221296 kb
Host smart-5565db65-c871-48e2-b22f-f03a50525710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199065895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.4199065895
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1436424023
Short name T869
Test name
Test status
Simulation time 117518174 ps
CPU time 2.95 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:36 PM PDT 24
Peak memory 219888 kb
Host smart-45cbff13-43bd-4c17-abf1-d4fdb8e220f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436424023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1436424023
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3911591967
Short name T297
Test name
Test status
Simulation time 142145987 ps
CPU time 4.27 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:38 PM PDT 24
Peak memory 214100 kb
Host smart-7367f955-8a1e-443e-b5c3-3907bb9d4516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911591967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3911591967
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1137992536
Short name T332
Test name
Test status
Simulation time 94673570 ps
CPU time 2.7 seconds
Started Aug 06 05:26:31 PM PDT 24
Finished Aug 06 05:26:34 PM PDT 24
Peak memory 208740 kb
Host smart-08e2dadf-6aa3-4fc1-bf99-8f7414bab199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137992536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1137992536
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3045510106
Short name T483
Test name
Test status
Simulation time 208659538 ps
CPU time 7.96 seconds
Started Aug 06 05:26:38 PM PDT 24
Finished Aug 06 05:26:46 PM PDT 24
Peak memory 207916 kb
Host smart-0143aaaf-9e7b-4537-aa6c-d268398ada8c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045510106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3045510106
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2394377718
Short name T815
Test name
Test status
Simulation time 32522406 ps
CPU time 2.23 seconds
Started Aug 06 05:26:31 PM PDT 24
Finished Aug 06 05:26:33 PM PDT 24
Peak memory 206652 kb
Host smart-f43ebd94-494f-4c07-9cbb-199fdca41397
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394377718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2394377718
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2606758677
Short name T536
Test name
Test status
Simulation time 10231305784 ps
CPU time 22.62 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:56 PM PDT 24
Peak memory 208440 kb
Host smart-47d0338b-e795-4cec-a220-efdda7d4d217
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606758677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2606758677
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3048291875
Short name T835
Test name
Test status
Simulation time 1306788657 ps
CPU time 3.13 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:39 PM PDT 24
Peak memory 210120 kb
Host smart-73a2e602-90e3-4d42-a159-be67d09eeeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048291875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3048291875
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2772722716
Short name T401
Test name
Test status
Simulation time 1697995492 ps
CPU time 16.83 seconds
Started Aug 06 05:26:29 PM PDT 24
Finished Aug 06 05:26:46 PM PDT 24
Peak memory 208420 kb
Host smart-803aeb98-35bc-493f-b26a-5c05e5765cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772722716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2772722716
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1145090153
Short name T118
Test name
Test status
Simulation time 952587338 ps
CPU time 18.74 seconds
Started Aug 06 05:26:33 PM PDT 24
Finished Aug 06 05:26:52 PM PDT 24
Peak memory 220444 kb
Host smart-3546f206-1134-480e-a415-b313fd0a5696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145090153 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1145090153
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2626315816
Short name T221
Test name
Test status
Simulation time 232235441 ps
CPU time 3.9 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:40 PM PDT 24
Peak memory 207392 kb
Host smart-2019e735-0a85-43c5-87fd-a28678cd2557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626315816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2626315816
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2986315968
Short name T596
Test name
Test status
Simulation time 25024211 ps
CPU time 1.36 seconds
Started Aug 06 05:26:34 PM PDT 24
Finished Aug 06 05:26:36 PM PDT 24
Peak memory 208420 kb
Host smart-8b0efec9-db47-4c3d-b501-2c399ad28d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986315968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2986315968
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3155974242
Short name T393
Test name
Test status
Simulation time 53714131 ps
CPU time 0.9 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:45 PM PDT 24
Peak memory 205864 kb
Host smart-740d8daa-d10b-4d49-a7a1-4295d5a01a9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155974242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3155974242
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2819437179
Short name T358
Test name
Test status
Simulation time 65508618 ps
CPU time 2.65 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:46 PM PDT 24
Peak memory 215228 kb
Host smart-1bb4d241-ac56-4bef-9e30-8927af8abaa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2819437179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2819437179
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1919184891
Short name T64
Test name
Test status
Simulation time 544652176 ps
CPU time 4.4 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:48 PM PDT 24
Peak memory 217012 kb
Host smart-e1880f3a-f3ff-4d2a-a6c6-df51c55262de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919184891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1919184891
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.474871862
Short name T868
Test name
Test status
Simulation time 263161291 ps
CPU time 4.16 seconds
Started Aug 06 05:26:45 PM PDT 24
Finished Aug 06 05:26:49 PM PDT 24
Peak memory 214312 kb
Host smart-08b72e74-4326-44d2-9ab7-1e822e16d715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474871862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.474871862
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1021371658
Short name T811
Test name
Test status
Simulation time 114665518 ps
CPU time 2.43 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:48 PM PDT 24
Peak memory 214552 kb
Host smart-30b23b4c-4c38-4668-84dc-b8bdf757f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021371658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1021371658
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2716297962
Short name T849
Test name
Test status
Simulation time 556366172 ps
CPU time 8.83 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:52 PM PDT 24
Peak memory 214152 kb
Host smart-0236304a-6731-4bc5-bdf7-40f02b15da14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716297962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2716297962
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3703568947
Short name T482
Test name
Test status
Simulation time 1514338915 ps
CPU time 4 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:47 PM PDT 24
Peak memory 219996 kb
Host smart-55520de4-7e25-4673-946b-4f1039e0e81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703568947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3703568947
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3578406463
Short name T338
Test name
Test status
Simulation time 79126570 ps
CPU time 3.94 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:50 PM PDT 24
Peak memory 207312 kb
Host smart-053adbd3-db54-4b61-b7c6-b940337445cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578406463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3578406463
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1346909819
Short name T273
Test name
Test status
Simulation time 926419502 ps
CPU time 17.14 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:53 PM PDT 24
Peak memory 208272 kb
Host smart-aab0d241-f5d7-4d63-9dd3-cb604a9a0f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346909819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1346909819
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3609888501
Short name T848
Test name
Test status
Simulation time 360133100 ps
CPU time 7.32 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:50 PM PDT 24
Peak memory 208632 kb
Host smart-edbaea88-6a28-4960-95ab-f82d6f8f8493
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609888501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3609888501
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.4284040815
Short name T593
Test name
Test status
Simulation time 161594372 ps
CPU time 3.41 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:40 PM PDT 24
Peak memory 208928 kb
Host smart-30f64f23-ab12-422f-817c-bd8e10f5e471
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284040815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.4284040815
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2667030099
Short name T323
Test name
Test status
Simulation time 68349752 ps
CPU time 2.51 seconds
Started Aug 06 05:26:44 PM PDT 24
Finished Aug 06 05:26:46 PM PDT 24
Peak memory 208668 kb
Host smart-8764378b-e8ce-4192-8c01-17201e519ab4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667030099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2667030099
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.4041185340
Short name T479
Test name
Test status
Simulation time 281447451 ps
CPU time 1.85 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:26:49 PM PDT 24
Peak memory 208968 kb
Host smart-4066e85d-a7d0-400d-a841-e0ff55776403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041185340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.4041185340
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.456476330
Short name T695
Test name
Test status
Simulation time 996114441 ps
CPU time 5.85 seconds
Started Aug 06 05:26:36 PM PDT 24
Finished Aug 06 05:26:42 PM PDT 24
Peak memory 208300 kb
Host smart-62c747a4-ea07-4ac0-893e-d9fc1a7fff6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456476330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.456476330
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3022291083
Short name T209
Test name
Test status
Simulation time 1055579683 ps
CPU time 37.87 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:27:24 PM PDT 24
Peak memory 221088 kb
Host smart-f32f8cbf-c23c-4241-8a5e-7b157ab83c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022291083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3022291083
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2236260487
Short name T180
Test name
Test status
Simulation time 406302596 ps
CPU time 5.04 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:51 PM PDT 24
Peak memory 222456 kb
Host smart-8d4db08b-d13b-4f88-aa86-d6f02f1c499f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236260487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2236260487
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.8301602
Short name T37
Test name
Test status
Simulation time 212870196 ps
CPU time 2.2 seconds
Started Aug 06 05:26:45 PM PDT 24
Finished Aug 06 05:26:47 PM PDT 24
Peak memory 210116 kb
Host smart-8edaeaed-b093-4e22-8c28-d49d6ece592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8301602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.8301602
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2600240217
Short name T769
Test name
Test status
Simulation time 10438885 ps
CPU time 0.73 seconds
Started Aug 06 05:26:45 PM PDT 24
Finished Aug 06 05:26:46 PM PDT 24
Peak memory 205948 kb
Host smart-d047901e-784b-491e-92b3-f2a346f6351a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600240217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2600240217
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.750791194
Short name T762
Test name
Test status
Simulation time 253570239 ps
CPU time 13.68 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:59 PM PDT 24
Peak memory 215328 kb
Host smart-a2db8c7c-c8b3-45d9-9d63-6879d97a3523
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750791194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.750791194
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2017456172
Short name T192
Test name
Test status
Simulation time 364502501 ps
CPU time 2.87 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:26:50 PM PDT 24
Peak memory 217392 kb
Host smart-7125bc86-f8ea-4955-80cc-3eca78f57bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017456172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2017456172
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2804277747
Short name T304
Test name
Test status
Simulation time 264266263 ps
CPU time 6.96 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:51 PM PDT 24
Peak memory 210036 kb
Host smart-76578ad4-5907-4eca-ba93-2fa6f84e5e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804277747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2804277747
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3876260621
Short name T267
Test name
Test status
Simulation time 491931469 ps
CPU time 2.5 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:45 PM PDT 24
Peak memory 210292 kb
Host smart-01de427d-4566-4424-a752-6ed171ef04aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876260621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3876260621
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2071968195
Short name T711
Test name
Test status
Simulation time 144432357 ps
CPU time 3.33 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:47 PM PDT 24
Peak memory 219628 kb
Host smart-9cd52df8-5522-475c-be58-9f0eb2eae4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071968195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2071968195
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3719206420
Short name T681
Test name
Test status
Simulation time 899206461 ps
CPU time 3.76 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:49 PM PDT 24
Peak memory 218208 kb
Host smart-40f83094-057d-4756-9704-bd459bba128d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719206420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3719206420
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2384014004
Short name T807
Test name
Test status
Simulation time 291470453 ps
CPU time 2.76 seconds
Started Aug 06 05:26:45 PM PDT 24
Finished Aug 06 05:26:47 PM PDT 24
Peak memory 206640 kb
Host smart-d8e8cfae-78f3-4c34-98b3-e196c8ca13f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384014004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2384014004
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.88606215
Short name T752
Test name
Test status
Simulation time 366069349 ps
CPU time 3.41 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:46 PM PDT 24
Peak memory 207916 kb
Host smart-f1bac5c1-7c43-4bd6-a32b-a4651f6bf327
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88606215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.88606215
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3829177570
Short name T36
Test name
Test status
Simulation time 85102365 ps
CPU time 2.05 seconds
Started Aug 06 05:26:44 PM PDT 24
Finished Aug 06 05:26:47 PM PDT 24
Peak memory 207328 kb
Host smart-08940afe-529a-4b1f-81f4-591566b5a4e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829177570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3829177570
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1405635515
Short name T419
Test name
Test status
Simulation time 1673973237 ps
CPU time 43.64 seconds
Started Aug 06 05:26:42 PM PDT 24
Finished Aug 06 05:27:26 PM PDT 24
Peak memory 208900 kb
Host smart-ada50093-79e6-479f-aaf2-1bb53d21c0f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405635515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1405635515
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1917286872
Short name T784
Test name
Test status
Simulation time 87095048 ps
CPU time 2 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:26:49 PM PDT 24
Peak memory 215416 kb
Host smart-319fbfa3-dd8b-4ffc-b597-8cf410184d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917286872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1917286872
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1839898802
Short name T519
Test name
Test status
Simulation time 175735231 ps
CPU time 2.67 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:48 PM PDT 24
Peak memory 207372 kb
Host smart-3e857a87-2282-45c2-8033-6e32f159f750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839898802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1839898802
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1483297348
Short name T119
Test name
Test status
Simulation time 919628783 ps
CPU time 16.74 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:27:03 PM PDT 24
Peak memory 222456 kb
Host smart-0668ed4c-1098-4731-8616-9fac1e1a174b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483297348 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1483297348
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3325255776
Short name T830
Test name
Test status
Simulation time 154459392 ps
CPU time 5.52 seconds
Started Aug 06 05:26:42 PM PDT 24
Finished Aug 06 05:26:48 PM PDT 24
Peak memory 210256 kb
Host smart-884f1ff1-a9cc-48d7-990e-7afdce6d2065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325255776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3325255776
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2792641098
Short name T158
Test name
Test status
Simulation time 191475703 ps
CPU time 1.75 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:45 PM PDT 24
Peak memory 210024 kb
Host smart-b33133cc-146a-47c9-a392-d2832424439b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792641098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2792641098
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.865171441
Short name T654
Test name
Test status
Simulation time 11671549 ps
CPU time 0.74 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:26:48 PM PDT 24
Peak memory 205952 kb
Host smart-f46222a0-ff62-45d6-8d46-e832f8091532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865171441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.865171441
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1892902808
Short name T196
Test name
Test status
Simulation time 75554927 ps
CPU time 3.74 seconds
Started Aug 06 05:26:48 PM PDT 24
Finished Aug 06 05:26:52 PM PDT 24
Peak memory 214348 kb
Host smart-466710d4-9b0a-434f-91ac-fd7f0417bac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892902808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1892902808
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3959793920
Short name T555
Test name
Test status
Simulation time 92823877 ps
CPU time 3.45 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:26:50 PM PDT 24
Peak memory 218316 kb
Host smart-a4efe701-fd3c-4af8-a2dd-663317245a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959793920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3959793920
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3595430957
Short name T265
Test name
Test status
Simulation time 263943939 ps
CPU time 5.03 seconds
Started Aug 06 05:26:49 PM PDT 24
Finished Aug 06 05:26:54 PM PDT 24
Peak memory 214344 kb
Host smart-0b20384b-0ed8-4350-a5e5-31215d7ede80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595430957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3595430957
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1468990245
Short name T626
Test name
Test status
Simulation time 369105228 ps
CPU time 1.88 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:46 PM PDT 24
Peak memory 206192 kb
Host smart-53246b2e-8e63-4878-8839-ac148058c004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468990245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1468990245
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.744252183
Short name T319
Test name
Test status
Simulation time 116904728 ps
CPU time 3.85 seconds
Started Aug 06 05:26:44 PM PDT 24
Finished Aug 06 05:26:48 PM PDT 24
Peak memory 207336 kb
Host smart-c21caf89-7585-4569-82b2-2a05a582ba13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744252183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.744252183
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.882343876
Short name T240
Test name
Test status
Simulation time 186183164 ps
CPU time 3.5 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:26:51 PM PDT 24
Peak memory 208296 kb
Host smart-e8862ffa-f788-4487-b532-f6b059629e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882343876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.882343876
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2283597703
Short name T428
Test name
Test status
Simulation time 91311798 ps
CPU time 2.12 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:49 PM PDT 24
Peak memory 208912 kb
Host smart-8a313a33-d805-4b93-b351-f8f028e5ef15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283597703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2283597703
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3867600555
Short name T699
Test name
Test status
Simulation time 174629647 ps
CPU time 3.78 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:49 PM PDT 24
Peak memory 208512 kb
Host smart-cfbe44da-c150-4f0d-9141-26ab27aea9e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867600555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3867600555
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3937197467
Short name T817
Test name
Test status
Simulation time 74425651 ps
CPU time 3.37 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:26:51 PM PDT 24
Peak memory 208564 kb
Host smart-77f2c272-ecc2-4020-adf5-b2950e7feefd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937197467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3937197467
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3381740300
Short name T384
Test name
Test status
Simulation time 208202557 ps
CPU time 2.56 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:46 PM PDT 24
Peak memory 216280 kb
Host smart-a0414ef6-1b22-4185-ab55-60f7bf162f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381740300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3381740300
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.859491162
Short name T108
Test name
Test status
Simulation time 522404517 ps
CPU time 2.52 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:49 PM PDT 24
Peak memory 206932 kb
Host smart-8b07bec1-5ddc-4f7b-8ca5-d8d6d3f3b6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859491162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.859491162
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1556193559
Short name T878
Test name
Test status
Simulation time 1217729080 ps
CPU time 38.28 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:27:25 PM PDT 24
Peak memory 222508 kb
Host smart-e5523398-5789-434b-bd15-7eb6c89057d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556193559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1556193559
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2780124249
Short name T778
Test name
Test status
Simulation time 277876576 ps
CPU time 9.97 seconds
Started Aug 06 05:26:45 PM PDT 24
Finished Aug 06 05:26:55 PM PDT 24
Peak memory 209120 kb
Host smart-56b5960e-58b4-46d0-a7e6-2906be1b3945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780124249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2780124249
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1312389380
Short name T60
Test name
Test status
Simulation time 191125572 ps
CPU time 1.98 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:26:49 PM PDT 24
Peak memory 209936 kb
Host smart-d50aaf2b-d21f-4a98-8d84-1ce9788b2066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312389380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1312389380
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2298280967
Short name T606
Test name
Test status
Simulation time 43633588 ps
CPU time 0.86 seconds
Started Aug 06 05:26:48 PM PDT 24
Finished Aug 06 05:26:49 PM PDT 24
Peak memory 205944 kb
Host smart-b989b513-8cec-4835-9179-1044fa5b0c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298280967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2298280967
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1390052468
Short name T381
Test name
Test status
Simulation time 306748243 ps
CPU time 8.98 seconds
Started Aug 06 05:26:50 PM PDT 24
Finished Aug 06 05:27:00 PM PDT 24
Peak memory 215420 kb
Host smart-ed636b95-9c8c-498a-948e-8ced6350217d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390052468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1390052468
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.599141394
Short name T21
Test name
Test status
Simulation time 160258834 ps
CPU time 2.92 seconds
Started Aug 06 05:26:50 PM PDT 24
Finished Aug 06 05:26:54 PM PDT 24
Peak memory 209328 kb
Host smart-c10310ee-a807-4253-8c25-f013104a55bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599141394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.599141394
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3274885649
Short name T870
Test name
Test status
Simulation time 158694083 ps
CPU time 3.64 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:50 PM PDT 24
Peak memory 210032 kb
Host smart-ea668d40-3ca9-4ef2-9313-6c53fbe204b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274885649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3274885649
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.4209767540
Short name T624
Test name
Test status
Simulation time 198854555 ps
CPU time 3.39 seconds
Started Aug 06 05:26:50 PM PDT 24
Finished Aug 06 05:26:54 PM PDT 24
Peak memory 214344 kb
Host smart-905e2357-35f3-40a2-ac49-f629c8043e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209767540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.4209767540
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1722195151
Short name T897
Test name
Test status
Simulation time 139320611 ps
CPU time 2.66 seconds
Started Aug 06 05:26:48 PM PDT 24
Finished Aug 06 05:26:51 PM PDT 24
Peak memory 214172 kb
Host smart-5db32118-95ec-40cb-b515-7544ac841873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722195151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1722195151
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.683580922
Short name T617
Test name
Test status
Simulation time 305197376 ps
CPU time 3.63 seconds
Started Aug 06 05:26:48 PM PDT 24
Finished Aug 06 05:26:52 PM PDT 24
Peak memory 209392 kb
Host smart-018963de-5532-4924-a217-238d3766bbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683580922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.683580922
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1757028581
Short name T707
Test name
Test status
Simulation time 8521803580 ps
CPU time 63.22 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:27:50 PM PDT 24
Peak memory 218600 kb
Host smart-fedbf1b5-7193-4233-952c-e31e1d907ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757028581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1757028581
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3983731383
Short name T871
Test name
Test status
Simulation time 100425788 ps
CPU time 2.93 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:26:50 PM PDT 24
Peak memory 208340 kb
Host smart-eaf6eaa0-04b9-42ef-a223-bac47d745398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983731383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3983731383
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3636622630
Short name T414
Test name
Test status
Simulation time 231386585 ps
CPU time 6.14 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:52 PM PDT 24
Peak memory 208188 kb
Host smart-0cefc9b7-da7f-47c9-afc0-83f06d6f9440
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636622630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3636622630
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1698462065
Short name T677
Test name
Test status
Simulation time 222359006 ps
CPU time 4.97 seconds
Started Aug 06 05:26:49 PM PDT 24
Finished Aug 06 05:26:54 PM PDT 24
Peak memory 208688 kb
Host smart-87ea9db3-3eed-47dd-a3f0-16a6554cc0db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698462065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1698462065
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1666144057
Short name T420
Test name
Test status
Simulation time 124989065 ps
CPU time 3.25 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:50 PM PDT 24
Peak memory 206980 kb
Host smart-2cd92819-a536-40a5-a444-facb1bdc6c65
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666144057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1666144057
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2426112222
Short name T858
Test name
Test status
Simulation time 1192748650 ps
CPU time 4.18 seconds
Started Aug 06 05:26:50 PM PDT 24
Finished Aug 06 05:26:54 PM PDT 24
Peak memory 208844 kb
Host smart-c4629f5c-874e-435b-b0b6-0ffe06d4ca78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426112222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2426112222
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2697110789
Short name T493
Test name
Test status
Simulation time 68339261 ps
CPU time 2.76 seconds
Started Aug 06 05:26:46 PM PDT 24
Finished Aug 06 05:26:49 PM PDT 24
Peak memory 206736 kb
Host smart-a04715f8-0cf0-4067-9f33-44ab6e84f386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697110789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2697110789
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3642230098
Short name T594
Test name
Test status
Simulation time 3024386974 ps
CPU time 11.15 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:26:58 PM PDT 24
Peak memory 221088 kb
Host smart-7609831d-1228-4fb9-9233-e767eeb167fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642230098 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3642230098
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3111647643
Short name T230
Test name
Test status
Simulation time 1764524226 ps
CPU time 13.93 seconds
Started Aug 06 05:26:48 PM PDT 24
Finished Aug 06 05:27:02 PM PDT 24
Peak memory 218268 kb
Host smart-3a65ae4a-e1bd-43ca-871b-c3d7b11575ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111647643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3111647643
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3826060058
Short name T577
Test name
Test status
Simulation time 127920946 ps
CPU time 2.71 seconds
Started Aug 06 05:26:47 PM PDT 24
Finished Aug 06 05:26:50 PM PDT 24
Peak memory 210500 kb
Host smart-69206688-caab-4fe2-8e35-d94b44929b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826060058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3826060058
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1860279367
Short name T730
Test name
Test status
Simulation time 41527618 ps
CPU time 0.77 seconds
Started Aug 06 05:25:00 PM PDT 24
Finished Aug 06 05:25:01 PM PDT 24
Peak memory 205900 kb
Host smart-8df66169-83ce-4aa2-a067-435cb7c516b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860279367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1860279367
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.4020362371
Short name T270
Test name
Test status
Simulation time 4245873132 ps
CPU time 108.78 seconds
Started Aug 06 05:24:44 PM PDT 24
Finished Aug 06 05:26:33 PM PDT 24
Peak memory 214812 kb
Host smart-94fb3931-7c2e-48bf-934d-96d5b42096a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020362371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.4020362371
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2584642909
Short name T675
Test name
Test status
Simulation time 415402453 ps
CPU time 2.42 seconds
Started Aug 06 05:24:41 PM PDT 24
Finished Aug 06 05:24:44 PM PDT 24
Peak memory 208064 kb
Host smart-b25714f5-770e-4fb2-9e03-60aa492241aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584642909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2584642909
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3445972735
Short name T636
Test name
Test status
Simulation time 60035635 ps
CPU time 2.31 seconds
Started Aug 06 05:24:43 PM PDT 24
Finished Aug 06 05:24:46 PM PDT 24
Peak memory 214340 kb
Host smart-60684275-6e8f-4248-bb38-4666ac960e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445972735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3445972735
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1811436342
Short name T106
Test name
Test status
Simulation time 252832469 ps
CPU time 3.13 seconds
Started Aug 06 05:24:44 PM PDT 24
Finished Aug 06 05:24:47 PM PDT 24
Peak memory 214252 kb
Host smart-154eb3d3-eee1-48cd-b641-458b7f04b5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811436342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1811436342
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1897377582
Short name T696
Test name
Test status
Simulation time 213578003 ps
CPU time 3.67 seconds
Started Aug 06 05:24:42 PM PDT 24
Finished Aug 06 05:24:46 PM PDT 24
Peak memory 214400 kb
Host smart-f212a1cd-45b3-467d-b148-3c5613bf75e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897377582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1897377582
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2498384768
Short name T763
Test name
Test status
Simulation time 3850384090 ps
CPU time 32.61 seconds
Started Aug 06 05:24:43 PM PDT 24
Finished Aug 06 05:25:16 PM PDT 24
Peak memory 218456 kb
Host smart-6625977c-80ac-40fe-b15f-a1349364dd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498384768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2498384768
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2647351950
Short name T12
Test name
Test status
Simulation time 703413393 ps
CPU time 18.23 seconds
Started Aug 06 05:24:57 PM PDT 24
Finished Aug 06 05:25:16 PM PDT 24
Peak memory 232176 kb
Host smart-38496dd7-a19c-4f02-9d78-df09dc2a236d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647351950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2647351950
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2161586591
Short name T498
Test name
Test status
Simulation time 380982689 ps
CPU time 3.32 seconds
Started Aug 06 05:24:43 PM PDT 24
Finished Aug 06 05:24:46 PM PDT 24
Peak memory 208740 kb
Host smart-e539a7e0-310e-4db6-8502-6dbe3e07ac64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161586591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2161586591
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1011630146
Short name T82
Test name
Test status
Simulation time 78473699 ps
CPU time 3.12 seconds
Started Aug 06 05:24:44 PM PDT 24
Finished Aug 06 05:24:47 PM PDT 24
Peak memory 207328 kb
Host smart-73776154-9059-46c5-bba2-ca54e4d253ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011630146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1011630146
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3123331765
Short name T283
Test name
Test status
Simulation time 176908289 ps
CPU time 4.13 seconds
Started Aug 06 05:24:43 PM PDT 24
Finished Aug 06 05:24:47 PM PDT 24
Peak memory 208604 kb
Host smart-0b085649-a646-49fc-b381-a22aac3d2dc0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123331765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3123331765
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2086186328
Short name T901
Test name
Test status
Simulation time 103429418 ps
CPU time 2.26 seconds
Started Aug 06 05:24:42 PM PDT 24
Finished Aug 06 05:24:44 PM PDT 24
Peak memory 208816 kb
Host smart-4f92ba19-ad74-41c9-96fc-e9ee33ac5d9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086186328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2086186328
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.588924219
Short name T799
Test name
Test status
Simulation time 377801600 ps
CPU time 5.54 seconds
Started Aug 06 05:25:00 PM PDT 24
Finished Aug 06 05:25:06 PM PDT 24
Peak memory 210112 kb
Host smart-5b6cfb80-8e63-418e-be0f-128125c41e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588924219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.588924219
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3446578437
Short name T409
Test name
Test status
Simulation time 1033071477 ps
CPU time 2.68 seconds
Started Aug 06 05:24:42 PM PDT 24
Finished Aug 06 05:24:45 PM PDT 24
Peak memory 208416 kb
Host smart-22d3fdd1-26bd-44f8-a145-d612ffdb0232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446578437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3446578437
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1651997743
Short name T235
Test name
Test status
Simulation time 2856015372 ps
CPU time 21 seconds
Started Aug 06 05:25:01 PM PDT 24
Finished Aug 06 05:25:22 PM PDT 24
Peak memory 218316 kb
Host smart-1df12975-94b8-418a-aee2-61a00a911007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651997743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1651997743
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3810715633
Short name T563
Test name
Test status
Simulation time 402730662 ps
CPU time 4.54 seconds
Started Aug 06 05:24:42 PM PDT 24
Finished Aug 06 05:24:46 PM PDT 24
Peak memory 210172 kb
Host smart-71713b20-115f-4c1a-b5b7-46d1d576aaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810715633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3810715633
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2765236307
Short name T539
Test name
Test status
Simulation time 1371158789 ps
CPU time 23.84 seconds
Started Aug 06 05:24:57 PM PDT 24
Finished Aug 06 05:25:21 PM PDT 24
Peak memory 210872 kb
Host smart-14704ee0-3eac-41e5-baf0-a924091304e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765236307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2765236307
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1356742204
Short name T839
Test name
Test status
Simulation time 18430320 ps
CPU time 0.92 seconds
Started Aug 06 05:26:43 PM PDT 24
Finished Aug 06 05:26:44 PM PDT 24
Peak memory 205940 kb
Host smart-50985d34-f802-46e1-b351-4f39b0a29fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356742204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1356742204
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1499375382
Short name T77
Test name
Test status
Simulation time 1278656689 ps
CPU time 12.8 seconds
Started Aug 06 05:26:53 PM PDT 24
Finished Aug 06 05:27:06 PM PDT 24
Peak memory 214236 kb
Host smart-8642737a-b28c-4d4a-8094-383b0a7f1cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499375382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1499375382
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1740299692
Short name T603
Test name
Test status
Simulation time 399603767 ps
CPU time 3.83 seconds
Started Aug 06 05:26:53 PM PDT 24
Finished Aug 06 05:26:57 PM PDT 24
Peak memory 214260 kb
Host smart-c830528d-8ae5-4440-ac67-6147794b65f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740299692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1740299692
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.805214205
Short name T757
Test name
Test status
Simulation time 674111420 ps
CPU time 3.7 seconds
Started Aug 06 05:26:56 PM PDT 24
Finished Aug 06 05:27:00 PM PDT 24
Peak memory 220288 kb
Host smart-0ecf4640-f083-45ff-99be-db5026b0f089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805214205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.805214205
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.621858613
Short name T766
Test name
Test status
Simulation time 349593300 ps
CPU time 4.11 seconds
Started Aug 06 05:26:53 PM PDT 24
Finished Aug 06 05:26:57 PM PDT 24
Peak memory 208644 kb
Host smart-9fade0fc-e3d0-4c99-8468-2b4ad2630b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621858613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.621858613
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1531907517
Short name T742
Test name
Test status
Simulation time 42743141 ps
CPU time 1.85 seconds
Started Aug 06 05:26:57 PM PDT 24
Finished Aug 06 05:26:59 PM PDT 24
Peak memory 207332 kb
Host smart-1832fd50-c8be-4966-b2d4-6c1619208945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531907517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1531907517
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1863026377
Short name T832
Test name
Test status
Simulation time 107320776 ps
CPU time 3.7 seconds
Started Aug 06 05:26:52 PM PDT 24
Finished Aug 06 05:26:55 PM PDT 24
Peak memory 208496 kb
Host smart-d7dd8fc2-b7aa-41f8-b1d3-723c946d843e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863026377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1863026377
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1861294403
Short name T527
Test name
Test status
Simulation time 907741931 ps
CPU time 6.63 seconds
Started Aug 06 05:26:48 PM PDT 24
Finished Aug 06 05:26:54 PM PDT 24
Peak memory 208180 kb
Host smart-218d2b40-c488-4279-b3e8-3ac1db8279ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861294403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1861294403
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.828950022
Short name T578
Test name
Test status
Simulation time 22763313 ps
CPU time 1.81 seconds
Started Aug 06 05:26:57 PM PDT 24
Finished Aug 06 05:26:59 PM PDT 24
Peak memory 206704 kb
Host smart-afc14fcb-8c36-46f8-8e9c-ff1b306f6341
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828950022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.828950022
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1368558657
Short name T499
Test name
Test status
Simulation time 117241423 ps
CPU time 1.94 seconds
Started Aug 06 05:26:53 PM PDT 24
Finished Aug 06 05:26:55 PM PDT 24
Peak memory 209972 kb
Host smart-3668f198-5e11-44af-9c4a-59f23e71b2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368558657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1368558657
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3673020515
Short name T739
Test name
Test status
Simulation time 142874623 ps
CPU time 3.29 seconds
Started Aug 06 05:26:59 PM PDT 24
Finished Aug 06 05:27:02 PM PDT 24
Peak memory 208728 kb
Host smart-f21ecd50-094e-4e81-b341-41043d2c6772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673020515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3673020515
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3179708408
Short name T72
Test name
Test status
Simulation time 1011852549 ps
CPU time 12.81 seconds
Started Aug 06 05:26:55 PM PDT 24
Finished Aug 06 05:27:08 PM PDT 24
Peak memory 216324 kb
Host smart-ef5acd78-710c-4669-8d52-e74ab8167ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179708408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3179708408
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1019521506
Short name T268
Test name
Test status
Simulation time 365505019 ps
CPU time 4.55 seconds
Started Aug 06 05:26:59 PM PDT 24
Finished Aug 06 05:27:03 PM PDT 24
Peak memory 218256 kb
Host smart-bbecf4ef-e989-4e23-adb0-69c67b9022e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019521506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1019521506
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1670089816
Short name T579
Test name
Test status
Simulation time 61241298 ps
CPU time 2.6 seconds
Started Aug 06 05:26:55 PM PDT 24
Finished Aug 06 05:26:58 PM PDT 24
Peak memory 210364 kb
Host smart-60b8f699-ac1c-45a0-a13c-194574897454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670089816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1670089816
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.994988959
Short name T464
Test name
Test status
Simulation time 15954688 ps
CPU time 0.8 seconds
Started Aug 06 05:26:57 PM PDT 24
Finished Aug 06 05:26:57 PM PDT 24
Peak memory 205980 kb
Host smart-817af4d0-2c94-4ed1-afc8-f2d6a5368843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994988959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.994988959
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.107755634
Short name T732
Test name
Test status
Simulation time 41965803 ps
CPU time 3.34 seconds
Started Aug 06 05:27:01 PM PDT 24
Finished Aug 06 05:27:04 PM PDT 24
Peak memory 215364 kb
Host smart-c8d63aed-f6e9-4611-9c4a-ec244a17399e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107755634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.107755634
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.4056608675
Short name T821
Test name
Test status
Simulation time 63121834 ps
CPU time 2.76 seconds
Started Aug 06 05:26:56 PM PDT 24
Finished Aug 06 05:26:59 PM PDT 24
Peak memory 207260 kb
Host smart-1c005294-07d7-43ca-9c12-0e50b99928b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056608675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.4056608675
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1152536511
Short name T97
Test name
Test status
Simulation time 148575610 ps
CPU time 3.3 seconds
Started Aug 06 05:26:56 PM PDT 24
Finished Aug 06 05:26:59 PM PDT 24
Peak memory 220684 kb
Host smart-3bbe7589-aa0d-440f-b84e-1bfaf90c26c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152536511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1152536511
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.600504029
Short name T194
Test name
Test status
Simulation time 409819542 ps
CPU time 4.75 seconds
Started Aug 06 05:26:57 PM PDT 24
Finished Aug 06 05:27:02 PM PDT 24
Peak memory 214328 kb
Host smart-810c37d6-2545-46e2-bfbd-a552b36794b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600504029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.600504029
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3670044451
Short name T421
Test name
Test status
Simulation time 2508646884 ps
CPU time 39.39 seconds
Started Aug 06 05:26:56 PM PDT 24
Finished Aug 06 05:27:35 PM PDT 24
Peak memory 208012 kb
Host smart-451e8b7f-a7cb-4a8a-80ad-53584584efb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670044451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3670044451
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.528273873
Short name T334
Test name
Test status
Simulation time 205119236 ps
CPU time 3.39 seconds
Started Aug 06 05:26:55 PM PDT 24
Finished Aug 06 05:26:58 PM PDT 24
Peak memory 207180 kb
Host smart-045f94e5-323d-49f1-9fcd-28525f3fd232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528273873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.528273873
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2903857378
Short name T653
Test name
Test status
Simulation time 153414995 ps
CPU time 5.67 seconds
Started Aug 06 05:26:55 PM PDT 24
Finished Aug 06 05:27:01 PM PDT 24
Peak memory 208124 kb
Host smart-932f6a81-c46f-45b0-9174-cfda1274653c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903857378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2903857378
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3790632990
Short name T608
Test name
Test status
Simulation time 34741963 ps
CPU time 2.45 seconds
Started Aug 06 05:26:54 PM PDT 24
Finished Aug 06 05:26:57 PM PDT 24
Peak memory 208628 kb
Host smart-789497ac-1205-4202-b557-f936f52de2b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790632990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3790632990
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2962371023
Short name T644
Test name
Test status
Simulation time 153752715 ps
CPU time 5.95 seconds
Started Aug 06 05:27:03 PM PDT 24
Finished Aug 06 05:27:09 PM PDT 24
Peak memory 207972 kb
Host smart-7cc79fe1-5221-4e52-9724-cabe5d116451
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962371023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2962371023
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.638030540
Short name T412
Test name
Test status
Simulation time 134986765 ps
CPU time 2.23 seconds
Started Aug 06 05:26:59 PM PDT 24
Finished Aug 06 05:27:01 PM PDT 24
Peak memory 208168 kb
Host smart-48e8bf33-b30e-4906-bb54-26351d88e444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638030540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.638030540
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3573141418
Short name T616
Test name
Test status
Simulation time 1752017247 ps
CPU time 22.31 seconds
Started Aug 06 05:26:50 PM PDT 24
Finished Aug 06 05:27:13 PM PDT 24
Peak memory 208384 kb
Host smart-cd2a8909-e279-4de4-aa26-abfa3b3cef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573141418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3573141418
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1871257969
Short name T54
Test name
Test status
Simulation time 1562983276 ps
CPU time 36.17 seconds
Started Aug 06 05:26:59 PM PDT 24
Finished Aug 06 05:27:35 PM PDT 24
Peak memory 222576 kb
Host smart-3a5baee0-7774-4aac-b040-5f0354609c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871257969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1871257969
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1696747273
Short name T429
Test name
Test status
Simulation time 75849729 ps
CPU time 3.93 seconds
Started Aug 06 05:26:59 PM PDT 24
Finished Aug 06 05:27:03 PM PDT 24
Peak memory 209456 kb
Host smart-13188192-d852-40d4-adbf-240e9a7f42c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696747273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1696747273
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.987714486
Short name T460
Test name
Test status
Simulation time 88362114 ps
CPU time 2.31 seconds
Started Aug 06 05:27:00 PM PDT 24
Finished Aug 06 05:27:03 PM PDT 24
Peak memory 210028 kb
Host smart-87ee9fbc-94ee-4079-b4c6-00f2b73830d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987714486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.987714486
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1186891076
Short name T726
Test name
Test status
Simulation time 253232724 ps
CPU time 1.01 seconds
Started Aug 06 05:26:57 PM PDT 24
Finished Aug 06 05:26:58 PM PDT 24
Peak memory 205968 kb
Host smart-6e5db148-8db5-47ec-8d5c-8b01bfcd440b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186891076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1186891076
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1079186039
Short name T385
Test name
Test status
Simulation time 59725621 ps
CPU time 3.35 seconds
Started Aug 06 05:26:56 PM PDT 24
Finished Aug 06 05:27:00 PM PDT 24
Peak memory 214224 kb
Host smart-dc3fba85-d0c7-49d6-abb5-7ade48f0f73e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1079186039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1079186039
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2665940776
Short name T559
Test name
Test status
Simulation time 773179417 ps
CPU time 4.32 seconds
Started Aug 06 05:27:01 PM PDT 24
Finished Aug 06 05:27:05 PM PDT 24
Peak memory 222696 kb
Host smart-41402a27-ca39-4cab-8dfd-a73ddc12c2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665940776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2665940776
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2034070710
Short name T724
Test name
Test status
Simulation time 235033591 ps
CPU time 5.89 seconds
Started Aug 06 05:27:01 PM PDT 24
Finished Aug 06 05:27:07 PM PDT 24
Peak memory 214348 kb
Host smart-bc8078d5-5af7-4df8-99c6-379c7493c4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034070710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2034070710
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.751963023
Short name T541
Test name
Test status
Simulation time 35795110 ps
CPU time 2.07 seconds
Started Aug 06 05:26:59 PM PDT 24
Finished Aug 06 05:27:01 PM PDT 24
Peak memory 214340 kb
Host smart-7c5f5675-21a1-4c23-8a36-aadb93c0cf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751963023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.751963023
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2343209535
Short name T278
Test name
Test status
Simulation time 178811502 ps
CPU time 3.1 seconds
Started Aug 06 05:26:57 PM PDT 24
Finished Aug 06 05:27:00 PM PDT 24
Peak memory 214120 kb
Host smart-8337ea96-339a-49b2-aac5-e39af011c38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343209535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2343209535
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.872289680
Short name T366
Test name
Test status
Simulation time 209328155 ps
CPU time 4.49 seconds
Started Aug 06 05:26:57 PM PDT 24
Finished Aug 06 05:27:02 PM PDT 24
Peak memory 222488 kb
Host smart-59a79998-e471-463e-98f0-2d53f642f425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872289680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.872289680
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2004787695
Short name T838
Test name
Test status
Simulation time 52310574 ps
CPU time 3.27 seconds
Started Aug 06 05:27:00 PM PDT 24
Finished Aug 06 05:27:04 PM PDT 24
Peak memory 209596 kb
Host smart-98eb1939-f5c4-4fb5-bd55-73cc8f25cdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004787695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2004787695
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.915759536
Short name T718
Test name
Test status
Simulation time 68708182 ps
CPU time 3.21 seconds
Started Aug 06 05:27:01 PM PDT 24
Finished Aug 06 05:27:04 PM PDT 24
Peak memory 206780 kb
Host smart-a9fab55c-597c-4f4b-b960-da8b4bd08be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915759536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.915759536
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1482027381
Short name T735
Test name
Test status
Simulation time 832354120 ps
CPU time 7.63 seconds
Started Aug 06 05:27:03 PM PDT 24
Finished Aug 06 05:27:11 PM PDT 24
Peak memory 208884 kb
Host smart-1c92e6f2-fe70-49fa-837b-de0d2d1b735c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482027381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1482027381
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2735215857
Short name T406
Test name
Test status
Simulation time 755047438 ps
CPU time 6.18 seconds
Started Aug 06 05:26:59 PM PDT 24
Finished Aug 06 05:27:06 PM PDT 24
Peak memory 208264 kb
Host smart-8d3af829-cfc3-47c9-9a70-4fda90aaf4c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735215857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2735215857
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2985804062
Short name T454
Test name
Test status
Simulation time 234649525 ps
CPU time 4.8 seconds
Started Aug 06 05:26:58 PM PDT 24
Finished Aug 06 05:27:03 PM PDT 24
Peak memory 207880 kb
Host smart-332a2bef-924d-4957-b18d-b5836c3e4c69
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985804062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2985804062
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2761481712
Short name T633
Test name
Test status
Simulation time 27037755 ps
CPU time 2.19 seconds
Started Aug 06 05:26:57 PM PDT 24
Finished Aug 06 05:27:00 PM PDT 24
Peak memory 208048 kb
Host smart-ce1ec646-e96c-47e3-aa6e-b2380340b6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761481712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2761481712
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.531689023
Short name T402
Test name
Test status
Simulation time 162823032 ps
CPU time 2.69 seconds
Started Aug 06 05:26:56 PM PDT 24
Finished Aug 06 05:26:58 PM PDT 24
Peak memory 206884 kb
Host smart-d4b6b264-e6e7-4fc0-9501-7f6703f95a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531689023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.531689023
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1285499003
Short name T713
Test name
Test status
Simulation time 59392910541 ps
CPU time 341.67 seconds
Started Aug 06 05:27:02 PM PDT 24
Finished Aug 06 05:32:44 PM PDT 24
Peak memory 222404 kb
Host smart-5f0e1264-5da3-4b7f-abda-6f40ceca2fae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285499003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1285499003
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2941543092
Short name T367
Test name
Test status
Simulation time 94373597 ps
CPU time 4.39 seconds
Started Aug 06 05:27:03 PM PDT 24
Finished Aug 06 05:27:08 PM PDT 24
Peak memory 210240 kb
Host smart-3d7db9fb-853f-47e9-a9d7-b190c705c16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941543092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2941543092
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.4116114660
Short name T157
Test name
Test status
Simulation time 125437085 ps
CPU time 2.5 seconds
Started Aug 06 05:27:00 PM PDT 24
Finished Aug 06 05:27:03 PM PDT 24
Peak memory 210040 kb
Host smart-3d33a57a-5780-4f90-b66a-41cdb9845514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116114660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.4116114660
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3080498079
Short name T751
Test name
Test status
Simulation time 15474219 ps
CPU time 0.72 seconds
Started Aug 06 05:27:20 PM PDT 24
Finished Aug 06 05:27:21 PM PDT 24
Peak memory 205956 kb
Host smart-b77019e4-d3a6-4a81-a278-4c89c7a896c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080498079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3080498079
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2919856159
Short name T306
Test name
Test status
Simulation time 58100374 ps
CPU time 3.98 seconds
Started Aug 06 05:26:58 PM PDT 24
Finished Aug 06 05:27:02 PM PDT 24
Peak memory 215540 kb
Host smart-87ec86db-f5c5-49a3-8b32-470c26517c86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919856159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2919856159
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.4232065436
Short name T5
Test name
Test status
Simulation time 33416382 ps
CPU time 2.09 seconds
Started Aug 06 05:27:02 PM PDT 24
Finished Aug 06 05:27:04 PM PDT 24
Peak memory 209664 kb
Host smart-578a529d-a32b-4b3b-a097-d90a7be822b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232065436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.4232065436
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1622052100
Short name T781
Test name
Test status
Simulation time 30904860 ps
CPU time 1.47 seconds
Started Aug 06 05:26:57 PM PDT 24
Finished Aug 06 05:26:59 PM PDT 24
Peak memory 208168 kb
Host smart-7335bf26-a522-4dc1-b325-d29e8aae9bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622052100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1622052100
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2569038032
Short name T843
Test name
Test status
Simulation time 89097677 ps
CPU time 1.64 seconds
Started Aug 06 05:27:00 PM PDT 24
Finished Aug 06 05:27:01 PM PDT 24
Peak memory 214400 kb
Host smart-520f10f2-64c2-419b-9ff8-11d4997e9a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569038032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2569038032
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2402074367
Short name T494
Test name
Test status
Simulation time 37576955 ps
CPU time 2.42 seconds
Started Aug 06 05:27:05 PM PDT 24
Finished Aug 06 05:27:08 PM PDT 24
Peak memory 214172 kb
Host smart-0473ca52-e14d-4adb-ab73-acc8ec863a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402074367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2402074367
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.705752008
Short name T189
Test name
Test status
Simulation time 25580133 ps
CPU time 1.66 seconds
Started Aug 06 05:26:57 PM PDT 24
Finished Aug 06 05:26:59 PM PDT 24
Peak memory 214804 kb
Host smart-2d180b83-0964-4d10-beac-63d71d2458b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705752008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.705752008
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3432435201
Short name T293
Test name
Test status
Simulation time 1144809251 ps
CPU time 8.51 seconds
Started Aug 06 05:27:01 PM PDT 24
Finished Aug 06 05:27:10 PM PDT 24
Peak memory 208468 kb
Host smart-e053f5b4-abb3-419c-82c4-1c1223075eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432435201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3432435201
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1276613099
Short name T834
Test name
Test status
Simulation time 945882815 ps
CPU time 21.41 seconds
Started Aug 06 05:27:01 PM PDT 24
Finished Aug 06 05:27:22 PM PDT 24
Peak memory 208808 kb
Host smart-d2e23d47-5b07-469f-9a36-221eff294ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276613099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1276613099
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2521807820
Short name T296
Test name
Test status
Simulation time 1320864100 ps
CPU time 9.48 seconds
Started Aug 06 05:26:57 PM PDT 24
Finished Aug 06 05:27:06 PM PDT 24
Peak memory 207036 kb
Host smart-abb3df83-96a0-4574-9776-9f4ae7af8e73
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521807820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2521807820
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3615617811
Short name T486
Test name
Test status
Simulation time 3455206558 ps
CPU time 60.32 seconds
Started Aug 06 05:27:07 PM PDT 24
Finished Aug 06 05:28:07 PM PDT 24
Peak memory 208824 kb
Host smart-e10f5bbe-7e11-456b-beb3-1e4ea1c0a0cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615617811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3615617811
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1911107129
Short name T659
Test name
Test status
Simulation time 74444401 ps
CPU time 2.75 seconds
Started Aug 06 05:27:01 PM PDT 24
Finished Aug 06 05:27:04 PM PDT 24
Peak memory 208940 kb
Host smart-bdab0a82-61b0-4e12-8e78-eb8045242299
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911107129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1911107129
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.4063438352
Short name T678
Test name
Test status
Simulation time 82887451 ps
CPU time 4.35 seconds
Started Aug 06 05:26:58 PM PDT 24
Finished Aug 06 05:27:02 PM PDT 24
Peak memory 210404 kb
Host smart-6457a11a-4436-4b76-a555-5173c49fc3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063438352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.4063438352
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.970319579
Short name T795
Test name
Test status
Simulation time 75299654 ps
CPU time 3.35 seconds
Started Aug 06 05:27:00 PM PDT 24
Finished Aug 06 05:27:03 PM PDT 24
Peak memory 208400 kb
Host smart-d2379c8e-c62c-4a33-99eb-ab16c2346590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970319579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.970319579
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.4065967753
Short name T208
Test name
Test status
Simulation time 2963513296 ps
CPU time 30.15 seconds
Started Aug 06 05:27:21 PM PDT 24
Finished Aug 06 05:27:51 PM PDT 24
Peak memory 222500 kb
Host smart-7b19d3ea-5271-470b-92a9-9cfad39f742a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065967753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.4065967753
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2032272250
Short name T760
Test name
Test status
Simulation time 1149161653 ps
CPU time 3.87 seconds
Started Aug 06 05:27:04 PM PDT 24
Finished Aug 06 05:27:08 PM PDT 24
Peak memory 206948 kb
Host smart-fbdbb089-e5a7-412d-a5f5-770c9320f699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032272250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2032272250
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3820786383
Short name T714
Test name
Test status
Simulation time 1052769982 ps
CPU time 6.91 seconds
Started Aug 06 05:27:18 PM PDT 24
Finished Aug 06 05:27:26 PM PDT 24
Peak memory 210960 kb
Host smart-ebe3753a-d268-4a2d-b402-c08a75f3b965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820786383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3820786383
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3784875898
Short name T668
Test name
Test status
Simulation time 29150880 ps
CPU time 0.93 seconds
Started Aug 06 05:27:20 PM PDT 24
Finished Aug 06 05:27:21 PM PDT 24
Peak memory 206100 kb
Host smart-44ecb776-e957-4940-96ac-c55499960896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784875898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3784875898
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1415602384
Short name T377
Test name
Test status
Simulation time 189195128 ps
CPU time 9.95 seconds
Started Aug 06 05:27:20 PM PDT 24
Finished Aug 06 05:27:30 PM PDT 24
Peak memory 222484 kb
Host smart-17cff059-f5c2-42a8-a423-95f82dedf78c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415602384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1415602384
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2316064973
Short name T23
Test name
Test status
Simulation time 92620420 ps
CPU time 1.55 seconds
Started Aug 06 05:27:22 PM PDT 24
Finished Aug 06 05:27:24 PM PDT 24
Peak memory 216120 kb
Host smart-465266b6-257f-4404-94fc-a9dac14e8ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316064973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2316064973
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1099816552
Short name T69
Test name
Test status
Simulation time 580184204 ps
CPU time 10.02 seconds
Started Aug 06 05:27:20 PM PDT 24
Finished Aug 06 05:27:30 PM PDT 24
Peak memory 208184 kb
Host smart-c1eb44d2-0d0a-4247-a925-69ea80cce063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099816552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1099816552
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.540026012
Short name T280
Test name
Test status
Simulation time 269273673 ps
CPU time 2.37 seconds
Started Aug 06 05:27:21 PM PDT 24
Finished Aug 06 05:27:23 PM PDT 24
Peak memory 215160 kb
Host smart-e12ded8f-907b-4797-a149-f4bb88b013db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540026012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.540026012
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3791113951
Short name T201
Test name
Test status
Simulation time 103590982 ps
CPU time 4.59 seconds
Started Aug 06 05:27:20 PM PDT 24
Finished Aug 06 05:27:25 PM PDT 24
Peak memory 209948 kb
Host smart-144d5fb8-404f-4eff-bc25-e9b0f94ce19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791113951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3791113951
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3270942078
Short name T444
Test name
Test status
Simulation time 202400355 ps
CPU time 4.9 seconds
Started Aug 06 05:27:22 PM PDT 24
Finished Aug 06 05:27:27 PM PDT 24
Peak memory 218248 kb
Host smart-089b9806-e4a0-4389-b49e-e9d82716d855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270942078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3270942078
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3892581497
Short name T789
Test name
Test status
Simulation time 66167016 ps
CPU time 3.39 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:27 PM PDT 24
Peak memory 208196 kb
Host smart-993d0bb7-8d48-405b-b8fb-aa0b890e181b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892581497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3892581497
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3974963736
Short name T796
Test name
Test status
Simulation time 159306210 ps
CPU time 3.56 seconds
Started Aug 06 05:27:19 PM PDT 24
Finished Aug 06 05:27:23 PM PDT 24
Peak memory 208664 kb
Host smart-58d862fe-cc86-4180-a69e-f0033e69867e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974963736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3974963736
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.141867717
Short name T673
Test name
Test status
Simulation time 426553190 ps
CPU time 4.74 seconds
Started Aug 06 05:27:18 PM PDT 24
Finished Aug 06 05:27:23 PM PDT 24
Peak memory 208948 kb
Host smart-f6f687ad-94c6-4dc2-89ce-02c122297097
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141867717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.141867717
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3735262731
Short name T417
Test name
Test status
Simulation time 131788356 ps
CPU time 4.03 seconds
Started Aug 06 05:27:19 PM PDT 24
Finished Aug 06 05:27:23 PM PDT 24
Peak memory 206868 kb
Host smart-f4f6f282-d8a9-456e-930a-7f226810a04e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735262731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3735262731
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3870192430
Short name T183
Test name
Test status
Simulation time 314758136 ps
CPU time 3.2 seconds
Started Aug 06 05:27:21 PM PDT 24
Finished Aug 06 05:27:24 PM PDT 24
Peak memory 209744 kb
Host smart-29c773d7-8c47-44a4-a210-10cc1a55152a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870192430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3870192430
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3074092964
Short name T590
Test name
Test status
Simulation time 1557274145 ps
CPU time 9.47 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:33 PM PDT 24
Peak memory 208528 kb
Host smart-bda50679-a8ac-44d7-bdf9-d8b0e8e3b6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074092964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3074092964
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2598463052
Short name T700
Test name
Test status
Simulation time 70380057 ps
CPU time 3.18 seconds
Started Aug 06 05:27:22 PM PDT 24
Finished Aug 06 05:27:25 PM PDT 24
Peak memory 208212 kb
Host smart-7eab3873-5b7d-4fd8-b78e-d1920bc892ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598463052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2598463052
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2464086772
Short name T589
Test name
Test status
Simulation time 74247834 ps
CPU time 1.59 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:25 PM PDT 24
Peak memory 209692 kb
Host smart-6a26412a-d14f-4861-81ce-78a19aa52e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464086772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2464086772
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3972974325
Short name T646
Test name
Test status
Simulation time 37047880 ps
CPU time 0.75 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:25 PM PDT 24
Peak memory 205828 kb
Host smart-4f8f4ce0-4b8f-4ee6-82de-f383931eb982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972974325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3972974325
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2210291416
Short name T86
Test name
Test status
Simulation time 100542652 ps
CPU time 5.69 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:28 PM PDT 24
Peak memory 214240 kb
Host smart-9673e567-120c-4af8-8477-cecb2e0d171b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2210291416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2210291416
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3265446658
Short name T29
Test name
Test status
Simulation time 93668193 ps
CPU time 5.19 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:29 PM PDT 24
Peak memory 222680 kb
Host smart-60eaeebd-4f33-4c7f-a552-7ce9627947c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265446658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3265446658
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1742565410
Short name T47
Test name
Test status
Simulation time 71588545 ps
CPU time 3.31 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:26 PM PDT 24
Peak memory 218284 kb
Host smart-cd55aeff-e5c5-48e3-96e5-f97f95a46779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742565410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1742565410
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2723442371
Short name T25
Test name
Test status
Simulation time 123056392 ps
CPU time 3.34 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:27 PM PDT 24
Peak memory 209336 kb
Host smart-44ebbd4d-c7f6-4b71-b280-403aec2da8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723442371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2723442371
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3837979836
Short name T18
Test name
Test status
Simulation time 80241528 ps
CPU time 2.89 seconds
Started Aug 06 05:27:26 PM PDT 24
Finished Aug 06 05:27:29 PM PDT 24
Peak memory 214292 kb
Host smart-118a24f8-c5fd-44ae-bda4-dfbaef4ee1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837979836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3837979836
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2166366510
Short name T745
Test name
Test status
Simulation time 353395775 ps
CPU time 8.49 seconds
Started Aug 06 05:27:26 PM PDT 24
Finished Aug 06 05:27:34 PM PDT 24
Peak memory 209164 kb
Host smart-7d159dda-17bf-4bec-9db8-f88c5e791378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166366510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2166366510
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3850566338
Short name T802
Test name
Test status
Simulation time 11519610616 ps
CPU time 98.08 seconds
Started Aug 06 05:27:22 PM PDT 24
Finished Aug 06 05:29:01 PM PDT 24
Peak memory 222456 kb
Host smart-f05b2daa-6b57-4ea2-bde6-25a6767f24ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850566338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3850566338
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3403122181
Short name T768
Test name
Test status
Simulation time 173464805 ps
CPU time 2.34 seconds
Started Aug 06 05:27:21 PM PDT 24
Finished Aug 06 05:27:23 PM PDT 24
Peak memory 208912 kb
Host smart-dbc7d741-d229-4b1b-b51e-d5c1d330c954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403122181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3403122181
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.595170516
Short name T237
Test name
Test status
Simulation time 80468862 ps
CPU time 3.99 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:28 PM PDT 24
Peak memory 208968 kb
Host smart-95182d05-dee9-4781-8103-4f0fe36b2f73
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595170516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.595170516
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1831283294
Short name T628
Test name
Test status
Simulation time 308729988 ps
CPU time 4.25 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:29 PM PDT 24
Peak memory 207060 kb
Host smart-d4d00f7a-6386-410b-893c-bc3cc1761ac1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831283294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1831283294
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2652179512
Short name T442
Test name
Test status
Simulation time 1714578294 ps
CPU time 5.29 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:29 PM PDT 24
Peak memory 208884 kb
Host smart-290c67c4-d7ae-4600-b106-9be0f5a5663d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652179512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2652179512
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3112851297
Short name T881
Test name
Test status
Simulation time 120597936 ps
CPU time 3.5 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:27 PM PDT 24
Peak memory 209040 kb
Host smart-15d32a46-1cca-4812-ae54-b819d29f9bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112851297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3112851297
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3762794477
Short name T392
Test name
Test status
Simulation time 142710733 ps
CPU time 3.73 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:26 PM PDT 24
Peak memory 208420 kb
Host smart-c45425af-ce1c-4563-a75b-a0b6b4e40638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762794477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3762794477
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2296443279
Short name T370
Test name
Test status
Simulation time 620772633 ps
CPU time 8.84 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:32 PM PDT 24
Peak memory 214308 kb
Host smart-ed59ac78-cc1f-4f8d-b411-88f7deee89f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296443279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2296443279
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.897779344
Short name T631
Test name
Test status
Simulation time 49573036 ps
CPU time 1.82 seconds
Started Aug 06 05:27:25 PM PDT 24
Finished Aug 06 05:27:27 PM PDT 24
Peak memory 209816 kb
Host smart-29db3815-8e21-43b7-b02d-6f3d0136a5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897779344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.897779344
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3326310668
Short name T410
Test name
Test status
Simulation time 96878225 ps
CPU time 0.75 seconds
Started Aug 06 05:27:21 PM PDT 24
Finished Aug 06 05:27:22 PM PDT 24
Peak memory 205932 kb
Host smart-52f71581-644e-4549-8968-5d9f6f76c3c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326310668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3326310668
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2150794295
Short name T40
Test name
Test status
Simulation time 151569604 ps
CPU time 2.16 seconds
Started Aug 06 05:27:22 PM PDT 24
Finished Aug 06 05:27:25 PM PDT 24
Peak memory 218036 kb
Host smart-985899bf-c9ad-448b-90b4-64363d23dbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150794295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2150794295
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2412359707
Short name T71
Test name
Test status
Simulation time 87980352 ps
CPU time 3.07 seconds
Started Aug 06 05:27:25 PM PDT 24
Finished Aug 06 05:27:28 PM PDT 24
Peak memory 214308 kb
Host smart-feda91ef-95b8-4626-ad16-574d18fa8902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412359707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2412359707
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2618618945
Short name T434
Test name
Test status
Simulation time 148788362 ps
CPU time 2.5 seconds
Started Aug 06 05:27:20 PM PDT 24
Finished Aug 06 05:27:23 PM PDT 24
Peak memory 214188 kb
Host smart-dcb36cbe-1305-4484-bf8f-867e735b31ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618618945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2618618945
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.4051435376
Short name T225
Test name
Test status
Simulation time 450857281 ps
CPU time 5.29 seconds
Started Aug 06 05:27:22 PM PDT 24
Finished Aug 06 05:27:27 PM PDT 24
Peak memory 215304 kb
Host smart-52455af9-d92d-4cbf-ab3f-82463a77649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051435376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.4051435376
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.974893468
Short name T505
Test name
Test status
Simulation time 92910471 ps
CPU time 3.88 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:28 PM PDT 24
Peak memory 214400 kb
Host smart-d39261ec-ba3f-4270-a0a3-e050be384226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974893468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.974893468
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1072511076
Short name T503
Test name
Test status
Simulation time 454610401 ps
CPU time 5.71 seconds
Started Aug 06 05:27:27 PM PDT 24
Finished Aug 06 05:27:33 PM PDT 24
Peak memory 207264 kb
Host smart-eaf78049-2670-418e-9ad0-31dd33cfc6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072511076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1072511076
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.4083475533
Short name T558
Test name
Test status
Simulation time 170034993 ps
CPU time 1.87 seconds
Started Aug 06 05:27:27 PM PDT 24
Finished Aug 06 05:27:29 PM PDT 24
Peak memory 207296 kb
Host smart-e2a7a434-61a8-4e52-aec8-e43b38e17acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083475533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.4083475533
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2384766432
Short name T534
Test name
Test status
Simulation time 93338809 ps
CPU time 3.93 seconds
Started Aug 06 05:27:25 PM PDT 24
Finished Aug 06 05:27:29 PM PDT 24
Peak memory 206988 kb
Host smart-4e09c3a0-1c65-43e1-807b-c5d23dee6662
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384766432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2384766432
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3980957332
Short name T804
Test name
Test status
Simulation time 133877245 ps
CPU time 4.29 seconds
Started Aug 06 05:27:22 PM PDT 24
Finished Aug 06 05:27:26 PM PDT 24
Peak memory 208572 kb
Host smart-37b21115-7486-43e4-9ee7-1ddbc0f9889b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980957332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3980957332
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.539339569
Short name T481
Test name
Test status
Simulation time 708914746 ps
CPU time 17.3 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:40 PM PDT 24
Peak memory 208188 kb
Host smart-98b94e0d-762b-402b-ad00-a359cb59b366
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539339569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.539339569
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2316761052
Short name T524
Test name
Test status
Simulation time 28905640 ps
CPU time 2.47 seconds
Started Aug 06 05:27:19 PM PDT 24
Finished Aug 06 05:27:22 PM PDT 24
Peak memory 215976 kb
Host smart-56ef83e5-f877-4703-bb20-b6e3808f122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316761052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2316761052
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1622231955
Short name T107
Test name
Test status
Simulation time 101792443 ps
CPU time 2.94 seconds
Started Aug 06 05:27:25 PM PDT 24
Finished Aug 06 05:27:28 PM PDT 24
Peak memory 208252 kb
Host smart-c669d6f9-16ed-4dcb-9178-4b12733d9c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622231955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1622231955
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3890568981
Short name T198
Test name
Test status
Simulation time 1725820587 ps
CPU time 32.06 seconds
Started Aug 06 05:27:21 PM PDT 24
Finished Aug 06 05:27:54 PM PDT 24
Peak memory 222440 kb
Host smart-1c9dd6a2-e27a-4c72-8e6f-6716544b2c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890568981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3890568981
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2820848771
Short name T680
Test name
Test status
Simulation time 195307434 ps
CPU time 2.9 seconds
Started Aug 06 05:27:25 PM PDT 24
Finished Aug 06 05:27:28 PM PDT 24
Peak memory 208336 kb
Host smart-9c58ce24-7656-4a51-b49b-0b2fb32a3099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820848771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2820848771
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.718271400
Short name T701
Test name
Test status
Simulation time 265467564 ps
CPU time 2.18 seconds
Started Aug 06 05:27:21 PM PDT 24
Finished Aug 06 05:27:23 PM PDT 24
Peak memory 210444 kb
Host smart-f7116133-4142-43aa-b236-df772fcc5ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718271400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.718271400
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3915078359
Short name T469
Test name
Test status
Simulation time 52852913 ps
CPU time 0.73 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:25 PM PDT 24
Peak memory 205976 kb
Host smart-6fe05514-e2a6-493a-ac2f-e9eacaa1ad90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915078359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3915078359
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.969360493
Short name T854
Test name
Test status
Simulation time 351293355 ps
CPU time 4.35 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:28 PM PDT 24
Peak memory 214380 kb
Host smart-066d0ece-1855-477d-b9fd-a49532244634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969360493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.969360493
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1741956561
Short name T241
Test name
Test status
Simulation time 113370205 ps
CPU time 3.27 seconds
Started Aug 06 05:27:21 PM PDT 24
Finished Aug 06 05:27:24 PM PDT 24
Peak memory 209264 kb
Host smart-7cbb0994-ab6b-4613-9444-3a95fb607b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741956561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1741956561
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.685518969
Short name T761
Test name
Test status
Simulation time 53539978 ps
CPU time 2.01 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:26 PM PDT 24
Peak memory 214396 kb
Host smart-38317707-f84d-44bf-b3ee-e0adc29648e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685518969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.685518969
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1870549866
Short name T635
Test name
Test status
Simulation time 131300800 ps
CPU time 2.89 seconds
Started Aug 06 05:27:22 PM PDT 24
Finished Aug 06 05:27:25 PM PDT 24
Peak memory 222360 kb
Host smart-fa341813-a7fe-424e-9294-11190e7bc3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870549866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1870549866
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1640252125
Short name T195
Test name
Test status
Simulation time 78372153 ps
CPU time 2.39 seconds
Started Aug 06 05:27:22 PM PDT 24
Finished Aug 06 05:27:25 PM PDT 24
Peak memory 207548 kb
Host smart-e8cf5244-715b-4c69-bb8f-ded866d032da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640252125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1640252125
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.670598363
Short name T463
Test name
Test status
Simulation time 1003274644 ps
CPU time 9.14 seconds
Started Aug 06 05:27:21 PM PDT 24
Finished Aug 06 05:27:31 PM PDT 24
Peak memory 214264 kb
Host smart-8eaddc83-c645-43e4-9b18-377f23eeb384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670598363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.670598363
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.4182136259
Short name T391
Test name
Test status
Simulation time 270382328 ps
CPU time 8.7 seconds
Started Aug 06 05:27:22 PM PDT 24
Finished Aug 06 05:27:31 PM PDT 24
Peak memory 208700 kb
Host smart-58d76d6c-ed66-480c-bfb9-87a6494e3690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182136259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.4182136259
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.946201207
Short name T523
Test name
Test status
Simulation time 736336269 ps
CPU time 6.67 seconds
Started Aug 06 05:27:20 PM PDT 24
Finished Aug 06 05:27:27 PM PDT 24
Peak memory 208212 kb
Host smart-1bf383df-dd33-471e-8115-cd3ebaf46df6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946201207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.946201207
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2066662388
Short name T348
Test name
Test status
Simulation time 250127143 ps
CPU time 2.41 seconds
Started Aug 06 05:27:20 PM PDT 24
Finished Aug 06 05:27:22 PM PDT 24
Peak memory 206936 kb
Host smart-360bba75-fdc3-4d1b-89ed-607dfffa8244
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066662388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2066662388
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3114022443
Short name T889
Test name
Test status
Simulation time 59072033 ps
CPU time 2.05 seconds
Started Aug 06 05:27:20 PM PDT 24
Finished Aug 06 05:27:22 PM PDT 24
Peak memory 208684 kb
Host smart-9ff1c881-dc18-4aca-a1f7-39d921791ab3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114022443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3114022443
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.725371158
Short name T475
Test name
Test status
Simulation time 86946615 ps
CPU time 3.73 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:27 PM PDT 24
Peak memory 208716 kb
Host smart-d3a8f1a4-be73-41c3-b1cc-67e63a90f1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725371158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.725371158
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3025130398
Short name T474
Test name
Test status
Simulation time 973436421 ps
CPU time 3.39 seconds
Started Aug 06 05:27:20 PM PDT 24
Finished Aug 06 05:27:23 PM PDT 24
Peak memory 206832 kb
Host smart-696e40a5-8c80-4c43-862f-e427f4d88991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025130398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3025130398
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.146699906
Short name T167
Test name
Test status
Simulation time 243533604 ps
CPU time 6.21 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:30 PM PDT 24
Peak memory 221328 kb
Host smart-f1012cb9-ca0e-4965-a8a0-04de1701606f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146699906 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.146699906
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2927583289
Short name T252
Test name
Test status
Simulation time 109487246 ps
CPU time 4.41 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:28 PM PDT 24
Peak memory 209308 kb
Host smart-500bcace-9c65-4143-97f8-4e49f30600c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927583289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2927583289
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3278635359
Short name T896
Test name
Test status
Simulation time 628914067 ps
CPU time 3.6 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:27 PM PDT 24
Peak memory 210320 kb
Host smart-c84ba116-7004-4b6d-8eee-411e8e37214b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278635359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3278635359
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2921871580
Short name T526
Test name
Test status
Simulation time 34777861 ps
CPU time 0.73 seconds
Started Aug 06 05:27:48 PM PDT 24
Finished Aug 06 05:27:49 PM PDT 24
Peak memory 205956 kb
Host smart-77e70a04-f4bd-432c-8ef1-3c90c50806eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921871580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2921871580
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2936011582
Short name T357
Test name
Test status
Simulation time 33656153 ps
CPU time 2.61 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:26 PM PDT 24
Peak memory 214516 kb
Host smart-4e6d105d-775b-44b5-8db4-d6c14e01c3e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936011582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2936011582
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3489181200
Short name T549
Test name
Test status
Simulation time 1916803048 ps
CPU time 6.43 seconds
Started Aug 06 05:27:51 PM PDT 24
Finished Aug 06 05:27:58 PM PDT 24
Peak memory 220360 kb
Host smart-aaf035d6-c5f1-4c69-ad9f-991c6bd6fcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489181200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3489181200
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1293375326
Short name T615
Test name
Test status
Simulation time 65260189 ps
CPU time 2.99 seconds
Started Aug 06 05:27:52 PM PDT 24
Finished Aug 06 05:27:55 PM PDT 24
Peak memory 210284 kb
Host smart-ac733c28-3e29-479c-bf58-b40d56270044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293375326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1293375326
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2381255707
Short name T488
Test name
Test status
Simulation time 102894916 ps
CPU time 3.84 seconds
Started Aug 06 05:27:52 PM PDT 24
Finished Aug 06 05:27:55 PM PDT 24
Peak memory 214256 kb
Host smart-2d6c96a2-9acc-4d85-82b9-57457b32ecf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381255707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2381255707
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.822438215
Short name T452
Test name
Test status
Simulation time 54005942 ps
CPU time 2.39 seconds
Started Aug 06 05:27:52 PM PDT 24
Finished Aug 06 05:27:55 PM PDT 24
Peak memory 209600 kb
Host smart-3821007c-20ee-4dc0-95ae-b4cf60e84258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822438215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.822438215
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2282120483
Short name T219
Test name
Test status
Simulation time 665649014 ps
CPU time 4.12 seconds
Started Aug 06 05:27:22 PM PDT 24
Finished Aug 06 05:27:27 PM PDT 24
Peak memory 208480 kb
Host smart-abbb6778-df6d-42f5-a878-a189b67a304f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282120483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2282120483
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2634549328
Short name T567
Test name
Test status
Simulation time 517783412 ps
CPU time 13.27 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:37 PM PDT 24
Peak memory 207948 kb
Host smart-3b78a621-7eeb-4e5e-b9c7-ff7e0f9fbc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634549328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2634549328
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1953300500
Short name T599
Test name
Test status
Simulation time 10461056787 ps
CPU time 26 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:50 PM PDT 24
Peak memory 208740 kb
Host smart-7d19e368-5ad4-4baf-9c28-bd64c0b57780
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953300500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1953300500
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.455308505
Short name T182
Test name
Test status
Simulation time 66036152 ps
CPU time 2.96 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:27 PM PDT 24
Peak memory 207976 kb
Host smart-78fd9ff0-79eb-48a7-b037-1dfdf20c1b6e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455308505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.455308505
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.4254921723
Short name T403
Test name
Test status
Simulation time 602763047 ps
CPU time 6.95 seconds
Started Aug 06 05:27:24 PM PDT 24
Finished Aug 06 05:27:31 PM PDT 24
Peak memory 208912 kb
Host smart-3fcd5786-3f0e-4498-a3bd-f3a664dd9fe6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254921723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.4254921723
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1596731696
Short name T552
Test name
Test status
Simulation time 129849703 ps
CPU time 2.4 seconds
Started Aug 06 05:27:48 PM PDT 24
Finished Aug 06 05:27:51 PM PDT 24
Peak memory 215788 kb
Host smart-fd7b420e-9eb8-46a7-9051-0d3dfc320472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596731696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1596731696
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3904008111
Short name T521
Test name
Test status
Simulation time 177173478 ps
CPU time 2.52 seconds
Started Aug 06 05:27:23 PM PDT 24
Finished Aug 06 05:27:26 PM PDT 24
Peak memory 206824 kb
Host smart-2c58b92f-a5c6-4510-b8cd-fc863e4343e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904008111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3904008111
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.220309547
Short name T1
Test name
Test status
Simulation time 111512838 ps
CPU time 5.81 seconds
Started Aug 06 05:27:52 PM PDT 24
Finished Aug 06 05:27:58 PM PDT 24
Peak memory 215020 kb
Host smart-c41617f8-9ae7-4ab7-b5da-12428496bdc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220309547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.220309547
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2561236065
Short name T432
Test name
Test status
Simulation time 1230510102 ps
CPU time 37.62 seconds
Started Aug 06 05:27:47 PM PDT 24
Finished Aug 06 05:28:24 PM PDT 24
Peak memory 214300 kb
Host smart-f8cab765-243c-40ac-958e-4c03a853df31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561236065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2561236065
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.393504966
Short name T56
Test name
Test status
Simulation time 84425289 ps
CPU time 1.78 seconds
Started Aug 06 05:27:52 PM PDT 24
Finished Aug 06 05:27:54 PM PDT 24
Peak memory 210132 kb
Host smart-f951a310-5c13-4770-b387-0e0a94d46c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393504966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.393504966
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2433106961
Short name T418
Test name
Test status
Simulation time 115604724 ps
CPU time 0.74 seconds
Started Aug 06 05:27:51 PM PDT 24
Finished Aug 06 05:27:52 PM PDT 24
Peak memory 205992 kb
Host smart-e451a869-1cac-4647-8a9e-83b41c15740b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433106961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2433106961
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2860005666
Short name T361
Test name
Test status
Simulation time 41196236 ps
CPU time 3.15 seconds
Started Aug 06 05:27:52 PM PDT 24
Finished Aug 06 05:27:55 PM PDT 24
Peak memory 214228 kb
Host smart-a5844d8a-3968-4b96-b219-d49b347c4154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2860005666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2860005666
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.200285189
Short name T852
Test name
Test status
Simulation time 99074420 ps
CPU time 2.95 seconds
Started Aug 06 05:27:50 PM PDT 24
Finished Aug 06 05:27:54 PM PDT 24
Peak memory 214536 kb
Host smart-e13c08a2-e1bf-42f4-a0b4-ddb91abfef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200285189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.200285189
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.666655197
Short name T485
Test name
Test status
Simulation time 110352670 ps
CPU time 2.73 seconds
Started Aug 06 05:27:48 PM PDT 24
Finished Aug 06 05:27:50 PM PDT 24
Peak memory 215236 kb
Host smart-3656a187-7cb4-4a1c-8eae-b11c5c2a7ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666655197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.666655197
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2798934220
Short name T279
Test name
Test status
Simulation time 141512584 ps
CPU time 6.12 seconds
Started Aug 06 05:27:52 PM PDT 24
Finished Aug 06 05:27:58 PM PDT 24
Peak memory 214272 kb
Host smart-f56f4a2b-a85e-43ee-87f0-f7b8d954ae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798934220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2798934220
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.727374654
Short name T53
Test name
Test status
Simulation time 39799447 ps
CPU time 2.29 seconds
Started Aug 06 05:27:49 PM PDT 24
Finished Aug 06 05:27:51 PM PDT 24
Peak memory 214256 kb
Host smart-5f0e3bf5-8200-45fa-835f-c207340a0701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727374654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.727374654
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2658479897
Short name T185
Test name
Test status
Simulation time 102272997 ps
CPU time 4.76 seconds
Started Aug 06 05:27:48 PM PDT 24
Finished Aug 06 05:27:53 PM PDT 24
Peak memory 209532 kb
Host smart-75613047-eb23-4aff-84b5-aa4595208ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658479897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2658479897
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1989488294
Short name T294
Test name
Test status
Simulation time 737253909 ps
CPU time 10.96 seconds
Started Aug 06 05:27:50 PM PDT 24
Finished Aug 06 05:28:01 PM PDT 24
Peak memory 214356 kb
Host smart-2a8b7aaf-417a-4f28-85c3-b04bd8c87930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989488294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1989488294
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1586551714
Short name T502
Test name
Test status
Simulation time 286368696 ps
CPU time 3.73 seconds
Started Aug 06 05:27:52 PM PDT 24
Finished Aug 06 05:27:56 PM PDT 24
Peak memory 208796 kb
Host smart-3903e63a-83fe-46c8-af59-a18f8aecfb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586551714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1586551714
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3031084175
Short name T842
Test name
Test status
Simulation time 62493922 ps
CPU time 2.84 seconds
Started Aug 06 05:27:48 PM PDT 24
Finished Aug 06 05:27:51 PM PDT 24
Peak memory 206712 kb
Host smart-50dd4fb6-9581-4774-88cf-0a6146cd0687
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031084175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3031084175
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1935718885
Short name T489
Test name
Test status
Simulation time 86459270 ps
CPU time 2.03 seconds
Started Aug 06 05:27:51 PM PDT 24
Finished Aug 06 05:27:53 PM PDT 24
Peak memory 208712 kb
Host smart-bc6cec70-0a69-4153-9122-29c6ba51f497
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935718885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1935718885
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2707740467
Short name T672
Test name
Test status
Simulation time 97810708 ps
CPU time 2.22 seconds
Started Aug 06 05:27:50 PM PDT 24
Finished Aug 06 05:27:52 PM PDT 24
Peak memory 208700 kb
Host smart-231fc5bd-4a6a-4e3d-b104-561652f6df3f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707740467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2707740467
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1755196676
Short name T400
Test name
Test status
Simulation time 228579333 ps
CPU time 2.57 seconds
Started Aug 06 05:27:51 PM PDT 24
Finished Aug 06 05:27:54 PM PDT 24
Peak memory 215596 kb
Host smart-7d2a3ff4-df6c-4840-bcf5-bbe68f038dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755196676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1755196676
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3316879395
Short name T630
Test name
Test status
Simulation time 42242147 ps
CPU time 2.3 seconds
Started Aug 06 05:27:50 PM PDT 24
Finished Aug 06 05:27:53 PM PDT 24
Peak memory 206820 kb
Host smart-0171596b-5904-4ac3-9118-59a0a9fc037b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316879395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3316879395
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1423260217
Short name T666
Test name
Test status
Simulation time 5809681902 ps
CPU time 19.38 seconds
Started Aug 06 05:27:50 PM PDT 24
Finished Aug 06 05:28:10 PM PDT 24
Peak memory 208664 kb
Host smart-387b7eb6-7bf5-486b-84a3-1e45e739a040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423260217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1423260217
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.713227376
Short name T565
Test name
Test status
Simulation time 170449430 ps
CPU time 7.55 seconds
Started Aug 06 05:27:53 PM PDT 24
Finished Aug 06 05:28:01 PM PDT 24
Peak memory 222544 kb
Host smart-6a20a6bd-9eef-441f-96ee-9b0385720202
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713227376 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.713227376
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1518784632
Short name T351
Test name
Test status
Simulation time 4266140998 ps
CPU time 40.14 seconds
Started Aug 06 05:27:51 PM PDT 24
Finished Aug 06 05:28:31 PM PDT 24
Peak memory 208736 kb
Host smart-d3a5c3aa-e7d6-4201-85d2-f4698fd63814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518784632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1518784632
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3183934018
Short name T141
Test name
Test status
Simulation time 105740593 ps
CPU time 1.26 seconds
Started Aug 06 05:27:50 PM PDT 24
Finished Aug 06 05:27:51 PM PDT 24
Peak memory 209632 kb
Host smart-365caf73-a59b-47fd-ba3d-951f1165b904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183934018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3183934018
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.46595233
Short name T806
Test name
Test status
Simulation time 16467112 ps
CPU time 0.76 seconds
Started Aug 06 05:24:57 PM PDT 24
Finished Aug 06 05:24:58 PM PDT 24
Peak memory 205912 kb
Host smart-9c69ecef-002a-49bf-a64c-85aa671ce0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46595233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.46595233
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2649259979
Short name T378
Test name
Test status
Simulation time 871883129 ps
CPU time 3.62 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:05 PM PDT 24
Peak memory 214264 kb
Host smart-0de998f1-204b-440e-bd87-a5fc3c4ccd78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649259979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2649259979
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2133270106
Short name T777
Test name
Test status
Simulation time 735470775 ps
CPU time 15.41 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:25:14 PM PDT 24
Peak memory 222580 kb
Host smart-9cdff8da-cfba-4208-99e9-25992b54ec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133270106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2133270106
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.4224799215
Short name T569
Test name
Test status
Simulation time 142436750 ps
CPU time 2.53 seconds
Started Aug 06 05:24:58 PM PDT 24
Finished Aug 06 05:25:01 PM PDT 24
Peak memory 210052 kb
Host smart-7068360c-6751-4ffb-b35f-a52c4c4c207c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224799215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.4224799215
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1388926248
Short name T92
Test name
Test status
Simulation time 189306377 ps
CPU time 4.63 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:25:04 PM PDT 24
Peak memory 214324 kb
Host smart-515a7c52-3266-4e8b-a5d4-b796bad69027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388926248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1388926248
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3738051503
Short name T89
Test name
Test status
Simulation time 130822821 ps
CPU time 4.6 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:06 PM PDT 24
Peak memory 215148 kb
Host smart-87fa0b15-26f5-4553-ba58-987a1c94de37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738051503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3738051503
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.922932866
Short name T792
Test name
Test status
Simulation time 42185108 ps
CPU time 2.73 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:25:02 PM PDT 24
Peak memory 219976 kb
Host smart-2680fff6-9786-4680-ae0d-1f2715c298b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922932866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.922932866
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3738762838
Short name T471
Test name
Test status
Simulation time 1290451995 ps
CPU time 6.82 seconds
Started Aug 06 05:24:58 PM PDT 24
Finished Aug 06 05:25:05 PM PDT 24
Peak memory 209388 kb
Host smart-8c679ce8-a02e-46ee-8311-c52b30deeae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738762838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3738762838
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4189526695
Short name T258
Test name
Test status
Simulation time 2237148535 ps
CPU time 28.63 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:31 PM PDT 24
Peak memory 208164 kb
Host smart-e1907516-4933-4dbe-a259-d0aa40ad6d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189526695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4189526695
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.4121183952
Short name T542
Test name
Test status
Simulation time 85113300 ps
CPU time 4.12 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:25:03 PM PDT 24
Peak memory 208664 kb
Host smart-293f5008-ef5d-47aa-be62-1f147a5b1f46
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121183952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.4121183952
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1403811631
Short name T774
Test name
Test status
Simulation time 442059127 ps
CPU time 7.05 seconds
Started Aug 06 05:24:58 PM PDT 24
Finished Aug 06 05:25:05 PM PDT 24
Peak memory 208964 kb
Host smart-4f824efd-ff75-4bbd-a509-f4d2732a41ff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403811631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1403811631
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.34015629
Short name T305
Test name
Test status
Simulation time 191934692 ps
CPU time 2.83 seconds
Started Aug 06 05:25:01 PM PDT 24
Finished Aug 06 05:25:04 PM PDT 24
Peak memory 208636 kb
Host smart-32722ac4-275b-4bac-85a9-2c2cc576cc21
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34015629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.34015629
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2897586361
Short name T336
Test name
Test status
Simulation time 33007013 ps
CPU time 2.37 seconds
Started Aug 06 05:25:00 PM PDT 24
Finished Aug 06 05:25:02 PM PDT 24
Peak memory 218192 kb
Host smart-147b5a74-6958-4555-9b3a-ab4ce0773865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897586361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2897586361
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2567867363
Short name T446
Test name
Test status
Simulation time 113266310 ps
CPU time 3.6 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:25:03 PM PDT 24
Peak memory 208548 kb
Host smart-3f723f0a-db0e-4b7a-8eff-65d0a44511f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567867363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2567867363
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3750512321
Short name T595
Test name
Test status
Simulation time 254656956 ps
CPU time 9.77 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:25:09 PM PDT 24
Peak memory 220204 kb
Host smart-81652db4-7a67-49a7-893c-f3540a050469
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750512321 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3750512321
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.377004604
Short name T274
Test name
Test status
Simulation time 64462634 ps
CPU time 3.5 seconds
Started Aug 06 05:25:04 PM PDT 24
Finished Aug 06 05:25:08 PM PDT 24
Peak memory 207076 kb
Host smart-a61a0ca7-3c85-4e9d-95c9-9e492402ede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377004604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.377004604
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2122034803
Short name T801
Test name
Test status
Simulation time 39559802 ps
CPU time 0.8 seconds
Started Aug 06 05:24:58 PM PDT 24
Finished Aug 06 05:24:59 PM PDT 24
Peak memory 205872 kb
Host smart-48139724-d0b8-4e97-81b1-84c1dc458750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122034803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2122034803
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1483066219
Short name T873
Test name
Test status
Simulation time 2972038514 ps
CPU time 11.35 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:14 PM PDT 24
Peak memory 215696 kb
Host smart-00d7ae3f-d1cb-46d5-8409-6109cd9c9e0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483066219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1483066219
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2234425997
Short name T382
Test name
Test status
Simulation time 83992906 ps
CPU time 1.5 seconds
Started Aug 06 05:24:58 PM PDT 24
Finished Aug 06 05:25:00 PM PDT 24
Peak memory 208192 kb
Host smart-75c9f49a-b6df-4425-ae75-977540f490dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234425997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2234425997
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3844151727
Short name T885
Test name
Test status
Simulation time 142232820 ps
CPU time 4.13 seconds
Started Aug 06 05:24:57 PM PDT 24
Finished Aug 06 05:25:01 PM PDT 24
Peak memory 209456 kb
Host smart-4adde078-c037-4cb5-8e9a-ad1a54041058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844151727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3844151727
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1957688373
Short name T322
Test name
Test status
Simulation time 103235068 ps
CPU time 3.58 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:06 PM PDT 24
Peak memory 214260 kb
Host smart-48948ca6-15ee-42ad-a3ec-5a398a42e36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957688373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1957688373
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1282389190
Short name T436
Test name
Test status
Simulation time 50903274 ps
CPU time 1.84 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:25:01 PM PDT 24
Peak memory 206100 kb
Host smart-7bf2d941-fb25-4e26-bd21-de6f89580682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282389190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1282389190
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3102459751
Short name T490
Test name
Test status
Simulation time 478749490 ps
CPU time 5.87 seconds
Started Aug 06 05:25:01 PM PDT 24
Finished Aug 06 05:25:07 PM PDT 24
Peak memory 218332 kb
Host smart-66e52ef7-b5df-4405-8bdd-fde0371c9d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102459751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3102459751
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2148105667
Short name T883
Test name
Test status
Simulation time 454588138 ps
CPU time 5.04 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:07 PM PDT 24
Peak memory 208948 kb
Host smart-e122d252-5241-4634-86c5-de07eb3eb9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148105667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2148105667
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3156946798
Short name T121
Test name
Test status
Simulation time 77150562 ps
CPU time 3.31 seconds
Started Aug 06 05:25:04 PM PDT 24
Finished Aug 06 05:25:07 PM PDT 24
Peak memory 208760 kb
Host smart-05e0ce01-9b0f-4b63-8096-93377f05d476
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156946798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3156946798
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3767165341
Short name T473
Test name
Test status
Simulation time 38700043 ps
CPU time 2.5 seconds
Started Aug 06 05:24:57 PM PDT 24
Finished Aug 06 05:25:00 PM PDT 24
Peak memory 206880 kb
Host smart-77b49b62-b0da-476d-8aa5-71eceb7dd5dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767165341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3767165341
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2648501268
Short name T619
Test name
Test status
Simulation time 3048572905 ps
CPU time 28.89 seconds
Started Aug 06 05:25:03 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 208572 kb
Host smart-81ed3dc7-61ca-4b95-988e-50b28796677f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648501268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2648501268
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2495567536
Short name T287
Test name
Test status
Simulation time 101888712 ps
CPU time 2.72 seconds
Started Aug 06 05:24:57 PM PDT 24
Finished Aug 06 05:25:00 PM PDT 24
Peak memory 209924 kb
Host smart-b09b7cb5-47e6-46be-a231-de8f030bf520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495567536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2495567536
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.522307007
Short name T639
Test name
Test status
Simulation time 88969133 ps
CPU time 2.74 seconds
Started Aug 06 05:25:01 PM PDT 24
Finished Aug 06 05:25:03 PM PDT 24
Peak memory 206884 kb
Host smart-02110e92-85ea-47d9-b7ee-ccb5050f6e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522307007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.522307007
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3611160610
Short name T740
Test name
Test status
Simulation time 503376500 ps
CPU time 8.35 seconds
Started Aug 06 05:24:58 PM PDT 24
Finished Aug 06 05:25:06 PM PDT 24
Peak memory 216540 kb
Host smart-4c7e005f-7b44-4d65-9b96-b9b25dc90d90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611160610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3611160610
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3682402323
Short name T823
Test name
Test status
Simulation time 1074678464 ps
CPU time 11.71 seconds
Started Aug 06 05:25:03 PM PDT 24
Finished Aug 06 05:25:15 PM PDT 24
Peak memory 209024 kb
Host smart-aec458b8-efca-4cdd-a57c-a0a7ab32eb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682402323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3682402323
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.423964714
Short name T103
Test name
Test status
Simulation time 11108032 ps
CPU time 0.76 seconds
Started Aug 06 05:25:04 PM PDT 24
Finished Aug 06 05:25:05 PM PDT 24
Peak memory 205952 kb
Host smart-9f052278-3e2d-4ad5-9ecb-54e3af66477f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423964714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.423964714
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.505020346
Short name T719
Test name
Test status
Simulation time 159849512 ps
CPU time 3.24 seconds
Started Aug 06 05:25:04 PM PDT 24
Finished Aug 06 05:25:07 PM PDT 24
Peak memory 217232 kb
Host smart-4055c14b-b20a-4025-98b7-04d5832b0986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505020346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.505020346
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3957605299
Short name T320
Test name
Test status
Simulation time 19115037 ps
CPU time 1.59 seconds
Started Aug 06 05:25:03 PM PDT 24
Finished Aug 06 05:25:05 PM PDT 24
Peak memory 208096 kb
Host smart-ada59ac2-6e7b-4b54-a9b3-2b21fb519937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957605299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3957605299
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3671545203
Short name T581
Test name
Test status
Simulation time 159831075 ps
CPU time 2.84 seconds
Started Aug 06 05:24:57 PM PDT 24
Finished Aug 06 05:25:00 PM PDT 24
Peak memory 222568 kb
Host smart-90ebf029-2278-4799-aa20-776698a3ea7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671545203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3671545203
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3284771894
Short name T88
Test name
Test status
Simulation time 83927667 ps
CPU time 3.44 seconds
Started Aug 06 05:25:01 PM PDT 24
Finished Aug 06 05:25:04 PM PDT 24
Peak memory 214172 kb
Host smart-b8cb4114-1240-4897-8e7f-fc8e4163da35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284771894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3284771894
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2167774615
Short name T337
Test name
Test status
Simulation time 83327806 ps
CPU time 3.4 seconds
Started Aug 06 05:25:00 PM PDT 24
Finished Aug 06 05:25:03 PM PDT 24
Peak memory 220812 kb
Host smart-0db60380-c9a2-4339-9037-cb377916e265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167774615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2167774615
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1442651132
Short name T737
Test name
Test status
Simulation time 580889949 ps
CPU time 11.14 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:13 PM PDT 24
Peak memory 218172 kb
Host smart-84dd57b6-8af0-411d-8d57-a250c41a33bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442651132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1442651132
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2378330528
Short name T610
Test name
Test status
Simulation time 19685951854 ps
CPU time 25.38 seconds
Started Aug 06 05:25:03 PM PDT 24
Finished Aug 06 05:25:28 PM PDT 24
Peak memory 208032 kb
Host smart-7f0c1988-a4f7-4766-a440-71b435f04578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378330528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2378330528
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1544028638
Short name T547
Test name
Test status
Simulation time 55824146 ps
CPU time 2.89 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:25:01 PM PDT 24
Peak memory 207952 kb
Host smart-6b84bda7-72b6-419b-8ca8-9a5cafa38335
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544028638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1544028638
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3730646382
Short name T123
Test name
Test status
Simulation time 1786800546 ps
CPU time 24.95 seconds
Started Aug 06 05:25:00 PM PDT 24
Finished Aug 06 05:25:25 PM PDT 24
Peak memory 207840 kb
Host smart-492b4d29-d904-4e85-bac7-6477af1f895f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730646382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3730646382
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2622085059
Short name T466
Test name
Test status
Simulation time 101495338 ps
CPU time 3.18 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:05 PM PDT 24
Peak memory 206788 kb
Host smart-657b97c1-a283-49a4-a97a-2216c1ec179b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622085059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2622085059
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2876368871
Short name T231
Test name
Test status
Simulation time 651302594 ps
CPU time 3.31 seconds
Started Aug 06 05:25:01 PM PDT 24
Finished Aug 06 05:25:05 PM PDT 24
Peak memory 209276 kb
Host smart-7be9fdb1-ccc1-42cd-bca0-4ba8e1dcd236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876368871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2876368871
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2787510869
Short name T550
Test name
Test status
Simulation time 261696244 ps
CPU time 3.85 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:06 PM PDT 24
Peak memory 208648 kb
Host smart-650a3c16-f6a3-487e-939a-c94f051f7447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787510869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2787510869
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.817523321
Short name T50
Test name
Test status
Simulation time 1463570907 ps
CPU time 50.85 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:25:50 PM PDT 24
Peak memory 222320 kb
Host smart-5dd39d2a-2e7e-452c-a045-65812139fd3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817523321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.817523321
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.989171135
Short name T171
Test name
Test status
Simulation time 4664861809 ps
CPU time 15.79 seconds
Started Aug 06 05:25:01 PM PDT 24
Finished Aug 06 05:25:16 PM PDT 24
Peak memory 221400 kb
Host smart-f3a2e3e7-9833-46d4-ae82-bf4d0e51102a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989171135 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.989171135
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2520738887
Short name T533
Test name
Test status
Simulation time 3536797660 ps
CPU time 9.2 seconds
Started Aug 06 05:25:04 PM PDT 24
Finished Aug 06 05:25:13 PM PDT 24
Peak memory 218208 kb
Host smart-81d72cf0-7d0b-4c50-b709-df253a912f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520738887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2520738887
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3736028109
Short name T173
Test name
Test status
Simulation time 268747150 ps
CPU time 2.42 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:25:02 PM PDT 24
Peak memory 210128 kb
Host smart-f395b892-331b-49ce-86a8-bbea5ddaa908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736028109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3736028109
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.4059187368
Short name T438
Test name
Test status
Simulation time 73380684 ps
CPU time 0.74 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:25:15 PM PDT 24
Peak memory 205872 kb
Host smart-59d2eed7-dade-41a0-8701-2aaf46426f59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059187368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.4059187368
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.815081106
Short name T342
Test name
Test status
Simulation time 233085784 ps
CPU time 12.24 seconds
Started Aug 06 05:25:01 PM PDT 24
Finished Aug 06 05:25:13 PM PDT 24
Peak memory 215936 kb
Host smart-cf0b6c97-df92-4aab-aa47-edbc3194b1ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815081106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.815081106
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.632160154
Short name T31
Test name
Test status
Simulation time 342651110 ps
CPU time 1.99 seconds
Started Aug 06 05:25:04 PM PDT 24
Finished Aug 06 05:25:06 PM PDT 24
Peak memory 205976 kb
Host smart-5d63f15b-8915-4c10-ae53-65fa64928b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632160154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.632160154
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.404387566
Short name T582
Test name
Test status
Simulation time 360865578 ps
CPU time 3.8 seconds
Started Aug 06 05:25:04 PM PDT 24
Finished Aug 06 05:25:08 PM PDT 24
Peak memory 214408 kb
Host smart-005434de-ceff-4fa7-ba8b-ed36f18e94e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404387566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.404387566
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.955160738
Short name T99
Test name
Test status
Simulation time 11135857571 ps
CPU time 33.08 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:25:32 PM PDT 24
Peak memory 222540 kb
Host smart-eddd7616-64b5-427a-8edc-483a8a29bee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955160738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.955160738
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.111183122
Short name T303
Test name
Test status
Simulation time 46924622 ps
CPU time 3.15 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:05 PM PDT 24
Peak memory 214360 kb
Host smart-47bf63bf-85ec-4c5e-a990-dfd66bfc0cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111183122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.111183122
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_random.2673529168
Short name T345
Test name
Test status
Simulation time 128899011 ps
CPU time 5.48 seconds
Started Aug 06 05:25:00 PM PDT 24
Finished Aug 06 05:25:06 PM PDT 24
Peak memory 218424 kb
Host smart-571a6d9a-beb2-4205-8f4e-befd4267fd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673529168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2673529168
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3476824359
Short name T638
Test name
Test status
Simulation time 115963320 ps
CPU time 3 seconds
Started Aug 06 05:25:03 PM PDT 24
Finished Aug 06 05:25:06 PM PDT 24
Peak memory 206808 kb
Host smart-0b1badc0-c9c5-4747-b71c-54ef30eb1816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476824359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3476824359
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1160790257
Short name T723
Test name
Test status
Simulation time 1410212451 ps
CPU time 8.66 seconds
Started Aug 06 05:25:01 PM PDT 24
Finished Aug 06 05:25:10 PM PDT 24
Peak memory 208084 kb
Host smart-893c3ea5-57a9-4e69-bcf4-d78684944fe8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160790257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1160790257
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2679678894
Short name T271
Test name
Test status
Simulation time 5698601699 ps
CPU time 26.59 seconds
Started Aug 06 05:25:00 PM PDT 24
Finished Aug 06 05:25:27 PM PDT 24
Peak memory 208004 kb
Host smart-191a39e4-1f06-4a27-94e2-8b758223340a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679678894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2679678894
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2601699207
Short name T286
Test name
Test status
Simulation time 367472618 ps
CPU time 5.11 seconds
Started Aug 06 05:25:01 PM PDT 24
Finished Aug 06 05:25:07 PM PDT 24
Peak memory 208556 kb
Host smart-4085cbb1-92a0-46f7-86c2-e1cf947fac76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601699207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2601699207
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.959494799
Short name T441
Test name
Test status
Simulation time 229756184 ps
CPU time 3.35 seconds
Started Aug 06 05:24:58 PM PDT 24
Finished Aug 06 05:25:01 PM PDT 24
Peak memory 215328 kb
Host smart-e4933edb-ad04-4429-a248-0a3ac624e2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959494799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.959494799
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.710137950
Short name T744
Test name
Test status
Simulation time 39406746 ps
CPU time 2.2 seconds
Started Aug 06 05:25:03 PM PDT 24
Finished Aug 06 05:25:05 PM PDT 24
Peak memory 206744 kb
Host smart-1a43696e-8295-40ef-8641-59fb214db8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710137950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.710137950
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2203968722
Short name T172
Test name
Test status
Simulation time 279394869 ps
CPU time 6.51 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:09 PM PDT 24
Peak memory 222432 kb
Host smart-a465f755-97b8-4a75-bfd4-7baa7134b121
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203968722 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2203968722
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3546381984
Short name T715
Test name
Test status
Simulation time 1162092513 ps
CPU time 4.62 seconds
Started Aug 06 05:24:59 PM PDT 24
Finished Aug 06 05:25:04 PM PDT 24
Peak memory 218240 kb
Host smart-56c89465-854f-4786-a7aa-e008e094f821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546381984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3546381984
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.230544804
Short name T155
Test name
Test status
Simulation time 33696886 ps
CPU time 1.65 seconds
Started Aug 06 05:25:02 PM PDT 24
Finished Aug 06 05:25:04 PM PDT 24
Peak memory 209644 kb
Host smart-da5d45d4-8429-4345-9a9f-22715b22884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230544804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.230544804
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.4106799051
Short name T396
Test name
Test status
Simulation time 10854926 ps
CPU time 0.73 seconds
Started Aug 06 05:25:12 PM PDT 24
Finished Aug 06 05:25:13 PM PDT 24
Peak memory 205932 kb
Host smart-3fd70f07-34d4-49be-9f4f-351c19775ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106799051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.4106799051
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3300190825
Short name T127
Test name
Test status
Simulation time 688283530 ps
CPU time 3.57 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:17 PM PDT 24
Peak memory 214288 kb
Host smart-de02109a-0f50-4559-bd37-70f86f45b5bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300190825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3300190825
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1243565879
Short name T248
Test name
Test status
Simulation time 270396337 ps
CPU time 2.2 seconds
Started Aug 06 05:25:12 PM PDT 24
Finished Aug 06 05:25:15 PM PDT 24
Peak memory 214320 kb
Host smart-f59e0671-082e-4752-a222-3156a6f50549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243565879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1243565879
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1026526028
Short name T800
Test name
Test status
Simulation time 313806620 ps
CPU time 9.35 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:22 PM PDT 24
Peak memory 214300 kb
Host smart-b83b47cf-c430-47b4-ad3d-c4e3d46f88d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026526028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1026526028
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1960782723
Short name T451
Test name
Test status
Simulation time 129671576 ps
CPU time 5.16 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:18 PM PDT 24
Peak memory 214272 kb
Host smart-3ece47be-7089-4b03-8189-d9547bd2dadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960782723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1960782723
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.437865031
Short name T782
Test name
Test status
Simulation time 93536851 ps
CPU time 3.38 seconds
Started Aug 06 05:25:16 PM PDT 24
Finished Aug 06 05:25:19 PM PDT 24
Peak memory 209696 kb
Host smart-eb8650f8-c3fa-42f9-9c81-8964439738d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437865031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.437865031
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2240962138
Short name T721
Test name
Test status
Simulation time 78184395 ps
CPU time 2.55 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:16 PM PDT 24
Peak memory 207316 kb
Host smart-39b6c235-0269-4ca7-b046-230e1c299722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240962138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2240962138
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3468494392
Short name T907
Test name
Test status
Simulation time 2556309648 ps
CPU time 26.4 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:39 PM PDT 24
Peak memory 208252 kb
Host smart-4784bba2-60dc-465f-bea0-44c1a6fee115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468494392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3468494392
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.154309933
Short name T851
Test name
Test status
Simulation time 6869845957 ps
CPU time 47.55 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:26:00 PM PDT 24
Peak memory 208904 kb
Host smart-da7d4409-cdd4-4824-8dbc-347d38943600
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154309933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.154309933
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1245346716
Short name T891
Test name
Test status
Simulation time 211708819 ps
CPU time 2.85 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:16 PM PDT 24
Peak memory 206840 kb
Host smart-432890a0-11e8-4015-8dec-6cf658d66c2d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245346716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1245346716
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2986321109
Short name T803
Test name
Test status
Simulation time 1287330849 ps
CPU time 37.5 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:51 PM PDT 24
Peak memory 208448 kb
Host smart-12f54d29-739c-45d3-a6cc-9c8a6cf2ca7e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986321109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2986321109
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2656796723
Short name T566
Test name
Test status
Simulation time 42539117 ps
CPU time 2.06 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:16 PM PDT 24
Peak memory 209428 kb
Host smart-fba6bf97-72fa-462e-8609-a35d62fce562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656796723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2656796723
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1256820689
Short name T443
Test name
Test status
Simulation time 301924552 ps
CPU time 3.62 seconds
Started Aug 06 05:25:17 PM PDT 24
Finished Aug 06 05:25:21 PM PDT 24
Peak memory 208656 kb
Host smart-024e6943-9a8c-4d12-bdf3-c028f655be3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256820689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1256820689
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.261241255
Short name T586
Test name
Test status
Simulation time 178730434 ps
CPU time 6.57 seconds
Started Aug 06 05:25:12 PM PDT 24
Finished Aug 06 05:25:19 PM PDT 24
Peak memory 216260 kb
Host smart-f98b20c1-69ef-4175-8079-20a7870a1b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261241255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.261241255
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3159133800
Short name T169
Test name
Test status
Simulation time 738099989 ps
CPU time 23.13 seconds
Started Aug 06 05:25:14 PM PDT 24
Finished Aug 06 05:25:38 PM PDT 24
Peak memory 220912 kb
Host smart-6102d83c-ca88-43e3-996e-6502fa213191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159133800 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3159133800
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1867895259
Short name T176
Test name
Test status
Simulation time 38799800 ps
CPU time 1.82 seconds
Started Aug 06 05:25:13 PM PDT 24
Finished Aug 06 05:25:15 PM PDT 24
Peak memory 209936 kb
Host smart-2d966969-b944-4035-8749-92a435e28216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867895259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1867895259
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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