Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11529

1

T1

4

T2

17

T3

14

auto[Attestation]

7705

1

T1

4

T2

3

T3

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2805	1			T1	1		T3	1		T4	5
auto[Aes]	3369	1			T3	6		T4	9		T15	2
auto[Kmac]	3439	1			T1	3		T2	20		T3	5
auto[Otbn]	3506	1			T1	1		T3	3		T4	5

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7820	1			T1	8		T2	8		T3	4
auto[OpGenId]	6115	1			T1	3		T3	5		T4	10
auto[OpGenSwOut]	5920	1			T1	5		T3	5		T4	14
auto[OpGenHwOut]	7199	1			T2	20		T3	10		T4	10
auto[OpDisable]	146	1			T3	1		T18	1		T44	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10870

1

T1

8

T2

8

T3

13

auto[OpDoneFail]

16330

1

T1

8

T2

20

T3

12

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6824	1			T1	1		T2	13		T3	8
auto[StInit]	3656	1			T1	2		T2	2		T3	3
auto[StCreatorRootKey]	3306	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2813	1			T1	2		T2	2		T3	5
auto[StOwnerKey]	2503	1			T1	2		T2	2		T3	4
auto[StDisabled]	8098	1			T1	7		T2	7		T3	3

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	353	1			T24	2		T186	2		T26	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	98	1			T18	1		T26	1		T44	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	92	1			T4	1		T37	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	66	1			T186	1		T27	1		T78	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	79	1			T4	1		T84	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	246	1			T187	1		T44	5		T77	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	360	1			T4	3		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	101	1			T4	1		T187	2		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	71	1			T4	1		T66	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	75	1			T187	1		T44	1		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	55	1			T186	1		T37	1		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	226	1			T4	1		T66	1		T182	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	334	1			T3	1		T17	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	110	1			T84	1		T27	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	89	1			T1	1		T4	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	62	1			T15	1		T51	1		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	51	1			T188	1		T99	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	216	1			T1	1		T3	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	299	1			T3	1		T4	2		T186	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	104	1			T26	1		T5	1		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T27	1		T45	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T44	3		T57	2		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	69	1			T187	1		T42	1		T51	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	228	1			T1	1		T84	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	93	1			T44	1		T98	4		T99	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	84	1			T19	1		T26	1		T184	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	79	1			T183	1		T44	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T1	1		T187	2		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	57	1			T4	1		T27	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	236	1			T18	1		T19	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	77	1			T44	2		T98	1		T99	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	85	1			T4	1		T44	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	83	1			T44	2		T57	1		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	71	1			T15	1		T44	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	47	1			T3	1		T190	1		T51	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	188	1			T16	1		T186	1		T44	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	80	1			T99	1		T7	2		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	87	1			T18	1		T188	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	89	1			T84	1		T5	1		T191	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T3	1		T37	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	56	1			T44	1		T192	1		T193	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	190	1			T1	1		T15	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	91	1			T36	1		T44	2		T98	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	88	1			T4	1		T26	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T188	1		T44	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	71	1			T5	1		T194	1		T193	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	73	1			T42	1		T193	1		T190	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	218	1			T15	1		T19	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	288	1			T4	1		T18	2		T24	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	95	1			T18	1		T26	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	62	1			T26	1		T44	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T15	1		T187	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	54	1			T44	1		T42	1		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	185	1			T27	3		T183	1		T78	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	475	1			T3	1		T18	2		T24	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	122	1			T85	1		T26	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	116	1			T27	1		T44	2		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	103	1			T16	1		T44	2		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	83	1			T3	2		T85	1		T193	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	262	1			T17	1		T187	1		T44	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	539	1			T2	12		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	104	1			T2	1		T42	1		T121	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	124	1			T2	1		T196	1		T187	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T2	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	87	1			T2	1		T14	1		T44	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	289	1			T2	1		T14	2		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	554	1			T84	1		T24	1		T97	16
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	111	1			T3	1		T26	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	115	1			T18	1		T183	1		T44	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	107	1			T3	1		T15	1		T97	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	77	1			T17	1		T19	1		T97	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	278	1			T15	2		T19	1		T97	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	60	1			T36	1		T98	1		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	97	1			T15	1		T44	1		T42	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	63	1			T3	1		T4	1		T26	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	56	1			T15	1		T57	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	53	1			T15	1		T187	1		T44	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	177	1			T15	1		T37	1		T183	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	63	1			T5	1		T98	3		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	113	1			T18	1		T26	2		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	105	1			T4	2		T19	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	102	1			T3	1		T85	1		T187	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	105	1			T44	3		T42	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	281	1			T3	1		T15	1		T85	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	65	1			T36	2		T44	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	128	1			T4	1		T14	1		T26	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	118	1			T4	1		T14	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	98	1			T196	1		T44	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	81	1			T37	1		T196	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	271	1			T2	3		T3	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	58	1			T36	2		T98	1		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	117	1			T4	1		T97	1		T44	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	102	1			T97	1		T44	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	101	1			T66	2		T183	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	93	1			T4	1		T37	1		T181	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	302	1			T84	1		T27	1		T183	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	221	1			T4	2		T84	1		T186	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	713	1			T18	1		T24	2		T186	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	188	1			T4	1		T186	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	700	1			T4	5		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	189	1			T1	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	673	1			T1	1		T3	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	214	1			T187	1		T27	1		T44	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	654	1			T1	1		T3	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	184	1			T1	1		T4	1		T187	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	429	1			T18	1		T19	2		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	192	1			T3	1		T15	1		T44	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	359	1			T4	1		T16	1		T186	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	209	1			T3	1		T84	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	372	1			T1	1		T15	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	210	1			T188	1		T57	1		T77	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	413	1			T4	1		T15	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	173	1			T15	1		T26	1		T187	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	579	1			T4	1		T18	3		T24	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	284	1			T3	2		T16	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	877	1			T3	1		T17	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	291	1			T2	3		T14	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	944	1			T2	14		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	281	1			T3	1		T15	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	961	1			T3	1		T15	2		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	156	1			T3	1		T4	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	350	1			T15	2		T36	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	300	1			T3	1		T4	2		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	469	1			T3	1		T15	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	278	1			T4	1		T14	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	483	1			T2	3		T3	1		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	282	1			T4	1		T97	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	491	1			T4	1		T84	1		T36	2