Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33273

1

T1

22

T2

31

T3

26

auto[1]

310

1

T113

8

T121

14

T136

14

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33289	1			T1	22		T2	31		T3	26
auto[134217728:268435455]	12	1			T113	1		T121	1		T136	2
auto[268435456:402653183]	6	1			T277	1		T242	1		T391	1
auto[402653184:536870911]	9	1			T123	2		T127	1		T291	1
auto[536870912:671088639]	9	1			T236	1		T242	1		T225	1
auto[671088640:805306367]	12	1			T136	1		T236	2		T229	1
auto[805306368:939524095]	7	1			T122	1		T225	1		T391	1
auto[939524096:1073741823]	7	1			T113	1		T238	1		T225	1
auto[1073741824:1207959551]	12	1			T121	1		T238	1		T277	1
auto[1207959552:1342177279]	10	1			T121	1		T122	1		T357	1
auto[1342177280:1476395007]	9	1			T238	1		T291	1		T381	1
auto[1476395008:1610612735]	9	1			T121	1		T238	1		T229	1
auto[1610612736:1744830463]	14	1			T121	1		T136	2		T277	1
auto[1744830464:1879048191]	10	1			T121	2		T136	2		T122	1
auto[1879048192:2013265919]	8	1			T121	1		T238	1		T277	1
auto[2013265920:2147483647]	9	1			T277	1		T236	1		T127	1
auto[2147483648:2281701375]	8	1			T122	1		T237	1		T225	1
auto[2281701376:2415919103]	7	1			T113	1		T236	1		T381	1
auto[2415919104:2550136831]	16	1			T136	1		T238	2		T236	1
auto[2550136832:2684354559]	12	1			T113	1		T277	1		T123	1
auto[2684354560:2818572287]	7	1			T238	1		T277	1		T222	1
auto[2818572288:2952790015]	7	1			T113	1		T121	1		T278	1
auto[2952790016:3087007743]	15	1			T136	2		T238	2		T229	1
auto[3087007744:3221225471]	8	1			T121	2		T136	1		T122	1
auto[3221225472:3355443199]	5	1			T291	1		T222	1		T316	1
auto[3355443200:3489660927]	8	1			T113	1		T229	1		T127	1
auto[3489660928:3623878655]	11	1			T121	1		T236	1		T229	1
auto[3623878656:3758096383]	10	1			T113	1		T136	1		T277	1
auto[3758096384:3892314111]	11	1			T237	1		T278	1		T391	1
auto[3892314112:4026531839]	8	1			T113	1		T357	1		T236	1
auto[4026531840:4160749567]	12	1			T121	1		T136	1		T277	1
auto[4160749568:4294967295]	6	1			T136	1		T314	1		T380	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33273	1			T1	22		T2	31		T3	26
auto[0:134217727]	auto[1]	16	1			T121	1		T122	2		T382	1
auto[134217728:268435455]	auto[1]	12	1			T113	1		T121	1		T136	2
auto[268435456:402653183]	auto[1]	6	1			T277	1		T242	1		T391	1
auto[402653184:536870911]	auto[1]	9	1			T123	2		T127	1		T291	1
auto[536870912:671088639]	auto[1]	9	1			T236	1		T242	1		T225	1
auto[671088640:805306367]	auto[1]	12	1			T136	1		T236	2		T229	1
auto[805306368:939524095]	auto[1]	7	1			T122	1		T225	1		T391	1
auto[939524096:1073741823]	auto[1]	7	1			T113	1		T238	1		T225	1
auto[1073741824:1207959551]	auto[1]	12	1			T121	1		T238	1		T277	1
auto[1207959552:1342177279]	auto[1]	10	1			T121	1		T122	1		T357	1
auto[1342177280:1476395007]	auto[1]	9	1			T238	1		T291	1		T381	1
auto[1476395008:1610612735]	auto[1]	9	1			T121	1		T238	1		T229	1
auto[1610612736:1744830463]	auto[1]	14	1			T121	1		T136	2		T277	1
auto[1744830464:1879048191]	auto[1]	10	1			T121	2		T136	2		T122	1
auto[1879048192:2013265919]	auto[1]	8	1			T121	1		T238	1		T277	1
auto[2013265920:2147483647]	auto[1]	9	1			T277	1		T236	1		T127	1
auto[2147483648:2281701375]	auto[1]	8	1			T122	1		T237	1		T225	1
auto[2281701376:2415919103]	auto[1]	7	1			T113	1		T236	1		T381	1
auto[2415919104:2550136831]	auto[1]	16	1			T136	1		T238	2		T236	1
auto[2550136832:2684354559]	auto[1]	12	1			T113	1		T277	1		T123	1
auto[2684354560:2818572287]	auto[1]	7	1			T238	1		T277	1		T222	1
auto[2818572288:2952790015]	auto[1]	7	1			T113	1		T121	1		T278	1
auto[2952790016:3087007743]	auto[1]	15	1			T136	2		T238	2		T229	1
auto[3087007744:3221225471]	auto[1]	8	1			T121	2		T136	1		T122	1
auto[3221225472:3355443199]	auto[1]	5	1			T291	1		T222	1		T316	1
auto[3355443200:3489660927]	auto[1]	8	1			T113	1		T229	1		T127	1
auto[3489660928:3623878655]	auto[1]	11	1			T121	1		T236	1		T229	1
auto[3623878656:3758096383]	auto[1]	10	1			T113	1		T136	1		T277	1
auto[3758096384:3892314111]	auto[1]	11	1			T237	1		T278	1		T391	1
auto[3892314112:4026531839]	auto[1]	8	1			T113	1		T357	1		T236	1
auto[4026531840:4160749567]	auto[1]	12	1			T121	1		T136	1		T277	1
auto[4160749568:4294967295]	auto[1]	6	1			T136	1		T314	1		T380	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1603

1

T3

6

T15

1

T16

3

auto[1]

1775

1

T4

4

T15

1

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T16	1		T44	1		T42	1
auto[134217728:268435455]	96	1			T4	1		T57	1		T42	1
auto[268435456:402653183]	102	1			T36	1		T57	1		T47	1
auto[402653184:536870911]	97	1			T24	1		T36	1		T183	2
auto[536870912:671088639]	96	1			T36	1		T44	4		T42	1
auto[671088640:805306367]	116	1			T66	1		T46	1		T192	1
auto[805306368:939524095]	114	1			T15	1		T187	1		T44	1
auto[939524096:1073741823]	102	1			T36	1		T44	1		T57	1
auto[1073741824:1207959551]	90	1			T44	1		T57	1		T327	1
auto[1207959552:1342177279]	127	1			T3	1		T24	1		T44	1
auto[1342177280:1476395007]	92	1			T3	1		T4	1		T44	1
auto[1476395008:1610612735]	103	1			T37	1		T26	1		T44	2
auto[1610612736:1744830463]	119	1			T3	1		T23	1		T36	1
auto[1744830464:1879048191]	90	1			T24	1		T37	1		T26	2
auto[1879048192:2013265919]	112	1			T4	1		T187	1		T44	2
auto[2013265920:2147483647]	92	1			T3	1		T18	1		T187	1
auto[2147483648:2281701375]	111	1			T66	1		T187	1		T27	1
auto[2281701376:2415919103]	103	1			T16	1		T24	1		T183	1
auto[2415919104:2550136831]	132	1			T18	1		T24	1		T36	1
auto[2550136832:2684354559]	98	1			T16	1		T44	3		T57	1
auto[2684354560:2818572287]	107	1			T15	1		T26	2		T66	1
auto[2818572288:2952790015]	107	1			T18	1		T187	1		T56	1
auto[2952790016:3087007743]	119	1			T23	1		T66	1		T187	1
auto[3087007744:3221225471]	115	1			T187	1		T44	2		T57	1
auto[3221225472:3355443199]	109	1			T16	1		T24	1		T37	1
auto[3355443200:3489660927]	111	1			T3	1		T16	1		T66	1
auto[3489660928:3623878655]	105	1			T23	1		T36	1		T27	1
auto[3623878656:3758096383]	114	1			T18	1		T36	1		T183	1
auto[3758096384:3892314111]	104	1			T36	1		T26	1		T44	1
auto[3892314112:4026531839]	102	1			T24	1		T27	1		T194	1
auto[4026531840:4160749567]	95	1			T4	1		T44	2		T56	1
auto[4160749568:4294967295]	97	1			T3	1		T26	1		T78	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	41	1			T16	1		T51	1		T99	1
auto[0:134217727]	auto[1]	60	1			T44	1		T42	1		T98	1
auto[134217728:268435455]	auto[0]	48	1			T57	1		T327	1		T7	1
auto[134217728:268435455]	auto[1]	48	1			T4	1		T42	1		T327	1
auto[268435456:402653183]	auto[0]	51	1			T57	1		T47	1		T99	1
auto[268435456:402653183]	auto[1]	51	1			T36	1		T60	1		T7	1
auto[402653184:536870911]	auto[0]	47	1			T36	1		T183	1		T44	1
auto[402653184:536870911]	auto[1]	50	1			T24	1		T183	1		T44	1
auto[536870912:671088639]	auto[0]	47	1			T36	1		T44	2		T42	1
auto[536870912:671088639]	auto[1]	49	1			T44	2		T224	1		T70	1
auto[671088640:805306367]	auto[0]	59	1			T66	1		T6	1		T303	1
auto[671088640:805306367]	auto[1]	57	1			T46	1		T192	1		T244	1
auto[805306368:939524095]	auto[0]	52	1			T15	1		T5	1		T98	1
auto[805306368:939524095]	auto[1]	62	1			T187	1		T44	1		T98	1
auto[939524096:1073741823]	auto[0]	46	1			T44	1		T51	1		T86	1
auto[939524096:1073741823]	auto[1]	56	1			T36	1		T57	1		T42	1
auto[1073741824:1207959551]	auto[0]	39	1			T44	1		T68	1		T264	1
auto[1073741824:1207959551]	auto[1]	51	1			T57	1		T327	1		T46	1
auto[1207959552:1342177279]	auto[0]	62	1			T3	1		T24	1		T51	2
auto[1207959552:1342177279]	auto[1]	65	1			T44	1		T56	1		T78	1
auto[1342177280:1476395007]	auto[0]	38	1			T3	1		T44	1		T50	1
auto[1342177280:1476395007]	auto[1]	54	1			T4	1		T57	1		T77	1
auto[1476395008:1610612735]	auto[0]	53	1			T44	1		T42	1		T327	1
auto[1476395008:1610612735]	auto[1]	50	1			T37	1		T26	1		T44	1
auto[1610612736:1744830463]	auto[0]	51	1			T3	1		T23	1		T66	1
auto[1610612736:1744830463]	auto[1]	68	1			T36	1		T26	1		T44	2
auto[1744830464:1879048191]	auto[0]	43	1			T24	1		T37	1		T26	2
auto[1744830464:1879048191]	auto[1]	47	1			T44	1		T77	1		T244	1
auto[1879048192:2013265919]	auto[0]	53	1			T48	1		T60	1		T233	1
auto[1879048192:2013265919]	auto[1]	59	1			T4	1		T187	1		T44	2
auto[2013265920:2147483647]	auto[0]	49	1			T3	1		T187	1		T44	2
auto[2013265920:2147483647]	auto[1]	43	1			T18	1		T99	1		T252	1
auto[2147483648:2281701375]	auto[0]	63	1			T66	1		T187	1		T27	1
auto[2147483648:2281701375]	auto[1]	48	1			T51	1		T303	2		T99	1
auto[2281701376:2415919103]	auto[0]	59	1			T16	1		T24	1		T183	1
auto[2281701376:2415919103]	auto[1]	44	1			T46	1		T68	1		T136	1
auto[2415919104:2550136831]	auto[0]	62	1			T18	1		T24	1		T36	1
auto[2415919104:2550136831]	auto[1]	70	1			T5	1		T42	1		T244	1
auto[2550136832:2684354559]	auto[0]	46	1			T44	2		T121	1		T7	1
auto[2550136832:2684354559]	auto[1]	52	1			T16	1		T44	1		T57	1
auto[2684354560:2818572287]	auto[0]	51	1			T26	2		T195	1		T51	1
auto[2684354560:2818572287]	auto[1]	56	1			T15	1		T66	1		T183	1
auto[2818572288:2952790015]	auto[0]	54	1			T18	1		T56	1		T42	1
auto[2818572288:2952790015]	auto[1]	53	1			T187	1		T42	1		T64	1
auto[2952790016:3087007743]	auto[0]	52	1			T44	1		T135	1		T194	1
auto[2952790016:3087007743]	auto[1]	67	1			T23	1		T66	1		T187	1
auto[3087007744:3221225471]	auto[0]	53	1			T187	1		T44	1		T190	1
auto[3087007744:3221225471]	auto[1]	62	1			T44	1		T57	1		T223	1
auto[3221225472:3355443199]	auto[0]	42	1			T16	1		T44	4		T113	1
auto[3221225472:3355443199]	auto[1]	67	1			T24	1		T37	1		T183	1
auto[3355443200:3489660927]	auto[0]	52	1			T3	1		T51	1		T30	1
auto[3355443200:3489660927]	auto[1]	59	1			T16	1		T66	1		T135	1
auto[3489660928:3623878655]	auto[0]	48	1			T23	1		T44	1		T42	1
auto[3489660928:3623878655]	auto[1]	57	1			T36	1		T27	1		T44	4
auto[3623878656:3758096383]	auto[0]	54	1			T18	1		T183	1		T42	1
auto[3623878656:3758096383]	auto[1]	60	1			T36	1		T57	1		T135	1
auto[3758096384:3892314111]	auto[0]	44	1			T36	1		T26	1		T42	1
auto[3758096384:3892314111]	auto[1]	60	1			T44	1		T77	1		T232	1
auto[3892314112:4026531839]	auto[0]	44	1			T98	2		T7	1		T237	2
auto[3892314112:4026531839]	auto[1]	58	1			T24	1		T27	1		T194	1
auto[4026531840:4160749567]	auto[0]	47	1			T44	1		T56	1		T77	1
auto[4026531840:4160749567]	auto[1]	48	1			T4	1		T44	1		T57	1
auto[4160749568:4294967295]	auto[0]	53	1			T3	1		T26	1		T99	1
auto[4160749568:4294967295]	auto[1]	44	1			T78	1		T224	1		T98	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1567

1

T3

6

T15

1

T16

1

auto[1]

1812

1

T4

4

T15

1

T16

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T4	1		T44	1		T77	1
auto[134217728:268435455]	128	1			T16	1		T18	1		T24	1
auto[268435456:402653183]	99	1			T57	1		T78	2		T42	1
auto[402653184:536870911]	102	1			T24	1		T66	1		T44	1
auto[536870912:671088639]	105	1			T3	2		T44	1		T6	1
auto[671088640:805306367]	111	1			T4	1		T36	1		T26	1
auto[805306368:939524095]	125	1			T16	1		T57	1		T42	1
auto[939524096:1073741823]	102	1			T4	1		T183	1		T44	2
auto[1073741824:1207959551]	100	1			T16	1		T23	1		T36	1
auto[1207959552:1342177279]	93	1			T36	2		T57	1		T327	1
auto[1342177280:1476395007]	117	1			T24	1		T44	2		T42	2
auto[1476395008:1610612735]	111	1			T3	1		T66	1		T187	1
auto[1610612736:1744830463]	112	1			T18	2		T66	1		T44	1
auto[1744830464:1879048191]	116	1			T23	1		T44	1		T57	1
auto[1879048192:2013265919]	90	1			T36	1		T26	1		T183	1
auto[2013265920:2147483647]	79	1			T23	1		T36	1		T44	1
auto[2147483648:2281701375]	101	1			T44	1		T57	1		T135	2
auto[2281701376:2415919103]	111	1			T16	2		T24	1		T26	1
auto[2415919104:2550136831]	110	1			T37	1		T27	1		T44	2
auto[2550136832:2684354559]	113	1			T24	1		T36	2		T27	1
auto[2684354560:2818572287]	96	1			T37	1		T27	1		T44	1
auto[2818572288:2952790015]	90	1			T15	1		T44	1		T50	1
auto[2952790016:3087007743]	93	1			T187	1		T44	1		T327	1
auto[3087007744:3221225471]	101	1			T4	1		T24	1		T187	2
auto[3221225472:3355443199]	125	1			T3	1		T15	1		T44	2
auto[3355443200:3489660927]	106	1			T3	1		T26	2		T187	1
auto[3489660928:3623878655]	100	1			T44	5		T57	2		T135	1
auto[3623878656:3758096383]	108	1			T44	3		T42	3		T327	1
auto[3758096384:3892314111]	109	1			T18	1		T36	1		T187	1
auto[3892314112:4026531839]	107	1			T66	2		T42	1		T46	1
auto[4026531840:4160749567]	97	1			T3	1		T24	1		T26	1
auto[4160749568:4294967295]	111	1			T187	1		T44	2		T113	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T44	1		T77	1		T135	1
auto[0:134217727]	auto[1]	53	1			T4	1		T5	1		T98	1
auto[134217728:268435455]	auto[0]	55	1			T18	1		T24	1		T44	1
auto[134217728:268435455]	auto[1]	73	1			T16	1		T183	1		T57	1
auto[268435456:402653183]	auto[0]	41	1			T42	1		T238	1		T117	1
auto[268435456:402653183]	auto[1]	58	1			T57	1		T78	2		T121	1
auto[402653184:536870911]	auto[0]	49	1			T66	1		T44	1		T42	1
auto[402653184:536870911]	auto[1]	53	1			T24	1		T135	1		T190	1
auto[536870912:671088639]	auto[0]	53	1			T3	2		T121	1		T271	1
auto[536870912:671088639]	auto[1]	52	1			T44	1		T6	1		T223	1
auto[671088640:805306367]	auto[0]	40	1			T26	1		T194	1		T98	1
auto[671088640:805306367]	auto[1]	71	1			T4	1		T36	1		T44	1
auto[805306368:939524095]	auto[0]	65	1			T57	1		T7	1		T95	1
auto[805306368:939524095]	auto[1]	60	1			T16	1		T42	1		T113	1
auto[939524096:1073741823]	auto[0]	44	1			T183	1		T44	1		T303	1
auto[939524096:1073741823]	auto[1]	58	1			T4	1		T44	1		T57	1
auto[1073741824:1207959551]	auto[0]	46	1			T23	1		T26	1		T44	2
auto[1073741824:1207959551]	auto[1]	54	1			T16	1		T36	1		T37	1
auto[1207959552:1342177279]	auto[0]	41	1			T46	1		T192	1		T113	1
auto[1207959552:1342177279]	auto[1]	52	1			T36	2		T57	1		T327	1
auto[1342177280:1476395007]	auto[0]	59	1			T24	1		T44	2		T42	1
auto[1342177280:1476395007]	auto[1]	58	1			T42	1		T193	1		T51	1
auto[1476395008:1610612735]	auto[0]	59	1			T3	1		T187	1		T44	1
auto[1476395008:1610612735]	auto[1]	52	1			T66	1		T99	1		T60	1
auto[1610612736:1744830463]	auto[0]	64	1			T18	2		T44	1		T327	1
auto[1610612736:1744830463]	auto[1]	48	1			T66	1		T223	1		T224	1
auto[1744830464:1879048191]	auto[0]	68	1			T23	1		T44	1		T57	1
auto[1744830464:1879048191]	auto[1]	48	1			T42	1		T113	1		T30	1
auto[1879048192:2013265919]	auto[0]	36	1			T36	1		T26	1		T56	1
auto[1879048192:2013265919]	auto[1]	54	1			T183	1		T327	1		T70	1
auto[2013265920:2147483647]	auto[0]	27	1			T36	1		T56	1		T303	1
auto[2013265920:2147483647]	auto[1]	52	1			T23	1		T44	1		T51	1
auto[2147483648:2281701375]	auto[0]	44	1			T135	1		T51	2		T98	2
auto[2147483648:2281701375]	auto[1]	57	1			T44	1		T57	1		T135	1
auto[2281701376:2415919103]	auto[0]	53	1			T16	1		T26	1		T66	1
auto[2281701376:2415919103]	auto[1]	58	1			T16	1		T24	1		T77	1
auto[2415919104:2550136831]	auto[0]	51	1			T37	1		T44	1		T42	1
auto[2415919104:2550136831]	auto[1]	59	1			T27	1		T44	1		T42	1
auto[2550136832:2684354559]	auto[0]	59	1			T24	1		T36	1		T27	1
auto[2550136832:2684354559]	auto[1]	54	1			T36	1		T44	1		T193	1
auto[2684354560:2818572287]	auto[0]	37	1			T37	1		T44	1		T51	1
auto[2684354560:2818572287]	auto[1]	59	1			T27	1		T121	1		T60	1
auto[2818572288:2952790015]	auto[0]	42	1			T50	1		T47	1		T99	1
auto[2818572288:2952790015]	auto[1]	48	1			T15	1		T44	1		T223	1
auto[2952790016:3087007743]	auto[0]	46	1			T187	1		T44	1		T135	2
auto[2952790016:3087007743]	auto[1]	47	1			T327	1		T46	1		T190	1
auto[3087007744:3221225471]	auto[0]	48	1			T24	1		T183	1		T44	1
auto[3087007744:3221225471]	auto[1]	53	1			T4	1		T187	2		T42	1
auto[3221225472:3355443199]	auto[0]	49	1			T3	1		T15	1		T44	1
auto[3221225472:3355443199]	auto[1]	76	1			T44	1		T57	1		T46	1
auto[3355443200:3489660927]	auto[0]	46	1			T3	1		T26	2		T44	1
auto[3355443200:3489660927]	auto[1]	60	1			T187	1		T77	1		T232	1
auto[3489660928:3623878655]	auto[0]	42	1			T44	1		T135	1		T223	1
auto[3489660928:3623878655]	auto[1]	58	1			T44	4		T57	2		T192	1
auto[3623878656:3758096383]	auto[0]	46	1			T42	1		T30	1		T47	1
auto[3623878656:3758096383]	auto[1]	62	1			T44	3		T42	2		T327	1
auto[3758096384:3892314111]	auto[0]	52	1			T18	1		T187	1		T44	1
auto[3758096384:3892314111]	auto[1]	57	1			T36	1		T183	1		T44	1
auto[3892314112:4026531839]	auto[0]	57	1			T66	2		T42	1		T113	1
auto[3892314112:4026531839]	auto[1]	50	1			T46	1		T224	1		T98	2
auto[4026531840:4160749567]	auto[0]	42	1			T3	1		T26	1		T44	2
auto[4026531840:4160749567]	auto[1]	55	1			T24	1		T86	1		T7	2
auto[4160749568:4294967295]	auto[0]	48	1			T113	1		T86	1		T98	1
auto[4160749568:4294967295]	auto[1]	63	1			T187	1		T44	2		T99	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1587

1

T3

5

T15

1

T16

3

auto[1]

1791

1

T3

1

T4

4

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T135	2		T6	2		T47	2
auto[134217728:268435455]	119	1			T3	1		T36	1		T66	1
auto[268435456:402653183]	100	1			T4	1		T16	1		T36	1
auto[402653184:536870911]	108	1			T18	1		T36	1		T66	1
auto[536870912:671088639]	113	1			T3	1		T16	1		T24	1
auto[671088640:805306367]	99	1			T37	1		T183	1		T46	1
auto[805306368:939524095]	101	1			T26	1		T44	1		T57	1
auto[939524096:1073741823]	98	1			T44	1		T56	1		T57	1
auto[1073741824:1207959551]	96	1			T16	1		T327	1		T68	1
auto[1207959552:1342177279]	114	1			T37	1		T26	2		T187	2
auto[1342177280:1476395007]	109	1			T15	1		T24	1		T44	1
auto[1476395008:1610612735]	98	1			T18	1		T66	1		T44	1
auto[1610612736:1744830463]	118	1			T3	1		T36	1		T187	2
auto[1744830464:1879048191]	87	1			T18	1		T36	1		T183	1
auto[1879048192:2013265919]	119	1			T15	1		T187	2		T44	2
auto[2013265920:2147483647]	101	1			T3	1		T4	1		T16	1
auto[2147483648:2281701375]	89	1			T16	1		T27	1		T44	2
auto[2281701376:2415919103]	105	1			T44	1		T57	1		T5	1
auto[2415919104:2550136831]	121	1			T44	2		T57	1		T46	1
auto[2550136832:2684354559]	113	1			T44	1		T223	1		T244	1
auto[2684354560:2818572287]	106	1			T24	1		T183	1		T44	3
auto[2818572288:2952790015]	102	1			T24	2		T26	2		T44	2
auto[2952790016:3087007743]	109	1			T23	1		T24	1		T36	1
auto[3087007744:3221225471]	102	1			T3	1		T4	1		T44	2
auto[3221225472:3355443199]	96	1			T18	1		T42	3		T193	1
auto[3355443200:3489660927]	97	1			T24	1		T66	1		T183	1
auto[3489660928:3623878655]	117	1			T26	1		T27	1		T44	2
auto[3623878656:3758096383]	108	1			T4	1		T183	1		T44	4
auto[3758096384:3892314111]	119	1			T3	1		T36	1		T37	1
auto[3892314112:4026531839]	109	1			T23	1		T50	1		T57	1
auto[4026531840:4160749567]	107	1			T23	1		T44	1		T42	1
auto[4160749568:4294967295]	99	1			T36	1		T26	1		T44	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T135	2		T6	2		T47	2
auto[0:134217727]	auto[1]	53	1			T7	1		T171	1		T43	1
auto[134217728:268435455]	auto[0]	60	1			T3	1		T66	1		T42	1
auto[134217728:268435455]	auto[1]	59	1			T36	1		T67	1		T244	1
auto[268435456:402653183]	auto[0]	52	1			T135	1		T6	1		T47	1
auto[268435456:402653183]	auto[1]	48	1			T4	1		T16	1		T36	1
auto[402653184:536870911]	auto[0]	49	1			T18	1		T36	1		T66	1
auto[402653184:536870911]	auto[1]	59	1			T44	2		T46	2		T135	1
auto[536870912:671088639]	auto[0]	61	1			T3	1		T24	1		T36	1
auto[536870912:671088639]	auto[1]	52	1			T16	1		T187	1		T27	1
auto[671088640:805306367]	auto[0]	44	1			T183	1		T46	1		T190	1
auto[671088640:805306367]	auto[1]	55	1			T37	1		T190	1		T51	1
auto[805306368:939524095]	auto[0]	52	1			T26	1		T44	1		T57	1
auto[805306368:939524095]	auto[1]	49	1			T121	1		T98	1		T252	1
auto[939524096:1073741823]	auto[0]	47	1			T44	1		T56	1		T51	1
auto[939524096:1073741823]	auto[1]	51	1			T57	1		T136	2		T60	1
auto[1073741824:1207959551]	auto[0]	41	1			T16	1		T68	1		T51	1
auto[1073741824:1207959551]	auto[1]	55	1			T327	1		T51	1		T60	1
auto[1207959552:1342177279]	auto[0]	52	1			T26	2		T187	2		T30	1
auto[1207959552:1342177279]	auto[1]	62	1			T37	1		T57	1		T42	1
auto[1342177280:1476395007]	auto[0]	54	1			T15	1		T24	1		T44	1
auto[1342177280:1476395007]	auto[1]	55	1			T42	1		T190	1		T86	1
auto[1476395008:1610612735]	auto[0]	49	1			T18	1		T66	1		T232	1
auto[1476395008:1610612735]	auto[1]	49	1			T44	1		T51	1		T263	1
auto[1610612736:1744830463]	auto[0]	64	1			T3	1		T36	1		T187	1
auto[1610612736:1744830463]	auto[1]	54	1			T187	1		T57	1		T77	1
auto[1744830464:1879048191]	auto[0]	35	1			T44	1		T46	1		T51	1
auto[1744830464:1879048191]	auto[1]	52	1			T18	1		T36	1		T183	1
auto[1879048192:2013265919]	auto[0]	50	1			T187	1		T44	2		T327	1
auto[1879048192:2013265919]	auto[1]	69	1			T15	1		T187	1		T46	1
auto[2013265920:2147483647]	auto[0]	53	1			T3	1		T16	1		T44	2
auto[2013265920:2147483647]	auto[1]	48	1			T4	1		T77	1		T51	1
auto[2147483648:2281701375]	auto[0]	36	1			T16	1		T44	1		T64	1
auto[2147483648:2281701375]	auto[1]	53	1			T27	1		T44	1		T42	1
auto[2281701376:2415919103]	auto[0]	53	1			T57	1		T5	1		T42	1
auto[2281701376:2415919103]	auto[1]	52	1			T44	1		T42	1		T193	1
auto[2415919104:2550136831]	auto[0]	54	1			T46	1		T252	1		T262	1
auto[2415919104:2550136831]	auto[1]	67	1			T44	2		T57	1		T98	1
auto[2550136832:2684354559]	auto[0]	52	1			T223	1		T60	1		T7	1
auto[2550136832:2684354559]	auto[1]	61	1			T44	1		T244	1		T99	1
auto[2684354560:2818572287]	auto[0]	41	1			T44	1		T98	1		T99	2
auto[2684354560:2818572287]	auto[1]	65	1			T24	1		T183	1		T44	2
auto[2818572288:2952790015]	auto[0]	46	1			T24	1		T44	1		T57	1
auto[2818572288:2952790015]	auto[1]	56	1			T24	1		T26	2		T44	1
auto[2952790016:3087007743]	auto[0]	40	1			T23	1		T26	1		T42	1
auto[2952790016:3087007743]	auto[1]	69	1			T24	1		T36	1		T44	1
auto[3087007744:3221225471]	auto[0]	42	1			T44	1		T42	1		T327	1
auto[3087007744:3221225471]	auto[1]	60	1			T3	1		T4	1		T44	1
auto[3221225472:3355443199]	auto[0]	46	1			T18	1		T42	3		T51	1
auto[3221225472:3355443199]	auto[1]	50	1			T193	1		T244	1		T99	2
auto[3355443200:3489660927]	auto[0]	42	1			T24	1		T183	1		T44	1
auto[3355443200:3489660927]	auto[1]	55	1			T66	1		T57	1		T7	3
auto[3489660928:3623878655]	auto[0]	63	1			T26	1		T27	1		T44	1
auto[3489660928:3623878655]	auto[1]	54	1			T44	1		T60	1		T258	2
auto[3623878656:3758096383]	auto[0]	42	1			T56	1		T121	1		T99	1
auto[3623878656:3758096383]	auto[1]	66	1			T4	1		T183	1		T44	4
auto[3758096384:3892314111]	auto[0]	64	1			T3	1		T37	1		T66	1
auto[3758096384:3892314111]	auto[1]	55	1			T36	1		T183	1		T42	1
auto[3892314112:4026531839]	auto[0]	55	1			T23	1		T50	1		T98	1
auto[3892314112:4026531839]	auto[1]	54	1			T57	1		T77	1		T78	1
auto[4026531840:4160749567]	auto[0]	54	1			T23	1		T42	1		T195	1
auto[4026531840:4160749567]	auto[1]	53	1			T44	1		T193	1		T99	2
auto[4160749568:4294967295]	auto[0]	48	1			T26	1		T44	2		T135	1
auto[4160749568:4294967295]	auto[1]	51	1			T36	1		T193	1		T98	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1579

1

T3

6

T15

1

T16

3

auto[1]

1800

1

T4

4

T15

1

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T18	1		T24	1		T44	3
auto[134217728:268435455]	116	1			T36	1		T44	1		T57	1
auto[268435456:402653183]	93	1			T15	1		T44	1		T113	1
auto[402653184:536870911]	126	1			T18	1		T44	1		T46	1
auto[536870912:671088639]	107	1			T42	2		T224	1		T99	2
auto[671088640:805306367]	118	1			T3	2		T24	1		T66	1
auto[805306368:939524095]	113	1			T3	1		T4	1		T183	1
auto[939524096:1073741823]	108	1			T37	1		T26	1		T327	1
auto[1073741824:1207959551]	102	1			T16	1		T24	1		T26	1
auto[1207959552:1342177279]	107	1			T16	1		T24	1		T36	1
auto[1342177280:1476395007]	122	1			T3	1		T23	1		T24	1
auto[1476395008:1610612735]	104	1			T26	1		T44	1		T42	1
auto[1610612736:1744830463]	108	1			T36	1		T26	1		T187	2
auto[1744830464:1879048191]	110	1			T37	1		T26	1		T66	2
auto[1879048192:2013265919]	112	1			T4	1		T16	1		T44	4
auto[2013265920:2147483647]	101	1			T15	1		T23	1		T56	1
auto[2147483648:2281701375]	86	1			T26	2		T187	1		T44	1
auto[2281701376:2415919103]	97	1			T4	1		T16	2		T18	1
auto[2415919104:2550136831]	100	1			T187	1		T183	1		T56	1
auto[2550136832:2684354559]	87	1			T99	1		T136	1		T265	1
auto[2684354560:2818572287]	96	1			T37	1		T187	1		T27	1
auto[2818572288:2952790015]	99	1			T44	1		T57	1		T194	1
auto[2952790016:3087007743]	109	1			T44	2		T5	1		T42	1
auto[3087007744:3221225471]	107	1			T3	1		T24	1		T26	1
auto[3221225472:3355443199]	98	1			T36	1		T42	1		T46	1
auto[3355443200:3489660927]	115	1			T24	1		T66	1		T44	1
auto[3489660928:3623878655]	103	1			T183	1		T44	1		T56	1
auto[3623878656:3758096383]	111	1			T36	1		T187	1		T183	2
auto[3758096384:3892314111]	91	1			T18	1		T183	1		T44	2
auto[3892314112:4026531839]	114	1			T3	1		T44	2		T135	1
auto[4026531840:4160749567]	126	1			T4	1		T36	1		T66	1
auto[4160749568:4294967295]	90	1			T23	1		T44	1		T42	1