Unified Coverage Report :: Group Instance : salt_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2970

1

T3

6

T4

4

T15

2

auto[1]

298

1

T113

6

T121

6

T136

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T23	1		T24	1		T36	1
auto[134217728:268435455]	109	1			T37	1		T26	1		T44	1
auto[268435456:402653183]	92	1			T27	1		T44	1		T78	1
auto[402653184:536870911]	82	1			T57	1		T42	1		T303	1
auto[536870912:671088639]	101	1			T3	1		T36	1		T44	1
auto[671088640:805306367]	92	1			T18	1		T24	1		T195	1
auto[805306368:939524095]	133	1			T3	1		T18	1		T44	1
auto[939524096:1073741823]	103	1			T16	1		T18	1		T24	1
auto[1073741824:1207959551]	91	1			T4	1		T36	1		T26	1
auto[1207959552:1342177279]	108	1			T23	1		T26	1		T44	1
auto[1342177280:1476395007]	83	1			T3	1		T24	1		T44	1
auto[1476395008:1610612735]	97	1			T24	1		T36	2		T66	1
auto[1610612736:1744830463]	123	1			T26	1		T183	1		T44	2
auto[1744830464:1879048191]	107	1			T26	1		T66	1		T187	1
auto[1879048192:2013265919]	111	1			T5	1		T46	2		T47	2
auto[2013265920:2147483647]	91	1			T44	4		T50	1		T42	1
auto[2147483648:2281701375]	104	1			T23	1		T66	1		T27	1
auto[2281701376:2415919103]	96	1			T3	1		T187	1		T44	1
auto[2415919104:2550136831]	100	1			T16	1		T36	1		T37	1
auto[2550136832:2684354559]	129	1			T15	1		T44	2		T77	1
auto[2684354560:2818572287]	100	1			T27	1		T192	1		T193	1
auto[2818572288:2952790015]	106	1			T4	1		T36	1		T327	2
auto[2952790016:3087007743]	111	1			T3	1		T4	1		T46	1
auto[3087007744:3221225471]	97	1			T24	1		T183	2		T44	1
auto[3221225472:3355443199]	110	1			T36	1		T26	1		T44	3
auto[3355443200:3489660927]	105	1			T26	1		T187	1		T44	2
auto[3489660928:3623878655]	103	1			T24	1		T44	2		T57	1
auto[3623878656:3758096383]	112	1			T66	1		T187	1		T77	1
auto[3758096384:3892314111]	89	1			T16	1		T187	2		T44	1
auto[3892314112:4026531839]	83	1			T18	1		T187	1		T183	1
auto[4026531840:4160749567]	93	1			T3	1		T4	1		T42	1
auto[4160749568:4294967295]	95	1			T15	1		T37	1		T263	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	99	1			T23	1		T24	1		T36	1
auto[0:134217727]	auto[1]	13	1			T136	1		T238	1		T123	1
auto[134217728:268435455]	auto[0]	99	1			T37	1		T26	1		T44	1
auto[134217728:268435455]	auto[1]	10	1			T121	1		T357	1		T237	1
auto[268435456:402653183]	auto[0]	85	1			T27	1		T44	1		T78	1
auto[268435456:402653183]	auto[1]	7	1			T381	1		T278	1		T334	1
auto[402653184:536870911]	auto[0]	76	1			T57	1		T42	1		T303	1
auto[402653184:536870911]	auto[1]	6	1			T229	1		T381	1		T257	1
auto[536870912:671088639]	auto[0]	88	1			T3	1		T36	1		T44	1
auto[536870912:671088639]	auto[1]	13	1			T121	1		T136	1		T242	1
auto[671088640:805306367]	auto[0]	83	1			T18	1		T24	1		T195	1
auto[671088640:805306367]	auto[1]	9	1			T136	1		T238	1		T254	1
auto[805306368:939524095]	auto[0]	118	1			T3	1		T18	1		T44	1
auto[805306368:939524095]	auto[1]	15	1			T238	2		T277	1		T357	1
auto[939524096:1073741823]	auto[0]	97	1			T16	1		T18	1		T24	1
auto[939524096:1073741823]	auto[1]	6	1			T122	1		T229	1		T391	1
auto[1073741824:1207959551]	auto[0]	78	1			T4	1		T36	1		T26	1
auto[1073741824:1207959551]	auto[1]	13	1			T121	1		T136	1		T123	1
auto[1207959552:1342177279]	auto[0]	100	1			T23	1		T26	1		T44	1
auto[1207959552:1342177279]	auto[1]	8	1			T238	1		T123	1		T229	1
auto[1342177280:1476395007]	auto[0]	78	1			T3	1		T24	1		T44	1
auto[1342177280:1476395007]	auto[1]	5	1			T127	1		T391	1		T395	1
auto[1476395008:1610612735]	auto[0]	88	1			T24	1		T36	2		T66	1
auto[1476395008:1610612735]	auto[1]	9	1			T113	1		T121	1		T277	1
auto[1610612736:1744830463]	auto[0]	108	1			T26	1		T183	1		T44	2
auto[1610612736:1744830463]	auto[1]	15	1			T113	1		T122	2		T236	1
auto[1744830464:1879048191]	auto[0]	99	1			T26	1		T66	1		T187	1
auto[1744830464:1879048191]	auto[1]	8	1			T113	1		T121	1		T238	1
auto[1879048192:2013265919]	auto[0]	97	1			T5	1		T46	2		T47	2
auto[1879048192:2013265919]	auto[1]	14	1			T238	1		T122	2		T236	1
auto[2013265920:2147483647]	auto[0]	85	1			T44	4		T50	1		T42	1
auto[2013265920:2147483647]	auto[1]	6	1			T277	1		T291	1		T334	1
auto[2147483648:2281701375]	auto[0]	91	1			T23	1		T66	1		T27	1
auto[2147483648:2281701375]	auto[1]	13	1			T136	1		T357	1		T229	1
auto[2281701376:2415919103]	auto[0]	88	1			T3	1		T187	1		T44	1
auto[2281701376:2415919103]	auto[1]	8	1			T380	1		T266	2		T267	1
auto[2415919104:2550136831]	auto[0]	89	1			T16	1		T36	1		T37	1
auto[2415919104:2550136831]	auto[1]	11	1			T113	1		T277	1		T242	1
auto[2550136832:2684354559]	auto[0]	119	1			T15	1		T44	2		T77	1
auto[2550136832:2684354559]	auto[1]	10	1			T136	1		T122	2		T236	1
auto[2684354560:2818572287]	auto[0]	88	1			T27	1		T192	1		T193	1
auto[2684354560:2818572287]	auto[1]	12	1			T238	1		T357	1		T242	1
auto[2818572288:2952790015]	auto[0]	97	1			T4	1		T36	1		T327	2
auto[2818572288:2952790015]	auto[1]	9	1			T136	1		T122	1		T254	1
auto[2952790016:3087007743]	auto[0]	105	1			T3	1		T4	1		T46	1
auto[2952790016:3087007743]	auto[1]	6	1			T136	1		T238	2		T381	1
auto[3087007744:3221225471]	auto[0]	87	1			T24	1		T183	2		T44	1
auto[3087007744:3221225471]	auto[1]	10	1			T113	2		T122	1		T278	1
auto[3221225472:3355443199]	auto[0]	103	1			T36	1		T26	1		T44	3
auto[3221225472:3355443199]	auto[1]	7	1			T121	1		T369	1		T254	1
auto[3355443200:3489660927]	auto[0]	95	1			T26	1		T187	1		T44	2
auto[3355443200:3489660927]	auto[1]	10	1			T238	1		T277	1		T291	1
auto[3489660928:3623878655]	auto[0]	100	1			T24	1		T44	2		T57	1
auto[3489660928:3623878655]	auto[1]	3	1			T278	1		T356	1		T396	1
auto[3623878656:3758096383]	auto[0]	104	1			T66	1		T187	1		T77	1
auto[3623878656:3758096383]	auto[1]	8	1			T122	1		T382	1		T278	1
auto[3758096384:3892314111]	auto[0]	79	1			T16	1		T187	2		T44	1
auto[3758096384:3892314111]	auto[1]	10	1			T369	1		T242	1		T381	1
auto[3892314112:4026531839]	auto[0]	77	1			T18	1		T187	1		T183	1
auto[3892314112:4026531839]	auto[1]	6	1			T238	1		T254	1		T222	1
auto[4026531840:4160749567]	auto[0]	82	1			T3	1		T4	1		T42	1
auto[4026531840:4160749567]	auto[1]	11	1			T238	1		T277	2		T237	1
auto[4160749568:4294967295]	auto[0]	88	1			T15	1		T37	1		T263	1
auto[4160749568:4294967295]	auto[1]	7	1			T136	1		T238	1		T229	1