Unified Coverage Report :: Group Instance : sealing_sw_binding_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1585

1

T3

5

T15

1

T16

2

auto[1]

1793

1

T3

1

T4

4

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T3	1		T24	1		T36	1
auto[134217728:268435455]	126	1			T183	1		T44	2		T57	1
auto[268435456:402653183]	120	1			T4	1		T66	1		T44	1
auto[402653184:536870911]	118	1			T4	1		T18	1		T23	1
auto[536870912:671088639]	94	1			T187	1		T183	1		T56	1
auto[671088640:805306367]	105	1			T27	1		T44	2		T56	1
auto[805306368:939524095]	100	1			T26	1		T44	1		T47	1
auto[939524096:1073741823]	108	1			T36	1		T44	1		T57	1
auto[1073741824:1207959551]	94	1			T16	1		T66	1		T5	1
auto[1207959552:1342177279]	127	1			T3	1		T24	1		T36	1
auto[1342177280:1476395007]	104	1			T66	1		T183	1		T44	2
auto[1476395008:1610612735]	107	1			T44	2		T194	1		T51	1
auto[1610612736:1744830463]	98	1			T15	1		T36	1		T44	1
auto[1744830464:1879048191]	96	1			T4	1		T37	1		T44	1
auto[1879048192:2013265919]	90	1			T18	1		T44	3		T57	1
auto[2013265920:2147483647]	117	1			T36	1		T183	1		T44	1
auto[2147483648:2281701375]	108	1			T3	1		T16	1		T37	1
auto[2281701376:2415919103]	89	1			T4	1		T44	1		T42	1
auto[2415919104:2550136831]	110	1			T26	2		T187	1		T44	2
auto[2550136832:2684354559]	93	1			T3	1		T16	2		T23	1
auto[2684354560:2818572287]	99	1			T183	1		T56	1		T78	1
auto[2818572288:2952790015]	116	1			T36	1		T26	1		T232	1
auto[2952790016:3087007743]	108	1			T15	1		T24	1		T57	1
auto[3087007744:3221225471]	105	1			T44	5		T42	3		T327	1
auto[3221225472:3355443199]	98	1			T24	1		T36	1		T187	1
auto[3355443200:3489660927]	91	1			T16	1		T66	1		T187	1
auto[3489660928:3623878655]	107	1			T3	1		T37	1		T44	1
auto[3623878656:3758096383]	105	1			T18	1		T44	1		T56	1
auto[3758096384:3892314111]	111	1			T24	1		T66	1		T44	1
auto[3892314112:4026531839]	101	1			T3	1		T23	1		T24	1
auto[4026531840:4160749567]	114	1			T24	1		T36	1		T187	2
auto[4160749568:4294967295]	111	1			T18	1		T66	1		T42	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	50	1			T3	1		T26	1		T27	1
auto[0:134217727]	auto[1]	58	1			T24	1		T36	1		T46	1
auto[134217728:268435455]	auto[0]	58	1			T183	1		T44	2		T47	1
auto[134217728:268435455]	auto[1]	68	1			T57	1		T78	1		T113	1
auto[268435456:402653183]	auto[0]	50	1			T66	1		T44	1		T42	1
auto[268435456:402653183]	auto[1]	70	1			T4	1		T78	1		T193	1
auto[402653184:536870911]	auto[0]	50	1			T18	1		T23	1		T44	1
auto[402653184:536870911]	auto[1]	68	1			T4	1		T26	1		T27	1
auto[536870912:671088639]	auto[0]	45	1			T187	1		T51	1		T223	1
auto[536870912:671088639]	auto[1]	49	1			T183	1		T56	1		T252	1
auto[671088640:805306367]	auto[0]	42	1			T44	1		T56	1		T42	1
auto[671088640:805306367]	auto[1]	63	1			T27	1		T44	1		T57	1
auto[805306368:939524095]	auto[0]	45	1			T26	1		T44	1		T47	1
auto[805306368:939524095]	auto[1]	55	1			T60	1		T117	1		T43	1
auto[939524096:1073741823]	auto[0]	56	1			T36	1		T44	1		T42	1
auto[939524096:1073741823]	auto[1]	52	1			T57	1		T6	1		T67	1
auto[1073741824:1207959551]	auto[0]	43	1			T42	2		T178	1		T202	1
auto[1073741824:1207959551]	auto[1]	51	1			T16	1		T66	1		T5	1
auto[1207959552:1342177279]	auto[0]	61	1			T3	1		T26	1		T44	1
auto[1207959552:1342177279]	auto[1]	66	1			T24	1		T36	1		T44	2
auto[1342177280:1476395007]	auto[0]	50	1			T66	1		T44	1		T99	1
auto[1342177280:1476395007]	auto[1]	54	1			T183	1		T44	1		T46	1
auto[1476395008:1610612735]	auto[0]	58	1			T44	1		T51	1		T99	1
auto[1476395008:1610612735]	auto[1]	49	1			T44	1		T194	1		T224	1
auto[1610612736:1744830463]	auto[0]	46	1			T15	1		T36	1		T44	1
auto[1610612736:1744830463]	auto[1]	52	1			T57	1		T121	1		T98	3
auto[1744830464:1879048191]	auto[0]	43	1			T44	1		T77	1		T51	1
auto[1744830464:1879048191]	auto[1]	53	1			T4	1		T37	1		T42	1
auto[1879048192:2013265919]	auto[0]	47	1			T18	1		T44	2		T232	1
auto[1879048192:2013265919]	auto[1]	43	1			T44	1		T57	1		T42	1
auto[2013265920:2147483647]	auto[0]	46	1			T46	1		T121	1		T98	1
auto[2013265920:2147483647]	auto[1]	71	1			T36	1		T183	1		T44	1
auto[2147483648:2281701375]	auto[0]	53	1			T3	1		T37	1		T26	1
auto[2147483648:2281701375]	auto[1]	55	1			T16	1		T44	1		T77	1
auto[2281701376:2415919103]	auto[0]	39	1			T46	1		T238	1		T264	1
auto[2281701376:2415919103]	auto[1]	50	1			T4	1		T44	1		T42	1
auto[2415919104:2550136831]	auto[0]	55	1			T26	2		T187	1		T57	1
auto[2415919104:2550136831]	auto[1]	55	1			T44	2		T327	1		T193	1
auto[2550136832:2684354559]	auto[0]	42	1			T16	1		T183	1		T44	2
auto[2550136832:2684354559]	auto[1]	51	1			T3	1		T16	1		T23	1
auto[2684354560:2818572287]	auto[0]	52	1			T183	1		T56	1		T272	1
auto[2684354560:2818572287]	auto[1]	47	1			T78	1		T135	1		T51	1
auto[2818572288:2952790015]	auto[0]	55	1			T36	1		T26	1		T51	1
auto[2818572288:2952790015]	auto[1]	61	1			T232	1		T51	1		T244	1
auto[2952790016:3087007743]	auto[0]	54	1			T24	1		T135	2		T223	1
auto[2952790016:3087007743]	auto[1]	54	1			T15	1		T57	1		T42	1
auto[3087007744:3221225471]	auto[0]	51	1			T44	3		T42	1		T327	1
auto[3087007744:3221225471]	auto[1]	54	1			T44	2		T42	2		T46	1
auto[3221225472:3355443199]	auto[0]	50	1			T24	1		T187	1		T135	1
auto[3221225472:3355443199]	auto[1]	48	1			T36	1		T44	1		T190	1
auto[3355443200:3489660927]	auto[0]	46	1			T16	1		T66	1		T187	1
auto[3355443200:3489660927]	auto[1]	45	1			T42	1		T46	1		T99	1
auto[3489660928:3623878655]	auto[0]	53	1			T3	1		T44	1		T195	1
auto[3489660928:3623878655]	auto[1]	54	1			T37	1		T50	1		T77	2
auto[3623878656:3758096383]	auto[0]	44	1			T18	1		T44	1		T56	1
auto[3623878656:3758096383]	auto[1]	61	1			T42	2		T30	1		T98	1
auto[3758096384:3892314111]	auto[0]	50	1			T46	1		T30	1		T47	1
auto[3758096384:3892314111]	auto[1]	61	1			T24	1		T66	1		T44	1
auto[3892314112:4026531839]	auto[0]	39	1			T3	1		T23	1		T24	1
auto[3892314112:4026531839]	auto[1]	62	1			T187	1		T42	1		T327	1
auto[4026531840:4160749567]	auto[0]	58	1			T24	1		T187	1		T190	1
auto[4026531840:4160749567]	auto[1]	56	1			T36	1		T187	1		T44	1
auto[4160749568:4294967295]	auto[0]	54	1			T18	1		T66	1		T42	1
auto[4160749568:4294967295]	auto[1]	57	1			T42	1		T135	1		T99	1