Unified Coverage Report :: Group Instance : attest_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1577

1

T3

6

T15

1

T16

2

auto[1]

1802

1

T4

4

T15

1

T16

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T44	2		T78	1		T42	1
auto[134217728:268435455]	90	1			T4	1		T36	1		T44	1
auto[268435456:402653183]	117	1			T36	1		T66	1		T42	3
auto[402653184:536870911]	115	1			T36	2		T44	1		T42	1
auto[536870912:671088639]	120	1			T23	1		T36	1		T26	2
auto[671088640:805306367]	100	1			T66	1		T57	1		T42	1
auto[805306368:939524095]	105	1			T3	1		T24	1		T42	2
auto[939524096:1073741823]	110	1			T36	2		T26	1		T56	1
auto[1073741824:1207959551]	99	1			T37	1		T187	1		T44	2
auto[1207959552:1342177279]	101	1			T3	1		T44	1		T57	1
auto[1342177280:1476395007]	113	1			T16	1		T183	1		T44	1
auto[1476395008:1610612735]	92	1			T24	1		T187	1		T27	1
auto[1610612736:1744830463]	106	1			T4	1		T16	1		T18	1
auto[1744830464:1879048191]	98	1			T16	1		T37	1		T187	1
auto[1879048192:2013265919]	93	1			T3	1		T57	3		T5	1
auto[2013265920:2147483647]	110	1			T24	2		T26	1		T187	1
auto[2147483648:2281701375]	107	1			T24	2		T37	1		T183	1
auto[2281701376:2415919103]	113	1			T15	1		T66	1		T44	2
auto[2415919104:2550136831]	107	1			T187	1		T44	4		T51	1
auto[2550136832:2684354559]	100	1			T4	1		T36	2		T44	1
auto[2684354560:2818572287]	121	1			T15	1		T18	2		T24	1
auto[2818572288:2952790015]	103	1			T3	1		T23	1		T26	1
auto[2952790016:3087007743]	102	1			T16	1		T26	1		T44	2
auto[3087007744:3221225471]	113	1			T187	1		T56	1		T232	1
auto[3221225472:3355443199]	120	1			T23	1		T44	4		T77	1
auto[3355443200:3489660927]	93	1			T3	1		T183	2		T44	1
auto[3489660928:3623878655]	102	1			T66	1		T27	1		T44	1
auto[3623878656:3758096383]	95	1			T4	1		T26	1		T66	1
auto[3758096384:3892314111]	105	1			T44	2		T78	1		T42	1
auto[3892314112:4026531839]	108	1			T18	1		T26	1		T44	2
auto[4026531840:4160749567]	91	1			T3	1		T44	1		T56	1
auto[4160749568:4294967295]	118	1			T16	1		T66	1		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T44	1		T42	1		T232	1
auto[0:134217727]	auto[1]	64	1			T44	1		T78	1		T99	1
auto[134217728:268435455]	auto[0]	43	1			T36	1		T44	1		T42	1
auto[134217728:268435455]	auto[1]	47	1			T4	1		T98	1		T99	1
auto[268435456:402653183]	auto[0]	59	1			T42	1		T135	1		T252	1
auto[268435456:402653183]	auto[1]	58	1			T36	1		T66	1		T42	2
auto[402653184:536870911]	auto[0]	58	1			T135	1		T232	1		T48	1
auto[402653184:536870911]	auto[1]	57	1			T36	2		T44	1		T42	1
auto[536870912:671088639]	auto[0]	52	1			T23	1		T26	2		T44	1
auto[536870912:671088639]	auto[1]	68	1			T36	1		T183	1		T42	1
auto[671088640:805306367]	auto[0]	48	1			T66	1		T57	1		T42	1
auto[671088640:805306367]	auto[1]	52	1			T194	1		T30	1		T223	1
auto[805306368:939524095]	auto[0]	56	1			T3	1		T24	1		T42	1
auto[805306368:939524095]	auto[1]	49	1			T42	1		T193	1		T303	1
auto[939524096:1073741823]	auto[0]	58	1			T36	1		T46	1		T51	1
auto[939524096:1073741823]	auto[1]	52	1			T36	1		T26	1		T56	1
auto[1073741824:1207959551]	auto[0]	44	1			T37	1		T44	2		T51	1
auto[1073741824:1207959551]	auto[1]	55	1			T187	1		T303	1		T244	1
auto[1207959552:1342177279]	auto[0]	51	1			T3	1		T46	2		T6	1
auto[1207959552:1342177279]	auto[1]	50	1			T44	1		T57	1		T5	1
auto[1342177280:1476395007]	auto[0]	50	1			T16	1		T44	1		T42	1
auto[1342177280:1476395007]	auto[1]	63	1			T183	1		T327	1		T60	2
auto[1476395008:1610612735]	auto[0]	42	1			T24	1		T187	1		T44	1
auto[1476395008:1610612735]	auto[1]	50	1			T27	1		T183	1		T77	1
auto[1610612736:1744830463]	auto[0]	61	1			T16	1		T18	1		T46	1
auto[1610612736:1744830463]	auto[1]	45	1			T4	1		T44	1		T67	1
auto[1744830464:1879048191]	auto[0]	46	1			T187	1		T57	1		T98	1
auto[1744830464:1879048191]	auto[1]	52	1			T16	1		T37	1		T42	1
auto[1879048192:2013265919]	auto[0]	49	1			T3	1		T195	1		T98	1
auto[1879048192:2013265919]	auto[1]	44	1			T57	3		T5	1		T327	1
auto[2013265920:2147483647]	auto[0]	60	1			T26	1		T187	1		T57	1
auto[2013265920:2147483647]	auto[1]	50	1			T24	2		T7	1		T264	1
auto[2147483648:2281701375]	auto[0]	51	1			T24	1		T183	1		T56	1
auto[2147483648:2281701375]	auto[1]	56	1			T24	1		T37	1		T42	1
auto[2281701376:2415919103]	auto[0]	46	1			T66	1		T68	1		T86	1
auto[2281701376:2415919103]	auto[1]	67	1			T15	1		T44	2		T77	1
auto[2415919104:2550136831]	auto[0]	56	1			T187	1		T44	2		T51	1
auto[2415919104:2550136831]	auto[1]	51	1			T44	2		T121	1		T21	1
auto[2550136832:2684354559]	auto[0]	36	1			T36	1		T44	1		T7	1
auto[2550136832:2684354559]	auto[1]	64	1			T4	1		T36	1		T42	1
auto[2684354560:2818572287]	auto[0]	45	1			T15	1		T18	1		T24	1
auto[2684354560:2818572287]	auto[1]	76	1			T18	1		T44	1		T78	1
auto[2818572288:2952790015]	auto[0]	51	1			T3	1		T23	1		T26	1
auto[2818572288:2952790015]	auto[1]	52	1			T44	2		T57	1		T42	1
auto[2952790016:3087007743]	auto[0]	43	1			T26	1		T44	1		T135	1
auto[2952790016:3087007743]	auto[1]	59	1			T16	1		T44	1		T57	1
auto[3087007744:3221225471]	auto[0]	39	1			T56	1		T223	1		T54	1
auto[3087007744:3221225471]	auto[1]	74	1			T187	1		T232	1		T99	1
auto[3221225472:3355443199]	auto[0]	61	1			T44	3		T77	1		T30	1
auto[3221225472:3355443199]	auto[1]	59	1			T23	1		T44	1		T86	1
auto[3355443200:3489660927]	auto[0]	51	1			T3	1		T183	2		T121	1
auto[3355443200:3489660927]	auto[1]	42	1			T44	1		T121	1		T272	1
auto[3489660928:3623878655]	auto[0]	48	1			T66	1		T194	1		T51	1
auto[3489660928:3623878655]	auto[1]	54	1			T27	1		T44	1		T50	1
auto[3623878656:3758096383]	auto[0]	42	1			T26	1		T66	1		T121	1
auto[3623878656:3758096383]	auto[1]	53	1			T4	1		T44	1		T77	1
auto[3758096384:3892314111]	auto[0]	49	1			T44	2		T42	1		T46	1
auto[3758096384:3892314111]	auto[1]	56	1			T78	1		T46	2		T99	1
auto[3892314112:4026531839]	auto[0]	46	1			T18	1		T26	1		T44	1
auto[3892314112:4026531839]	auto[1]	62	1			T44	1		T57	1		T51	1
auto[4026531840:4160749567]	auto[0]	44	1			T3	1		T44	1		T56	1
auto[4026531840:4160749567]	auto[1]	47	1			T193	1		T113	1		T98	1
auto[4160749568:4294967295]	auto[0]	44	1			T27	1		T44	2		T192	1
auto[4160749568:4294967295]	auto[1]	74	1			T16	1		T66	1		T44	1