Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.04 98.07 98.53 100.00 99.02 98.41 91.22


Total test records in report: 1079
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T1006 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4209333388 Aug 07 04:49:16 PM PDT 24 Aug 07 04:49:21 PM PDT 24 754431481 ps
T1007 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.942506728 Aug 07 04:49:08 PM PDT 24 Aug 07 04:49:14 PM PDT 24 538898731 ps
T1008 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3111082172 Aug 07 04:49:21 PM PDT 24 Aug 07 04:49:22 PM PDT 24 17042677 ps
T156 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1623117013 Aug 07 04:49:25 PM PDT 24 Aug 07 04:49:32 PM PDT 24 311854689 ps
T1009 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1147642638 Aug 07 04:49:37 PM PDT 24 Aug 07 04:49:38 PM PDT 24 10574684 ps
T1010 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.470779775 Aug 07 04:48:48 PM PDT 24 Aug 07 04:48:49 PM PDT 24 34083277 ps
T1011 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1108972448 Aug 07 04:49:10 PM PDT 24 Aug 07 04:49:11 PM PDT 24 118298136 ps
T153 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3934162884 Aug 07 04:49:30 PM PDT 24 Aug 07 04:49:36 PM PDT 24 336645413 ps
T1012 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3915025221 Aug 07 04:49:16 PM PDT 24 Aug 07 04:49:19 PM PDT 24 169861154 ps
T1013 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2580250094 Aug 07 04:49:09 PM PDT 24 Aug 07 04:49:09 PM PDT 24 190617924 ps
T1014 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1251456224 Aug 07 04:49:33 PM PDT 24 Aug 07 04:49:34 PM PDT 24 51391483 ps
T1015 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3310238233 Aug 07 04:49:13 PM PDT 24 Aug 07 04:49:14 PM PDT 24 9904251 ps
T1016 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4023364471 Aug 07 04:49:09 PM PDT 24 Aug 07 04:49:12 PM PDT 24 192722071 ps
T1017 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1887761673 Aug 07 04:49:05 PM PDT 24 Aug 07 04:49:08 PM PDT 24 242393690 ps
T1018 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3935244472 Aug 07 04:49:04 PM PDT 24 Aug 07 04:49:05 PM PDT 24 18332375 ps
T1019 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1821871411 Aug 07 04:49:25 PM PDT 24 Aug 07 04:49:27 PM PDT 24 102998238 ps
T1020 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1615729123 Aug 07 04:49:16 PM PDT 24 Aug 07 04:49:19 PM PDT 24 100617087 ps
T1021 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3023365644 Aug 07 04:49:04 PM PDT 24 Aug 07 04:49:06 PM PDT 24 45496240 ps
T1022 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.250953185 Aug 07 04:49:43 PM PDT 24 Aug 07 04:49:46 PM PDT 24 38538418 ps
T1023 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1904552973 Aug 07 04:49:02 PM PDT 24 Aug 07 04:49:06 PM PDT 24 95935030 ps
T1024 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3254185312 Aug 07 04:49:24 PM PDT 24 Aug 07 04:49:27 PM PDT 24 236735393 ps
T1025 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4072039962 Aug 07 04:49:32 PM PDT 24 Aug 07 04:49:34 PM PDT 24 128571554 ps
T1026 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2201801446 Aug 07 04:49:20 PM PDT 24 Aug 07 04:49:25 PM PDT 24 360986661 ps
T146 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4099988060 Aug 07 04:49:08 PM PDT 24 Aug 07 04:49:15 PM PDT 24 1016768778 ps
T1027 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1729858862 Aug 07 04:48:59 PM PDT 24 Aug 07 04:49:00 PM PDT 24 149678147 ps
T1028 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1137498685 Aug 07 04:49:02 PM PDT 24 Aug 07 04:49:04 PM PDT 24 176172866 ps
T1029 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1805810696 Aug 07 04:49:01 PM PDT 24 Aug 07 04:49:03 PM PDT 24 393927775 ps
T1030 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4247029212 Aug 07 04:48:54 PM PDT 24 Aug 07 04:48:56 PM PDT 24 132341909 ps
T1031 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3934228275 Aug 07 04:49:27 PM PDT 24 Aug 07 04:49:28 PM PDT 24 28969915 ps
T1032 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.197983437 Aug 07 04:49:05 PM PDT 24 Aug 07 04:49:09 PM PDT 24 69351423 ps
T1033 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.972305414 Aug 07 04:49:33 PM PDT 24 Aug 07 04:49:33 PM PDT 24 144708747 ps
T1034 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1378223889 Aug 07 04:49:23 PM PDT 24 Aug 07 04:49:24 PM PDT 24 54218720 ps
T1035 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1593726970 Aug 07 04:49:17 PM PDT 24 Aug 07 04:49:19 PM PDT 24 151328028 ps
T1036 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3007884408 Aug 07 04:49:17 PM PDT 24 Aug 07 04:49:23 PM PDT 24 2024473671 ps
T1037 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2136979172 Aug 07 04:49:15 PM PDT 24 Aug 07 04:49:16 PM PDT 24 111759636 ps
T1038 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3668884107 Aug 07 04:49:10 PM PDT 24 Aug 07 04:49:12 PM PDT 24 208792941 ps
T1039 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1945675051 Aug 07 04:48:55 PM PDT 24 Aug 07 04:49:08 PM PDT 24 919873878 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2536554918 Aug 07 04:48:45 PM PDT 24 Aug 07 04:49:00 PM PDT 24 444434963 ps
T1041 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.602563011 Aug 07 04:49:09 PM PDT 24 Aug 07 04:49:15 PM PDT 24 438995932 ps
T1042 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2981825593 Aug 07 04:49:21 PM PDT 24 Aug 07 04:49:25 PM PDT 24 86581448 ps
T1043 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.4170232332 Aug 07 04:49:00 PM PDT 24 Aug 07 04:49:03 PM PDT 24 90101730 ps
T154 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.283507516 Aug 07 04:49:01 PM PDT 24 Aug 07 04:49:11 PM PDT 24 545654593 ps
T1044 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.286310093 Aug 07 04:49:34 PM PDT 24 Aug 07 04:49:35 PM PDT 24 13929074 ps
T1045 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1610839824 Aug 07 04:49:26 PM PDT 24 Aug 07 04:49:27 PM PDT 24 8163843 ps
T1046 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2565545492 Aug 07 04:49:15 PM PDT 24 Aug 07 04:49:17 PM PDT 24 236422633 ps
T1047 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3546361227 Aug 07 04:49:07 PM PDT 24 Aug 07 04:49:09 PM PDT 24 431478062 ps
T1048 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1063513199 Aug 07 04:49:10 PM PDT 24 Aug 07 04:49:11 PM PDT 24 25080717 ps
T1049 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3599547056 Aug 07 04:49:35 PM PDT 24 Aug 07 04:49:36 PM PDT 24 10012473 ps
T1050 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1733892087 Aug 07 04:49:06 PM PDT 24 Aug 07 04:49:08 PM PDT 24 235458352 ps
T1051 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.724912936 Aug 07 04:49:10 PM PDT 24 Aug 07 04:49:12 PM PDT 24 629767405 ps
T1052 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.690918263 Aug 07 04:49:11 PM PDT 24 Aug 07 04:49:12 PM PDT 24 36496402 ps
T1053 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.68033095 Aug 07 04:48:43 PM PDT 24 Aug 07 04:48:44 PM PDT 24 65169009 ps
T1054 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1009640457 Aug 07 04:48:55 PM PDT 24 Aug 07 04:48:59 PM PDT 24 89983480 ps
T1055 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3386951485 Aug 07 04:49:12 PM PDT 24 Aug 07 04:49:13 PM PDT 24 34475291 ps
T157 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2479324271 Aug 07 04:48:46 PM PDT 24 Aug 07 04:48:51 PM PDT 24 418243156 ps
T1056 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2970344493 Aug 07 04:49:25 PM PDT 24 Aug 07 04:49:26 PM PDT 24 12737900 ps
T1057 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3266385907 Aug 07 04:49:25 PM PDT 24 Aug 07 04:49:28 PM PDT 24 35184641 ps
T1058 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.509760950 Aug 07 04:49:27 PM PDT 24 Aug 07 04:49:29 PM PDT 24 91979530 ps
T1059 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2139658650 Aug 07 04:49:35 PM PDT 24 Aug 07 04:49:36 PM PDT 24 11202925 ps
T1060 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2893526385 Aug 07 04:49:22 PM PDT 24 Aug 07 04:49:24 PM PDT 24 102865255 ps
T1061 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.170066545 Aug 07 04:49:00 PM PDT 24 Aug 07 04:49:04 PM PDT 24 79998749 ps
T1062 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.49464305 Aug 07 04:49:06 PM PDT 24 Aug 07 04:49:09 PM PDT 24 123654514 ps
T1063 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.177136470 Aug 07 04:49:03 PM PDT 24 Aug 07 04:49:04 PM PDT 24 75648185 ps
T1064 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2597566270 Aug 07 04:49:21 PM PDT 24 Aug 07 04:49:28 PM PDT 24 1102043738 ps
T1065 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1317406130 Aug 07 04:49:35 PM PDT 24 Aug 07 04:49:36 PM PDT 24 82183830 ps
T1066 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.769070538 Aug 07 04:48:46 PM PDT 24 Aug 07 04:48:51 PM PDT 24 859687485 ps
T1067 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.406642590 Aug 07 04:49:05 PM PDT 24 Aug 07 04:49:06 PM PDT 24 140342017 ps
T1068 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2186626331 Aug 07 04:49:16 PM PDT 24 Aug 07 04:49:19 PM PDT 24 364780733 ps
T1069 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.627039703 Aug 07 04:49:27 PM PDT 24 Aug 07 04:49:29 PM PDT 24 161002896 ps
T1070 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.624850575 Aug 07 04:49:35 PM PDT 24 Aug 07 04:49:37 PM PDT 24 222541378 ps
T1071 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.592904533 Aug 07 04:48:46 PM PDT 24 Aug 07 04:48:47 PM PDT 24 104232216 ps
T1072 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.810198842 Aug 07 04:49:07 PM PDT 24 Aug 07 04:49:08 PM PDT 24 88984398 ps
T1073 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3882986673 Aug 07 04:49:25 PM PDT 24 Aug 07 04:49:28 PM PDT 24 41386456 ps
T1074 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1932570836 Aug 07 04:49:22 PM PDT 24 Aug 07 04:49:27 PM PDT 24 412909195 ps
T1075 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1647323241 Aug 07 04:49:00 PM PDT 24 Aug 07 04:49:01 PM PDT 24 25947294 ps
T1076 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.289441399 Aug 07 04:49:06 PM PDT 24 Aug 07 04:49:14 PM PDT 24 220884818 ps
T1077 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1927283037 Aug 07 04:49:05 PM PDT 24 Aug 07 04:49:08 PM PDT 24 168912102 ps
T1078 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1049257588 Aug 07 04:49:14 PM PDT 24 Aug 07 04:49:15 PM PDT 24 38583529 ps
T1079 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3812481990 Aug 07 04:49:23 PM PDT 24 Aug 07 04:49:24 PM PDT 24 17020789 ps

Test location /workspace/coverage/default/44.keymgr_lc_disable.3520887488
Short name T16
Test name
Test status
Simulation time 308054555 ps
CPU time 3.39 seconds
Started Aug 07 06:19:30 PM PDT 24
Finished Aug 07 06:19:33 PM PDT 24
Peak memory 208044 kb
Host smart-901060e9-924a-44a9-862b-ca9bc99d2077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520887488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3520887488
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3394932864
Short name T44
Test name
Test status
Simulation time 1674088436 ps
CPU time 40.24 seconds
Started Aug 07 06:19:19 PM PDT 24
Finished Aug 07 06:20:00 PM PDT 24
Peak memory 215948 kb
Host smart-fd631aca-bc62-4d0a-bb78-a9ed97af0796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394932864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3394932864
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.4202012896
Short name T57
Test name
Test status
Simulation time 130327670 ps
CPU time 8.99 seconds
Started Aug 07 06:18:24 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 220588 kb
Host smart-ba65b726-969e-4b1c-b984-d6caba110d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202012896 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.4202012896
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3091638027
Short name T24
Test name
Test status
Simulation time 56592924 ps
CPU time 3.16 seconds
Started Aug 07 06:16:59 PM PDT 24
Finished Aug 07 06:17:02 PM PDT 24
Peak memory 214264 kb
Host smart-ac4294ec-528c-4bf5-88d8-56748bdc5c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091638027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3091638027
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3827339409
Short name T7
Test name
Test status
Simulation time 58431743645 ps
CPU time 321.66 seconds
Started Aug 07 06:19:01 PM PDT 24
Finished Aug 07 06:24:23 PM PDT 24
Peak memory 219800 kb
Host smart-21885f9e-965f-4083-b08e-17fef23506d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827339409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3827339409
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3612322769
Short name T40
Test name
Test status
Simulation time 1722957431 ps
CPU time 15.39 seconds
Started Aug 07 06:16:59 PM PDT 24
Finished Aug 07 06:17:14 PM PDT 24
Peak memory 238028 kb
Host smart-3344a9f1-5dd5-47dd-a036-ace1227d7e8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612322769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3612322769
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1846585355
Short name T55
Test name
Test status
Simulation time 1457923961 ps
CPU time 18.74 seconds
Started Aug 07 06:19:16 PM PDT 24
Finished Aug 07 06:19:34 PM PDT 24
Peak memory 222476 kb
Host smart-302a3aad-e641-4c01-945d-51d9c74186e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846585355 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1846585355
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1654917817
Short name T64
Test name
Test status
Simulation time 14813066714 ps
CPU time 59.97 seconds
Started Aug 07 06:19:43 PM PDT 24
Finished Aug 07 06:20:44 PM PDT 24
Peak memory 222516 kb
Host smart-77b7a950-0780-49e8-9d55-aaa771a8ce09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654917817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1654917817
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3125343971
Short name T238
Test name
Test status
Simulation time 1643448545 ps
CPU time 46.47 seconds
Started Aug 07 06:19:06 PM PDT 24
Finished Aug 07 06:19:53 PM PDT 24
Peak memory 214364 kb
Host smart-aafadd43-249f-424e-91be-2def1a981a77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125343971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3125343971
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2708633812
Short name T47
Test name
Test status
Simulation time 44221600 ps
CPU time 2.45 seconds
Started Aug 07 06:18:46 PM PDT 24
Finished Aug 07 06:18:49 PM PDT 24
Peak memory 222320 kb
Host smart-2b64ceeb-4538-42ba-ac73-94cc4e95f865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708633812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2708633812
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3007968692
Short name T8
Test name
Test status
Simulation time 1680483518 ps
CPU time 3.98 seconds
Started Aug 07 06:19:12 PM PDT 24
Finished Aug 07 06:19:17 PM PDT 24
Peak memory 214544 kb
Host smart-deb48e69-b306-4a2e-bc7a-0ad7c89768cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007968692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3007968692
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2822173525
Short name T109
Test name
Test status
Simulation time 708832292 ps
CPU time 4.81 seconds
Started Aug 07 04:49:25 PM PDT 24
Finished Aug 07 04:49:30 PM PDT 24
Peak memory 214608 kb
Host smart-aaac89cc-9cdd-4221-974b-706b4c8d4030
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822173525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2822173525
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2467151177
Short name T60
Test name
Test status
Simulation time 803011774 ps
CPU time 22.91 seconds
Started Aug 07 06:18:45 PM PDT 24
Finished Aug 07 06:19:08 PM PDT 24
Peak memory 222672 kb
Host smart-3aca62fe-537c-4e84-84a7-a08d100b58a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467151177 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2467151177
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.520794207
Short name T121
Test name
Test status
Simulation time 2404163460 ps
CPU time 31.39 seconds
Started Aug 07 06:18:06 PM PDT 24
Finished Aug 07 06:18:38 PM PDT 24
Peak memory 215768 kb
Host smart-78f0a8c9-60d5-41f4-89af-e2c35447065a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520794207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.520794207
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2408828811
Short name T113
Test name
Test status
Simulation time 482980632 ps
CPU time 5.69 seconds
Started Aug 07 06:16:56 PM PDT 24
Finished Aug 07 06:17:02 PM PDT 24
Peak memory 214328 kb
Host smart-62dc51df-b813-4006-b138-68b690887841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2408828811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2408828811
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.4096147840
Short name T4
Test name
Test status
Simulation time 229044243 ps
CPU time 4.83 seconds
Started Aug 07 06:18:44 PM PDT 24
Finished Aug 07 06:18:49 PM PDT 24
Peak memory 214696 kb
Host smart-e352136c-8e89-4feb-acc0-d92fc7e66e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096147840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.4096147840
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1161425286
Short name T391
Test name
Test status
Simulation time 266763018 ps
CPU time 7.62 seconds
Started Aug 07 06:19:26 PM PDT 24
Finished Aug 07 06:19:34 PM PDT 24
Peak memory 214328 kb
Host smart-45eb93b9-f342-496b-8a23-f5b67255c806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1161425286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1161425286
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1374460703
Short name T178
Test name
Test status
Simulation time 28129731149 ps
CPU time 56.81 seconds
Started Aug 07 06:18:56 PM PDT 24
Finished Aug 07 06:19:53 PM PDT 24
Peak memory 222484 kb
Host smart-52171874-d1c1-4cbd-9248-866cb88fd7f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374460703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1374460703
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2506388463
Short name T145
Test name
Test status
Simulation time 1351777841 ps
CPU time 7.57 seconds
Started Aug 07 04:49:22 PM PDT 24
Finished Aug 07 04:49:30 PM PDT 24
Peak memory 214276 kb
Host smart-2762c03f-6fe7-4464-9714-3af3993c37cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506388463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2506388463
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2754518276
Short name T314
Test name
Test status
Simulation time 1003158451 ps
CPU time 7.15 seconds
Started Aug 07 06:17:24 PM PDT 24
Finished Aug 07 06:17:32 PM PDT 24
Peak memory 215192 kb
Host smart-2b37eee5-859f-41cb-8ab0-d09f05ccf862
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754518276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2754518276
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.218055335
Short name T115
Test name
Test status
Simulation time 608658316 ps
CPU time 3.06 seconds
Started Aug 07 04:48:49 PM PDT 24
Finished Aug 07 04:48:53 PM PDT 24
Peak memory 214604 kb
Host smart-bb0ccd28-f581-4ea8-a4de-64ea7d57833d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218055335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.218055335
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2118534247
Short name T61
Test name
Test status
Simulation time 202923817 ps
CPU time 3.46 seconds
Started Aug 07 06:17:59 PM PDT 24
Finished Aug 07 06:18:03 PM PDT 24
Peak memory 219164 kb
Host smart-a9cf692b-187f-482a-a10d-03cb05a6efc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118534247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2118534247
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.194441837
Short name T99
Test name
Test status
Simulation time 2294823382 ps
CPU time 20.09 seconds
Started Aug 07 06:18:37 PM PDT 24
Finished Aug 07 06:18:57 PM PDT 24
Peak memory 216704 kb
Host smart-5983a9b2-de22-4550-be10-481cd6afc118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194441837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.194441837
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.604290522
Short name T356
Test name
Test status
Simulation time 182927567 ps
CPU time 9.79 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:10 PM PDT 24
Peak memory 215908 kb
Host smart-54e2ce31-f7ef-4884-8442-ea53425ad5ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604290522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.604290522
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3970369279
Short name T26
Test name
Test status
Simulation time 199728767 ps
CPU time 6.01 seconds
Started Aug 07 06:18:41 PM PDT 24
Finished Aug 07 06:18:47 PM PDT 24
Peak memory 214384 kb
Host smart-90864a65-496c-4d36-9287-4412193d0b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970369279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3970369279
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3726530234
Short name T37
Test name
Test status
Simulation time 120356420 ps
CPU time 5.29 seconds
Started Aug 07 06:18:20 PM PDT 24
Finished Aug 07 06:18:26 PM PDT 24
Peak memory 218384 kb
Host smart-a68626f6-4250-4c98-9037-8d90890cb3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726530234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3726530234
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.351376774
Short name T737
Test name
Test status
Simulation time 55210341 ps
CPU time 2.68 seconds
Started Aug 07 06:18:39 PM PDT 24
Finished Aug 07 06:18:41 PM PDT 24
Peak memory 210332 kb
Host smart-61362270-c037-407c-919f-e075eff06382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351376774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.351376774
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.4015286491
Short name T137
Test name
Test status
Simulation time 73647347 ps
CPU time 2.97 seconds
Started Aug 07 06:17:34 PM PDT 24
Finished Aug 07 06:17:37 PM PDT 24
Peak memory 217872 kb
Host smart-d9f1ced7-84f6-4b18-bfa0-de826b4df490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015286491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.4015286491
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.415095572
Short name T313
Test name
Test status
Simulation time 446064423 ps
CPU time 7.13 seconds
Started Aug 07 06:19:04 PM PDT 24
Finished Aug 07 06:19:12 PM PDT 24
Peak memory 222316 kb
Host smart-2c4a56bd-4d43-4238-b0f0-d9df4e7c5629
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415095572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.415095572
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.796121434
Short name T630
Test name
Test status
Simulation time 171441091 ps
CPU time 3.86 seconds
Started Aug 07 06:18:46 PM PDT 24
Finished Aug 07 06:18:50 PM PDT 24
Peak memory 214352 kb
Host smart-b1c85136-bd5d-4b33-8f42-73c37797e24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796121434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.796121434
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1596668328
Short name T49
Test name
Test status
Simulation time 9686694301 ps
CPU time 225.68 seconds
Started Aug 07 06:19:23 PM PDT 24
Finished Aug 07 06:23:09 PM PDT 24
Peak memory 216784 kb
Host smart-c22cee16-2cf7-43b2-a96f-14c810e30fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596668328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1596668328
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1071469217
Short name T122
Test name
Test status
Simulation time 94780923 ps
CPU time 5.35 seconds
Started Aug 07 06:18:50 PM PDT 24
Finished Aug 07 06:18:55 PM PDT 24
Peak memory 214336 kb
Host smart-c1b2abc9-92ee-465c-a4fc-25afc172b460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1071469217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1071469217
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1216617740
Short name T98
Test name
Test status
Simulation time 502803791 ps
CPU time 13.71 seconds
Started Aug 07 06:19:12 PM PDT 24
Finished Aug 07 06:19:25 PM PDT 24
Peak memory 215168 kb
Host smart-007f7157-1866-4f61-8e96-da6d7f5c0883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216617740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1216617740
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1896336614
Short name T214
Test name
Test status
Simulation time 684491754 ps
CPU time 33.77 seconds
Started Aug 07 06:19:29 PM PDT 24
Finished Aug 07 06:20:03 PM PDT 24
Peak memory 222408 kb
Host smart-eabe8b15-0ff6-4c39-a1a4-02def5f3fdf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896336614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1896336614
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2948148116
Short name T400
Test name
Test status
Simulation time 67861300 ps
CPU time 0.84 seconds
Started Aug 07 06:17:50 PM PDT 24
Finished Aug 07 06:17:50 PM PDT 24
Peak memory 205956 kb
Host smart-03a025b4-6290-4039-84b9-822c5038f4de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948148116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2948148116
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.4196448756
Short name T205
Test name
Test status
Simulation time 134635455811 ps
CPU time 443.57 seconds
Started Aug 07 06:19:31 PM PDT 24
Finished Aug 07 06:26:55 PM PDT 24
Peak memory 222668 kb
Host smart-d3cf3639-e04c-45f7-bc85-b7f2e748a7bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196448756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.4196448756
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1149155904
Short name T277
Test name
Test status
Simulation time 167941720 ps
CPU time 9.04 seconds
Started Aug 07 06:19:14 PM PDT 24
Finished Aug 07 06:19:23 PM PDT 24
Peak memory 215116 kb
Host smart-89c1ac27-8533-41db-98ed-2bfebb89a618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149155904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1149155904
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.602769711
Short name T254
Test name
Test status
Simulation time 54768769 ps
CPU time 3.8 seconds
Started Aug 07 06:18:45 PM PDT 24
Finished Aug 07 06:18:49 PM PDT 24
Peak memory 215264 kb
Host smart-33832e52-9da8-4bff-b68e-5b035e0e8c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=602769711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.602769711
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.631250740
Short name T91
Test name
Test status
Simulation time 1586772573 ps
CPU time 3.94 seconds
Started Aug 07 06:17:24 PM PDT 24
Finished Aug 07 06:17:28 PM PDT 24
Peak memory 222452 kb
Host smart-b3a429bb-3c53-4335-94f2-3af83e2771a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631250740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.631250740
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.739560029
Short name T151
Test name
Test status
Simulation time 904979934 ps
CPU time 6.56 seconds
Started Aug 07 04:49:24 PM PDT 24
Finished Aug 07 04:49:30 PM PDT 24
Peak memory 214204 kb
Host smart-6c742c9b-9234-41cd-9ccd-9a36dee2af19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739560029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
739560029
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2290841470
Short name T89
Test name
Test status
Simulation time 81414514 ps
CPU time 3.78 seconds
Started Aug 07 06:18:04 PM PDT 24
Finished Aug 07 06:18:08 PM PDT 24
Peak memory 214320 kb
Host smart-4aa4aad7-69db-425a-82ce-f0ddc405dea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290841470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2290841470
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2604156673
Short name T42
Test name
Test status
Simulation time 834376674 ps
CPU time 16.27 seconds
Started Aug 07 06:17:28 PM PDT 24
Finished Aug 07 06:17:45 PM PDT 24
Peak memory 215648 kb
Host smart-61330077-ae2b-4652-9995-e0a78951134c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604156673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2604156673
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.988582682
Short name T229
Test name
Test status
Simulation time 448025905 ps
CPU time 6.48 seconds
Started Aug 07 06:17:24 PM PDT 24
Finished Aug 07 06:17:31 PM PDT 24
Peak memory 214268 kb
Host smart-07b18d9f-4bfe-47e3-adcd-8396cda71eae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988582682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.988582682
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2978931571
Short name T392
Test name
Test status
Simulation time 1458656301 ps
CPU time 76.73 seconds
Started Aug 07 06:17:37 PM PDT 24
Finished Aug 07 06:18:54 PM PDT 24
Peak memory 214988 kb
Host smart-580edefb-b8fa-4320-8af3-2075e1bf7b5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978931571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2978931571
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2104899916
Short name T140
Test name
Test status
Simulation time 75877768 ps
CPU time 2.54 seconds
Started Aug 07 06:17:20 PM PDT 24
Finished Aug 07 06:17:22 PM PDT 24
Peak memory 218132 kb
Host smart-77e60c89-109c-439b-9cba-6fe8cce9a81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104899916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2104899916
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.539040219
Short name T141
Test name
Test status
Simulation time 903325098 ps
CPU time 6.38 seconds
Started Aug 07 06:18:30 PM PDT 24
Finished Aug 07 06:18:37 PM PDT 24
Peak memory 218464 kb
Host smart-3d0b3ac8-a167-4a24-ad99-16b41128ed1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539040219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.539040219
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1458950582
Short name T139
Test name
Test status
Simulation time 203131254 ps
CPU time 5.48 seconds
Started Aug 07 06:17:35 PM PDT 24
Finished Aug 07 06:17:41 PM PDT 24
Peak memory 222800 kb
Host smart-c1ade64d-367c-4509-af94-b80215dc0989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458950582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1458950582
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.99404959
Short name T155
Test name
Test status
Simulation time 490641884 ps
CPU time 9.62 seconds
Started Aug 07 04:49:17 PM PDT 24
Finished Aug 07 04:49:27 PM PDT 24
Peak memory 216852 kb
Host smart-b1ba2252-6bbf-4f70-bb2f-09fde5a7ff08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99404959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.99404959
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3510091709
Short name T23
Test name
Test status
Simulation time 122528164 ps
CPU time 3.73 seconds
Started Aug 07 06:16:54 PM PDT 24
Finished Aug 07 06:16:57 PM PDT 24
Peak memory 214260 kb
Host smart-a9c24811-9e89-4884-b117-d7e6a5326061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510091709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3510091709
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3273996182
Short name T272
Test name
Test status
Simulation time 469066149 ps
CPU time 5.31 seconds
Started Aug 07 06:17:42 PM PDT 24
Finished Aug 07 06:17:47 PM PDT 24
Peak memory 222440 kb
Host smart-a19b3271-c389-49ad-afec-d0cd4b1a21bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273996182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3273996182
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.4235326774
Short name T300
Test name
Test status
Simulation time 6409548249 ps
CPU time 81.04 seconds
Started Aug 07 06:17:06 PM PDT 24
Finished Aug 07 06:18:27 PM PDT 24
Peak memory 216088 kb
Host smart-ed0da6a7-cd47-4a1e-b7e4-1ba6618b11f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235326774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.4235326774
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.173172218
Short name T46
Test name
Test status
Simulation time 106153203 ps
CPU time 1.99 seconds
Started Aug 07 06:18:21 PM PDT 24
Finished Aug 07 06:18:23 PM PDT 24
Peak memory 214508 kb
Host smart-21f7e964-9f0b-4a7f-b6c8-51592173fee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173172218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.173172218
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3463768375
Short name T379
Test name
Test status
Simulation time 78022747 ps
CPU time 2.46 seconds
Started Aug 07 06:19:12 PM PDT 24
Finished Aug 07 06:19:15 PM PDT 24
Peak memory 209892 kb
Host smart-6ce8a4a9-a7f5-4a26-819d-9720a6fc15cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463768375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3463768375
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2078822491
Short name T138
Test name
Test status
Simulation time 114826002 ps
CPU time 4.83 seconds
Started Aug 07 06:17:05 PM PDT 24
Finished Aug 07 06:17:10 PM PDT 24
Peak memory 217808 kb
Host smart-9abf8c09-0d53-4bf9-b1e4-9691559599f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078822491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2078822491
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3911261588
Short name T87
Test name
Test status
Simulation time 46328335 ps
CPU time 3.27 seconds
Started Aug 07 06:17:39 PM PDT 24
Finished Aug 07 06:17:42 PM PDT 24
Peak memory 222516 kb
Host smart-b9a037b2-cbf1-49b0-ada0-9239974296ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911261588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3911261588
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4099988060
Short name T146
Test name
Test status
Simulation time 1016768778 ps
CPU time 7.02 seconds
Started Aug 07 04:49:08 PM PDT 24
Finished Aug 07 04:49:15 PM PDT 24
Peak memory 206104 kb
Host smart-b4095da4-878e-47c9-b25d-56c41bb2b2f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099988060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4099988060
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1082830050
Short name T34
Test name
Test status
Simulation time 509688106 ps
CPU time 3.39 seconds
Started Aug 07 06:18:21 PM PDT 24
Finished Aug 07 06:18:24 PM PDT 24
Peak memory 222140 kb
Host smart-a53e741b-4ff9-4203-a6f7-48de5c783347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082830050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1082830050
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3441317537
Short name T143
Test name
Test status
Simulation time 319105364 ps
CPU time 2.08 seconds
Started Aug 07 06:16:58 PM PDT 24
Finished Aug 07 06:17:00 PM PDT 24
Peak memory 217320 kb
Host smart-9abb885a-4b6c-4519-b598-1721e2bdf222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441317537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3441317537
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.4199673051
Short name T839
Test name
Test status
Simulation time 65838144717 ps
CPU time 279.98 seconds
Started Aug 07 06:17:47 PM PDT 24
Finished Aug 07 06:22:27 PM PDT 24
Peak memory 222484 kb
Host smart-f670fca8-de41-4406-a56f-23aec0b4eb42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199673051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.4199673051
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2108545805
Short name T487
Test name
Test status
Simulation time 192838078 ps
CPU time 2.98 seconds
Started Aug 07 06:17:48 PM PDT 24
Finished Aug 07 06:17:51 PM PDT 24
Peak memory 208680 kb
Host smart-92116bf5-dd3b-4e29-8972-02c8752a54c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108545805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2108545805
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2423783978
Short name T247
Test name
Test status
Simulation time 119170322 ps
CPU time 4.07 seconds
Started Aug 07 06:17:57 PM PDT 24
Finished Aug 07 06:18:01 PM PDT 24
Peak memory 221696 kb
Host smart-09929393-771f-4d3d-9d72-53691aa46fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423783978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2423783978
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.308137546
Short name T36
Test name
Test status
Simulation time 94197213 ps
CPU time 3.07 seconds
Started Aug 07 06:18:20 PM PDT 24
Finished Aug 07 06:18:23 PM PDT 24
Peak memory 214264 kb
Host smart-02097f7e-812e-4e78-bf54-f44f9d2d1f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308137546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.308137546
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.58139548
Short name T54
Test name
Test status
Simulation time 2360380028 ps
CPU time 60.12 seconds
Started Aug 07 06:18:29 PM PDT 24
Finished Aug 07 06:19:30 PM PDT 24
Peak memory 222492 kb
Host smart-abb8ec51-9706-418a-8e19-e1e4f5e1f36e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58139548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.58139548
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1785703925
Short name T366
Test name
Test status
Simulation time 418094960 ps
CPU time 3.03 seconds
Started Aug 07 06:19:47 PM PDT 24
Finished Aug 07 06:19:50 PM PDT 24
Peak memory 214288 kb
Host smart-60ce405e-b0a0-45c1-8cba-e3d79805bbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785703925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1785703925
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.196348059
Short name T159
Test name
Test status
Simulation time 125152217 ps
CPU time 5.57 seconds
Started Aug 07 04:48:48 PM PDT 24
Finished Aug 07 04:48:54 PM PDT 24
Peak memory 215588 kb
Host smart-68d2a102-c554-4f60-a363-4e9e53f3adb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196348059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
196348059
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3714289944
Short name T147
Test name
Test status
Simulation time 474902848 ps
CPU time 4.37 seconds
Started Aug 07 06:17:18 PM PDT 24
Finished Aug 07 06:17:22 PM PDT 24
Peak memory 209952 kb
Host smart-f2d0e4db-720e-413a-9d5a-746a5c6a3fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714289944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3714289944
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2045756193
Short name T181
Test name
Test status
Simulation time 413053263 ps
CPU time 3.83 seconds
Started Aug 07 06:16:55 PM PDT 24
Finished Aug 07 06:16:59 PM PDT 24
Peak memory 208860 kb
Host smart-1020a448-7c16-4cdd-bce4-2d5bf59a56a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045756193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2045756193
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2783131034
Short name T276
Test name
Test status
Simulation time 840004421 ps
CPU time 10.18 seconds
Started Aug 07 06:17:00 PM PDT 24
Finished Aug 07 06:17:11 PM PDT 24
Peak memory 215180 kb
Host smart-05b17d08-e93f-441c-bd2d-ae89de4c420f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2783131034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2783131034
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1055959448
Short name T883
Test name
Test status
Simulation time 4480732648 ps
CPU time 30.68 seconds
Started Aug 07 06:18:05 PM PDT 24
Finished Aug 07 06:18:36 PM PDT 24
Peak memory 222588 kb
Host smart-60540f87-47b8-4098-b26e-11b2289cfe8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055959448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1055959448
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1755669945
Short name T452
Test name
Test status
Simulation time 110581361 ps
CPU time 5.91 seconds
Started Aug 07 06:18:07 PM PDT 24
Finished Aug 07 06:18:14 PM PDT 24
Peak memory 215192 kb
Host smart-ef2ac890-7510-40bb-be0a-f1fc303a1525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755669945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1755669945
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1683750828
Short name T358
Test name
Test status
Simulation time 573840305 ps
CPU time 15.92 seconds
Started Aug 07 06:17:07 PM PDT 24
Finished Aug 07 06:17:23 PM PDT 24
Peak memory 222492 kb
Host smart-ddf30a20-c172-4c2d-9824-8b9410b60267
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683750828 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1683750828
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1406756059
Short name T397
Test name
Test status
Simulation time 44200703 ps
CPU time 3.24 seconds
Started Aug 07 06:18:11 PM PDT 24
Finished Aug 07 06:18:14 PM PDT 24
Peak memory 214628 kb
Host smart-08725d0e-11b6-457e-93fe-1bc3e80b6aea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406756059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1406756059
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.818819206
Short name T282
Test name
Test status
Simulation time 851917320 ps
CPU time 9.97 seconds
Started Aug 07 06:18:14 PM PDT 24
Finished Aug 07 06:18:25 PM PDT 24
Peak memory 221964 kb
Host smart-3e82aefd-0c4b-49a5-b3ce-526fd304dead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818819206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.818819206
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.391024928
Short name T395
Test name
Test status
Simulation time 4980049373 ps
CPU time 76.65 seconds
Started Aug 07 06:18:44 PM PDT 24
Finished Aug 07 06:20:01 PM PDT 24
Peak memory 215372 kb
Host smart-b3776b57-1417-4f1e-b803-9a90fd0fe8fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391024928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.391024928
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3719453771
Short name T351
Test name
Test status
Simulation time 2618733108 ps
CPU time 5.45 seconds
Started Aug 07 06:19:12 PM PDT 24
Finished Aug 07 06:19:17 PM PDT 24
Peak memory 209640 kb
Host smart-63264c67-0df2-4239-ab98-03282541389d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719453771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3719453771
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1941215715
Short name T305
Test name
Test status
Simulation time 323428885 ps
CPU time 4.11 seconds
Started Aug 07 06:19:20 PM PDT 24
Finished Aug 07 06:19:25 PM PDT 24
Peak memory 222416 kb
Host smart-dc18e563-144e-4691-9f32-5e1907ce18ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941215715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1941215715
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.719238898
Short name T166
Test name
Test status
Simulation time 78316886 ps
CPU time 2.51 seconds
Started Aug 07 04:49:54 PM PDT 24
Finished Aug 07 04:49:56 PM PDT 24
Peak memory 214284 kb
Host smart-bfd2b294-6582-40de-a08e-3c4d835017ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719238898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.719238898
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3951415061
Short name T164
Test name
Test status
Simulation time 337944843 ps
CPU time 4.49 seconds
Started Aug 07 04:49:02 PM PDT 24
Finished Aug 07 04:49:06 PM PDT 24
Peak memory 214300 kb
Host smart-88bc4d3b-cbc8-4739-96f8-f1429b774b06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951415061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3951415061
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.283507516
Short name T154
Test name
Test status
Simulation time 545654593 ps
CPU time 9.4 seconds
Started Aug 07 04:49:01 PM PDT 24
Finished Aug 07 04:49:11 PM PDT 24
Peak memory 214204 kb
Host smart-5afdbf98-25da-42e6-8ab3-8be53456cb78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283507516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.283507516
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3708526327
Short name T160
Test name
Test status
Simulation time 393328481 ps
CPU time 6.12 seconds
Started Aug 07 04:49:25 PM PDT 24
Finished Aug 07 04:49:31 PM PDT 24
Peak memory 215560 kb
Host smart-c90faccd-401b-4c6c-8dc2-0a1561bfd941
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708526327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3708526327
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2322805182
Short name T162
Test name
Test status
Simulation time 54449952 ps
CPU time 1.31 seconds
Started Aug 07 06:18:50 PM PDT 24
Finished Aug 07 06:18:51 PM PDT 24
Peak memory 209908 kb
Host smart-cb621ab7-0ab7-47cb-b2be-1043674d6d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322805182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2322805182
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3401480354
Short name T41
Test name
Test status
Simulation time 229541484 ps
CPU time 5.34 seconds
Started Aug 07 06:17:16 PM PDT 24
Finished Aug 07 06:17:21 PM PDT 24
Peak memory 233632 kb
Host smart-062d10b7-8ef0-4308-a9ef-c7a7d2f02231
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401480354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3401480354
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.598757841
Short name T142
Test name
Test status
Simulation time 79507705 ps
CPU time 3.63 seconds
Started Aug 07 06:19:23 PM PDT 24
Finished Aug 07 06:19:27 PM PDT 24
Peak memory 222604 kb
Host smart-f77ec1ac-5095-476f-8de8-3a08bec22154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598757841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.598757841
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1821013989
Short name T674
Test name
Test status
Simulation time 323452763 ps
CPU time 2.63 seconds
Started Aug 07 06:17:08 PM PDT 24
Finished Aug 07 06:17:10 PM PDT 24
Peak memory 222408 kb
Host smart-d3ac0ba0-d1aa-48a0-9751-cdf94dab4b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821013989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1821013989
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2322162891
Short name T78
Test name
Test status
Simulation time 449179844 ps
CPU time 4.24 seconds
Started Aug 07 06:17:02 PM PDT 24
Finished Aug 07 06:17:07 PM PDT 24
Peak memory 208248 kb
Host smart-9efedd09-5b9e-49b7-aa46-0edee6a88d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322162891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2322162891
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1201321580
Short name T211
Test name
Test status
Simulation time 89655020 ps
CPU time 3.88 seconds
Started Aug 07 06:17:42 PM PDT 24
Finished Aug 07 06:17:46 PM PDT 24
Peak memory 209536 kb
Host smart-c9c6e2fb-a8e0-4b68-a1a6-15e0494d8463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201321580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1201321580
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2412776154
Short name T873
Test name
Test status
Simulation time 162679586 ps
CPU time 2.7 seconds
Started Aug 07 06:18:10 PM PDT 24
Finished Aug 07 06:18:13 PM PDT 24
Peak memory 210168 kb
Host smart-8add5891-61f2-4b96-87a2-75ec3afd9659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412776154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2412776154
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3479009167
Short name T38
Test name
Test status
Simulation time 110417901 ps
CPU time 2.53 seconds
Started Aug 07 06:18:17 PM PDT 24
Finished Aug 07 06:18:20 PM PDT 24
Peak memory 209596 kb
Host smart-1fe4677e-2ebb-4f5c-a673-5e1746753e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479009167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3479009167
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.278820495
Short name T208
Test name
Test status
Simulation time 89964811 ps
CPU time 2.24 seconds
Started Aug 07 06:18:18 PM PDT 24
Finished Aug 07 06:18:20 PM PDT 24
Peak memory 219388 kb
Host smart-0bcc2043-3872-4e03-b31a-38cd9f8acdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278820495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.278820495
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2870906811
Short name T10
Test name
Test status
Simulation time 2408805149 ps
CPU time 38.56 seconds
Started Aug 07 06:18:28 PM PDT 24
Finished Aug 07 06:19:07 PM PDT 24
Peak memory 222664 kb
Host smart-5fbea55f-0ad8-4c78-8a26-f3b5ebccd695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870906811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2870906811
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1651523073
Short name T242
Test name
Test status
Simulation time 649453184 ps
CPU time 9.33 seconds
Started Aug 07 06:18:31 PM PDT 24
Finished Aug 07 06:18:41 PM PDT 24
Peak memory 214640 kb
Host smart-fc9bee73-d228-4b23-bff3-5b6c6122dd14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651523073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1651523073
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2230623340
Short name T216
Test name
Test status
Simulation time 59161166 ps
CPU time 2.82 seconds
Started Aug 07 06:18:39 PM PDT 24
Finished Aug 07 06:18:42 PM PDT 24
Peak memory 220340 kb
Host smart-2b547d0d-0a02-4795-bfae-15ed1bbbeeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230623340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2230623340
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1411538780
Short name T289
Test name
Test status
Simulation time 103204253 ps
CPU time 3.9 seconds
Started Aug 07 06:18:49 PM PDT 24
Finished Aug 07 06:18:53 PM PDT 24
Peak memory 215140 kb
Host smart-913c7e6c-56a0-4b1a-bc9d-46b3ada857c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411538780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1411538780
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3045194353
Short name T335
Test name
Test status
Simulation time 129625949 ps
CPU time 7.18 seconds
Started Aug 07 06:18:55 PM PDT 24
Finished Aug 07 06:19:02 PM PDT 24
Peak memory 214968 kb
Host smart-362edb87-b08f-4bd1-a8ea-cbdc35c8b126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045194353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3045194353
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.668257283
Short name T347
Test name
Test status
Simulation time 123852310 ps
CPU time 2.45 seconds
Started Aug 07 06:19:25 PM PDT 24
Finished Aug 07 06:19:28 PM PDT 24
Peak memory 214336 kb
Host smart-27febb10-d6fd-4b49-a2ee-6455bde00cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668257283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.668257283
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.197983437
Short name T1032
Test name
Test status
Simulation time 69351423 ps
CPU time 4.12 seconds
Started Aug 07 04:49:05 PM PDT 24
Finished Aug 07 04:49:09 PM PDT 24
Peak memory 206104 kb
Host smart-9a28f5d6-dfdc-4f95-b062-d34f8b32dd63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197983437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.197983437
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.4260987767
Short name T923
Test name
Test status
Simulation time 1048898869 ps
CPU time 11.65 seconds
Started Aug 07 04:48:41 PM PDT 24
Finished Aug 07 04:48:53 PM PDT 24
Peak memory 206176 kb
Host smart-e9e21ecc-970a-4d43-8fc7-9eb214998eb2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260987767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.4
260987767
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.122867491
Short name T918
Test name
Test status
Simulation time 46909556 ps
CPU time 1.56 seconds
Started Aug 07 04:49:00 PM PDT 24
Finished Aug 07 04:49:02 PM PDT 24
Peak memory 206076 kb
Host smart-b88fcdef-7133-4891-b7c4-3b641997d0b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122867491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.122867491
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3386951485
Short name T1055
Test name
Test status
Simulation time 34475291 ps
CPU time 1.34 seconds
Started Aug 07 04:49:12 PM PDT 24
Finished Aug 07 04:49:13 PM PDT 24
Peak memory 214348 kb
Host smart-2110524f-c2ff-4c21-93b3-b1ece7f2f1f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386951485 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3386951485
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4247029212
Short name T1030
Test name
Test status
Simulation time 132341909 ps
CPU time 1.34 seconds
Started Aug 07 04:48:54 PM PDT 24
Finished Aug 07 04:48:56 PM PDT 24
Peak memory 206096 kb
Host smart-da9cf727-a051-4d3b-a00e-a3a58a161de2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247029212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.4247029212
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.68033095
Short name T1053
Test name
Test status
Simulation time 65169009 ps
CPU time 0.8 seconds
Started Aug 07 04:48:43 PM PDT 24
Finished Aug 07 04:48:44 PM PDT 24
Peak memory 205852 kb
Host smart-30daf851-0629-4bd7-a4ff-66d2847c33b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68033095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.68033095
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2136491111
Short name T953
Test name
Test status
Simulation time 113169313 ps
CPU time 3.31 seconds
Started Aug 07 04:48:46 PM PDT 24
Finished Aug 07 04:48:50 PM PDT 24
Peak memory 206048 kb
Host smart-9a8e1405-eade-446e-a9a4-8683ca182588
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136491111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2136491111
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3277823378
Short name T950
Test name
Test status
Simulation time 211703242 ps
CPU time 2.35 seconds
Started Aug 07 04:48:53 PM PDT 24
Finished Aug 07 04:48:56 PM PDT 24
Peak memory 214724 kb
Host smart-62386b8f-f203-4400-a58f-f8249fc1f590
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277823378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3277823378
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.394362178
Short name T936
Test name
Test status
Simulation time 86726932 ps
CPU time 3.44 seconds
Started Aug 07 04:48:42 PM PDT 24
Finished Aug 07 04:48:46 PM PDT 24
Peak memory 220500 kb
Host smart-23b9ea97-1610-4eb8-964e-3abe0bac9b19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394362178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.394362178
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.70049990
Short name T978
Test name
Test status
Simulation time 103654835 ps
CPU time 3.45 seconds
Started Aug 07 04:48:50 PM PDT 24
Finished Aug 07 04:48:53 PM PDT 24
Peak memory 216432 kb
Host smart-2f425964-fd3a-4d45-ae4f-b7c23b89c805
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70049990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.70049990
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1965223095
Short name T946
Test name
Test status
Simulation time 159715897 ps
CPU time 4.13 seconds
Started Aug 07 04:48:44 PM PDT 24
Finished Aug 07 04:48:49 PM PDT 24
Peak memory 214216 kb
Host smart-8234b96a-d319-454e-b649-0b8705fbf8c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965223095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1965223095
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.942506728
Short name T1007
Test name
Test status
Simulation time 538898731 ps
CPU time 5.2 seconds
Started Aug 07 04:49:08 PM PDT 24
Finished Aug 07 04:49:14 PM PDT 24
Peak memory 206172 kb
Host smart-235559bb-f1ca-4865-a51e-aced1d18a008
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942506728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.942506728
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.932235856
Short name T915
Test name
Test status
Simulation time 4287905371 ps
CPU time 11.43 seconds
Started Aug 07 04:48:52 PM PDT 24
Finished Aug 07 04:49:03 PM PDT 24
Peak memory 206240 kb
Host smart-c8430723-7839-4112-b18e-e0ba310252c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932235856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.932235856
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.592904533
Short name T1071
Test name
Test status
Simulation time 104232216 ps
CPU time 1.1 seconds
Started Aug 07 04:48:46 PM PDT 24
Finished Aug 07 04:48:47 PM PDT 24
Peak memory 206048 kb
Host smart-349d5a88-d89c-4778-b47c-e3adb449bae2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592904533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.592904533
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.470779775
Short name T1010
Test name
Test status
Simulation time 34083277 ps
CPU time 1.14 seconds
Started Aug 07 04:48:48 PM PDT 24
Finished Aug 07 04:48:49 PM PDT 24
Peak memory 206024 kb
Host smart-c8b9793f-51bb-45da-bf26-ada9620c7874
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470779775 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.470779775
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1267601267
Short name T133
Test name
Test status
Simulation time 67878927 ps
CPU time 1.22 seconds
Started Aug 07 04:48:51 PM PDT 24
Finished Aug 07 04:48:52 PM PDT 24
Peak memory 206112 kb
Host smart-885a1ff2-5c66-445c-a0dd-46d9c3860678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267601267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1267601267
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1311354433
Short name T963
Test name
Test status
Simulation time 37925955 ps
CPU time 0.74 seconds
Started Aug 07 04:48:47 PM PDT 24
Finished Aug 07 04:48:48 PM PDT 24
Peak memory 205900 kb
Host smart-56581d49-baf0-410f-ad15-d1ab0e39241d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311354433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1311354433
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.724912936
Short name T1051
Test name
Test status
Simulation time 629767405 ps
CPU time 2.31 seconds
Started Aug 07 04:49:10 PM PDT 24
Finished Aug 07 04:49:12 PM PDT 24
Peak memory 206140 kb
Host smart-90638b72-334d-4695-9be1-4ba75d911de5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724912936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.724912936
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4005386780
Short name T968
Test name
Test status
Simulation time 210724868 ps
CPU time 1.72 seconds
Started Aug 07 04:48:59 PM PDT 24
Finished Aug 07 04:49:06 PM PDT 24
Peak memory 214764 kb
Host smart-460a83ce-2ddf-4898-8768-3525a97c2cbe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005386780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4005386780
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2536554918
Short name T1040
Test name
Test status
Simulation time 444434963 ps
CPU time 14.68 seconds
Started Aug 07 04:48:45 PM PDT 24
Finished Aug 07 04:49:00 PM PDT 24
Peak memory 214364 kb
Host smart-e2753ad9-0d68-449a-bcd8-aae5dea5edd0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536554918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2536554918
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4090558091
Short name T996
Test name
Test status
Simulation time 145878463 ps
CPU time 2.78 seconds
Started Aug 07 04:48:46 PM PDT 24
Finished Aug 07 04:48:49 PM PDT 24
Peak memory 214440 kb
Host smart-007672c9-4a9d-4060-aae9-5d0fab4f14d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090558091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4090558091
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1283708568
Short name T991
Test name
Test status
Simulation time 19586261 ps
CPU time 1.49 seconds
Started Aug 07 04:49:08 PM PDT 24
Finished Aug 07 04:49:10 PM PDT 24
Peak memory 214360 kb
Host smart-8dcb5efa-f7d7-4a0c-808f-aa10337aea5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283708568 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1283708568
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3596573002
Short name T132
Test name
Test status
Simulation time 20532084 ps
CPU time 0.91 seconds
Started Aug 07 04:48:55 PM PDT 24
Finished Aug 07 04:48:56 PM PDT 24
Peak memory 205916 kb
Host smart-95d07da8-943d-4cd3-a06f-f6781483d862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596573002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3596573002
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1063513199
Short name T1048
Test name
Test status
Simulation time 25080717 ps
CPU time 0.92 seconds
Started Aug 07 04:49:10 PM PDT 24
Finished Aug 07 04:49:11 PM PDT 24
Peak memory 205888 kb
Host smart-9d05d61a-66e2-4136-8e15-46ae2d971a13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063513199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1063513199
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.406642590
Short name T1067
Test name
Test status
Simulation time 140342017 ps
CPU time 1.48 seconds
Started Aug 07 04:49:05 PM PDT 24
Finished Aug 07 04:49:06 PM PDT 24
Peak memory 206136 kb
Host smart-797019bb-068d-4002-ab7d-e5fc86a5b885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406642590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.406642590
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.4195553724
Short name T969
Test name
Test status
Simulation time 414959303 ps
CPU time 14.53 seconds
Started Aug 07 04:49:12 PM PDT 24
Finished Aug 07 04:49:26 PM PDT 24
Peak memory 214648 kb
Host smart-db143e67-92ba-476c-9f12-6ba4ca8d7a68
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195553724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.4195553724
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.4170232332
Short name T1043
Test name
Test status
Simulation time 90101730 ps
CPU time 2.55 seconds
Started Aug 07 04:49:00 PM PDT 24
Finished Aug 07 04:49:03 PM PDT 24
Peak memory 217080 kb
Host smart-7637f8ab-c6c1-40c4-8d05-aed7e452cb74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170232332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.4170232332
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2608278130
Short name T999
Test name
Test status
Simulation time 78656366 ps
CPU time 2.63 seconds
Started Aug 07 04:49:08 PM PDT 24
Finished Aug 07 04:49:11 PM PDT 24
Peak memory 215672 kb
Host smart-64501604-9e3f-4725-bfd8-c8f08a9335e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608278130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2608278130
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2893526385
Short name T1060
Test name
Test status
Simulation time 102865255 ps
CPU time 1.81 seconds
Started Aug 07 04:49:22 PM PDT 24
Finished Aug 07 04:49:24 PM PDT 24
Peak memory 214380 kb
Host smart-18f77855-1718-481b-b413-b3120d831d84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893526385 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2893526385
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.918821647
Short name T982
Test name
Test status
Simulation time 132384184 ps
CPU time 1.6 seconds
Started Aug 07 04:49:35 PM PDT 24
Finished Aug 07 04:49:37 PM PDT 24
Peak memory 206304 kb
Host smart-6c332a86-03d5-4a8b-8289-fb5f63788e14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918821647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.918821647
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.4283833105
Short name T911
Test name
Test status
Simulation time 43871477 ps
CPU time 0.73 seconds
Started Aug 07 04:49:23 PM PDT 24
Finished Aug 07 04:49:28 PM PDT 24
Peak memory 205840 kb
Host smart-76fb42c5-ac12-47f2-b753-6aa8daf837f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283833105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.4283833105
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1137498685
Short name T1028
Test name
Test status
Simulation time 176172866 ps
CPU time 2.02 seconds
Started Aug 07 04:49:02 PM PDT 24
Finished Aug 07 04:49:04 PM PDT 24
Peak memory 205964 kb
Host smart-0fa41a24-9877-49d3-a464-8a3eafa79622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137498685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1137498685
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.641639928
Short name T974
Test name
Test status
Simulation time 705884883 ps
CPU time 4.65 seconds
Started Aug 07 04:49:02 PM PDT 24
Finished Aug 07 04:49:07 PM PDT 24
Peak memory 214608 kb
Host smart-ac391b80-31a6-435d-956b-fb93e547eed4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641639928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.641639928
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4023364471
Short name T1016
Test name
Test status
Simulation time 192722071 ps
CPU time 2.57 seconds
Started Aug 07 04:49:09 PM PDT 24
Finished Aug 07 04:49:12 PM PDT 24
Peak memory 214324 kb
Host smart-3e680eab-56c6-421c-b2ba-26648db7d821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023364471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.4023364471
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1897253288
Short name T961
Test name
Test status
Simulation time 40888739 ps
CPU time 1.52 seconds
Started Aug 07 04:49:24 PM PDT 24
Finished Aug 07 04:49:26 PM PDT 24
Peak memory 214468 kb
Host smart-5650f9dc-33f0-4340-9c39-a7bb912c3668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897253288 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1897253288
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2185224791
Short name T979
Test name
Test status
Simulation time 80938741 ps
CPU time 1.32 seconds
Started Aug 07 04:49:23 PM PDT 24
Finished Aug 07 04:49:24 PM PDT 24
Peak memory 206068 kb
Host smart-9c13409e-40a5-438d-847c-9fd20aa6133a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185224791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2185224791
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.716242823
Short name T960
Test name
Test status
Simulation time 15980291 ps
CPU time 0.89 seconds
Started Aug 07 04:49:01 PM PDT 24
Finished Aug 07 04:49:02 PM PDT 24
Peak memory 205852 kb
Host smart-a4cd0ac0-a1c1-4e16-84fe-0167616329bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716242823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.716242823
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2821764444
Short name T962
Test name
Test status
Simulation time 309232060 ps
CPU time 3.19 seconds
Started Aug 07 04:49:10 PM PDT 24
Finished Aug 07 04:49:13 PM PDT 24
Peak memory 206116 kb
Host smart-c1a26085-3a81-452f-ae6c-5784d2d38235
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821764444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2821764444
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3546361227
Short name T1047
Test name
Test status
Simulation time 431478062 ps
CPU time 1.76 seconds
Started Aug 07 04:49:07 PM PDT 24
Finished Aug 07 04:49:09 PM PDT 24
Peak memory 214612 kb
Host smart-c86d43aa-4f0a-4181-a5db-e629357668b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546361227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3546361227
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3309361887
Short name T964
Test name
Test status
Simulation time 114564354 ps
CPU time 4.75 seconds
Started Aug 07 04:49:13 PM PDT 24
Finished Aug 07 04:49:18 PM PDT 24
Peak memory 214592 kb
Host smart-e5e86cec-1b35-4bad-a057-55d805ea3960
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309361887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3309361887
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.310576620
Short name T955
Test name
Test status
Simulation time 51734917 ps
CPU time 1.7 seconds
Started Aug 07 04:49:10 PM PDT 24
Finished Aug 07 04:49:12 PM PDT 24
Peak memory 214308 kb
Host smart-1a6d958c-fd8f-4aee-89b6-e009029cc8d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310576620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.310576620
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1623117013
Short name T156
Test name
Test status
Simulation time 311854689 ps
CPU time 7.16 seconds
Started Aug 07 04:49:25 PM PDT 24
Finished Aug 07 04:49:32 PM PDT 24
Peak memory 214228 kb
Host smart-cf46fb87-a63f-4e08-9af3-b923c0510267
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623117013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1623117013
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.810198842
Short name T1072
Test name
Test status
Simulation time 88984398 ps
CPU time 1.33 seconds
Started Aug 07 04:49:07 PM PDT 24
Finished Aug 07 04:49:08 PM PDT 24
Peak memory 206108 kb
Host smart-4754ca2e-a08a-4c02-b49e-fbe988cc03a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810198842 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.810198842
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2580854242
Short name T956
Test name
Test status
Simulation time 13266828 ps
CPU time 1.14 seconds
Started Aug 07 04:49:06 PM PDT 24
Finished Aug 07 04:49:08 PM PDT 24
Peak memory 206164 kb
Host smart-68ebce90-5cde-43ba-9a2f-5894b573ccba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580854242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2580854242
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.286310093
Short name T1044
Test name
Test status
Simulation time 13929074 ps
CPU time 0.67 seconds
Started Aug 07 04:49:34 PM PDT 24
Finished Aug 07 04:49:35 PM PDT 24
Peak memory 205884 kb
Host smart-bdcbaa38-bd03-4502-9868-8c1c30cbb96c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286310093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.286310093
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4258989189
Short name T129
Test name
Test status
Simulation time 120175896 ps
CPU time 1.98 seconds
Started Aug 07 04:49:02 PM PDT 24
Finished Aug 07 04:49:04 PM PDT 24
Peak memory 206196 kb
Host smart-1fd11711-5569-4a20-aba6-fcbdba1f0d39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258989189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4258989189
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1805810696
Short name T1029
Test name
Test status
Simulation time 393927775 ps
CPU time 2.52 seconds
Started Aug 07 04:49:01 PM PDT 24
Finished Aug 07 04:49:03 PM PDT 24
Peak memory 214680 kb
Host smart-20958bfc-f0ea-4173-90b6-871a9ca29913
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805810696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1805810696
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.453569590
Short name T110
Test name
Test status
Simulation time 346995447 ps
CPU time 7.09 seconds
Started Aug 07 04:49:00 PM PDT 24
Finished Aug 07 04:49:07 PM PDT 24
Peak memory 214664 kb
Host smart-851e5c5d-1892-4d72-ac10-7d6c4bddef7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453569590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.453569590
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1887761673
Short name T1017
Test name
Test status
Simulation time 242393690 ps
CPU time 2.42 seconds
Started Aug 07 04:49:05 PM PDT 24
Finished Aug 07 04:49:08 PM PDT 24
Peak memory 216480 kb
Host smart-10bdb153-f273-437d-8731-0eab1f12eea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887761673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1887761673
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3196690388
Short name T1002
Test name
Test status
Simulation time 29717098 ps
CPU time 1.88 seconds
Started Aug 07 04:49:02 PM PDT 24
Finished Aug 07 04:49:04 PM PDT 24
Peak memory 214396 kb
Host smart-152a4cfd-335d-4c58-92f9-958533a4a7a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196690388 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3196690388
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3097448704
Short name T942
Test name
Test status
Simulation time 23006582 ps
CPU time 1.09 seconds
Started Aug 07 04:49:25 PM PDT 24
Finished Aug 07 04:49:27 PM PDT 24
Peak memory 206004 kb
Host smart-fd49c2c9-9e29-4d54-ab96-29502edd2104
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097448704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3097448704
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3805099182
Short name T998
Test name
Test status
Simulation time 12090149 ps
CPU time 0.72 seconds
Started Aug 07 04:49:22 PM PDT 24
Finished Aug 07 04:49:22 PM PDT 24
Peak memory 205884 kb
Host smart-3fc31d72-59b9-4cff-adfd-b42c7ce8191c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805099182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3805099182
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1273476467
Short name T990
Test name
Test status
Simulation time 139110836 ps
CPU time 2.39 seconds
Started Aug 07 04:49:14 PM PDT 24
Finished Aug 07 04:49:16 PM PDT 24
Peak memory 206100 kb
Host smart-f084d3c2-39dd-441b-995f-e33cc5a55adc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273476467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1273476467
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.689126928
Short name T951
Test name
Test status
Simulation time 110807294 ps
CPU time 3.81 seconds
Started Aug 07 04:49:10 PM PDT 24
Finished Aug 07 04:49:14 PM PDT 24
Peak memory 214768 kb
Host smart-0aef177a-d0a6-4ce1-9cb1-49375af4b129
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689126928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.689126928
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.289441399
Short name T1076
Test name
Test status
Simulation time 220884818 ps
CPU time 7.85 seconds
Started Aug 07 04:49:06 PM PDT 24
Finished Aug 07 04:49:14 PM PDT 24
Peak memory 214560 kb
Host smart-7f48851e-be17-4fab-9ee1-293f8cd0ff01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289441399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.289441399
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2186626331
Short name T1068
Test name
Test status
Simulation time 364780733 ps
CPU time 3.47 seconds
Started Aug 07 04:49:16 PM PDT 24
Finished Aug 07 04:49:19 PM PDT 24
Peak memory 214412 kb
Host smart-b30439fa-d6d0-4a4f-a766-ee27d3838c67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186626331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2186626331
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.690918263
Short name T1052
Test name
Test status
Simulation time 36496402 ps
CPU time 1.51 seconds
Started Aug 07 04:49:11 PM PDT 24
Finished Aug 07 04:49:12 PM PDT 24
Peak memory 214376 kb
Host smart-6b6c0ada-a80c-4e13-9507-fd58477966f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690918263 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.690918263
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2324828017
Short name T987
Test name
Test status
Simulation time 27993825 ps
CPU time 1.04 seconds
Started Aug 07 04:49:07 PM PDT 24
Finished Aug 07 04:49:08 PM PDT 24
Peak memory 206088 kb
Host smart-1c72fe6f-022e-4bb3-85d6-78a5250399e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324828017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2324828017
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2988247662
Short name T925
Test name
Test status
Simulation time 10271655 ps
CPU time 0.82 seconds
Started Aug 07 04:49:02 PM PDT 24
Finished Aug 07 04:49:03 PM PDT 24
Peak memory 205788 kb
Host smart-e3fc8e53-31ef-47dc-bc9c-45631e1233a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988247662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2988247662
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3023365644
Short name T1021
Test name
Test status
Simulation time 45496240 ps
CPU time 1.76 seconds
Started Aug 07 04:49:04 PM PDT 24
Finished Aug 07 04:49:06 PM PDT 24
Peak memory 206072 kb
Host smart-fb2c4a2e-4764-4673-be8b-c972a23b6c5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023365644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3023365644
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3254185312
Short name T1024
Test name
Test status
Simulation time 236735393 ps
CPU time 2.72 seconds
Started Aug 07 04:49:24 PM PDT 24
Finished Aug 07 04:49:27 PM PDT 24
Peak memory 214608 kb
Host smart-5fcfdb30-1654-4684-b5ac-ac9d099babae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254185312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3254185312
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.653692587
Short name T933
Test name
Test status
Simulation time 2410647978 ps
CPU time 7.97 seconds
Started Aug 07 04:49:10 PM PDT 24
Finished Aug 07 04:49:18 PM PDT 24
Peak memory 220464 kb
Host smart-f3dcc6bd-97d8-4ce2-94c8-b3b9eeae35b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653692587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.653692587
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2535143002
Short name T931
Test name
Test status
Simulation time 168763993 ps
CPU time 3.42 seconds
Started Aug 07 04:49:32 PM PDT 24
Finished Aug 07 04:49:36 PM PDT 24
Peak memory 214324 kb
Host smart-9df511fc-ab8c-45dd-8acd-660fedf5b827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535143002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2535143002
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.627039703
Short name T1069
Test name
Test status
Simulation time 161002896 ps
CPU time 1.64 seconds
Started Aug 07 04:49:27 PM PDT 24
Finished Aug 07 04:49:29 PM PDT 24
Peak memory 214348 kb
Host smart-22ec70ee-ebb3-4d69-93a7-63ea8ac5f67d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627039703 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.627039703
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3406529141
Short name T945
Test name
Test status
Simulation time 14380366 ps
CPU time 0.91 seconds
Started Aug 07 04:49:26 PM PDT 24
Finished Aug 07 04:49:27 PM PDT 24
Peak memory 205928 kb
Host smart-101a5340-b846-49b5-8918-23e75f2cb36d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406529141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3406529141
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1147642638
Short name T1009
Test name
Test status
Simulation time 10574684 ps
CPU time 0.72 seconds
Started Aug 07 04:49:37 PM PDT 24
Finished Aug 07 04:49:38 PM PDT 24
Peak memory 205876 kb
Host smart-4a9cdd3b-c3b1-4817-8475-64e920f3d478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147642638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1147642638
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.451055872
Short name T134
Test name
Test status
Simulation time 175747393 ps
CPU time 1.95 seconds
Started Aug 07 04:49:10 PM PDT 24
Finished Aug 07 04:49:12 PM PDT 24
Peak memory 206004 kb
Host smart-a1fc3771-8eb3-4de9-92d7-80476555b2d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451055872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.451055872
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1733892087
Short name T1050
Test name
Test status
Simulation time 235458352 ps
CPU time 2.26 seconds
Started Aug 07 04:49:06 PM PDT 24
Finished Aug 07 04:49:08 PM PDT 24
Peak memory 214552 kb
Host smart-fff5fb6b-1215-41ba-b5b0-edc57caeaeca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733892087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1733892087
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1904552973
Short name T1023
Test name
Test status
Simulation time 95935030 ps
CPU time 3.54 seconds
Started Aug 07 04:49:02 PM PDT 24
Finished Aug 07 04:49:06 PM PDT 24
Peak memory 220496 kb
Host smart-e3e2d368-7e18-4616-8f38-dbe0027c914f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904552973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1904552973
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1581162562
Short name T935
Test name
Test status
Simulation time 174681927 ps
CPU time 3.29 seconds
Started Aug 07 04:49:28 PM PDT 24
Finished Aug 07 04:49:32 PM PDT 24
Peak memory 214192 kb
Host smart-ba61bde2-7d12-420f-9fde-15ed34a9cbae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581162562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1581162562
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3266385907
Short name T1057
Test name
Test status
Simulation time 35184641 ps
CPU time 2.44 seconds
Started Aug 07 04:49:25 PM PDT 24
Finished Aug 07 04:49:28 PM PDT 24
Peak memory 214268 kb
Host smart-767f6b81-c790-47ed-a13f-a837b98c9ef9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266385907 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3266385907
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.156902922
Short name T965
Test name
Test status
Simulation time 19755172 ps
CPU time 1.05 seconds
Started Aug 07 04:49:09 PM PDT 24
Finished Aug 07 04:49:10 PM PDT 24
Peak memory 206148 kb
Host smart-ca935ac7-28ae-4029-b862-10d54f82aa0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156902922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.156902922
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3935244472
Short name T1018
Test name
Test status
Simulation time 18332375 ps
CPU time 0.71 seconds
Started Aug 07 04:49:04 PM PDT 24
Finished Aug 07 04:49:05 PM PDT 24
Peak memory 205832 kb
Host smart-0d4f5104-294d-4ed6-9b50-1cd905f60625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935244472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3935244472
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1615729123
Short name T1020
Test name
Test status
Simulation time 100617087 ps
CPU time 2.21 seconds
Started Aug 07 04:49:16 PM PDT 24
Finished Aug 07 04:49:19 PM PDT 24
Peak memory 206072 kb
Host smart-d30fc945-fcd1-429b-ab22-f3f32622c2ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615729123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1615729123
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.806993492
Short name T952
Test name
Test status
Simulation time 305675333 ps
CPU time 3.28 seconds
Started Aug 07 04:49:26 PM PDT 24
Finished Aug 07 04:49:29 PM PDT 24
Peak memory 214508 kb
Host smart-76376075-986c-4630-bcd9-d0453b403dc0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806993492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.806993492
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2981825593
Short name T1042
Test name
Test status
Simulation time 86581448 ps
CPU time 4.1 seconds
Started Aug 07 04:49:21 PM PDT 24
Finished Aug 07 04:49:25 PM PDT 24
Peak memory 214632 kb
Host smart-c0d26f3f-0203-4bc9-96ff-eb754142f287
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981825593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2981825593
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4072039962
Short name T1025
Test name
Test status
Simulation time 128571554 ps
CPU time 2.23 seconds
Started Aug 07 04:49:32 PM PDT 24
Finished Aug 07 04:49:34 PM PDT 24
Peak memory 214344 kb
Host smart-ee022029-46cd-4ac1-bc69-b1d99155dec7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072039962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4072039962
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3934162884
Short name T153
Test name
Test status
Simulation time 336645413 ps
CPU time 6.02 seconds
Started Aug 07 04:49:30 PM PDT 24
Finished Aug 07 04:49:36 PM PDT 24
Peak memory 214312 kb
Host smart-faa5c8b6-6b04-4bb0-b14b-9c3b51ffec37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934162884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3934162884
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.967565656
Short name T929
Test name
Test status
Simulation time 150795055 ps
CPU time 1.13 seconds
Started Aug 07 04:49:09 PM PDT 24
Finished Aug 07 04:49:10 PM PDT 24
Peak memory 206156 kb
Host smart-ce70cde4-3dd5-413f-93f0-36565949a393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967565656 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.967565656
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3869500477
Short name T938
Test name
Test status
Simulation time 22650110 ps
CPU time 0.95 seconds
Started Aug 07 04:49:27 PM PDT 24
Finished Aug 07 04:49:28 PM PDT 24
Peak memory 205848 kb
Host smart-49f8cdea-aed7-47f6-8f69-a1d5ea5dce01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869500477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3869500477
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1319076510
Short name T973
Test name
Test status
Simulation time 13091867 ps
CPU time 0.72 seconds
Started Aug 07 04:49:02 PM PDT 24
Finished Aug 07 04:49:03 PM PDT 24
Peak memory 205868 kb
Host smart-131d5259-be0f-4c71-9c9f-796abf07df57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319076510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1319076510
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3915025221
Short name T1012
Test name
Test status
Simulation time 169861154 ps
CPU time 3 seconds
Started Aug 07 04:49:16 PM PDT 24
Finished Aug 07 04:49:19 PM PDT 24
Peak memory 206256 kb
Host smart-a1a1c1be-72fd-4c24-a0b5-f281cd234bec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915025221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3915025221
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4047633610
Short name T924
Test name
Test status
Simulation time 1429794546 ps
CPU time 2.85 seconds
Started Aug 07 04:49:09 PM PDT 24
Finished Aug 07 04:49:12 PM PDT 24
Peak memory 214596 kb
Host smart-3d6ec4a8-3ca0-40f3-9d7b-65828ca65326
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047633610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.4047633610
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4209333388
Short name T1006
Test name
Test status
Simulation time 754431481 ps
CPU time 5.25 seconds
Started Aug 07 04:49:16 PM PDT 24
Finished Aug 07 04:49:21 PM PDT 24
Peak memory 222832 kb
Host smart-b1a09c40-3973-4efc-af6d-486444de6b4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209333388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.4209333388
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.250953185
Short name T1022
Test name
Test status
Simulation time 38538418 ps
CPU time 2.61 seconds
Started Aug 07 04:49:43 PM PDT 24
Finished Aug 07 04:49:46 PM PDT 24
Peak memory 217824 kb
Host smart-b1a657e2-324b-48bf-9a38-96e7bb1d9536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250953185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.250953185
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.624850575
Short name T1070
Test name
Test status
Simulation time 222541378 ps
CPU time 1.62 seconds
Started Aug 07 04:49:35 PM PDT 24
Finished Aug 07 04:49:37 PM PDT 24
Peak memory 214412 kb
Host smart-647eaffc-ab16-4d9d-ab97-c2840b812cb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624850575 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.624850575
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1821871411
Short name T1019
Test name
Test status
Simulation time 102998238 ps
CPU time 1.32 seconds
Started Aug 07 04:49:25 PM PDT 24
Finished Aug 07 04:49:27 PM PDT 24
Peak memory 206112 kb
Host smart-3f0414f2-9790-46f5-a3c6-2d09db228c2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821871411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1821871411
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2126689431
Short name T1004
Test name
Test status
Simulation time 38154624 ps
CPU time 0.76 seconds
Started Aug 07 04:49:07 PM PDT 24
Finished Aug 07 04:49:08 PM PDT 24
Peak memory 205872 kb
Host smart-ba55a60a-5bfb-446a-9f47-cae8af52a14e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126689431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2126689431
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.308983324
Short name T966
Test name
Test status
Simulation time 218262235 ps
CPU time 1.43 seconds
Started Aug 07 04:49:28 PM PDT 24
Finished Aug 07 04:49:30 PM PDT 24
Peak memory 205952 kb
Host smart-103b6edd-2ced-4c09-a496-de58827c72e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308983324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.308983324
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1848433865
Short name T112
Test name
Test status
Simulation time 194950121 ps
CPU time 3.45 seconds
Started Aug 07 04:49:15 PM PDT 24
Finished Aug 07 04:49:18 PM PDT 24
Peak memory 214612 kb
Host smart-822a7ba8-687c-47ca-b1b5-0b57752b3a5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848433865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1848433865
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2201801446
Short name T1026
Test name
Test status
Simulation time 360986661 ps
CPU time 4.53 seconds
Started Aug 07 04:49:20 PM PDT 24
Finished Aug 07 04:49:25 PM PDT 24
Peak memory 214484 kb
Host smart-d1c3830c-a5b3-4c60-85af-fd5d457a7b5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201801446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2201801446
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1973240522
Short name T926
Test name
Test status
Simulation time 416782423 ps
CPU time 3.02 seconds
Started Aug 07 04:49:27 PM PDT 24
Finished Aug 07 04:49:30 PM PDT 24
Peak memory 216632 kb
Host smart-9a9361fc-be12-4801-ad90-3392deb70d04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973240522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1973240522
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.4292773506
Short name T130
Test name
Test status
Simulation time 909076116 ps
CPU time 15.94 seconds
Started Aug 07 04:48:50 PM PDT 24
Finished Aug 07 04:49:07 PM PDT 24
Peak memory 206068 kb
Host smart-26ca97c1-eddb-4774-9fd0-5e74ee99a8b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292773506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.4
292773506
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1910082412
Short name T985
Test name
Test status
Simulation time 4172770882 ps
CPU time 14.05 seconds
Started Aug 07 04:49:05 PM PDT 24
Finished Aug 07 04:49:19 PM PDT 24
Peak memory 206216 kb
Host smart-c6d28954-6148-4be5-a4cf-6fde7faa237e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910082412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
910082412
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3312502376
Short name T944
Test name
Test status
Simulation time 141910011 ps
CPU time 1.02 seconds
Started Aug 07 04:49:03 PM PDT 24
Finished Aug 07 04:49:04 PM PDT 24
Peak memory 205948 kb
Host smart-7b06a93d-c0f4-4f97-ac4a-16c8d5af0acc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312502376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
312502376
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1247789805
Short name T992
Test name
Test status
Simulation time 211319192 ps
CPU time 1.79 seconds
Started Aug 07 04:49:14 PM PDT 24
Finished Aug 07 04:49:16 PM PDT 24
Peak memory 206164 kb
Host smart-6deafb84-3219-42a1-80e1-aeacc7184b9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247789805 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1247789805
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1647323241
Short name T1075
Test name
Test status
Simulation time 25947294 ps
CPU time 1.08 seconds
Started Aug 07 04:49:00 PM PDT 24
Finished Aug 07 04:49:01 PM PDT 24
Peak memory 206128 kb
Host smart-f7dbe18b-53b4-4e67-bfe4-9a87f7cce855
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647323241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1647323241
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.382059612
Short name T947
Test name
Test status
Simulation time 30092233 ps
CPU time 0.76 seconds
Started Aug 07 04:48:43 PM PDT 24
Finished Aug 07 04:48:44 PM PDT 24
Peak memory 205852 kb
Host smart-7710db30-d9f9-4bc8-8fb4-40aa3c5a1028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382059612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.382059612
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3702675412
Short name T131
Test name
Test status
Simulation time 247359913 ps
CPU time 2.03 seconds
Started Aug 07 04:49:12 PM PDT 24
Finished Aug 07 04:49:15 PM PDT 24
Peak memory 206188 kb
Host smart-5f6c81fc-7207-4829-9702-18d945ee812c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702675412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3702675412
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.769070538
Short name T1066
Test name
Test status
Simulation time 859687485 ps
CPU time 4.56 seconds
Started Aug 07 04:48:46 PM PDT 24
Finished Aug 07 04:48:51 PM PDT 24
Peak memory 214588 kb
Host smart-99968beb-3d6b-42ab-8800-4792e1c67916
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769070538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.769070538
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.735646928
Short name T977
Test name
Test status
Simulation time 2257720322 ps
CPU time 12.75 seconds
Started Aug 07 04:49:22 PM PDT 24
Finished Aug 07 04:49:35 PM PDT 24
Peak memory 222892 kb
Host smart-dbe18f47-408b-4ee6-8df2-c947c9c78ad1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735646928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.735646928
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2876179785
Short name T927
Test name
Test status
Simulation time 22878546 ps
CPU time 1.6 seconds
Started Aug 07 04:48:51 PM PDT 24
Finished Aug 07 04:48:53 PM PDT 24
Peak memory 215564 kb
Host smart-67a6cdc4-babc-4553-9889-e63c44b35a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876179785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2876179785
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2595674111
Short name T909
Test name
Test status
Simulation time 38910028 ps
CPU time 0.78 seconds
Started Aug 07 04:49:19 PM PDT 24
Finished Aug 07 04:49:20 PM PDT 24
Peak memory 205832 kb
Host smart-ccc065a0-e6ca-4760-a7dc-e5965d3e7869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595674111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2595674111
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3111082172
Short name T1008
Test name
Test status
Simulation time 17042677 ps
CPU time 0.71 seconds
Started Aug 07 04:49:21 PM PDT 24
Finished Aug 07 04:49:22 PM PDT 24
Peak memory 205868 kb
Host smart-5202f82e-06d7-4d17-b96a-c7c93b5b4604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111082172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3111082172
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3231508422
Short name T921
Test name
Test status
Simulation time 16399862 ps
CPU time 0.73 seconds
Started Aug 07 04:49:31 PM PDT 24
Finished Aug 07 04:49:32 PM PDT 24
Peak memory 205884 kb
Host smart-ec10bc15-bb68-4dff-8ca4-7ab896bd3f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231508422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3231508422
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1317406130
Short name T1065
Test name
Test status
Simulation time 82183830 ps
CPU time 0.95 seconds
Started Aug 07 04:49:35 PM PDT 24
Finished Aug 07 04:49:36 PM PDT 24
Peak memory 205788 kb
Host smart-f5e6452d-a848-4371-858e-00f30321ad6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317406130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1317406130
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.972305414
Short name T1033
Test name
Test status
Simulation time 144708747 ps
CPU time 0.85 seconds
Started Aug 07 04:49:33 PM PDT 24
Finished Aug 07 04:49:33 PM PDT 24
Peak memory 205860 kb
Host smart-e67baa74-85ba-4474-8052-216bfda6c4a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972305414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.972305414
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2580250094
Short name T1013
Test name
Test status
Simulation time 190617924 ps
CPU time 0.73 seconds
Started Aug 07 04:49:09 PM PDT 24
Finished Aug 07 04:49:09 PM PDT 24
Peak memory 205768 kb
Host smart-0eda28a9-d671-48c6-bc54-b96ee2323550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580250094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2580250094
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.129495835
Short name T981
Test name
Test status
Simulation time 7319031 ps
CPU time 0.71 seconds
Started Aug 07 04:49:06 PM PDT 24
Finished Aug 07 04:49:07 PM PDT 24
Peak memory 205792 kb
Host smart-32d7f6ed-48f5-4f30-a8a2-1215afb25397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129495835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.129495835
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1511546424
Short name T983
Test name
Test status
Simulation time 19502708 ps
CPU time 0.81 seconds
Started Aug 07 04:49:05 PM PDT 24
Finished Aug 07 04:49:06 PM PDT 24
Peak memory 205768 kb
Host smart-1b9f2591-99c9-4cc8-9904-65b1ab7d097b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511546424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1511546424
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3730697453
Short name T980
Test name
Test status
Simulation time 16629623 ps
CPU time 0.74 seconds
Started Aug 07 04:49:17 PM PDT 24
Finished Aug 07 04:49:18 PM PDT 24
Peak memory 205924 kb
Host smart-9ec033c1-5b4a-4afc-b8e5-87fded2924f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730697453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3730697453
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2774070671
Short name T932
Test name
Test status
Simulation time 20159370 ps
CPU time 0.75 seconds
Started Aug 07 04:49:11 PM PDT 24
Finished Aug 07 04:49:11 PM PDT 24
Peak memory 205880 kb
Host smart-f501c9a1-9bd3-48f6-a6f2-3273af78a780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774070671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2774070671
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.565802742
Short name T1001
Test name
Test status
Simulation time 741496641 ps
CPU time 4.27 seconds
Started Aug 07 04:49:23 PM PDT 24
Finished Aug 07 04:49:28 PM PDT 24
Peak memory 206060 kb
Host smart-aaf2d23e-7622-4d19-81aa-cf1914b199bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565802742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.565802742
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.611299805
Short name T994
Test name
Test status
Simulation time 3059674150 ps
CPU time 26.15 seconds
Started Aug 07 04:49:10 PM PDT 24
Finished Aug 07 04:49:36 PM PDT 24
Peak memory 206220 kb
Host smart-dd84d636-675a-406f-9017-4924e5191e1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611299805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.611299805
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3136559065
Short name T150
Test name
Test status
Simulation time 16180413 ps
CPU time 1.08 seconds
Started Aug 07 04:48:54 PM PDT 24
Finished Aug 07 04:48:55 PM PDT 24
Peak memory 206112 kb
Host smart-3c516186-ce95-41b0-b4c0-1c94dcc0f86d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136559065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
136559065
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2311842946
Short name T170
Test name
Test status
Simulation time 30073701 ps
CPU time 1.37 seconds
Started Aug 07 04:48:49 PM PDT 24
Finished Aug 07 04:48:51 PM PDT 24
Peak memory 206064 kb
Host smart-483cb03e-7ac2-4ad9-9107-73d563c8919d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311842946 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2311842946
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.177136470
Short name T1063
Test name
Test status
Simulation time 75648185 ps
CPU time 0.97 seconds
Started Aug 07 04:49:03 PM PDT 24
Finished Aug 07 04:49:04 PM PDT 24
Peak memory 205868 kb
Host smart-aefb5354-8e9f-45e1-a3a0-256c3d7d4d6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177136470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.177136470
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.4199706460
Short name T957
Test name
Test status
Simulation time 19860197 ps
CPU time 0.8 seconds
Started Aug 07 04:49:23 PM PDT 24
Finished Aug 07 04:49:24 PM PDT 24
Peak memory 205860 kb
Host smart-5edf581f-f003-4f35-a380-839af6cd3f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199706460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.4199706460
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3882986673
Short name T1073
Test name
Test status
Simulation time 41386456 ps
CPU time 2.44 seconds
Started Aug 07 04:49:25 PM PDT 24
Finished Aug 07 04:49:28 PM PDT 24
Peak memory 206112 kb
Host smart-c1d4708c-90ad-4015-888b-4d511282b762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882986673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3882986673
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1009640457
Short name T1054
Test name
Test status
Simulation time 89983480 ps
CPU time 3.27 seconds
Started Aug 07 04:48:55 PM PDT 24
Finished Aug 07 04:48:59 PM PDT 24
Peak memory 214612 kb
Host smart-e600ec4d-7b3a-4dd5-9308-819af67fc317
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009640457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1009640457
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.4134717436
Short name T114
Test name
Test status
Simulation time 278411875 ps
CPU time 4.49 seconds
Started Aug 07 04:49:01 PM PDT 24
Finished Aug 07 04:49:06 PM PDT 24
Peak memory 214620 kb
Host smart-655cdc0e-d0f8-4e6d-9b3c-cdc6634a81f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134717436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.4134717436
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.264946952
Short name T930
Test name
Test status
Simulation time 64055402 ps
CPU time 1.84 seconds
Started Aug 07 04:48:53 PM PDT 24
Finished Aug 07 04:48:55 PM PDT 24
Peak memory 214380 kb
Host smart-f931ab55-dd3f-4687-a90b-2702ed4adc93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264946952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.264946952
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1419634327
Short name T161
Test name
Test status
Simulation time 832311784 ps
CPU time 6.36 seconds
Started Aug 07 04:49:01 PM PDT 24
Finished Aug 07 04:49:08 PM PDT 24
Peak memory 214244 kb
Host smart-ca5e316c-1a50-431c-ad0f-230afbbc2de2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419634327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1419634327
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3501546679
Short name T914
Test name
Test status
Simulation time 42333865 ps
CPU time 0.73 seconds
Started Aug 07 04:49:18 PM PDT 24
Finished Aug 07 04:49:19 PM PDT 24
Peak memory 205864 kb
Host smart-53365984-1d54-440d-a1d6-50fc1a52be8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501546679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3501546679
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2136979172
Short name T1037
Test name
Test status
Simulation time 111759636 ps
CPU time 0.77 seconds
Started Aug 07 04:49:15 PM PDT 24
Finished Aug 07 04:49:16 PM PDT 24
Peak memory 205876 kb
Host smart-8bbcf06f-501f-41ab-b848-679f523029fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136979172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2136979172
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1515022202
Short name T949
Test name
Test status
Simulation time 44633410 ps
CPU time 0.83 seconds
Started Aug 07 04:49:24 PM PDT 24
Finished Aug 07 04:49:25 PM PDT 24
Peak memory 205872 kb
Host smart-885abcc5-bb5c-4f8a-9ba5-f7ec7c9d60a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515022202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1515022202
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1610839824
Short name T1045
Test name
Test status
Simulation time 8163843 ps
CPU time 0.69 seconds
Started Aug 07 04:49:26 PM PDT 24
Finished Aug 07 04:49:27 PM PDT 24
Peak memory 205848 kb
Host smart-745b6cf3-4acf-46b5-b547-cfd3c3c9ef17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610839824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1610839824
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1378223889
Short name T1034
Test name
Test status
Simulation time 54218720 ps
CPU time 0.88 seconds
Started Aug 07 04:49:23 PM PDT 24
Finished Aug 07 04:49:24 PM PDT 24
Peak memory 205856 kb
Host smart-c58feade-42e2-4000-a6fc-7349ace2fd7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378223889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1378223889
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3599547056
Short name T1049
Test name
Test status
Simulation time 10012473 ps
CPU time 0.82 seconds
Started Aug 07 04:49:35 PM PDT 24
Finished Aug 07 04:49:36 PM PDT 24
Peak memory 205808 kb
Host smart-6d77f5ba-7c68-45f6-adc5-5a8f8a13a908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599547056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3599547056
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4259334341
Short name T943
Test name
Test status
Simulation time 30026821 ps
CPU time 0.77 seconds
Started Aug 07 04:49:31 PM PDT 24
Finished Aug 07 04:49:31 PM PDT 24
Peak memory 205888 kb
Host smart-cc2a0b47-95ed-4672-a2ad-e342f0a436ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259334341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4259334341
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3310238233
Short name T1015
Test name
Test status
Simulation time 9904251 ps
CPU time 0.76 seconds
Started Aug 07 04:49:13 PM PDT 24
Finished Aug 07 04:49:14 PM PDT 24
Peak memory 205912 kb
Host smart-cec68b86-0ec0-4658-bc76-9482b27f915f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310238233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3310238233
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3812481990
Short name T1079
Test name
Test status
Simulation time 17020789 ps
CPU time 1.02 seconds
Started Aug 07 04:49:23 PM PDT 24
Finished Aug 07 04:49:24 PM PDT 24
Peak memory 206008 kb
Host smart-bda6dcf1-0f33-4282-8948-32cb192e2190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812481990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3812481990
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2263002756
Short name T916
Test name
Test status
Simulation time 12031454 ps
CPU time 0.68 seconds
Started Aug 07 04:49:16 PM PDT 24
Finished Aug 07 04:49:16 PM PDT 24
Peak memory 205868 kb
Host smart-60e554e2-72c7-4ee5-a4e2-d5230af22aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263002756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2263002756
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2507234138
Short name T984
Test name
Test status
Simulation time 1027575764 ps
CPU time 7.45 seconds
Started Aug 07 04:48:51 PM PDT 24
Finished Aug 07 04:48:59 PM PDT 24
Peak memory 206196 kb
Host smart-837e9059-a281-451c-9947-8c084ec946c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507234138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
507234138
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1945675051
Short name T1039
Test name
Test status
Simulation time 919873878 ps
CPU time 8.01 seconds
Started Aug 07 04:48:55 PM PDT 24
Finished Aug 07 04:49:08 PM PDT 24
Peak memory 206276 kb
Host smart-323bfb39-5fa2-49a1-8c0f-688264d265f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945675051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
945675051
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1729858862
Short name T1027
Test name
Test status
Simulation time 149678147 ps
CPU time 0.95 seconds
Started Aug 07 04:48:59 PM PDT 24
Finished Aug 07 04:49:00 PM PDT 24
Peak memory 205948 kb
Host smart-47a658e6-9d96-4e16-aa73-245a2c73fa88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729858862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
729858862
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1593726970
Short name T1035
Test name
Test status
Simulation time 151328028 ps
CPU time 1.84 seconds
Started Aug 07 04:49:17 PM PDT 24
Finished Aug 07 04:49:19 PM PDT 24
Peak memory 214292 kb
Host smart-6ba40aa6-9e80-4633-91f7-47184105375e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593726970 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1593726970
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3303836283
Short name T989
Test name
Test status
Simulation time 17168767 ps
CPU time 1.08 seconds
Started Aug 07 04:49:03 PM PDT 24
Finished Aug 07 04:49:04 PM PDT 24
Peak memory 206204 kb
Host smart-7a570ef5-28ba-45e5-8b76-df3ae2b679f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303836283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3303836283
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3736180025
Short name T1005
Test name
Test status
Simulation time 16512597 ps
CPU time 0.92 seconds
Started Aug 07 04:48:54 PM PDT 24
Finished Aug 07 04:48:55 PM PDT 24
Peak memory 206040 kb
Host smart-6f8fc85c-b53e-4d7c-9224-2e8f496e9d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736180025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3736180025
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1979404737
Short name T997
Test name
Test status
Simulation time 19832305 ps
CPU time 1.66 seconds
Started Aug 07 04:49:06 PM PDT 24
Finished Aug 07 04:49:08 PM PDT 24
Peak memory 206056 kb
Host smart-9338153c-a742-4c2a-8ed8-c425a89097de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979404737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1979404737
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1577961705
Short name T111
Test name
Test status
Simulation time 361714667 ps
CPU time 5.73 seconds
Started Aug 07 04:48:57 PM PDT 24
Finished Aug 07 04:49:02 PM PDT 24
Peak memory 214596 kb
Host smart-3cad3243-03b5-4b2a-9485-2086f412d1da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577961705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1577961705
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.170066545
Short name T1061
Test name
Test status
Simulation time 79998749 ps
CPU time 3.73 seconds
Started Aug 07 04:49:00 PM PDT 24
Finished Aug 07 04:49:04 PM PDT 24
Peak memory 214500 kb
Host smart-ff355d09-944d-429d-8ab4-777490d21071
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170066545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.170066545
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1697728650
Short name T913
Test name
Test status
Simulation time 55098757 ps
CPU time 1.64 seconds
Started Aug 07 04:49:06 PM PDT 24
Finished Aug 07 04:49:07 PM PDT 24
Peak memory 214436 kb
Host smart-c0ba738e-cc7a-4c57-b232-157b34e9aa30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697728650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1697728650
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2479324271
Short name T157
Test name
Test status
Simulation time 418243156 ps
CPU time 4.88 seconds
Started Aug 07 04:48:46 PM PDT 24
Finished Aug 07 04:48:51 PM PDT 24
Peak memory 206368 kb
Host smart-0ec61615-3f11-4cc3-b1a6-f3f72f3c068e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479324271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2479324271
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1908072170
Short name T988
Test name
Test status
Simulation time 11682206 ps
CPU time 0.87 seconds
Started Aug 07 04:49:28 PM PDT 24
Finished Aug 07 04:49:29 PM PDT 24
Peak memory 205872 kb
Host smart-b33c44f2-db93-4ed8-bfd1-0689f3876226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908072170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1908072170
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.4118094993
Short name T948
Test name
Test status
Simulation time 37107693 ps
CPU time 0.71 seconds
Started Aug 07 04:49:17 PM PDT 24
Finished Aug 07 04:49:18 PM PDT 24
Peak memory 205824 kb
Host smart-f5d0360f-6123-4360-8eae-0b59798c3ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118094993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.4118094993
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1251456224
Short name T1014
Test name
Test status
Simulation time 51391483 ps
CPU time 0.77 seconds
Started Aug 07 04:49:33 PM PDT 24
Finished Aug 07 04:49:34 PM PDT 24
Peak memory 205932 kb
Host smart-76dee5ee-8add-41ba-9f4a-f3495ae84028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251456224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1251456224
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.73263746
Short name T912
Test name
Test status
Simulation time 118632429 ps
CPU time 0.89 seconds
Started Aug 07 04:49:31 PM PDT 24
Finished Aug 07 04:49:32 PM PDT 24
Peak memory 205888 kb
Host smart-a913c4ff-9fce-422d-95d9-e6b7a03abdca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73263746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.73263746
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1049257588
Short name T1078
Test name
Test status
Simulation time 38583529 ps
CPU time 0.88 seconds
Started Aug 07 04:49:14 PM PDT 24
Finished Aug 07 04:49:15 PM PDT 24
Peak memory 205912 kb
Host smart-353aea75-6a61-4a37-aa09-a3bb827108d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049257588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1049257588
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.688226834
Short name T937
Test name
Test status
Simulation time 9640974 ps
CPU time 0.69 seconds
Started Aug 07 04:49:18 PM PDT 24
Finished Aug 07 04:49:19 PM PDT 24
Peak memory 205872 kb
Host smart-0e73f261-c4e3-472e-b82f-f9cc5e3736e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688226834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.688226834
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1108972448
Short name T1011
Test name
Test status
Simulation time 118298136 ps
CPU time 0.81 seconds
Started Aug 07 04:49:10 PM PDT 24
Finished Aug 07 04:49:11 PM PDT 24
Peak memory 205880 kb
Host smart-6c421619-1bf8-48fa-b95a-25c783c5f298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108972448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1108972448
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2139658650
Short name T1059
Test name
Test status
Simulation time 11202925 ps
CPU time 0.83 seconds
Started Aug 07 04:49:35 PM PDT 24
Finished Aug 07 04:49:36 PM PDT 24
Peak memory 205788 kb
Host smart-4935714d-ba42-469e-a439-96b60a0aa521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139658650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2139658650
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2198985728
Short name T920
Test name
Test status
Simulation time 86732216 ps
CPU time 0.81 seconds
Started Aug 07 04:49:14 PM PDT 24
Finished Aug 07 04:49:15 PM PDT 24
Peak memory 205976 kb
Host smart-68a24b62-9343-439c-8d55-4e7f4ed02448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198985728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2198985728
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2627676811
Short name T922
Test name
Test status
Simulation time 8577454 ps
CPU time 0.73 seconds
Started Aug 07 04:49:15 PM PDT 24
Finished Aug 07 04:49:16 PM PDT 24
Peak memory 205888 kb
Host smart-09bc5d2c-7b8c-43ee-bfc0-9aff0232b0ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627676811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2627676811
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3586796320
Short name T971
Test name
Test status
Simulation time 117466183 ps
CPU time 1.16 seconds
Started Aug 07 04:49:38 PM PDT 24
Finished Aug 07 04:49:39 PM PDT 24
Peak memory 206484 kb
Host smart-4b87b970-185e-4d30-8dd3-3dde26f3cf5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586796320 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3586796320
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1823941572
Short name T959
Test name
Test status
Simulation time 39388889 ps
CPU time 0.87 seconds
Started Aug 07 04:49:12 PM PDT 24
Finished Aug 07 04:49:13 PM PDT 24
Peak memory 205976 kb
Host smart-702979f8-f609-4dbf-866e-1f74b6b1d739
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823941572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1823941572
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1522968156
Short name T941
Test name
Test status
Simulation time 12426611 ps
CPU time 0.71 seconds
Started Aug 07 04:49:04 PM PDT 24
Finished Aug 07 04:49:05 PM PDT 24
Peak memory 205776 kb
Host smart-7a903ce6-5dde-414b-9e5a-d3ae8df5ec23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522968156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1522968156
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2261176015
Short name T995
Test name
Test status
Simulation time 50830346 ps
CPU time 2.12 seconds
Started Aug 07 04:48:48 PM PDT 24
Finished Aug 07 04:48:50 PM PDT 24
Peak memory 206096 kb
Host smart-2de44a96-8feb-4825-ae21-69d9c8ad914c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261176015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2261176015
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1112222680
Short name T108
Test name
Test status
Simulation time 159486036 ps
CPU time 4.68 seconds
Started Aug 07 04:48:45 PM PDT 24
Finished Aug 07 04:48:50 PM PDT 24
Peak memory 214620 kb
Host smart-72d8cd18-eecf-4e5e-b264-864e04dd1d4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112222680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1112222680
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2792959220
Short name T976
Test name
Test status
Simulation time 172350650 ps
CPU time 7.73 seconds
Started Aug 07 04:48:58 PM PDT 24
Finished Aug 07 04:49:05 PM PDT 24
Peak memory 214564 kb
Host smart-d99e03dc-6726-4984-ade1-a1e9c5c6367d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792959220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2792959220
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3502679008
Short name T910
Test name
Test status
Simulation time 48309814 ps
CPU time 2.72 seconds
Started Aug 07 04:48:47 PM PDT 24
Finished Aug 07 04:48:49 PM PDT 24
Peak memory 214212 kb
Host smart-e9b4648f-4b7d-43a7-8135-07dfd9899671
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502679008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3502679008
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3771953941
Short name T144
Test name
Test status
Simulation time 467230239 ps
CPU time 5.33 seconds
Started Aug 07 04:48:59 PM PDT 24
Finished Aug 07 04:49:04 PM PDT 24
Peak memory 214300 kb
Host smart-5840373f-c96e-4a64-bada-440ec2032fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771953941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3771953941
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.4250955678
Short name T972
Test name
Test status
Simulation time 40736619 ps
CPU time 1.75 seconds
Started Aug 07 04:49:25 PM PDT 24
Finished Aug 07 04:49:27 PM PDT 24
Peak memory 214368 kb
Host smart-c568b95a-2198-432a-8cd1-3ba1b4bc7d29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250955678 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.4250955678
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4147002824
Short name T939
Test name
Test status
Simulation time 19744060 ps
CPU time 0.87 seconds
Started Aug 07 04:48:48 PM PDT 24
Finished Aug 07 04:48:49 PM PDT 24
Peak memory 205916 kb
Host smart-d9fee4f4-8b63-4687-9b33-e1cfb53d1f2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147002824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.4147002824
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2097546062
Short name T919
Test name
Test status
Simulation time 27455560 ps
CPU time 0.81 seconds
Started Aug 07 04:48:47 PM PDT 24
Finished Aug 07 04:48:48 PM PDT 24
Peak memory 205788 kb
Host smart-240d3046-d083-45f8-8c61-4b74ddfd6cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097546062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2097546062
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.46310156
Short name T128
Test name
Test status
Simulation time 247182559 ps
CPU time 3.08 seconds
Started Aug 07 04:49:00 PM PDT 24
Finished Aug 07 04:49:03 PM PDT 24
Peak memory 206364 kb
Host smart-a5d934c6-bdc5-48b2-a97b-399c50bd42b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46310156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same
_csr_outstanding.46310156
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3636010279
Short name T116
Test name
Test status
Simulation time 149022638 ps
CPU time 2.58 seconds
Started Aug 07 04:49:09 PM PDT 24
Finished Aug 07 04:49:12 PM PDT 24
Peak memory 214592 kb
Host smart-8b17b1f5-8f2f-4e40-9201-28d53d1c2f47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636010279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3636010279
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1932570836
Short name T1074
Test name
Test status
Simulation time 412909195 ps
CPU time 5.55 seconds
Started Aug 07 04:49:22 PM PDT 24
Finished Aug 07 04:49:27 PM PDT 24
Peak memory 214684 kb
Host smart-f7bb7496-e87a-483f-ad51-89d4af0a35a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932570836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1932570836
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3007884408
Short name T1036
Test name
Test status
Simulation time 2024473671 ps
CPU time 5.15 seconds
Started Aug 07 04:49:17 PM PDT 24
Finished Aug 07 04:49:23 PM PDT 24
Peak memory 216460 kb
Host smart-476c58dd-3052-43c3-a5e1-f3fcfce3fa94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007884408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3007884408
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.49464305
Short name T1062
Test name
Test status
Simulation time 123654514 ps
CPU time 2.45 seconds
Started Aug 07 04:49:06 PM PDT 24
Finished Aug 07 04:49:09 PM PDT 24
Peak memory 206116 kb
Host smart-a861afe7-5e8c-4f9a-8c49-283635005d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49464305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.49464305
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2501935529
Short name T958
Test name
Test status
Simulation time 101848189 ps
CPU time 1.89 seconds
Started Aug 07 04:48:48 PM PDT 24
Finished Aug 07 04:48:50 PM PDT 24
Peak memory 214340 kb
Host smart-8d332b95-9d3a-4270-b537-e810513ec8a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501935529 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2501935529
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3600612688
Short name T917
Test name
Test status
Simulation time 29123783 ps
CPU time 1.63 seconds
Started Aug 07 04:48:57 PM PDT 24
Finished Aug 07 04:48:59 PM PDT 24
Peak memory 206092 kb
Host smart-10a33d41-193f-4d8b-874b-3b73f064eac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600612688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3600612688
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2407943695
Short name T934
Test name
Test status
Simulation time 11337859 ps
CPU time 0.7 seconds
Started Aug 07 04:48:49 PM PDT 24
Finished Aug 07 04:48:49 PM PDT 24
Peak memory 205856 kb
Host smart-3b5d9815-a342-4cf6-8b4b-e80b54b669c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407943695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2407943695
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1361369879
Short name T1000
Test name
Test status
Simulation time 42144876 ps
CPU time 1.59 seconds
Started Aug 07 04:49:09 PM PDT 24
Finished Aug 07 04:49:11 PM PDT 24
Peak memory 206080 kb
Host smart-db3429a4-55bb-4acb-a41c-8ab5b157e56a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361369879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1361369879
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3137990190
Short name T986
Test name
Test status
Simulation time 446768673 ps
CPU time 2.29 seconds
Started Aug 07 04:49:14 PM PDT 24
Finished Aug 07 04:49:16 PM PDT 24
Peak memory 214492 kb
Host smart-63a9bbc6-ef7f-4a07-9041-ec6163d8f603
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137990190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3137990190
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3387889446
Short name T940
Test name
Test status
Simulation time 277073072 ps
CPU time 3.46 seconds
Started Aug 07 04:49:05 PM PDT 24
Finished Aug 07 04:49:08 PM PDT 24
Peak memory 214596 kb
Host smart-c7cfcf2b-0a50-47e2-a3bf-e6b4a84b7c00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387889446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3387889446
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1012853235
Short name T967
Test name
Test status
Simulation time 105738656 ps
CPU time 3.45 seconds
Started Aug 07 04:49:00 PM PDT 24
Finished Aug 07 04:49:03 PM PDT 24
Peak memory 214348 kb
Host smart-eb72df5a-fd96-480b-a77d-111f822deb04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012853235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1012853235
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3387396709
Short name T152
Test name
Test status
Simulation time 1576916514 ps
CPU time 8.72 seconds
Started Aug 07 04:49:28 PM PDT 24
Finished Aug 07 04:49:37 PM PDT 24
Peak memory 214216 kb
Host smart-01edd530-2e19-4032-90a1-2a1581d1bc9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387396709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3387396709
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1112811798
Short name T1003
Test name
Test status
Simulation time 71466987 ps
CPU time 2.14 seconds
Started Aug 07 04:49:10 PM PDT 24
Finished Aug 07 04:49:12 PM PDT 24
Peak memory 222520 kb
Host smart-9f844b2f-2174-4fac-9b30-5b7bddbf3f7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112811798 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1112811798
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3934228275
Short name T1031
Test name
Test status
Simulation time 28969915 ps
CPU time 0.93 seconds
Started Aug 07 04:49:27 PM PDT 24
Finished Aug 07 04:49:28 PM PDT 24
Peak memory 206092 kb
Host smart-194f2635-da78-4453-b988-83772b50c26c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934228275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3934228275
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3812257373
Short name T928
Test name
Test status
Simulation time 11354988 ps
CPU time 0.74 seconds
Started Aug 07 04:49:19 PM PDT 24
Finished Aug 07 04:49:20 PM PDT 24
Peak memory 205860 kb
Host smart-67df3568-c626-41f4-88f4-5abf8fff6141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812257373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3812257373
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.777009643
Short name T975
Test name
Test status
Simulation time 84188290 ps
CPU time 2.56 seconds
Started Aug 07 04:48:56 PM PDT 24
Finished Aug 07 04:48:59 PM PDT 24
Peak memory 206112 kb
Host smart-0edfe1fe-1a68-4418-b6ad-26f6bd4e6e3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777009643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.777009643
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1927283037
Short name T1077
Test name
Test status
Simulation time 168912102 ps
CPU time 3.32 seconds
Started Aug 07 04:49:05 PM PDT 24
Finished Aug 07 04:49:08 PM PDT 24
Peak memory 214676 kb
Host smart-bc888ff9-beef-45c8-bf94-05a57fe03a5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927283037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1927283037
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.602563011
Short name T1041
Test name
Test status
Simulation time 438995932 ps
CPU time 5.56 seconds
Started Aug 07 04:49:09 PM PDT 24
Finished Aug 07 04:49:15 PM PDT 24
Peak memory 220532 kb
Host smart-137a0b9a-42dd-4ca6-adb6-9371bea1c791
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602563011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.602563011
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2597566270
Short name T1064
Test name
Test status
Simulation time 1102043738 ps
CPU time 6.81 seconds
Started Aug 07 04:49:21 PM PDT 24
Finished Aug 07 04:49:28 PM PDT 24
Peak memory 217608 kb
Host smart-122364e3-b300-41b9-80c6-f63356e0d960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597566270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2597566270
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.943712239
Short name T158
Test name
Test status
Simulation time 223276715 ps
CPU time 4.77 seconds
Started Aug 07 04:49:06 PM PDT 24
Finished Aug 07 04:49:11 PM PDT 24
Peak memory 214308 kb
Host smart-86cd4dd3-9f0c-4400-9d20-e949221ac9d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943712239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
943712239
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.509760950
Short name T1058
Test name
Test status
Simulation time 91979530 ps
CPU time 1.99 seconds
Started Aug 07 04:49:27 PM PDT 24
Finished Aug 07 04:49:29 PM PDT 24
Peak memory 214356 kb
Host smart-b5540b48-7bd5-4d9b-9a79-5e6c714587ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509760950 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.509760950
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2613423449
Short name T993
Test name
Test status
Simulation time 37741784 ps
CPU time 0.93 seconds
Started Aug 07 04:49:05 PM PDT 24
Finished Aug 07 04:49:06 PM PDT 24
Peak memory 205916 kb
Host smart-03e1a99f-29eb-4469-b6ba-9fea0b1f71da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613423449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2613423449
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2970344493
Short name T1056
Test name
Test status
Simulation time 12737900 ps
CPU time 0.77 seconds
Started Aug 07 04:49:25 PM PDT 24
Finished Aug 07 04:49:26 PM PDT 24
Peak memory 205852 kb
Host smart-387e181a-5985-42b7-a07a-a3766d8ce096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970344493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2970344493
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1767370219
Short name T954
Test name
Test status
Simulation time 370653295 ps
CPU time 2.74 seconds
Started Aug 07 04:49:08 PM PDT 24
Finished Aug 07 04:49:11 PM PDT 24
Peak memory 206112 kb
Host smart-d7413ec2-f5d1-4468-a29b-6425649ccc8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767370219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1767370219
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2565545492
Short name T1046
Test name
Test status
Simulation time 236422633 ps
CPU time 1.65 seconds
Started Aug 07 04:49:15 PM PDT 24
Finished Aug 07 04:49:17 PM PDT 24
Peak memory 214532 kb
Host smart-26d453a7-bfa2-4499-ba1e-81d764706b75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565545492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2565545492
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1978271444
Short name T970
Test name
Test status
Simulation time 1834819959 ps
CPU time 9.69 seconds
Started Aug 07 04:48:59 PM PDT 24
Finished Aug 07 04:49:09 PM PDT 24
Peak memory 214708 kb
Host smart-c8188284-fa29-429a-b23e-a490c851e8ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978271444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1978271444
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3668884107
Short name T1038
Test name
Test status
Simulation time 208792941 ps
CPU time 1.77 seconds
Started Aug 07 04:49:10 PM PDT 24
Finished Aug 07 04:49:12 PM PDT 24
Peak memory 206116 kb
Host smart-f7cef509-9459-43ab-9950-1e2d537bf5f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668884107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3668884107
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3020379022
Short name T149
Test name
Test status
Simulation time 394532780 ps
CPU time 4.47 seconds
Started Aug 07 04:49:07 PM PDT 24
Finished Aug 07 04:49:11 PM PDT 24
Peak memory 214252 kb
Host smart-251a094f-e3d8-4120-8c8a-5bf31bcd6b55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020379022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3020379022
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1582463039
Short name T554
Test name
Test status
Simulation time 45046238 ps
CPU time 0.86 seconds
Started Aug 07 06:16:55 PM PDT 24
Finished Aug 07 06:16:56 PM PDT 24
Peak memory 205856 kb
Host smart-3549e0eb-4404-4769-99b2-dfad3887bf72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582463039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1582463039
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2319941104
Short name T344
Test name
Test status
Simulation time 44998696 ps
CPU time 1.89 seconds
Started Aug 07 06:16:58 PM PDT 24
Finished Aug 07 06:17:00 PM PDT 24
Peak memory 214296 kb
Host smart-398799e5-5f33-428c-a9f6-45d96ee79ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319941104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2319941104
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.901968900
Short name T626
Test name
Test status
Simulation time 2781124156 ps
CPU time 61.74 seconds
Started Aug 07 06:16:55 PM PDT 24
Finished Aug 07 06:17:57 PM PDT 24
Peak memory 219808 kb
Host smart-f73956e7-4aee-4f20-8b61-817d4e003184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901968900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.901968900
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1712518103
Short name T580
Test name
Test status
Simulation time 396125574 ps
CPU time 4.64 seconds
Started Aug 07 06:16:55 PM PDT 24
Finished Aug 07 06:17:00 PM PDT 24
Peak memory 219828 kb
Host smart-c18695a2-cce8-4714-a1c4-9546e6f540bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712518103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1712518103
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2243930690
Short name T628
Test name
Test status
Simulation time 403322912 ps
CPU time 6.44 seconds
Started Aug 07 06:16:59 PM PDT 24
Finished Aug 07 06:17:05 PM PDT 24
Peak memory 209616 kb
Host smart-96f4b8ec-4bd7-40ce-8a58-a92fffef829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243930690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2243930690
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.707688797
Short name T11
Test name
Test status
Simulation time 1026211417 ps
CPU time 15.77 seconds
Started Aug 07 06:16:57 PM PDT 24
Finished Aug 07 06:17:12 PM PDT 24
Peak memory 238616 kb
Host smart-137845db-2f7f-4b3e-ba8b-59e7d7528de8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707688797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.707688797
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.568310367
Short name T404
Test name
Test status
Simulation time 51044725 ps
CPU time 2.66 seconds
Started Aug 07 06:16:53 PM PDT 24
Finished Aug 07 06:16:56 PM PDT 24
Peak memory 206872 kb
Host smart-66493376-329e-4b2a-9faa-db325b0e2275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568310367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.568310367
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1814752098
Short name T447
Test name
Test status
Simulation time 642795105 ps
CPU time 5.11 seconds
Started Aug 07 06:16:54 PM PDT 24
Finished Aug 07 06:16:59 PM PDT 24
Peak memory 207980 kb
Host smart-4876344d-8605-4957-8c8f-c3f8a29a7ec1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814752098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1814752098
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.30281351
Short name T2
Test name
Test status
Simulation time 2364195314 ps
CPU time 8.8 seconds
Started Aug 07 06:16:52 PM PDT 24
Finished Aug 07 06:17:01 PM PDT 24
Peak memory 208700 kb
Host smart-c748158e-54af-4c4f-b7f4-0294f45369a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30281351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.30281351
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2121167810
Short name T637
Test name
Test status
Simulation time 251920712 ps
CPU time 3.57 seconds
Started Aug 07 06:16:53 PM PDT 24
Finished Aug 07 06:16:57 PM PDT 24
Peak memory 214320 kb
Host smart-e2a07697-440e-46f6-90f3-2e1cae0a70ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121167810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2121167810
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1289061531
Short name T172
Test name
Test status
Simulation time 57788658 ps
CPU time 2.2 seconds
Started Aug 07 06:16:57 PM PDT 24
Finished Aug 07 06:16:59 PM PDT 24
Peak memory 206844 kb
Host smart-474bf591-c6fd-4f9e-923e-864ac2160f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289061531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1289061531
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.819111441
Short name T624
Test name
Test status
Simulation time 27189847104 ps
CPU time 103.12 seconds
Started Aug 07 06:16:53 PM PDT 24
Finished Aug 07 06:18:36 PM PDT 24
Peak memory 222552 kb
Host smart-f4204780-f5f0-4810-9180-0f64d3071534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819111441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.819111441
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.837222495
Short name T647
Test name
Test status
Simulation time 128240740 ps
CPU time 9.18 seconds
Started Aug 07 06:16:57 PM PDT 24
Finished Aug 07 06:17:06 PM PDT 24
Peak memory 222400 kb
Host smart-a9055fbd-2920-45ca-af34-9aa7bd9be2d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837222495 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.837222495
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3247137813
Short name T638
Test name
Test status
Simulation time 261956682 ps
CPU time 6.95 seconds
Started Aug 07 06:16:56 PM PDT 24
Finished Aug 07 06:17:03 PM PDT 24
Peak memory 214364 kb
Host smart-696f2582-520a-4627-be51-987261d2fd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247137813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3247137813
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1677053027
Short name T731
Test name
Test status
Simulation time 498279128 ps
CPU time 5.07 seconds
Started Aug 07 06:16:56 PM PDT 24
Finished Aug 07 06:17:01 PM PDT 24
Peak memory 210316 kb
Host smart-a950fa31-aa43-4f44-9b3d-0be1a632efc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677053027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1677053027
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2226178714
Short name T667
Test name
Test status
Simulation time 9501149 ps
CPU time 0.75 seconds
Started Aug 07 06:17:05 PM PDT 24
Finished Aug 07 06:17:06 PM PDT 24
Peak memory 205952 kb
Host smart-bb1da13b-dd7d-4bce-95f4-8125e668ee36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226178714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2226178714
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2611765606
Short name T593
Test name
Test status
Simulation time 1908512096 ps
CPU time 12.91 seconds
Started Aug 07 06:17:01 PM PDT 24
Finished Aug 07 06:17:14 PM PDT 24
Peak memory 209924 kb
Host smart-6f32326e-6830-4d03-b555-9d7bfd99f675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611765606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2611765606
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_random.4216299685
Short name T521
Test name
Test status
Simulation time 13161685394 ps
CPU time 54.44 seconds
Started Aug 07 06:17:08 PM PDT 24
Finished Aug 07 06:18:03 PM PDT 24
Peak memory 208956 kb
Host smart-c719c62c-d676-441b-9902-1ea35aa866bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216299685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.4216299685
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2511778216
Short name T672
Test name
Test status
Simulation time 66857400 ps
CPU time 2.91 seconds
Started Aug 07 06:17:09 PM PDT 24
Finished Aug 07 06:17:12 PM PDT 24
Peak memory 208680 kb
Host smart-e5c4643f-e39a-407f-85bb-5eac9bb3339f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511778216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2511778216
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.716302502
Short name T802
Test name
Test status
Simulation time 194979254 ps
CPU time 5.62 seconds
Started Aug 07 06:17:07 PM PDT 24
Finished Aug 07 06:17:13 PM PDT 24
Peak memory 209148 kb
Host smart-e8797167-1327-4b55-9fec-2df1b091bea7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716302502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.716302502
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3476829604
Short name T598
Test name
Test status
Simulation time 68723901 ps
CPU time 3.26 seconds
Started Aug 07 06:17:07 PM PDT 24
Finished Aug 07 06:17:11 PM PDT 24
Peak memory 208532 kb
Host smart-47d0a44f-757f-4dd8-9a19-4e2c310595b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476829604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3476829604
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2131564051
Short name T405
Test name
Test status
Simulation time 34467002 ps
CPU time 2.6 seconds
Started Aug 07 06:16:59 PM PDT 24
Finished Aug 07 06:17:01 PM PDT 24
Peak memory 208792 kb
Host smart-f79eebb7-bf39-484c-986b-0af5fb21f176
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131564051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2131564051
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.584554291
Short name T636
Test name
Test status
Simulation time 181056431 ps
CPU time 5.25 seconds
Started Aug 07 06:17:08 PM PDT 24
Finished Aug 07 06:17:13 PM PDT 24
Peak memory 209252 kb
Host smart-28ecd924-2c14-4ff8-9dc7-f8168cbbd5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584554291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.584554291
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1639585223
Short name T509
Test name
Test status
Simulation time 566087561 ps
CPU time 3.76 seconds
Started Aug 07 06:16:53 PM PDT 24
Finished Aug 07 06:16:57 PM PDT 24
Peak memory 206820 kb
Host smart-b95b4331-6653-47ef-ae62-17f7d3a9f3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639585223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1639585223
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2263501059
Short name T822
Test name
Test status
Simulation time 2177999973 ps
CPU time 40.65 seconds
Started Aug 07 06:17:02 PM PDT 24
Finished Aug 07 06:17:43 PM PDT 24
Peak memory 215728 kb
Host smart-d7261239-b777-48ee-9fc5-fd360b779677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263501059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2263501059
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.6403952
Short name T609
Test name
Test status
Simulation time 35225753 ps
CPU time 0.7 seconds
Started Aug 07 06:17:44 PM PDT 24
Finished Aug 07 06:17:45 PM PDT 24
Peak memory 205964 kb
Host smart-0f36920a-8e17-40e9-acf5-19bd844ab5ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6403952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.6403952
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3755495287
Short name T291
Test name
Test status
Simulation time 553725243 ps
CPU time 8.3 seconds
Started Aug 07 06:17:35 PM PDT 24
Finished Aug 07 06:17:43 PM PDT 24
Peak memory 215616 kb
Host smart-8c54618c-010e-4da3-89a1-5d21a214acd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3755495287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3755495287
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3049618523
Short name T832
Test name
Test status
Simulation time 592103163 ps
CPU time 11.84 seconds
Started Aug 07 06:17:35 PM PDT 24
Finished Aug 07 06:17:47 PM PDT 24
Peak memory 209312 kb
Host smart-b4b7f85d-df35-4402-a72c-7303b769ed0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049618523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3049618523
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1991960252
Short name T306
Test name
Test status
Simulation time 93369636 ps
CPU time 2.01 seconds
Started Aug 07 06:17:35 PM PDT 24
Finished Aug 07 06:17:38 PM PDT 24
Peak memory 214364 kb
Host smart-6608aac7-b186-44d5-8769-9bfbc8a2b9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991960252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1991960252
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.904701128
Short name T271
Test name
Test status
Simulation time 135100081 ps
CPU time 4.51 seconds
Started Aug 07 06:17:35 PM PDT 24
Finished Aug 07 06:17:39 PM PDT 24
Peak memory 215364 kb
Host smart-8ca19849-8030-45f9-a42a-1bbd306872b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904701128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.904701128
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.105624190
Short name T721
Test name
Test status
Simulation time 398837676 ps
CPU time 3.38 seconds
Started Aug 07 06:17:33 PM PDT 24
Finished Aug 07 06:17:37 PM PDT 24
Peak memory 207088 kb
Host smart-e6dc431c-d652-435c-b61d-a4b9eb311a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105624190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.105624190
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3455758519
Short name T896
Test name
Test status
Simulation time 87930395 ps
CPU time 3.95 seconds
Started Aug 07 06:17:35 PM PDT 24
Finished Aug 07 06:17:39 PM PDT 24
Peak memory 210172 kb
Host smart-a15a0e55-29e6-418a-b101-ab0267b0fd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455758519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3455758519
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.384358926
Short name T788
Test name
Test status
Simulation time 42041356 ps
CPU time 2.19 seconds
Started Aug 07 06:17:34 PM PDT 24
Finished Aug 07 06:17:36 PM PDT 24
Peak memory 206792 kb
Host smart-c4c7e1b4-1466-49b9-995c-863632ed2274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384358926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.384358926
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1587512135
Short name T491
Test name
Test status
Simulation time 3365410736 ps
CPU time 35.85 seconds
Started Aug 07 06:17:32 PM PDT 24
Finished Aug 07 06:18:08 PM PDT 24
Peak memory 208820 kb
Host smart-8c626efa-4fa3-4744-89c0-d52d0b21c250
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587512135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1587512135
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2271353378
Short name T631
Test name
Test status
Simulation time 639480842 ps
CPU time 4.63 seconds
Started Aug 07 06:17:34 PM PDT 24
Finished Aug 07 06:17:39 PM PDT 24
Peak memory 208184 kb
Host smart-48a376f5-24e0-43c9-b87a-f12c02ac52dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271353378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2271353378
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1555208052
Short name T738
Test name
Test status
Simulation time 357453472 ps
CPU time 6.54 seconds
Started Aug 07 06:17:35 PM PDT 24
Finished Aug 07 06:17:42 PM PDT 24
Peak memory 208848 kb
Host smart-73269bf0-19f8-4519-98a2-76baf3226b10
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555208052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1555208052
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1117624440
Short name T309
Test name
Test status
Simulation time 166663115 ps
CPU time 2.5 seconds
Started Aug 07 06:17:34 PM PDT 24
Finished Aug 07 06:17:36 PM PDT 24
Peak memory 208916 kb
Host smart-f1ebc82f-300c-4aa0-bd1d-e4bf4830a4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117624440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1117624440
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.161905854
Short name T429
Test name
Test status
Simulation time 260752274 ps
CPU time 4.54 seconds
Started Aug 07 06:17:35 PM PDT 24
Finished Aug 07 06:17:39 PM PDT 24
Peak memory 206780 kb
Host smart-da603725-0365-431a-a492-25e5c9f0a878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161905854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.161905854
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.956826776
Short name T213
Test name
Test status
Simulation time 2931717291 ps
CPU time 68.07 seconds
Started Aug 07 06:17:40 PM PDT 24
Finished Aug 07 06:18:48 PM PDT 24
Peak memory 216544 kb
Host smart-34b15df0-ee6a-49f4-895b-032908398db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956826776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.956826776
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2624937528
Short name T167
Test name
Test status
Simulation time 413833084 ps
CPU time 17.62 seconds
Started Aug 07 06:17:42 PM PDT 24
Finished Aug 07 06:18:00 PM PDT 24
Peak memory 222512 kb
Host smart-fda19732-bc2d-46f0-9c71-e226862a0b68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624937528 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2624937528
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3758566645
Short name T713
Test name
Test status
Simulation time 351048384 ps
CPU time 4.21 seconds
Started Aug 07 06:17:32 PM PDT 24
Finished Aug 07 06:17:37 PM PDT 24
Peak memory 208808 kb
Host smart-e16951e1-7d44-45b3-ad1f-ae5152247c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758566645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3758566645
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.853840856
Short name T370
Test name
Test status
Simulation time 99416612 ps
CPU time 2.33 seconds
Started Aug 07 06:17:38 PM PDT 24
Finished Aug 07 06:17:41 PM PDT 24
Peak memory 210084 kb
Host smart-4956a2c8-9f94-40c1-8fc8-daa5ba9d0465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853840856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.853840856
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3320570326
Short name T889
Test name
Test status
Simulation time 1003469348 ps
CPU time 4.26 seconds
Started Aug 07 06:17:38 PM PDT 24
Finished Aug 07 06:17:43 PM PDT 24
Peak memory 214352 kb
Host smart-ee01c0b4-d171-45ea-a5e8-6c7e8576c679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3320570326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3320570326
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1138442676
Short name T288
Test name
Test status
Simulation time 6272514044 ps
CPU time 16.27 seconds
Started Aug 07 06:17:40 PM PDT 24
Finished Aug 07 06:17:56 PM PDT 24
Peak memory 214372 kb
Host smart-ff40d676-24c5-4900-8ce0-bb7635320e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138442676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1138442676
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2789507216
Short name T66
Test name
Test status
Simulation time 285221378 ps
CPU time 4.05 seconds
Started Aug 07 06:17:40 PM PDT 24
Finished Aug 07 06:17:44 PM PDT 24
Peak memory 207792 kb
Host smart-73822391-9b3f-40ac-a0d2-b1e63a8b1671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789507216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2789507216
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3003219483
Short name T223
Test name
Test status
Simulation time 34144485 ps
CPU time 2.45 seconds
Started Aug 07 06:17:43 PM PDT 24
Finished Aug 07 06:17:45 PM PDT 24
Peak memory 208248 kb
Host smart-186fdcab-46e0-49a9-8f42-10cb037b0789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003219483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3003219483
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2529288776
Short name T632
Test name
Test status
Simulation time 114293002 ps
CPU time 3.31 seconds
Started Aug 07 06:17:43 PM PDT 24
Finished Aug 07 06:17:46 PM PDT 24
Peak memory 208748 kb
Host smart-5bea9bcb-91b5-4bb4-a9e7-551e2c0e49bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529288776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2529288776
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1779593004
Short name T817
Test name
Test status
Simulation time 42149005 ps
CPU time 1.85 seconds
Started Aug 07 06:17:40 PM PDT 24
Finished Aug 07 06:17:42 PM PDT 24
Peak memory 207352 kb
Host smart-b3fffdd7-86ed-44fe-8060-bf0df30a432f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779593004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1779593004
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3347819630
Short name T710
Test name
Test status
Simulation time 287938849 ps
CPU time 3.42 seconds
Started Aug 07 06:17:39 PM PDT 24
Finished Aug 07 06:17:43 PM PDT 24
Peak memory 208476 kb
Host smart-ffab6465-a542-49de-98f9-b439a3d02b89
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347819630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3347819630
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1836853076
Short name T106
Test name
Test status
Simulation time 110973903 ps
CPU time 3.65 seconds
Started Aug 07 06:17:40 PM PDT 24
Finished Aug 07 06:17:44 PM PDT 24
Peak memory 208280 kb
Host smart-8a802916-e9a7-4363-bca3-67f0ec787338
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836853076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1836853076
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2014176334
Short name T875
Test name
Test status
Simulation time 539562954 ps
CPU time 4.4 seconds
Started Aug 07 06:17:48 PM PDT 24
Finished Aug 07 06:17:53 PM PDT 24
Peak memory 215440 kb
Host smart-00062770-3aac-4a55-9bd5-8a93c8e2094e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014176334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2014176334
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3200209696
Short name T753
Test name
Test status
Simulation time 86926397 ps
CPU time 3.08 seconds
Started Aug 07 06:17:42 PM PDT 24
Finished Aug 07 06:17:46 PM PDT 24
Peak memory 206876 kb
Host smart-d3bbd27a-633b-4de7-94a4-6b1b1d4aa0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200209696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3200209696
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1722042951
Short name T259
Test name
Test status
Simulation time 633299732 ps
CPU time 26.37 seconds
Started Aug 07 06:17:45 PM PDT 24
Finished Aug 07 06:18:11 PM PDT 24
Peak memory 219632 kb
Host smart-39a8ddb5-7b7a-45b4-aabc-a1a3553bf955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722042951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1722042951
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2106566350
Short name T183
Test name
Test status
Simulation time 1005660707 ps
CPU time 11.18 seconds
Started Aug 07 06:17:40 PM PDT 24
Finished Aug 07 06:17:51 PM PDT 24
Peak memory 209552 kb
Host smart-00c47ec1-9c9b-47e8-a0da-8096e10039a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106566350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2106566350
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2990212640
Short name T683
Test name
Test status
Simulation time 45795641 ps
CPU time 2.4 seconds
Started Aug 07 06:17:48 PM PDT 24
Finished Aug 07 06:17:51 PM PDT 24
Peak memory 209800 kb
Host smart-b1336c4b-bf93-4e5f-bda7-e6019d48f8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990212640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2990212640
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3177527176
Short name T906
Test name
Test status
Simulation time 98220231 ps
CPU time 0.75 seconds
Started Aug 07 06:17:48 PM PDT 24
Finished Aug 07 06:17:49 PM PDT 24
Peak memory 206048 kb
Host smart-55619667-940d-4895-b296-3e7a966b5b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177527176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3177527176
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.890043755
Short name T257
Test name
Test status
Simulation time 221461398 ps
CPU time 3.96 seconds
Started Aug 07 06:17:48 PM PDT 24
Finished Aug 07 06:17:53 PM PDT 24
Peak memory 214328 kb
Host smart-0e1a7972-1873-46fa-b13f-e3119c14e285
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890043755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.890043755
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1735298704
Short name T21
Test name
Test status
Simulation time 86200185 ps
CPU time 2.17 seconds
Started Aug 07 06:17:47 PM PDT 24
Finished Aug 07 06:17:49 PM PDT 24
Peak memory 221460 kb
Host smart-4cd5e0e5-2d12-4ca7-8c64-81d578fd0f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735298704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1735298704
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1600847045
Short name T50
Test name
Test status
Simulation time 62446994 ps
CPU time 1.84 seconds
Started Aug 07 06:17:46 PM PDT 24
Finished Aug 07 06:17:48 PM PDT 24
Peak memory 208960 kb
Host smart-512e705f-e1c6-45f3-abf3-55508ffea6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600847045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1600847045
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3736863441
Short name T248
Test name
Test status
Simulation time 691472985 ps
CPU time 3.96 seconds
Started Aug 07 06:17:44 PM PDT 24
Finished Aug 07 06:17:48 PM PDT 24
Peak memory 215700 kb
Host smart-8d947747-380e-4f54-983f-571531f9196c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736863441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3736863441
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3683320446
Short name T246
Test name
Test status
Simulation time 271672315 ps
CPU time 3.75 seconds
Started Aug 07 06:17:46 PM PDT 24
Finished Aug 07 06:17:50 PM PDT 24
Peak memory 214348 kb
Host smart-30ad6eed-db4e-4187-9cd9-e57a8abe175c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683320446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3683320446
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.234848792
Short name T425
Test name
Test status
Simulation time 268182207 ps
CPU time 5.4 seconds
Started Aug 07 06:17:45 PM PDT 24
Finished Aug 07 06:17:50 PM PDT 24
Peak memory 214420 kb
Host smart-be0c804a-c771-4af1-a23d-5aa1badd417c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234848792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.234848792
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.442466955
Short name T793
Test name
Test status
Simulation time 4331204477 ps
CPU time 60.11 seconds
Started Aug 07 06:17:46 PM PDT 24
Finished Aug 07 06:18:46 PM PDT 24
Peak memory 219060 kb
Host smart-4c98a023-b109-478e-8dbb-53d6b29835d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442466955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.442466955
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.367509462
Short name T660
Test name
Test status
Simulation time 200741900 ps
CPU time 3.05 seconds
Started Aug 07 06:17:45 PM PDT 24
Finished Aug 07 06:17:48 PM PDT 24
Peak memory 208524 kb
Host smart-96f471ce-19e9-42e9-b5f3-5b8aea5611f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367509462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.367509462
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1190895428
Short name T635
Test name
Test status
Simulation time 1536647503 ps
CPU time 16.33 seconds
Started Aug 07 06:17:47 PM PDT 24
Finished Aug 07 06:18:03 PM PDT 24
Peak memory 209196 kb
Host smart-05a758be-0c41-4835-8dc4-5e00705549f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190895428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1190895428
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3537846689
Short name T854
Test name
Test status
Simulation time 61810450 ps
CPU time 2.16 seconds
Started Aug 07 06:17:48 PM PDT 24
Finished Aug 07 06:17:51 PM PDT 24
Peak memory 207012 kb
Host smart-80e4baa6-3df3-4638-87e3-3136e4c3e5b0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537846689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3537846689
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3073832531
Short name T538
Test name
Test status
Simulation time 847390656 ps
CPU time 3.3 seconds
Started Aug 07 06:17:44 PM PDT 24
Finished Aug 07 06:17:47 PM PDT 24
Peak memory 206820 kb
Host smart-d3efe42e-9aef-45ea-805c-9c48604be983
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073832531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3073832531
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.758200494
Short name T528
Test name
Test status
Simulation time 158982392 ps
CPU time 3.57 seconds
Started Aug 07 06:17:48 PM PDT 24
Finished Aug 07 06:17:52 PM PDT 24
Peak memory 220644 kb
Host smart-01baebc8-45a0-4b79-b1d4-ecf2bc5f97b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758200494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.758200494
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.582707866
Short name T542
Test name
Test status
Simulation time 25049557 ps
CPU time 1.93 seconds
Started Aug 07 06:17:47 PM PDT 24
Finished Aug 07 06:17:49 PM PDT 24
Peak memory 208508 kb
Host smart-d26ede14-386c-4eb9-8f10-e3221e9d67b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582707866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.582707866
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2264619009
Short name T606
Test name
Test status
Simulation time 1498247045 ps
CPU time 4.16 seconds
Started Aug 07 06:17:47 PM PDT 24
Finished Aug 07 06:17:51 PM PDT 24
Peak memory 207304 kb
Host smart-554164ea-8feb-4100-b79a-e4cb0fccb069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264619009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2264619009
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2457467924
Short name T565
Test name
Test status
Simulation time 1380461398 ps
CPU time 6.92 seconds
Started Aug 07 06:17:46 PM PDT 24
Finished Aug 07 06:17:53 PM PDT 24
Peak memory 211132 kb
Host smart-3344a944-1d76-4cf8-b822-15beb3bb21c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457467924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2457467924
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3671971145
Short name T436
Test name
Test status
Simulation time 22713071 ps
CPU time 0.81 seconds
Started Aug 07 06:17:51 PM PDT 24
Finished Aug 07 06:17:52 PM PDT 24
Peak memory 205960 kb
Host smart-6d05b955-2bf3-46f8-9625-ffd36d96b818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671971145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3671971145
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1698720253
Short name T396
Test name
Test status
Simulation time 60632253 ps
CPU time 3.28 seconds
Started Aug 07 06:17:46 PM PDT 24
Finished Aug 07 06:17:49 PM PDT 24
Peak memory 215272 kb
Host smart-a2c3865f-7748-4960-9326-d83b46261f7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1698720253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1698720253
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1493673352
Short name T212
Test name
Test status
Simulation time 191778677 ps
CPU time 3.46 seconds
Started Aug 07 06:17:47 PM PDT 24
Finished Aug 07 06:17:51 PM PDT 24
Peak memory 209512 kb
Host smart-3d4e453d-99a7-4449-846d-281cb4510538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493673352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1493673352
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2467424
Short name T858
Test name
Test status
Simulation time 438993747 ps
CPU time 4.63 seconds
Started Aug 07 06:17:48 PM PDT 24
Finished Aug 07 06:17:53 PM PDT 24
Peak memory 210332 kb
Host smart-447d5900-d1b1-4861-a63a-e91662ada9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2467424
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2461361936
Short name T841
Test name
Test status
Simulation time 146661728 ps
CPU time 3.96 seconds
Started Aug 07 06:17:47 PM PDT 24
Finished Aug 07 06:17:51 PM PDT 24
Peak memory 214348 kb
Host smart-dd156b63-2f50-44dc-ac43-824308c7c0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461361936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2461361936
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.157596023
Short name T607
Test name
Test status
Simulation time 245090975 ps
CPU time 2.29 seconds
Started Aug 07 06:17:47 PM PDT 24
Finished Aug 07 06:17:49 PM PDT 24
Peak memory 214288 kb
Host smart-6020fb45-3298-4b1c-9c73-09db47a29233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157596023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.157596023
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2626891461
Short name T321
Test name
Test status
Simulation time 71186273 ps
CPU time 2.68 seconds
Started Aug 07 06:17:48 PM PDT 24
Finished Aug 07 06:17:51 PM PDT 24
Peak memory 222580 kb
Host smart-4957cc4d-7241-4fd4-b1d9-b2e8712cda6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626891461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2626891461
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.485315228
Short name T497
Test name
Test status
Simulation time 326214299 ps
CPU time 4.6 seconds
Started Aug 07 06:17:48 PM PDT 24
Finished Aug 07 06:17:53 PM PDT 24
Peak memory 214320 kb
Host smart-bb214864-1e2c-46d3-be07-294d47d3b48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485315228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.485315228
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.41960562
Short name T19
Test name
Test status
Simulation time 147298293 ps
CPU time 1.66 seconds
Started Aug 07 06:17:46 PM PDT 24
Finished Aug 07 06:17:47 PM PDT 24
Peak memory 206776 kb
Host smart-30b698d0-fead-41d9-8945-2fb894a15697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41960562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.41960562
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.4061119593
Short name T476
Test name
Test status
Simulation time 124227861 ps
CPU time 3.24 seconds
Started Aug 07 06:17:48 PM PDT 24
Finished Aug 07 06:17:52 PM PDT 24
Peak memory 207296 kb
Host smart-8c7b5d8b-1a45-442a-8f5b-16257e59959a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061119593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.4061119593
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1288929410
Short name T383
Test name
Test status
Simulation time 62134596 ps
CPU time 3.41 seconds
Started Aug 07 06:17:45 PM PDT 24
Finished Aug 07 06:17:48 PM PDT 24
Peak memory 208976 kb
Host smart-2c9c5f02-fdb8-4407-a881-bfdf7d3908ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288929410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1288929410
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.176977584
Short name T438
Test name
Test status
Simulation time 452880710 ps
CPU time 2.28 seconds
Started Aug 07 06:17:46 PM PDT 24
Finished Aug 07 06:17:49 PM PDT 24
Peak memory 208564 kb
Host smart-abf19848-1775-412d-9271-0fa42d59019f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176977584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.176977584
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1426441561
Short name T666
Test name
Test status
Simulation time 723516143 ps
CPU time 7.07 seconds
Started Aug 07 06:17:46 PM PDT 24
Finished Aug 07 06:17:53 PM PDT 24
Peak memory 208732 kb
Host smart-668d3c0e-d374-443b-9802-0c085c95b229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426441561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1426441561
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2565710712
Short name T179
Test name
Test status
Simulation time 5986211066 ps
CPU time 69.05 seconds
Started Aug 07 06:17:56 PM PDT 24
Finished Aug 07 06:19:06 PM PDT 24
Peak memory 216752 kb
Host smart-edc95ec2-168c-4036-9c7a-c7dbba80be74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565710712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2565710712
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.351470281
Short name T120
Test name
Test status
Simulation time 247961164 ps
CPU time 9.06 seconds
Started Aug 07 06:17:57 PM PDT 24
Finished Aug 07 06:18:06 PM PDT 24
Peak memory 220128 kb
Host smart-7861edde-0677-469c-b768-3dcff4c291e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351470281 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.351470281
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.624805922
Short name T908
Test name
Test status
Simulation time 239739254 ps
CPU time 6.5 seconds
Started Aug 07 06:17:49 PM PDT 24
Finished Aug 07 06:17:56 PM PDT 24
Peak memory 209328 kb
Host smart-ca4170eb-79d4-4b07-a3ec-e44b809ab245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624805922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.624805922
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1137435277
Short name T163
Test name
Test status
Simulation time 73828218 ps
CPU time 1.99 seconds
Started Aug 07 06:17:48 PM PDT 24
Finished Aug 07 06:17:50 PM PDT 24
Peak memory 210056 kb
Host smart-49ab37d6-121c-4e91-9d8e-3859ec966600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137435277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1137435277
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3502042008
Short name T862
Test name
Test status
Simulation time 20937553 ps
CPU time 0.88 seconds
Started Aug 07 06:17:50 PM PDT 24
Finished Aug 07 06:17:51 PM PDT 24
Peak memory 205984 kb
Host smart-985768a1-7ed0-4d03-bb87-45135f71a231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502042008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3502042008
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2726577534
Short name T360
Test name
Test status
Simulation time 113152062 ps
CPU time 2.58 seconds
Started Aug 07 06:17:50 PM PDT 24
Finished Aug 07 06:17:53 PM PDT 24
Peak memory 214348 kb
Host smart-28aee6b6-ddcd-4ee8-b0ae-81cd1d8eaa39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726577534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2726577534
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2524126107
Short name T63
Test name
Test status
Simulation time 91691390 ps
CPU time 3.9 seconds
Started Aug 07 06:17:51 PM PDT 24
Finished Aug 07 06:17:55 PM PDT 24
Peak memory 218792 kb
Host smart-b042ee96-4a46-48f4-807b-4cda54c76866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524126107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2524126107
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1886829644
Short name T726
Test name
Test status
Simulation time 30425809 ps
CPU time 1.3 seconds
Started Aug 07 06:17:52 PM PDT 24
Finished Aug 07 06:17:53 PM PDT 24
Peak memory 207528 kb
Host smart-73026d46-8c5d-4b2f-9d34-13aad50b2304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886829644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1886829644
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3743016610
Short name T253
Test name
Test status
Simulation time 199016264 ps
CPU time 2.21 seconds
Started Aug 07 06:17:50 PM PDT 24
Finished Aug 07 06:17:52 PM PDT 24
Peak memory 214468 kb
Host smart-f2dd9481-0a6e-4658-932e-a8de65fbd28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743016610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3743016610
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.376229348
Short name T837
Test name
Test status
Simulation time 176441586 ps
CPU time 2.14 seconds
Started Aug 07 06:17:52 PM PDT 24
Finished Aug 07 06:17:54 PM PDT 24
Peak memory 221688 kb
Host smart-2618ab64-2ba1-4f41-aebe-ec5ae5f91d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376229348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.376229348
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.784244525
Short name T124
Test name
Test status
Simulation time 159072434 ps
CPU time 4.92 seconds
Started Aug 07 06:17:56 PM PDT 24
Finished Aug 07 06:18:01 PM PDT 24
Peak memory 222520 kb
Host smart-e0787a3e-4d29-4b33-9f3c-aa8c4a7fd476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784244525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.784244525
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1340128945
Short name T107
Test name
Test status
Simulation time 155220146 ps
CPU time 2.92 seconds
Started Aug 07 06:17:52 PM PDT 24
Finished Aug 07 06:17:55 PM PDT 24
Peak memory 210012 kb
Host smart-6620e989-be56-4083-a975-a51c9043fa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340128945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1340128945
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1804837886
Short name T758
Test name
Test status
Simulation time 149644263 ps
CPU time 5.85 seconds
Started Aug 07 06:17:52 PM PDT 24
Finished Aug 07 06:17:58 PM PDT 24
Peak memory 206988 kb
Host smart-53fbfab6-9903-4cec-b9ec-1aed953535f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804837886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1804837886
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3186997722
Short name T515
Test name
Test status
Simulation time 21993929 ps
CPU time 1.82 seconds
Started Aug 07 06:17:53 PM PDT 24
Finished Aug 07 06:17:55 PM PDT 24
Peak memory 206952 kb
Host smart-02855419-9b2e-40d7-ae29-72818c5c4603
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186997722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3186997722
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.4088460539
Short name T804
Test name
Test status
Simulation time 61259585 ps
CPU time 3.19 seconds
Started Aug 07 06:17:53 PM PDT 24
Finished Aug 07 06:17:56 PM PDT 24
Peak memory 207372 kb
Host smart-b1d47188-d007-423d-8fe1-011e4c2980a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088460539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4088460539
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1565268789
Short name T696
Test name
Test status
Simulation time 1450208827 ps
CPU time 20.03 seconds
Started Aug 07 06:17:55 PM PDT 24
Finished Aug 07 06:18:16 PM PDT 24
Peak memory 208916 kb
Host smart-0eb55249-db15-4298-b7ac-3ef8b2c100e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565268789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1565268789
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3327070262
Short name T587
Test name
Test status
Simulation time 558606323 ps
CPU time 4.35 seconds
Started Aug 07 06:17:52 PM PDT 24
Finished Aug 07 06:17:57 PM PDT 24
Peak memory 218356 kb
Host smart-b0f5137a-0592-4651-b18e-4e6eba2bba18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327070262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3327070262
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3369210829
Short name T723
Test name
Test status
Simulation time 175333498 ps
CPU time 2.29 seconds
Started Aug 07 06:17:51 PM PDT 24
Finished Aug 07 06:17:54 PM PDT 24
Peak memory 206908 kb
Host smart-a19ec600-0c16-4895-bb7c-4281280e089b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369210829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3369210829
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.4034045965
Short name T262
Test name
Test status
Simulation time 2146191454 ps
CPU time 16.42 seconds
Started Aug 07 06:17:51 PM PDT 24
Finished Aug 07 06:18:08 PM PDT 24
Peak memory 216824 kb
Host smart-6e9445fb-8344-445a-91a5-98c6e129a392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034045965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.4034045965
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.940660702
Short name T707
Test name
Test status
Simulation time 33998281 ps
CPU time 2.26 seconds
Started Aug 07 06:17:52 PM PDT 24
Finished Aug 07 06:17:54 PM PDT 24
Peak memory 207712 kb
Host smart-fb3ee094-b4b6-4513-9ecb-2656824889ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940660702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.940660702
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1540862228
Short name T376
Test name
Test status
Simulation time 84120234 ps
CPU time 2.37 seconds
Started Aug 07 06:17:52 PM PDT 24
Finished Aug 07 06:17:55 PM PDT 24
Peak memory 210328 kb
Host smart-aaee03b5-2265-407f-bd38-d5d79817faa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540862228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1540862228
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3844145743
Short name T888
Test name
Test status
Simulation time 41786971 ps
CPU time 0.78 seconds
Started Aug 07 06:18:00 PM PDT 24
Finished Aug 07 06:18:01 PM PDT 24
Peak memory 205988 kb
Host smart-182efdad-cf3d-4a8e-a161-bbb6bfa6b332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844145743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3844145743
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2414090238
Short name T380
Test name
Test status
Simulation time 54394930 ps
CPU time 2.34 seconds
Started Aug 07 06:17:56 PM PDT 24
Finished Aug 07 06:17:59 PM PDT 24
Peak memory 214332 kb
Host smart-eaabf978-e8f6-4207-bed9-3919bb3774e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414090238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2414090238
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1976958615
Short name T755
Test name
Test status
Simulation time 2773543580 ps
CPU time 24.72 seconds
Started Aug 07 06:18:00 PM PDT 24
Finished Aug 07 06:18:25 PM PDT 24
Peak memory 217752 kb
Host smart-b782e2c9-116f-4c9a-aa67-755ece937e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976958615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1976958615
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2508951752
Short name T749
Test name
Test status
Simulation time 586854651 ps
CPU time 1.99 seconds
Started Aug 07 06:18:04 PM PDT 24
Finished Aug 07 06:18:06 PM PDT 24
Peak memory 208908 kb
Host smart-b4b1cd2b-a77d-453c-bb6a-09656b12dd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508951752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2508951752
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3656326055
Short name T608
Test name
Test status
Simulation time 103992100 ps
CPU time 1.98 seconds
Started Aug 07 06:17:59 PM PDT 24
Finished Aug 07 06:18:01 PM PDT 24
Peak memory 214336 kb
Host smart-0d417fdf-a430-4649-b34f-5742b1c63da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656326055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3656326055
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1915798585
Short name T868
Test name
Test status
Simulation time 41566420 ps
CPU time 2.42 seconds
Started Aug 07 06:17:58 PM PDT 24
Finished Aug 07 06:18:01 PM PDT 24
Peak memory 214308 kb
Host smart-45f6f5bc-52de-41eb-87ad-e727333c7440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915798585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1915798585
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1408420876
Short name T468
Test name
Test status
Simulation time 260000121 ps
CPU time 3.2 seconds
Started Aug 07 06:17:58 PM PDT 24
Finished Aug 07 06:18:01 PM PDT 24
Peak memory 207424 kb
Host smart-9555b4a8-4420-48c2-99cc-e094fa776131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408420876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1408420876
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2154105502
Short name T324
Test name
Test status
Simulation time 514088300 ps
CPU time 6.35 seconds
Started Aug 07 06:17:58 PM PDT 24
Finished Aug 07 06:18:04 PM PDT 24
Peak memory 206924 kb
Host smart-7f2d6ca8-485b-4b43-8e1a-b770c2683e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154105502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2154105502
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2538505600
Short name T573
Test name
Test status
Simulation time 367053340 ps
CPU time 4.32 seconds
Started Aug 07 06:17:58 PM PDT 24
Finished Aug 07 06:18:03 PM PDT 24
Peak memory 207112 kb
Host smart-1b318ffe-c397-4b5a-93ca-1f7144347c41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538505600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2538505600
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2320718981
Short name T799
Test name
Test status
Simulation time 195196972 ps
CPU time 6.89 seconds
Started Aug 07 06:17:59 PM PDT 24
Finished Aug 07 06:18:06 PM PDT 24
Peak memory 208524 kb
Host smart-a506e91b-f4d8-4300-8d3b-249c3831e875
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320718981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2320718981
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1600085268
Short name T443
Test name
Test status
Simulation time 1907562746 ps
CPU time 7.08 seconds
Started Aug 07 06:17:58 PM PDT 24
Finished Aug 07 06:18:06 PM PDT 24
Peak memory 208516 kb
Host smart-916a6c82-f633-4198-9176-16c246e2558c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600085268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1600085268
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3954934732
Short name T821
Test name
Test status
Simulation time 100464710 ps
CPU time 1.72 seconds
Started Aug 07 06:17:57 PM PDT 24
Finished Aug 07 06:17:59 PM PDT 24
Peak memory 208840 kb
Host smart-ed012b75-539a-4434-b189-ac0ed43e4c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954934732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3954934732
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3757532250
Short name T186
Test name
Test status
Simulation time 4218587410 ps
CPU time 18.46 seconds
Started Aug 07 06:17:53 PM PDT 24
Finished Aug 07 06:18:12 PM PDT 24
Peak memory 208592 kb
Host smart-f186c6dd-ed87-407a-8563-6310c041b628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757532250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3757532250
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1345361544
Short name T850
Test name
Test status
Simulation time 13286705753 ps
CPU time 50.09 seconds
Started Aug 07 06:18:04 PM PDT 24
Finished Aug 07 06:18:54 PM PDT 24
Peak memory 220588 kb
Host smart-631435a6-e90b-4d0b-9c95-791576decd77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345361544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1345361544
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3055329113
Short name T693
Test name
Test status
Simulation time 688287423 ps
CPU time 4.85 seconds
Started Aug 07 06:17:58 PM PDT 24
Finished Aug 07 06:18:03 PM PDT 24
Peak memory 208176 kb
Host smart-43a9fb2b-dbbc-4ea6-927a-dcaba3b2ae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055329113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3055329113
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2595724304
Short name T557
Test name
Test status
Simulation time 40806810 ps
CPU time 2.16 seconds
Started Aug 07 06:17:57 PM PDT 24
Finished Aug 07 06:18:00 PM PDT 24
Peak memory 214324 kb
Host smart-344617b6-ed78-495c-a322-1b11a48ebc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595724304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2595724304
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1463719866
Short name T401
Test name
Test status
Simulation time 10529257 ps
CPU time 0.75 seconds
Started Aug 07 06:17:57 PM PDT 24
Finished Aug 07 06:17:57 PM PDT 24
Peak memory 205960 kb
Host smart-a797fb0e-d7fc-409a-ad13-02b54e5c9777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463719866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1463719866
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2751095821
Short name T237
Test name
Test status
Simulation time 41991431 ps
CPU time 3.5 seconds
Started Aug 07 06:17:58 PM PDT 24
Finished Aug 07 06:18:02 PM PDT 24
Peak memory 215464 kb
Host smart-fe887edd-c5ec-497a-9146-54198a3fe8a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751095821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2751095821
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3145685393
Short name T759
Test name
Test status
Simulation time 196359000 ps
CPU time 4.23 seconds
Started Aug 07 06:17:59 PM PDT 24
Finished Aug 07 06:18:03 PM PDT 24
Peak memory 210272 kb
Host smart-333a18a1-7279-40dd-b79b-50cd5df29bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145685393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3145685393
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2006252785
Short name T18
Test name
Test status
Simulation time 1623745619 ps
CPU time 17.26 seconds
Started Aug 07 06:17:59 PM PDT 24
Finished Aug 07 06:18:16 PM PDT 24
Peak memory 214348 kb
Host smart-ec681384-3529-474e-b1c6-9ceee936bc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006252785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2006252785
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3856724667
Short name T824
Test name
Test status
Simulation time 1933344576 ps
CPU time 27.2 seconds
Started Aug 07 06:17:58 PM PDT 24
Finished Aug 07 06:18:26 PM PDT 24
Peak memory 214404 kb
Host smart-5eab735f-583f-4258-8e20-3c0bd3e2930e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856724667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3856724667
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.44966375
Short name T250
Test name
Test status
Simulation time 67132987 ps
CPU time 2.43 seconds
Started Aug 07 06:18:00 PM PDT 24
Finished Aug 07 06:18:03 PM PDT 24
Peak memory 214392 kb
Host smart-b9530e2d-263e-4439-9d49-22109dda6ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44966375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.44966375
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.379271547
Short name T204
Test name
Test status
Simulation time 142856645 ps
CPU time 3.35 seconds
Started Aug 07 06:17:57 PM PDT 24
Finished Aug 07 06:18:01 PM PDT 24
Peak memory 222512 kb
Host smart-4f6670e7-de7b-4817-8d24-629ca949cdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379271547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.379271547
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1617543803
Short name T493
Test name
Test status
Simulation time 46912427 ps
CPU time 1.93 seconds
Started Aug 07 06:18:04 PM PDT 24
Finished Aug 07 06:18:06 PM PDT 24
Peak memory 207564 kb
Host smart-392e85e9-a5aa-49dc-b9a6-6cdcef12c68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617543803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1617543803
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3495583138
Short name T475
Test name
Test status
Simulation time 44159947 ps
CPU time 2.44 seconds
Started Aug 07 06:18:00 PM PDT 24
Finished Aug 07 06:18:03 PM PDT 24
Peak memory 207192 kb
Host smart-e52fbecc-78bc-49cc-89c7-4c1f9f255dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495583138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3495583138
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.371484629
Short name T752
Test name
Test status
Simulation time 354471717 ps
CPU time 9.3 seconds
Started Aug 07 06:18:00 PM PDT 24
Finished Aug 07 06:18:10 PM PDT 24
Peak memory 208560 kb
Host smart-71b02242-c45d-4621-87f9-03555b3c7787
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371484629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.371484629
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3453148692
Short name T884
Test name
Test status
Simulation time 65041338 ps
CPU time 3.05 seconds
Started Aug 07 06:18:00 PM PDT 24
Finished Aug 07 06:18:03 PM PDT 24
Peak memory 208116 kb
Host smart-1daf6dd5-af36-47b4-9940-29990bef0593
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453148692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3453148692
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3344664496
Short name T795
Test name
Test status
Simulation time 702883756 ps
CPU time 5.9 seconds
Started Aug 07 06:17:57 PM PDT 24
Finished Aug 07 06:18:03 PM PDT 24
Peak memory 208768 kb
Host smart-ffa0e42c-e70f-4a29-a952-a4a1bfe579a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344664496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3344664496
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2938882651
Short name T575
Test name
Test status
Simulation time 101572346 ps
CPU time 4.49 seconds
Started Aug 07 06:18:05 PM PDT 24
Finished Aug 07 06:18:10 PM PDT 24
Peak memory 214292 kb
Host smart-6deae6ba-9d50-43bc-8ae8-22e23ec4822e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938882651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2938882651
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.950578058
Short name T785
Test name
Test status
Simulation time 626955970 ps
CPU time 3.8 seconds
Started Aug 07 06:17:56 PM PDT 24
Finished Aug 07 06:18:00 PM PDT 24
Peak memory 206832 kb
Host smart-fb451218-69dd-459e-8370-04c7f6285179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950578058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.950578058
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3615521594
Short name T258
Test name
Test status
Simulation time 9673314745 ps
CPU time 76.32 seconds
Started Aug 07 06:18:04 PM PDT 24
Finished Aug 07 06:19:21 PM PDT 24
Peak memory 217012 kb
Host smart-51448a80-aa2d-4fa2-918a-beae42733092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615521594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3615521594
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3295599277
Short name T169
Test name
Test status
Simulation time 399776796 ps
CPU time 14.77 seconds
Started Aug 07 06:17:58 PM PDT 24
Finished Aug 07 06:18:13 PM PDT 24
Peak memory 222600 kb
Host smart-fd8a7e58-3e22-4983-933b-bb820d0e6139
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295599277 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3295599277
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4000323940
Short name T791
Test name
Test status
Simulation time 489204719 ps
CPU time 9.58 seconds
Started Aug 07 06:18:00 PM PDT 24
Finished Aug 07 06:18:09 PM PDT 24
Peak memory 207772 kb
Host smart-ffc55a16-6063-40b9-8ce5-ecca072ff001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000323940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4000323940
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1598308802
Short name T727
Test name
Test status
Simulation time 10312995 ps
CPU time 0.71 seconds
Started Aug 07 06:18:04 PM PDT 24
Finished Aug 07 06:18:05 PM PDT 24
Peak memory 205980 kb
Host smart-76794d22-c054-446c-b831-977ca11b7d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598308802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1598308802
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3192819474
Short name T123
Test name
Test status
Simulation time 221449785 ps
CPU time 4.07 seconds
Started Aug 07 06:18:04 PM PDT 24
Finished Aug 07 06:18:09 PM PDT 24
Peak memory 214628 kb
Host smart-feed2fcd-09aa-4ab7-9159-373561dd6805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3192819474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3192819474
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2177146072
Short name T30
Test name
Test status
Simulation time 179432783 ps
CPU time 3.46 seconds
Started Aug 07 06:18:05 PM PDT 24
Finished Aug 07 06:18:08 PM PDT 24
Peak memory 206280 kb
Host smart-0e8db347-f22f-4a54-b6ba-9cb79ce709e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177146072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2177146072
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1297117855
Short name T68
Test name
Test status
Simulation time 175010506 ps
CPU time 1.96 seconds
Started Aug 07 06:18:04 PM PDT 24
Finished Aug 07 06:18:06 PM PDT 24
Peak memory 207700 kb
Host smart-5f17d848-2c60-4408-ac0d-f715660da0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297117855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1297117855
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3551357355
Short name T739
Test name
Test status
Simulation time 114613357 ps
CPU time 5.39 seconds
Started Aug 07 06:18:05 PM PDT 24
Finished Aug 07 06:18:11 PM PDT 24
Peak memory 214280 kb
Host smart-9bdb2d81-7c46-478a-b9e8-358b6a7d1afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551357355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3551357355
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3157687769
Short name T485
Test name
Test status
Simulation time 542914366 ps
CPU time 3.28 seconds
Started Aug 07 06:18:05 PM PDT 24
Finished Aug 07 06:18:09 PM PDT 24
Peak memory 209832 kb
Host smart-60a0e4f6-fa5c-46fa-86f9-13a96658e47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157687769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3157687769
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2688223330
Short name T708
Test name
Test status
Simulation time 89475370 ps
CPU time 3.98 seconds
Started Aug 07 06:18:07 PM PDT 24
Finished Aug 07 06:18:11 PM PDT 24
Peak memory 208308 kb
Host smart-96acfd0e-d7fa-4187-b2f0-4f224cf8bd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688223330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2688223330
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3825360087
Short name T256
Test name
Test status
Simulation time 128712216 ps
CPU time 4.33 seconds
Started Aug 07 06:18:03 PM PDT 24
Finished Aug 07 06:18:07 PM PDT 24
Peak memory 208904 kb
Host smart-a6075cd2-12c5-426c-8656-c22fb1eb2239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825360087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3825360087
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3538664163
Short name T437
Test name
Test status
Simulation time 18092240537 ps
CPU time 54.56 seconds
Started Aug 07 06:18:04 PM PDT 24
Finished Aug 07 06:18:59 PM PDT 24
Peak memory 208612 kb
Host smart-463052a4-f802-429c-9ecd-3d7edf622fc3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538664163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3538664163
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1252951065
Short name T478
Test name
Test status
Simulation time 2134615563 ps
CPU time 6.98 seconds
Started Aug 07 06:18:03 PM PDT 24
Finished Aug 07 06:18:10 PM PDT 24
Peak memory 208584 kb
Host smart-11b37292-38ec-42b2-bd86-9be5434f3450
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252951065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1252951065
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.988451668
Short name T260
Test name
Test status
Simulation time 157017966 ps
CPU time 4.78 seconds
Started Aug 07 06:18:03 PM PDT 24
Finished Aug 07 06:18:07 PM PDT 24
Peak memory 208680 kb
Host smart-12a79adf-d22a-43b2-b232-25f3c09eca2f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988451668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.988451668
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1357793950
Short name T811
Test name
Test status
Simulation time 312421360 ps
CPU time 3.07 seconds
Started Aug 07 06:18:05 PM PDT 24
Finished Aug 07 06:18:09 PM PDT 24
Peak memory 218268 kb
Host smart-cb45467a-b0eb-4cfd-9608-b6458a252c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357793950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1357793950
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2830796304
Short name T403
Test name
Test status
Simulation time 129988639 ps
CPU time 2.96 seconds
Started Aug 07 06:18:05 PM PDT 24
Finished Aug 07 06:18:08 PM PDT 24
Peak memory 207780 kb
Host smart-fe422acb-fcae-46e9-bbc4-f8dd6214a8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830796304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2830796304
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1245226613
Short name T296
Test name
Test status
Simulation time 108242209 ps
CPU time 7.63 seconds
Started Aug 07 06:18:01 PM PDT 24
Finished Aug 07 06:18:09 PM PDT 24
Peak memory 221824 kb
Host smart-601a0483-d0b7-4a11-be7b-7ee95d8e6172
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245226613 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1245226613
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.958852847
Short name T845
Test name
Test status
Simulation time 65111316 ps
CPU time 4.13 seconds
Started Aug 07 06:18:01 PM PDT 24
Finished Aug 07 06:18:06 PM PDT 24
Peak memory 207876 kb
Host smart-870a64bb-ecfc-4bde-869b-ecd5f55c8da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958852847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.958852847
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.4219343418
Short name T765
Test name
Test status
Simulation time 134622487 ps
CPU time 1.91 seconds
Started Aug 07 06:18:04 PM PDT 24
Finished Aug 07 06:18:06 PM PDT 24
Peak memory 209988 kb
Host smart-95b1d6d5-2189-4618-97b0-3ae746fa531d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219343418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4219343418
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2275560601
Short name T734
Test name
Test status
Simulation time 33480304 ps
CPU time 0.97 seconds
Started Aug 07 06:18:10 PM PDT 24
Finished Aug 07 06:18:11 PM PDT 24
Peak memory 206132 kb
Host smart-f65f7d78-1266-4b88-a41c-c18679083932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275560601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2275560601
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2814151474
Short name T31
Test name
Test status
Simulation time 64716896 ps
CPU time 1.29 seconds
Started Aug 07 06:18:14 PM PDT 24
Finished Aug 07 06:18:15 PM PDT 24
Peak memory 207888 kb
Host smart-d884a794-bf30-4e05-8976-2762b9faa51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814151474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2814151474
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.336441178
Short name T548
Test name
Test status
Simulation time 81465153 ps
CPU time 1.98 seconds
Started Aug 07 06:18:05 PM PDT 24
Finished Aug 07 06:18:07 PM PDT 24
Peak memory 209120 kb
Host smart-18531cd6-e7be-4028-b54c-82e352f9f358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336441178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.336441178
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.896050737
Short name T364
Test name
Test status
Simulation time 51940865 ps
CPU time 2.13 seconds
Started Aug 07 06:18:09 PM PDT 24
Finished Aug 07 06:18:11 PM PDT 24
Peak memory 214368 kb
Host smart-3c9552e7-14c1-48d5-8c15-9733e37298e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896050737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.896050737
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3347286765
Short name T285
Test name
Test status
Simulation time 660303715 ps
CPU time 2.68 seconds
Started Aug 07 06:18:09 PM PDT 24
Finished Aug 07 06:18:12 PM PDT 24
Peak memory 214276 kb
Host smart-f201e851-c806-4774-a52d-269535f02af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347286765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3347286765
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3046382732
Short name T750
Test name
Test status
Simulation time 109154768 ps
CPU time 3.05 seconds
Started Aug 07 06:18:05 PM PDT 24
Finished Aug 07 06:18:08 PM PDT 24
Peak memory 214756 kb
Host smart-f3578f23-abbc-4ca4-8ca3-3733449522a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046382732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3046382732
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.262880735
Short name T745
Test name
Test status
Simulation time 110942262 ps
CPU time 3.18 seconds
Started Aug 07 06:18:05 PM PDT 24
Finished Aug 07 06:18:09 PM PDT 24
Peak memory 207136 kb
Host smart-915bd310-dcf3-4a7b-b34d-d0fc2060f919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262880735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.262880735
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3070516856
Short name T732
Test name
Test status
Simulation time 206508853 ps
CPU time 2.68 seconds
Started Aug 07 06:18:06 PM PDT 24
Finished Aug 07 06:18:08 PM PDT 24
Peak memory 206876 kb
Host smart-3b665fd0-4bb5-4ae6-9b17-f85567785161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070516856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3070516856
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2431833578
Short name T480
Test name
Test status
Simulation time 35015700 ps
CPU time 2.3 seconds
Started Aug 07 06:18:05 PM PDT 24
Finished Aug 07 06:18:07 PM PDT 24
Peak memory 208776 kb
Host smart-3e49b1b7-83a6-4f3e-922a-1cf9f9847f34
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431833578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2431833578
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3931989443
Short name T813
Test name
Test status
Simulation time 51747958 ps
CPU time 2.87 seconds
Started Aug 07 06:18:04 PM PDT 24
Finished Aug 07 06:18:07 PM PDT 24
Peak memory 208872 kb
Host smart-377e537c-5253-4a13-8030-a56441c690f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931989443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3931989443
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.4273900577
Short name T406
Test name
Test status
Simulation time 351726280 ps
CPU time 9.54 seconds
Started Aug 07 06:18:06 PM PDT 24
Finished Aug 07 06:18:15 PM PDT 24
Peak memory 209008 kb
Host smart-4846cf52-c6b3-4018-9049-85464065bb88
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273900577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.4273900577
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.641945648
Short name T685
Test name
Test status
Simulation time 196902037 ps
CPU time 3.09 seconds
Started Aug 07 06:18:08 PM PDT 24
Finished Aug 07 06:18:11 PM PDT 24
Peak memory 218452 kb
Host smart-94d0e2a0-a785-4c7f-bc6a-a1ca265bd065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641945648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.641945648
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2347537606
Short name T534
Test name
Test status
Simulation time 449476621 ps
CPU time 2.78 seconds
Started Aug 07 06:18:07 PM PDT 24
Finished Aug 07 06:18:10 PM PDT 24
Peak memory 207332 kb
Host smart-5654c3e9-2307-4a85-9553-0b0f95b7caba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347537606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2347537606
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2877971552
Short name T794
Test name
Test status
Simulation time 115610167 ps
CPU time 5.15 seconds
Started Aug 07 06:18:09 PM PDT 24
Finished Aug 07 06:18:15 PM PDT 24
Peak memory 209472 kb
Host smart-fcf97a22-29f4-4794-811a-5f687833adb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877971552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2877971552
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.940564643
Short name T651
Test name
Test status
Simulation time 65917195 ps
CPU time 2.13 seconds
Started Aug 07 06:18:09 PM PDT 24
Finished Aug 07 06:18:11 PM PDT 24
Peak memory 209908 kb
Host smart-4918da63-e33e-4b0d-8f75-8cc80270683e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940564643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.940564643
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3411117602
Short name T584
Test name
Test status
Simulation time 19275537 ps
CPU time 1.02 seconds
Started Aug 07 06:18:07 PM PDT 24
Finished Aug 07 06:18:09 PM PDT 24
Peak memory 206140 kb
Host smart-4ea7ea00-f469-4288-9abf-5f99f60d652d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411117602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3411117602
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3943997713
Short name T394
Test name
Test status
Simulation time 2432003683 ps
CPU time 6.78 seconds
Started Aug 07 06:18:13 PM PDT 24
Finished Aug 07 06:18:20 PM PDT 24
Peak memory 214404 kb
Host smart-783e173f-3f4a-42a3-9bc6-8fc959448923
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3943997713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3943997713
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.107916761
Short name T826
Test name
Test status
Simulation time 250746019 ps
CPU time 2.43 seconds
Started Aug 07 06:18:13 PM PDT 24
Finished Aug 07 06:18:16 PM PDT 24
Peak memory 209932 kb
Host smart-ebfe51dd-c5c4-4d40-b3ac-9afc491ac274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107916761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.107916761
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1843178198
Short name T71
Test name
Test status
Simulation time 64452467 ps
CPU time 1.53 seconds
Started Aug 07 06:18:09 PM PDT 24
Finished Aug 07 06:18:11 PM PDT 24
Peak memory 207320 kb
Host smart-d6f2bd78-811c-4f8a-a7d3-70dcdb548cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843178198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1843178198
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.962306619
Short name T90
Test name
Test status
Simulation time 94969928 ps
CPU time 4.84 seconds
Started Aug 07 06:18:10 PM PDT 24
Finished Aug 07 06:18:15 PM PDT 24
Peak memory 221072 kb
Host smart-d6756cb6-5a2d-4014-bb10-8f32d611875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962306619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.962306619
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3983452368
Short name T287
Test name
Test status
Simulation time 326470638 ps
CPU time 6.88 seconds
Started Aug 07 06:18:14 PM PDT 24
Finished Aug 07 06:18:21 PM PDT 24
Peak memory 222404 kb
Host smart-5edba220-ae97-46c2-85e4-6926ea279f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983452368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3983452368
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2155374173
Short name T549
Test name
Test status
Simulation time 204780119 ps
CPU time 4.14 seconds
Started Aug 07 06:18:11 PM PDT 24
Finished Aug 07 06:18:15 PM PDT 24
Peak memory 219444 kb
Host smart-8e133627-823e-45ac-933a-0dea799cd854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155374173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2155374173
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1288591848
Short name T192
Test name
Test status
Simulation time 87472775 ps
CPU time 2.03 seconds
Started Aug 07 06:18:17 PM PDT 24
Finished Aug 07 06:18:19 PM PDT 24
Peak memory 206972 kb
Host smart-057ddb9a-2669-457c-95ec-029bfd24bedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288591848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1288591848
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2572296261
Short name T535
Test name
Test status
Simulation time 340195379 ps
CPU time 7.51 seconds
Started Aug 07 06:18:08 PM PDT 24
Finished Aug 07 06:18:16 PM PDT 24
Peak memory 208520 kb
Host smart-78744b21-77b8-46be-8d91-0db3b0d8c105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572296261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2572296261
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2809668350
Short name T691
Test name
Test status
Simulation time 63387773 ps
CPU time 3.18 seconds
Started Aug 07 06:18:14 PM PDT 24
Finished Aug 07 06:18:17 PM PDT 24
Peak memory 207032 kb
Host smart-1f114d27-9d2b-4822-bacd-3f02b1d35666
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809668350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2809668350
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1400184898
Short name T361
Test name
Test status
Simulation time 54808117 ps
CPU time 1.84 seconds
Started Aug 07 06:18:17 PM PDT 24
Finished Aug 07 06:18:19 PM PDT 24
Peak memory 206768 kb
Host smart-7d45e07d-0743-4ad4-9c72-5b829ce3c6b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400184898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1400184898
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.61058014
Short name T514
Test name
Test status
Simulation time 21815672 ps
CPU time 2.01 seconds
Started Aug 07 06:18:08 PM PDT 24
Finished Aug 07 06:18:10 PM PDT 24
Peak memory 208476 kb
Host smart-21c31948-25bc-4cd3-8205-11ca17d19830
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61058014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.61058014
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1922109622
Short name T553
Test name
Test status
Simulation time 40949986 ps
CPU time 2.39 seconds
Started Aug 07 06:18:08 PM PDT 24
Finished Aug 07 06:18:11 PM PDT 24
Peak memory 207040 kb
Host smart-c69e4bcc-f1c9-42d3-abfa-3016fbfe51b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922109622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1922109622
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1071005335
Short name T206
Test name
Test status
Simulation time 3717452106 ps
CPU time 83.46 seconds
Started Aug 07 06:18:09 PM PDT 24
Finished Aug 07 06:19:33 PM PDT 24
Peak memory 215836 kb
Host smart-b52ec41a-998a-4122-ba2a-9730f00aa553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071005335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1071005335
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1050191502
Short name T70
Test name
Test status
Simulation time 338704932 ps
CPU time 7.92 seconds
Started Aug 07 06:18:17 PM PDT 24
Finished Aug 07 06:18:25 PM PDT 24
Peak memory 220008 kb
Host smart-6aa71604-0ac2-4395-9f56-94af300d665e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050191502 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1050191502
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3428829399
Short name T417
Test name
Test status
Simulation time 5276505876 ps
CPU time 33.94 seconds
Started Aug 07 06:18:12 PM PDT 24
Finished Aug 07 06:18:46 PM PDT 24
Peak memory 209720 kb
Host smart-534adaa3-178b-4773-8477-7d3296c1e0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428829399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3428829399
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.412222748
Short name T706
Test name
Test status
Simulation time 80414515 ps
CPU time 2.44 seconds
Started Aug 07 06:18:19 PM PDT 24
Finished Aug 07 06:18:21 PM PDT 24
Peak memory 210096 kb
Host smart-e4d8966f-dd13-42db-ab69-c4b083534d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412222748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.412222748
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2708052006
Short name T442
Test name
Test status
Simulation time 12556921 ps
CPU time 0.8 seconds
Started Aug 07 06:17:10 PM PDT 24
Finished Aug 07 06:17:11 PM PDT 24
Peak memory 205956 kb
Host smart-96ef2ff5-e9dc-4ece-8f48-501a924bc8d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708052006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2708052006
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3574644654
Short name T323
Test name
Test status
Simulation time 62665174 ps
CPU time 4.67 seconds
Started Aug 07 06:17:08 PM PDT 24
Finished Aug 07 06:17:12 PM PDT 24
Peak memory 215220 kb
Host smart-bfb329fb-0e07-4b8b-8186-433190e68f6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3574644654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3574644654
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3258640085
Short name T33
Test name
Test status
Simulation time 71810736 ps
CPU time 3.02 seconds
Started Aug 07 06:17:04 PM PDT 24
Finished Aug 07 06:17:07 PM PDT 24
Peak memory 215808 kb
Host smart-f09f8543-a7ae-42b4-986a-73c623a9c085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258640085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3258640085
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1722013913
Short name T194
Test name
Test status
Simulation time 233529788 ps
CPU time 4.64 seconds
Started Aug 07 06:17:06 PM PDT 24
Finished Aug 07 06:17:11 PM PDT 24
Peak memory 208540 kb
Host smart-50be9393-b3a7-4cf3-940a-049424b63072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722013913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1722013913
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.70765635
Short name T95
Test name
Test status
Simulation time 477389111 ps
CPU time 16.12 seconds
Started Aug 07 06:17:08 PM PDT 24
Finished Aug 07 06:17:24 PM PDT 24
Peak memory 214364 kb
Host smart-3a5dd49d-ebe2-49cb-9693-994b7e0fce7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70765635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.70765635
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1717469864
Short name T898
Test name
Test status
Simulation time 110648133 ps
CPU time 2.86 seconds
Started Aug 07 06:17:07 PM PDT 24
Finished Aug 07 06:17:10 PM PDT 24
Peak memory 214268 kb
Host smart-489c2d75-6f1c-4762-bc51-06887e62705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717469864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1717469864
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1383360159
Short name T644
Test name
Test status
Simulation time 118129482 ps
CPU time 3.1 seconds
Started Aug 07 06:17:09 PM PDT 24
Finished Aug 07 06:17:12 PM PDT 24
Peak memory 214352 kb
Host smart-82b65810-a1f4-44d2-bc7e-1f0ec0f63530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383360159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1383360159
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.4153325671
Short name T303
Test name
Test status
Simulation time 1221910470 ps
CPU time 5.94 seconds
Started Aug 07 06:17:04 PM PDT 24
Finished Aug 07 06:17:10 PM PDT 24
Peak memory 218584 kb
Host smart-81673d0a-3e4f-43f7-b7da-c21f2d3c7471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153325671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.4153325671
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3877358378
Short name T12
Test name
Test status
Simulation time 352915006 ps
CPU time 7.64 seconds
Started Aug 07 06:17:08 PM PDT 24
Finished Aug 07 06:17:16 PM PDT 24
Peak memory 237284 kb
Host smart-90eb9826-fe9a-4713-9b19-ca9a38dc7d3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877358378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3877358378
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2406794863
Short name T290
Test name
Test status
Simulation time 65123624 ps
CPU time 3.38 seconds
Started Aug 07 06:17:04 PM PDT 24
Finished Aug 07 06:17:08 PM PDT 24
Peak memory 208388 kb
Host smart-ccea29e6-88c7-4bbe-b417-e1cb0a5ca311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406794863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2406794863
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2795682350
Short name T770
Test name
Test status
Simulation time 458697671 ps
CPU time 5.57 seconds
Started Aug 07 06:17:06 PM PDT 24
Finished Aug 07 06:17:12 PM PDT 24
Peak memory 208292 kb
Host smart-33e7435e-649c-42b3-afef-59163f745ad0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795682350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2795682350
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2228133891
Short name T899
Test name
Test status
Simulation time 248131819 ps
CPU time 3.25 seconds
Started Aug 07 06:17:06 PM PDT 24
Finished Aug 07 06:17:10 PM PDT 24
Peak memory 208768 kb
Host smart-34db0a1a-27ab-4ad8-8635-198daa547fa3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228133891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2228133891
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2537392662
Short name T564
Test name
Test status
Simulation time 1421058743 ps
CPU time 16.68 seconds
Started Aug 07 06:17:04 PM PDT 24
Finished Aug 07 06:17:21 PM PDT 24
Peak memory 208216 kb
Host smart-6c7244dc-3dec-42d4-b7d6-4c82e9ec8d1d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537392662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2537392662
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.72944217
Short name T808
Test name
Test status
Simulation time 174710386 ps
CPU time 2.79 seconds
Started Aug 07 06:17:08 PM PDT 24
Finished Aug 07 06:17:11 PM PDT 24
Peak memory 208716 kb
Host smart-f57a9ad4-adf1-4109-bd91-3e3b4ff360e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72944217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.72944217
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.150195644
Short name T543
Test name
Test status
Simulation time 451116783 ps
CPU time 4.65 seconds
Started Aug 07 06:17:05 PM PDT 24
Finished Aug 07 06:17:10 PM PDT 24
Peak memory 208252 kb
Host smart-40ea2974-300d-4d73-9e42-64dc2d5768ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150195644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.150195644
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1368800561
Short name T327
Test name
Test status
Simulation time 210046870 ps
CPU time 4.18 seconds
Started Aug 07 06:17:07 PM PDT 24
Finished Aug 07 06:17:11 PM PDT 24
Peak memory 209304 kb
Host smart-9349c3d1-0dfe-4b0c-a46c-4e4b7961ef1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368800561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1368800561
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.875863202
Short name T459
Test name
Test status
Simulation time 63195963 ps
CPU time 2.52 seconds
Started Aug 07 06:17:09 PM PDT 24
Finished Aug 07 06:17:12 PM PDT 24
Peak memory 209956 kb
Host smart-f8e17cab-17ae-4dc1-b4c8-9cd6f05deff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875863202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.875863202
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.462969325
Short name T668
Test name
Test status
Simulation time 19938777 ps
CPU time 0.82 seconds
Started Aug 07 06:18:17 PM PDT 24
Finished Aug 07 06:18:18 PM PDT 24
Peak memory 205988 kb
Host smart-783a580d-db5d-42bd-abd5-1108a0513066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462969325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.462969325
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2312368386
Short name T28
Test name
Test status
Simulation time 67544225 ps
CPU time 2.99 seconds
Started Aug 07 06:18:11 PM PDT 24
Finished Aug 07 06:18:15 PM PDT 24
Peak memory 218632 kb
Host smart-45cf3d56-d339-4961-baa5-086ad38ae23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312368386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2312368386
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4001538739
Short name T670
Test name
Test status
Simulation time 69835103 ps
CPU time 1.97 seconds
Started Aug 07 06:18:07 PM PDT 24
Finished Aug 07 06:18:10 PM PDT 24
Peak memory 208868 kb
Host smart-e0bad383-3458-488d-9196-6783ae15ec18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001538739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4001538739
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3673589304
Short name T231
Test name
Test status
Simulation time 211211343 ps
CPU time 3.04 seconds
Started Aug 07 06:18:09 PM PDT 24
Finished Aug 07 06:18:13 PM PDT 24
Peak memory 214340 kb
Host smart-cc7c6ee1-bb97-487f-897c-1b66168b2576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673589304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3673589304
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2293013975
Short name T365
Test name
Test status
Simulation time 221146119 ps
CPU time 3.12 seconds
Started Aug 07 06:18:07 PM PDT 24
Finished Aug 07 06:18:11 PM PDT 24
Peak memory 214268 kb
Host smart-876ea7a5-6ebe-4ee1-81e2-8ebe3d7cb4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293013975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2293013975
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2269229142
Short name T219
Test name
Test status
Simulation time 50288484 ps
CPU time 3.13 seconds
Started Aug 07 06:18:09 PM PDT 24
Finished Aug 07 06:18:12 PM PDT 24
Peak memory 209580 kb
Host smart-c227bb44-123e-45c3-b568-c4be72b026bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269229142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2269229142
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1226045130
Short name T455
Test name
Test status
Simulation time 242519859 ps
CPU time 4.45 seconds
Started Aug 07 06:18:08 PM PDT 24
Finished Aug 07 06:18:13 PM PDT 24
Peak memory 207596 kb
Host smart-f75419e9-ffcf-4795-a587-34b0893c2921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226045130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1226045130
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2188732655
Short name T191
Test name
Test status
Simulation time 476164443 ps
CPU time 14.17 seconds
Started Aug 07 06:18:08 PM PDT 24
Finished Aug 07 06:18:23 PM PDT 24
Peak memory 208180 kb
Host smart-54471ff6-fc27-4d74-bc88-c8c3edbce871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188732655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2188732655
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.360396578
Short name T756
Test name
Test status
Simulation time 159767959 ps
CPU time 4.07 seconds
Started Aug 07 06:18:15 PM PDT 24
Finished Aug 07 06:18:20 PM PDT 24
Peak memory 208736 kb
Host smart-84a483a6-7464-4515-90ca-4dbfb4f3fbea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360396578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.360396578
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3954121447
Short name T590
Test name
Test status
Simulation time 163191869 ps
CPU time 3.87 seconds
Started Aug 07 06:18:08 PM PDT 24
Finished Aug 07 06:18:12 PM PDT 24
Peak memory 208804 kb
Host smart-c2e466b7-5e89-456c-ab0f-ded2f42d7073
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954121447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3954121447
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3655693139
Short name T536
Test name
Test status
Simulation time 508364169 ps
CPU time 6.94 seconds
Started Aug 07 06:18:08 PM PDT 24
Finished Aug 07 06:18:15 PM PDT 24
Peak memory 208000 kb
Host smart-f0084f11-4ab2-4191-8c70-3fdcd3b7d762
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655693139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3655693139
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4034605326
Short name T757
Test name
Test status
Simulation time 203817368 ps
CPU time 3.08 seconds
Started Aug 07 06:18:12 PM PDT 24
Finished Aug 07 06:18:15 PM PDT 24
Peak memory 215964 kb
Host smart-22421aff-30c2-417b-9e01-d5c59646a389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034605326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4034605326
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1104878644
Short name T531
Test name
Test status
Simulation time 62545561 ps
CPU time 2.35 seconds
Started Aug 07 06:18:09 PM PDT 24
Finished Aug 07 06:18:12 PM PDT 24
Peak memory 208616 kb
Host smart-c8354299-2c67-409f-8dc3-9b33ace3ce47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104878644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1104878644
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2837786534
Short name T295
Test name
Test status
Simulation time 1374281370 ps
CPU time 52.4 seconds
Started Aug 07 06:18:12 PM PDT 24
Finished Aug 07 06:19:05 PM PDT 24
Peak memory 222496 kb
Host smart-39b42829-f60c-4456-ad57-2dbe3ce9b938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837786534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2837786534
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1414235620
Short name T422
Test name
Test status
Simulation time 843904605 ps
CPU time 4.7 seconds
Started Aug 07 06:18:13 PM PDT 24
Finished Aug 07 06:18:18 PM PDT 24
Peak memory 210460 kb
Host smart-8b925cda-441f-41b0-9306-b3283b3a2877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414235620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1414235620
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3452456255
Short name T377
Test name
Test status
Simulation time 211251367 ps
CPU time 4.3 seconds
Started Aug 07 06:18:14 PM PDT 24
Finished Aug 07 06:18:19 PM PDT 24
Peak memory 210192 kb
Host smart-fd216018-b748-4cd6-92cb-9211a67ef149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452456255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3452456255
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.268143247
Short name T642
Test name
Test status
Simulation time 23119718 ps
CPU time 0.74 seconds
Started Aug 07 06:18:15 PM PDT 24
Finished Aug 07 06:18:16 PM PDT 24
Peak memory 205976 kb
Host smart-c3c6d253-f489-4a16-aaba-8b31b9b40059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268143247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.268143247
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1599444600
Short name T357
Test name
Test status
Simulation time 196551250 ps
CPU time 3.94 seconds
Started Aug 07 06:18:16 PM PDT 24
Finished Aug 07 06:18:20 PM PDT 24
Peak memory 214332 kb
Host smart-c7f96efe-a7fa-4976-94c1-1f506fd3e776
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1599444600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1599444600
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.4208646057
Short name T905
Test name
Test status
Simulation time 99949846 ps
CPU time 1.88 seconds
Started Aug 07 06:18:16 PM PDT 24
Finished Aug 07 06:18:18 PM PDT 24
Peak memory 214340 kb
Host smart-66b19dd9-b5e4-4f00-81ba-4e24b9f22a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208646057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.4208646057
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2582931475
Short name T518
Test name
Test status
Simulation time 4363137736 ps
CPU time 53.39 seconds
Started Aug 07 06:18:17 PM PDT 24
Finished Aug 07 06:19:10 PM PDT 24
Peak memory 214368 kb
Host smart-60c2e46d-1df1-48c0-b2b9-a5cd72d898d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582931475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2582931475
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.4213325332
Short name T249
Test name
Test status
Simulation time 158930617 ps
CPU time 4.12 seconds
Started Aug 07 06:18:17 PM PDT 24
Finished Aug 07 06:18:22 PM PDT 24
Peak memory 222388 kb
Host smart-640524be-696e-47d3-a2f4-ab61a854add3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213325332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.4213325332
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.136914796
Short name T623
Test name
Test status
Simulation time 117518497 ps
CPU time 2.95 seconds
Started Aug 07 06:18:15 PM PDT 24
Finished Aug 07 06:18:18 PM PDT 24
Peak memory 209012 kb
Host smart-0d105196-6e4f-4b6b-941b-62f7c3b9f503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136914796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.136914796
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1676155407
Short name T871
Test name
Test status
Simulation time 331430531 ps
CPU time 4.04 seconds
Started Aug 07 06:18:16 PM PDT 24
Finished Aug 07 06:18:20 PM PDT 24
Peak memory 207648 kb
Host smart-b169ba8b-d7c7-4a97-97af-8e665b69faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676155407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1676155407
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3554198798
Short name T716
Test name
Test status
Simulation time 169203399 ps
CPU time 3.98 seconds
Started Aug 07 06:18:14 PM PDT 24
Finished Aug 07 06:18:18 PM PDT 24
Peak memory 208720 kb
Host smart-829f11e8-2f36-4441-b74f-1d13deefb102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554198798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3554198798
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1684828205
Short name T836
Test name
Test status
Simulation time 47027764 ps
CPU time 2.68 seconds
Started Aug 07 06:18:15 PM PDT 24
Finished Aug 07 06:18:18 PM PDT 24
Peak memory 206792 kb
Host smart-b55efb66-fad2-4443-bd54-3bd1bbf762c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684828205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1684828205
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.4086250054
Short name T561
Test name
Test status
Simulation time 29984488 ps
CPU time 2.09 seconds
Started Aug 07 06:18:18 PM PDT 24
Finished Aug 07 06:18:20 PM PDT 24
Peak memory 206856 kb
Host smart-a3b05d52-7f4d-4e1b-8d6d-660261b573a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086250054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.4086250054
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.606540433
Short name T505
Test name
Test status
Simulation time 33755997 ps
CPU time 2.07 seconds
Started Aug 07 06:18:17 PM PDT 24
Finished Aug 07 06:18:19 PM PDT 24
Peak memory 207044 kb
Host smart-a85953d9-9c2a-4b36-b249-d3c2cd850fcf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606540433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.606540433
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1957226145
Short name T843
Test name
Test status
Simulation time 678869030 ps
CPU time 4.67 seconds
Started Aug 07 06:18:16 PM PDT 24
Finished Aug 07 06:18:21 PM PDT 24
Peak memory 218456 kb
Host smart-84c571bc-01cc-4844-b94f-b95a8e56cd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957226145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1957226145
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3348275480
Short name T805
Test name
Test status
Simulation time 141769381 ps
CPU time 4.67 seconds
Started Aug 07 06:18:18 PM PDT 24
Finished Aug 07 06:18:22 PM PDT 24
Peak memory 208836 kb
Host smart-ce74554f-8d7a-4ef3-b395-f9c8a043522f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348275480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3348275480
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.538756400
Short name T119
Test name
Test status
Simulation time 1196632813 ps
CPU time 23.17 seconds
Started Aug 07 06:18:16 PM PDT 24
Finished Aug 07 06:18:40 PM PDT 24
Peak memory 222600 kb
Host smart-565c168f-8948-4ea8-97c4-ce55d524960b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538756400 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.538756400
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1843395939
Short name T193
Test name
Test status
Simulation time 142049009 ps
CPU time 2.89 seconds
Started Aug 07 06:18:14 PM PDT 24
Finished Aug 07 06:18:17 PM PDT 24
Peak memory 208140 kb
Host smart-0a247f34-5383-452e-9f46-03b91b88bc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843395939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1843395939
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2114729112
Short name T552
Test name
Test status
Simulation time 56162606 ps
CPU time 2.31 seconds
Started Aug 07 06:18:16 PM PDT 24
Finished Aug 07 06:18:18 PM PDT 24
Peak memory 210176 kb
Host smart-f94103ee-3769-40e8-8c22-0fbc49f5a960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114729112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2114729112
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3439441498
Short name T96
Test name
Test status
Simulation time 25507530 ps
CPU time 1.08 seconds
Started Aug 07 06:18:22 PM PDT 24
Finished Aug 07 06:18:23 PM PDT 24
Peak memory 206176 kb
Host smart-21da5a90-d832-4951-8a81-398ed9e1d1e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439441498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3439441498
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3232082629
Short name T267
Test name
Test status
Simulation time 993491336 ps
CPU time 13.36 seconds
Started Aug 07 06:18:15 PM PDT 24
Finished Aug 07 06:18:29 PM PDT 24
Peak memory 215092 kb
Host smart-304011a0-4bbd-4a6c-b372-4cb5a48e5dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3232082629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3232082629
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2390586754
Short name T390
Test name
Test status
Simulation time 125554784 ps
CPU time 3.38 seconds
Started Aug 07 06:18:16 PM PDT 24
Finished Aug 07 06:18:20 PM PDT 24
Peak memory 208232 kb
Host smart-87a6895a-8488-4220-a0c4-a2c0ac4a0f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390586754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2390586754
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.254814181
Short name T907
Test name
Test status
Simulation time 242494197 ps
CPU time 7.58 seconds
Started Aug 07 06:18:24 PM PDT 24
Finished Aug 07 06:18:31 PM PDT 24
Peak memory 219800 kb
Host smart-7dc59f30-c402-4ddb-98d8-94326e4f0c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254814181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.254814181
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_random.2058782050
Short name T625
Test name
Test status
Simulation time 59424331 ps
CPU time 3.65 seconds
Started Aug 07 06:18:13 PM PDT 24
Finished Aug 07 06:18:17 PM PDT 24
Peak memory 214388 kb
Host smart-45acfe6c-c03f-48dd-a04a-7d7df8515a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058782050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2058782050
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1395425312
Short name T421
Test name
Test status
Simulation time 42197072 ps
CPU time 1.93 seconds
Started Aug 07 06:18:14 PM PDT 24
Finished Aug 07 06:18:17 PM PDT 24
Peak memory 206852 kb
Host smart-c10ec859-1857-4611-9586-b897fe2b66ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395425312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1395425312
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3859512883
Short name T876
Test name
Test status
Simulation time 173883117 ps
CPU time 5.13 seconds
Started Aug 07 06:18:16 PM PDT 24
Finished Aug 07 06:18:22 PM PDT 24
Peak memory 206940 kb
Host smart-ff5aaae8-b6d3-4875-80b5-a7802e748ea1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859512883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3859512883
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3007277423
Short name T792
Test name
Test status
Simulation time 766302516 ps
CPU time 8.61 seconds
Started Aug 07 06:18:16 PM PDT 24
Finished Aug 07 06:18:25 PM PDT 24
Peak memory 208788 kb
Host smart-40d378de-2e4d-4ee2-9205-7231bc3ce613
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007277423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3007277423
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.611518612
Short name T828
Test name
Test status
Simulation time 303232309 ps
CPU time 2.82 seconds
Started Aug 07 06:18:15 PM PDT 24
Finished Aug 07 06:18:18 PM PDT 24
Peak memory 206928 kb
Host smart-35b6fe20-7e62-4dad-b03f-adb850787bd9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611518612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.611518612
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.4016328841
Short name T195
Test name
Test status
Simulation time 86558970 ps
CPU time 1.66 seconds
Started Aug 07 06:18:21 PM PDT 24
Finished Aug 07 06:18:23 PM PDT 24
Peak memory 208128 kb
Host smart-50279683-b0fe-46be-aedd-76322bde729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016328841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.4016328841
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2597565141
Short name T789
Test name
Test status
Simulation time 212849876 ps
CPU time 2.57 seconds
Started Aug 07 06:18:14 PM PDT 24
Finished Aug 07 06:18:17 PM PDT 24
Peak memory 208628 kb
Host smart-9a68361c-6a30-4686-8c30-84d9f9d5b39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597565141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2597565141
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1874223316
Short name T547
Test name
Test status
Simulation time 4394377386 ps
CPU time 29.24 seconds
Started Aug 07 06:18:21 PM PDT 24
Finished Aug 07 06:18:50 PM PDT 24
Peak memory 221524 kb
Host smart-c67b2d8b-2c08-4028-a57d-967c64423adc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874223316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1874223316
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1546832449
Short name T448
Test name
Test status
Simulation time 393046661 ps
CPU time 7.88 seconds
Started Aug 07 06:18:21 PM PDT 24
Finished Aug 07 06:18:29 PM PDT 24
Peak memory 208876 kb
Host smart-22c67317-b165-4367-a845-a89b79212f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546832449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1546832449
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3685231365
Short name T583
Test name
Test status
Simulation time 34600041 ps
CPU time 2.09 seconds
Started Aug 07 06:18:23 PM PDT 24
Finished Aug 07 06:18:25 PM PDT 24
Peak memory 209708 kb
Host smart-89774fae-7edd-4db7-9217-9924a94ee778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685231365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3685231365
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.297653739
Short name T902
Test name
Test status
Simulation time 44030689 ps
CPU time 0.74 seconds
Started Aug 07 06:18:28 PM PDT 24
Finished Aug 07 06:18:29 PM PDT 24
Peak memory 206004 kb
Host smart-2680bce2-e16a-4789-8aee-039be40b095a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297653739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.297653739
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2322977729
Short name T278
Test name
Test status
Simulation time 478188172 ps
CPU time 13.85 seconds
Started Aug 07 06:18:22 PM PDT 24
Finished Aug 07 06:18:36 PM PDT 24
Peak memory 222588 kb
Host smart-68bec1bb-b549-4bbe-96a0-8dc0ee68fb90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322977729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2322977729
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2938532991
Short name T479
Test name
Test status
Simulation time 1434511755 ps
CPU time 3.96 seconds
Started Aug 07 06:18:20 PM PDT 24
Finished Aug 07 06:18:24 PM PDT 24
Peak memory 218312 kb
Host smart-f62ec366-48f3-458c-b3d8-e41ccb1cd8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938532991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2938532991
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2930559609
Short name T92
Test name
Test status
Simulation time 2397329496 ps
CPU time 16 seconds
Started Aug 07 06:18:24 PM PDT 24
Finished Aug 07 06:18:41 PM PDT 24
Peak memory 214356 kb
Host smart-5e4fcca3-afb7-43ed-b938-d4946aaa68ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930559609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2930559609
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.142004686
Short name T834
Test name
Test status
Simulation time 190196315 ps
CPU time 2.81 seconds
Started Aug 07 06:18:22 PM PDT 24
Finished Aug 07 06:18:24 PM PDT 24
Peak memory 220680 kb
Host smart-4a902ed0-9896-4f21-8409-301fa3acd70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142004686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.142004686
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2411615944
Short name T823
Test name
Test status
Simulation time 106545120 ps
CPU time 2.26 seconds
Started Aug 07 06:18:23 PM PDT 24
Finished Aug 07 06:18:25 PM PDT 24
Peak memory 207424 kb
Host smart-eeffa0d1-6882-421c-8bfa-cce15427970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411615944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2411615944
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.669609972
Short name T173
Test name
Test status
Simulation time 97160752 ps
CPU time 2.27 seconds
Started Aug 07 06:18:23 PM PDT 24
Finished Aug 07 06:18:25 PM PDT 24
Peak memory 206892 kb
Host smart-b235706d-512a-42f8-992c-84992002434d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669609972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.669609972
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3708408440
Short name T777
Test name
Test status
Simulation time 237270513 ps
CPU time 5.71 seconds
Started Aug 07 06:18:22 PM PDT 24
Finished Aug 07 06:18:28 PM PDT 24
Peak memory 208560 kb
Host smart-515afdb9-2563-4b8d-b4a3-7d6953386331
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708408440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3708408440
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3072634331
Short name T872
Test name
Test status
Simulation time 945186467 ps
CPU time 10.41 seconds
Started Aug 07 06:18:22 PM PDT 24
Finished Aug 07 06:18:32 PM PDT 24
Peak memory 209024 kb
Host smart-e8bf59ca-7204-43c7-bf23-956091a4d0be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072634331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3072634331
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3728145131
Short name T419
Test name
Test status
Simulation time 23933430 ps
CPU time 1.9 seconds
Started Aug 07 06:18:26 PM PDT 24
Finished Aug 07 06:18:29 PM PDT 24
Peak memory 208560 kb
Host smart-c05631ff-0aaa-4760-adc6-8dd8125c9b37
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728145131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3728145131
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2285729259
Short name T592
Test name
Test status
Simulation time 44461121 ps
CPU time 2.05 seconds
Started Aug 07 06:18:24 PM PDT 24
Finished Aug 07 06:18:26 PM PDT 24
Peak memory 208100 kb
Host smart-f9d3c797-0fd2-4655-aa09-80303f9cc12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285729259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2285729259
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.622292928
Short name T610
Test name
Test status
Simulation time 32995641 ps
CPU time 2.18 seconds
Started Aug 07 06:18:21 PM PDT 24
Finished Aug 07 06:18:23 PM PDT 24
Peak memory 206808 kb
Host smart-b30ae972-8370-4072-a320-e67ab62679a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622292928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.622292928
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2548255037
Short name T203
Test name
Test status
Simulation time 2196556754 ps
CPU time 31.59 seconds
Started Aug 07 06:18:26 PM PDT 24
Finished Aug 07 06:18:58 PM PDT 24
Peak memory 222536 kb
Host smart-5df24671-9154-4c60-964a-6e970a5d5b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548255037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2548255037
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.483601279
Short name T901
Test name
Test status
Simulation time 892684552 ps
CPU time 9.61 seconds
Started Aug 07 06:18:23 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 208356 kb
Host smart-3d030395-f0ea-4e3b-a922-6964e29aa65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483601279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.483601279
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3383851408
Short name T863
Test name
Test status
Simulation time 675817685 ps
CPU time 2.28 seconds
Started Aug 07 06:18:22 PM PDT 24
Finished Aug 07 06:18:25 PM PDT 24
Peak memory 210268 kb
Host smart-3b0c6501-f0d2-4a08-8d9b-9db2e1d815dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383851408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3383851408
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2703014579
Short name T431
Test name
Test status
Simulation time 10160104 ps
CPU time 0.84 seconds
Started Aug 07 06:18:26 PM PDT 24
Finished Aug 07 06:18:27 PM PDT 24
Peak memory 205980 kb
Host smart-1a44dee8-2a56-43ad-9f83-97c267eda931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703014579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2703014579
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3017007732
Short name T225
Test name
Test status
Simulation time 121576773 ps
CPU time 6.08 seconds
Started Aug 07 06:18:28 PM PDT 24
Finished Aug 07 06:18:34 PM PDT 24
Peak memory 215056 kb
Host smart-6f7e8293-b135-4e50-bf4b-b4dc1c437b6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017007732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3017007732
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.303404099
Short name T349
Test name
Test status
Simulation time 33229285 ps
CPU time 1.82 seconds
Started Aug 07 06:18:26 PM PDT 24
Finished Aug 07 06:18:28 PM PDT 24
Peak memory 214428 kb
Host smart-54934a32-2dea-4661-80da-ec428405bdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303404099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.303404099
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2859761093
Short name T86
Test name
Test status
Simulation time 856543485 ps
CPU time 5.32 seconds
Started Aug 07 06:18:28 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 214368 kb
Host smart-eecf9e1a-c8a9-4c2a-abe3-f136c598de92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859761093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2859761093
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.561659712
Short name T887
Test name
Test status
Simulation time 60767112 ps
CPU time 2.79 seconds
Started Aug 07 06:18:30 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 219848 kb
Host smart-35298449-acd1-43ef-b34c-2f066302c148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561659712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.561659712
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.4253636261
Short name T56
Test name
Test status
Simulation time 99061327 ps
CPU time 5.3 seconds
Started Aug 07 06:18:31 PM PDT 24
Finished Aug 07 06:18:36 PM PDT 24
Peak memory 214416 kb
Host smart-e8dfa3a7-370a-4175-942b-14d88b2d875b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253636261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.4253636261
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1140813471
Short name T507
Test name
Test status
Simulation time 131290517 ps
CPU time 3.46 seconds
Started Aug 07 06:18:29 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 214380 kb
Host smart-4dc613b1-926b-4a58-86c4-0ae7d7701d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140813471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1140813471
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3639219400
Short name T646
Test name
Test status
Simulation time 335284856 ps
CPU time 4.98 seconds
Started Aug 07 06:18:28 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 206920 kb
Host smart-9505b844-42bd-4bd7-bb05-806983562d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639219400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3639219400
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1232987126
Short name T599
Test name
Test status
Simulation time 59996175 ps
CPU time 2.32 seconds
Started Aug 07 06:18:26 PM PDT 24
Finished Aug 07 06:18:28 PM PDT 24
Peak memory 206820 kb
Host smart-05fc902e-86d7-4c3e-abaa-8a6662269b11
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232987126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1232987126
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3745996607
Short name T297
Test name
Test status
Simulation time 106194789 ps
CPU time 2.91 seconds
Started Aug 07 06:18:30 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 206804 kb
Host smart-365a1077-38de-4f8b-b195-90303931b718
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745996607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3745996607
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.759240611
Short name T882
Test name
Test status
Simulation time 172804975 ps
CPU time 5.26 seconds
Started Aug 07 06:18:30 PM PDT 24
Finished Aug 07 06:18:36 PM PDT 24
Peak memory 208360 kb
Host smart-11c45380-2ab1-44a9-ad77-477d8205613a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759240611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.759240611
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.4101184489
Short name T343
Test name
Test status
Simulation time 96552770 ps
CPU time 3.36 seconds
Started Aug 07 06:18:29 PM PDT 24
Finished Aug 07 06:18:32 PM PDT 24
Peak memory 210372 kb
Host smart-3f313543-fbe4-4506-bee5-1456f8d72d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101184489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.4101184489
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1124360711
Short name T890
Test name
Test status
Simulation time 1814763694 ps
CPU time 29.75 seconds
Started Aug 07 06:18:28 PM PDT 24
Finished Aug 07 06:18:58 PM PDT 24
Peak memory 208920 kb
Host smart-1a5f6e1a-a85c-455a-8911-1df187a0b6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124360711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1124360711
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2875788682
Short name T648
Test name
Test status
Simulation time 430801370 ps
CPU time 7.35 seconds
Started Aug 07 06:18:25 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 218376 kb
Host smart-bf587d89-8bf4-4813-9d39-a230b2dd5941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875788682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2875788682
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3269403202
Short name T59
Test name
Test status
Simulation time 109569640 ps
CPU time 3.83 seconds
Started Aug 07 06:18:29 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 210076 kb
Host smart-06e752a2-460a-4789-8ee9-83ec16995dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269403202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3269403202
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.4215332351
Short name T677
Test name
Test status
Simulation time 22220278 ps
CPU time 0.81 seconds
Started Aug 07 06:18:30 PM PDT 24
Finished Aug 07 06:18:31 PM PDT 24
Peak memory 205968 kb
Host smart-af3b3e85-3254-43ae-8fc3-b7594d19d06a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215332351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.4215332351
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2627559755
Short name T255
Test name
Test status
Simulation time 136936131 ps
CPU time 2.97 seconds
Started Aug 07 06:18:29 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 215560 kb
Host smart-22f531cb-c988-4f4c-9025-6adf8c418a3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627559755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2627559755
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3068606974
Short name T695
Test name
Test status
Simulation time 2989296861 ps
CPU time 16.4 seconds
Started Aug 07 06:18:26 PM PDT 24
Finished Aug 07 06:18:43 PM PDT 24
Peak memory 214560 kb
Host smart-0114d13d-cbda-48dc-a44e-e5e96450a9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068606974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3068606974
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3738079100
Short name T76
Test name
Test status
Simulation time 43621905 ps
CPU time 2.5 seconds
Started Aug 07 06:18:25 PM PDT 24
Finished Aug 07 06:18:27 PM PDT 24
Peak memory 222380 kb
Host smart-2ec3431c-0102-4995-ab64-764bb84e5eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738079100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3738079100
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3170660932
Short name T735
Test name
Test status
Simulation time 147379196 ps
CPU time 2.8 seconds
Started Aug 07 06:18:30 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 214328 kb
Host smart-2b2c056b-d249-48c0-bb56-183c942fa585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170660932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3170660932
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2049311656
Short name T346
Test name
Test status
Simulation time 129470709 ps
CPU time 2.43 seconds
Started Aug 07 06:18:31 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 222428 kb
Host smart-f7055ebb-405e-4819-8e82-17bd5a3f9133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049311656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2049311656
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.149900088
Short name T275
Test name
Test status
Simulation time 258253917 ps
CPU time 4 seconds
Started Aug 07 06:18:31 PM PDT 24
Finished Aug 07 06:18:35 PM PDT 24
Peak memory 222468 kb
Host smart-1450da3b-6434-410a-a595-76e1f1058ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149900088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.149900088
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1614466994
Short name T414
Test name
Test status
Simulation time 178635993 ps
CPU time 5.58 seconds
Started Aug 07 06:18:26 PM PDT 24
Finished Aug 07 06:18:32 PM PDT 24
Peak memory 210332 kb
Host smart-b60794d8-db26-4814-aaa0-0b4f6ec5b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614466994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1614466994
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3451238098
Short name T460
Test name
Test status
Simulation time 137084979 ps
CPU time 2.5 seconds
Started Aug 07 06:18:29 PM PDT 24
Finished Aug 07 06:18:32 PM PDT 24
Peak memory 208880 kb
Host smart-b07a114d-74a9-4330-bb56-3dbdfbd7e64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451238098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3451238098
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.397481746
Short name T618
Test name
Test status
Simulation time 2305218395 ps
CPU time 20.35 seconds
Started Aug 07 06:18:27 PM PDT 24
Finished Aug 07 06:18:47 PM PDT 24
Peak memory 208540 kb
Host smart-06c65f3a-9ac1-4718-a1e6-683802977c69
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397481746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.397481746
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.4189091171
Short name T450
Test name
Test status
Simulation time 801957376 ps
CPU time 6.13 seconds
Started Aug 07 06:18:25 PM PDT 24
Finished Aug 07 06:18:31 PM PDT 24
Peak memory 208464 kb
Host smart-b1c05399-613c-48c2-97ac-70a98eddd6e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189091171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4189091171
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2015697852
Short name T722
Test name
Test status
Simulation time 202072180 ps
CPU time 4.57 seconds
Started Aug 07 06:18:28 PM PDT 24
Finished Aug 07 06:18:32 PM PDT 24
Peak memory 208896 kb
Host smart-20cf7cc7-3b63-41ab-bd58-99e1ccbfac8b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015697852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2015697852
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2457948801
Short name T386
Test name
Test status
Simulation time 398496294 ps
CPU time 4.17 seconds
Started Aug 07 06:18:29 PM PDT 24
Finished Aug 07 06:18:34 PM PDT 24
Peak memory 209064 kb
Host smart-945ca981-e3d0-4c36-b094-1580acfb264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457948801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2457948801
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3675803206
Short name T389
Test name
Test status
Simulation time 142712234 ps
CPU time 4.58 seconds
Started Aug 07 06:18:29 PM PDT 24
Finished Aug 07 06:18:34 PM PDT 24
Peak memory 208496 kb
Host smart-eebe1f44-87dc-4ab7-97a5-b4940e21a2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675803206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3675803206
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.77749975
Short name T840
Test name
Test status
Simulation time 3955183499 ps
CPU time 31.41 seconds
Started Aug 07 06:18:28 PM PDT 24
Finished Aug 07 06:18:59 PM PDT 24
Peak memory 221332 kb
Host smart-6f4f657e-19fe-4249-ad38-e9bd90ca1231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77749975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.77749975
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.4058545706
Short name T73
Test name
Test status
Simulation time 136335743 ps
CPU time 9.52 seconds
Started Aug 07 06:18:28 PM PDT 24
Finished Aug 07 06:18:37 PM PDT 24
Peak memory 222840 kb
Host smart-93aa73a3-5fc5-403f-b9c9-5fe8634b278c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058545706 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.4058545706
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2938657185
Short name T495
Test name
Test status
Simulation time 45037412 ps
CPU time 3.21 seconds
Started Aug 07 06:18:28 PM PDT 24
Finished Aug 07 06:18:32 PM PDT 24
Peak memory 209920 kb
Host smart-0383517f-b321-43fc-b995-65ccddd7f4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938657185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2938657185
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3306681270
Short name T375
Test name
Test status
Simulation time 62891718 ps
CPU time 2.47 seconds
Started Aug 07 06:18:28 PM PDT 24
Finished Aug 07 06:18:31 PM PDT 24
Peak memory 214388 kb
Host smart-4a164f77-aeed-468a-98db-a87908d16f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306681270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3306681270
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2358039709
Short name T746
Test name
Test status
Simulation time 68921231 ps
CPU time 0.79 seconds
Started Aug 07 06:18:37 PM PDT 24
Finished Aug 07 06:18:38 PM PDT 24
Peak memory 205976 kb
Host smart-b80532fa-0bce-43db-8469-25bd311e7c99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358039709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2358039709
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2527307036
Short name T67
Test name
Test status
Simulation time 203445959 ps
CPU time 2.17 seconds
Started Aug 07 06:18:34 PM PDT 24
Finished Aug 07 06:18:36 PM PDT 24
Peak memory 208428 kb
Host smart-880e12c5-7c4b-4993-9ee6-6b3844a5b1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527307036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2527307036
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2865328938
Short name T568
Test name
Test status
Simulation time 141389362 ps
CPU time 4.11 seconds
Started Aug 07 06:18:37 PM PDT 24
Finished Aug 07 06:18:41 PM PDT 24
Peak memory 215992 kb
Host smart-af7121cd-4350-475a-ba52-5bc85058c5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865328938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2865328938
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1091640049
Short name T775
Test name
Test status
Simulation time 220395635 ps
CPU time 3 seconds
Started Aug 07 06:18:33 PM PDT 24
Finished Aug 07 06:18:36 PM PDT 24
Peak memory 220180 kb
Host smart-d1e4f68a-f779-4a8a-a379-ff46b8982400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091640049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1091640049
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.425160990
Short name T586
Test name
Test status
Simulation time 71485954 ps
CPU time 3.47 seconds
Started Aug 07 06:18:33 PM PDT 24
Finished Aug 07 06:18:36 PM PDT 24
Peak memory 209016 kb
Host smart-1e9d9419-28fe-4229-9a2d-2d964d5e9767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425160990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.425160990
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1445803628
Short name T797
Test name
Test status
Simulation time 940580793 ps
CPU time 21.15 seconds
Started Aug 07 06:18:35 PM PDT 24
Finished Aug 07 06:18:56 PM PDT 24
Peak memory 214380 kb
Host smart-7a9c7944-3ee8-495e-a434-4960714a184d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445803628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1445803628
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1395629431
Short name T245
Test name
Test status
Simulation time 162985974 ps
CPU time 3.23 seconds
Started Aug 07 06:18:37 PM PDT 24
Finished Aug 07 06:18:41 PM PDT 24
Peak memory 207548 kb
Host smart-6a1cabf2-9c85-4a44-9205-c768c8e4e16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395629431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1395629431
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1304276902
Short name T355
Test name
Test status
Simulation time 80603207 ps
CPU time 3.69 seconds
Started Aug 07 06:18:34 PM PDT 24
Finished Aug 07 06:18:37 PM PDT 24
Peak memory 209096 kb
Host smart-2f2846e6-639b-499d-9254-7ca101d6c26b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304276902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1304276902
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3034605609
Short name T846
Test name
Test status
Simulation time 71342990 ps
CPU time 3.13 seconds
Started Aug 07 06:18:31 PM PDT 24
Finished Aug 07 06:18:35 PM PDT 24
Peak memory 208656 kb
Host smart-076ef815-237c-4f27-aecb-d97bc7d146e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034605609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3034605609
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2720157076
Short name T649
Test name
Test status
Simulation time 26940006 ps
CPU time 2.16 seconds
Started Aug 07 06:18:31 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 208528 kb
Host smart-53164b78-569a-4775-b7a1-7dbda4ceffb8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720157076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2720157076
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3158971270
Short name T718
Test name
Test status
Simulation time 81476065 ps
CPU time 3.08 seconds
Started Aug 07 06:18:33 PM PDT 24
Finished Aug 07 06:18:36 PM PDT 24
Peak memory 208528 kb
Host smart-063818ba-4ec5-46d0-89a1-a04d619ff1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158971270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3158971270
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1112079047
Short name T698
Test name
Test status
Simulation time 106765422 ps
CPU time 2.69 seconds
Started Aug 07 06:18:35 PM PDT 24
Finished Aug 07 06:18:38 PM PDT 24
Peak memory 206888 kb
Host smart-5af643b1-4192-4410-8b35-a68f98e9ded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112079047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1112079047
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3506184453
Short name T243
Test name
Test status
Simulation time 9557226045 ps
CPU time 39.92 seconds
Started Aug 07 06:18:31 PM PDT 24
Finished Aug 07 06:19:11 PM PDT 24
Peak memory 217260 kb
Host smart-66ffd717-7c89-4ede-b653-0a3838ca1309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506184453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3506184453
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1155101265
Short name T43
Test name
Test status
Simulation time 2248479362 ps
CPU time 8.73 seconds
Started Aug 07 06:18:34 PM PDT 24
Finished Aug 07 06:18:43 PM PDT 24
Peak memory 222632 kb
Host smart-54a77ab8-d79a-45bb-85e5-15fa2c2a54ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155101265 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1155101265
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3504653496
Short name T864
Test name
Test status
Simulation time 50692436 ps
CPU time 3.15 seconds
Started Aug 07 06:18:32 PM PDT 24
Finished Aug 07 06:18:36 PM PDT 24
Peak memory 218400 kb
Host smart-56a9762d-c7dd-4397-9945-b9c1f3c17784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504653496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3504653496
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.4066767405
Short name T35
Test name
Test status
Simulation time 53272987 ps
CPU time 1.75 seconds
Started Aug 07 06:18:32 PM PDT 24
Finished Aug 07 06:18:34 PM PDT 24
Peak memory 209548 kb
Host smart-3d43618c-6c91-4e69-b18a-cfa674539f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066767405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.4066767405
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3177976745
Short name T741
Test name
Test status
Simulation time 21816455 ps
CPU time 0.85 seconds
Started Aug 07 06:18:38 PM PDT 24
Finished Aug 07 06:18:39 PM PDT 24
Peak memory 205896 kb
Host smart-fc3bd3ac-1c71-4b49-908c-8b88364e0f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177976745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3177976745
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.148324634
Short name T266
Test name
Test status
Simulation time 741640171 ps
CPU time 10.16 seconds
Started Aug 07 06:18:33 PM PDT 24
Finished Aug 07 06:18:43 PM PDT 24
Peak memory 214352 kb
Host smart-65421e9b-444e-4946-9e8f-4418bce896ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=148324634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.148324634
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2137909107
Short name T879
Test name
Test status
Simulation time 50038040 ps
CPU time 2.02 seconds
Started Aug 07 06:18:40 PM PDT 24
Finished Aug 07 06:18:42 PM PDT 24
Peak memory 222328 kb
Host smart-13985017-bbbc-4f68-982a-114a1cd59e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137909107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2137909107
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2321148413
Short name T232
Test name
Test status
Simulation time 76850940 ps
CPU time 2.42 seconds
Started Aug 07 06:18:39 PM PDT 24
Finished Aug 07 06:18:42 PM PDT 24
Peak memory 222400 kb
Host smart-f9054467-751b-4faa-8387-a5ee72317a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321148413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2321148413
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_random.2433671905
Short name T525
Test name
Test status
Simulation time 717197845 ps
CPU time 3.89 seconds
Started Aug 07 06:18:33 PM PDT 24
Finished Aug 07 06:18:37 PM PDT 24
Peak memory 206976 kb
Host smart-64b592f3-9670-410f-8ef6-a4a9e4ebb84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433671905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2433671905
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.495915394
Short name T446
Test name
Test status
Simulation time 33684015 ps
CPU time 2.23 seconds
Started Aug 07 06:18:31 PM PDT 24
Finished Aug 07 06:18:34 PM PDT 24
Peak memory 206964 kb
Host smart-4d09f08c-7d6b-4d7f-b9d1-436ccc3ae73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495915394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.495915394
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3676291768
Short name T766
Test name
Test status
Simulation time 1222464524 ps
CPU time 16.38 seconds
Started Aug 07 06:18:34 PM PDT 24
Finished Aug 07 06:18:50 PM PDT 24
Peak memory 208292 kb
Host smart-fc4ca90e-637f-451d-a6e3-ce7272e71062
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676291768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3676291768
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.46913154
Short name T261
Test name
Test status
Simulation time 35300057 ps
CPU time 2.51 seconds
Started Aug 07 06:18:37 PM PDT 24
Finished Aug 07 06:18:40 PM PDT 24
Peak memory 208692 kb
Host smart-a45c90c8-958c-4151-a04d-895cdc1e50d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46913154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.46913154
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2549686780
Short name T639
Test name
Test status
Simulation time 677995645 ps
CPU time 15.54 seconds
Started Aug 07 06:18:37 PM PDT 24
Finished Aug 07 06:18:53 PM PDT 24
Peak memory 208724 kb
Host smart-08eb4f4b-5bf3-4a61-9ce9-97b6b0c93f63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549686780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2549686780
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3418474992
Short name T589
Test name
Test status
Simulation time 52254866 ps
CPU time 2.3 seconds
Started Aug 07 06:18:37 PM PDT 24
Finished Aug 07 06:18:39 PM PDT 24
Peak memory 209752 kb
Host smart-938848b1-b71b-4f9c-86d0-8d4a7f62ede7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418474992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3418474992
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.548086657
Short name T466
Test name
Test status
Simulation time 460616527 ps
CPU time 9.3 seconds
Started Aug 07 06:18:38 PM PDT 24
Finished Aug 07 06:18:48 PM PDT 24
Peak memory 207880 kb
Host smart-7cdcdb84-0adf-458f-8600-a4f88d7a2b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548086657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.548086657
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.98306301
Short name T680
Test name
Test status
Simulation time 357447917 ps
CPU time 7.68 seconds
Started Aug 07 06:18:38 PM PDT 24
Finished Aug 07 06:18:46 PM PDT 24
Peak memory 222060 kb
Host smart-10e05fc5-e0ca-4aaf-969a-d9060f49f539
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98306301 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.98306301
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4284810100
Short name T776
Test name
Test status
Simulation time 174017077 ps
CPU time 4.48 seconds
Started Aug 07 06:18:39 PM PDT 24
Finished Aug 07 06:18:44 PM PDT 24
Peak memory 208792 kb
Host smart-f5e11fbf-251c-4fd0-8aa9-e832f52e2d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284810100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4284810100
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3975820523
Short name T503
Test name
Test status
Simulation time 74228881 ps
CPU time 1.9 seconds
Started Aug 07 06:18:38 PM PDT 24
Finished Aug 07 06:18:40 PM PDT 24
Peak memory 209756 kb
Host smart-40a1b316-da5f-4eda-bca3-84f28b5432c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975820523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3975820523
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1893872324
Short name T464
Test name
Test status
Simulation time 29051173 ps
CPU time 0.93 seconds
Started Aug 07 06:18:46 PM PDT 24
Finished Aug 07 06:18:47 PM PDT 24
Peak memory 205988 kb
Host smart-d13f1e79-7e05-47ac-be2a-87237eb97cab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893872324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1893872324
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3359373911
Short name T393
Test name
Test status
Simulation time 43368955 ps
CPU time 3.18 seconds
Started Aug 07 06:18:39 PM PDT 24
Finished Aug 07 06:18:42 PM PDT 24
Peak memory 214116 kb
Host smart-5461e7a5-26e7-43a4-8fb0-2d360863c49f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359373911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3359373911
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2025175444
Short name T615
Test name
Test status
Simulation time 135096727 ps
CPU time 2.12 seconds
Started Aug 07 06:18:38 PM PDT 24
Finished Aug 07 06:18:40 PM PDT 24
Peak memory 218300 kb
Host smart-05465482-5b96-4f75-9b2e-3e565afdc90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025175444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2025175444
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3376717444
Short name T571
Test name
Test status
Simulation time 57862102 ps
CPU time 2.72 seconds
Started Aug 07 06:18:40 PM PDT 24
Finished Aug 07 06:18:43 PM PDT 24
Peak memory 209240 kb
Host smart-6481b241-c1bc-4bdd-9b9b-5c7f7c8f4d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376717444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3376717444
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.553666219
Short name T175
Test name
Test status
Simulation time 62600877 ps
CPU time 2.06 seconds
Started Aug 07 06:18:38 PM PDT 24
Finished Aug 07 06:18:41 PM PDT 24
Peak memory 215400 kb
Host smart-63bcd738-e2d3-464e-8070-d4988c6dbb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553666219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.553666219
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3978443160
Short name T252
Test name
Test status
Simulation time 54180431 ps
CPU time 2.46 seconds
Started Aug 07 06:18:39 PM PDT 24
Finished Aug 07 06:18:41 PM PDT 24
Peak memory 214372 kb
Host smart-526dbd39-b197-41da-a04a-00ee7375978f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978443160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3978443160
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_random.1227053443
Short name T616
Test name
Test status
Simulation time 260254395 ps
CPU time 4.41 seconds
Started Aug 07 06:18:41 PM PDT 24
Finished Aug 07 06:18:46 PM PDT 24
Peak memory 209208 kb
Host smart-48b39e66-dbd2-4697-94ca-ed7bbc67a612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227053443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1227053443
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.852525431
Short name T484
Test name
Test status
Simulation time 85539660 ps
CPU time 2.65 seconds
Started Aug 07 06:18:40 PM PDT 24
Finished Aug 07 06:18:42 PM PDT 24
Peak memory 208500 kb
Host smart-e663527e-e7b8-45d8-af23-fa4e49894242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852525431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.852525431
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.601815262
Short name T643
Test name
Test status
Simulation time 67809917 ps
CPU time 3.37 seconds
Started Aug 07 06:18:42 PM PDT 24
Finished Aug 07 06:18:45 PM PDT 24
Peak memory 208296 kb
Host smart-e796b569-7e61-4480-9041-17b0b4e0b937
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601815262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.601815262
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.185245096
Short name T654
Test name
Test status
Simulation time 51297350 ps
CPU time 2.6 seconds
Started Aug 07 06:18:38 PM PDT 24
Finished Aug 07 06:18:41 PM PDT 24
Peak memory 207500 kb
Host smart-c02b46ff-2242-42ed-8cb1-11a31dfad34c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185245096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.185245096
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3656335905
Short name T733
Test name
Test status
Simulation time 145670987 ps
CPU time 2.82 seconds
Started Aug 07 06:18:39 PM PDT 24
Finished Aug 07 06:18:42 PM PDT 24
Peak memory 208864 kb
Host smart-648627db-173b-4899-ab68-1db607a9db76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656335905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3656335905
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2170102915
Short name T224
Test name
Test status
Simulation time 1255519408 ps
CPU time 22.03 seconds
Started Aug 07 06:18:40 PM PDT 24
Finished Aug 07 06:19:02 PM PDT 24
Peak memory 209628 kb
Host smart-82cda880-f9e4-4b10-9407-5d798e0d8be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170102915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2170102915
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.969780945
Short name T1
Test name
Test status
Simulation time 26946717 ps
CPU time 1.69 seconds
Started Aug 07 06:18:40 PM PDT 24
Finished Aug 07 06:18:42 PM PDT 24
Peak memory 206620 kb
Host smart-f79b5551-e070-498c-bc0e-d17ca0fe44c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969780945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.969780945
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3857939682
Short name T556
Test name
Test status
Simulation time 73453728 ps
CPU time 3.7 seconds
Started Aug 07 06:18:39 PM PDT 24
Finished Aug 07 06:18:43 PM PDT 24
Peak memory 209496 kb
Host smart-8f32f3e1-03ad-418b-83a2-bc606a4842aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857939682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3857939682
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1428164837
Short name T445
Test name
Test status
Simulation time 101524571 ps
CPU time 2.01 seconds
Started Aug 07 06:18:37 PM PDT 24
Finished Aug 07 06:18:39 PM PDT 24
Peak memory 209832 kb
Host smart-40edd0a0-a061-4106-9bfe-5e4f03344443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428164837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1428164837
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.526958531
Short name T663
Test name
Test status
Simulation time 12955021 ps
CPU time 0.79 seconds
Started Aug 07 06:18:44 PM PDT 24
Finished Aug 07 06:18:45 PM PDT 24
Peak memory 205972 kb
Host smart-e21b13bf-0897-4746-bcff-c5d605881bbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526958531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.526958531
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2221079808
Short name T702
Test name
Test status
Simulation time 637855063 ps
CPU time 5.85 seconds
Started Aug 07 06:18:44 PM PDT 24
Finished Aug 07 06:18:50 PM PDT 24
Peak memory 221996 kb
Host smart-5f9d87b8-8154-4d52-b6d1-fd41e48003e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221079808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2221079808
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1724338437
Short name T3
Test name
Test status
Simulation time 175813407 ps
CPU time 4.91 seconds
Started Aug 07 06:18:46 PM PDT 24
Finished Aug 07 06:18:51 PM PDT 24
Peak memory 209856 kb
Host smart-4c9c69b4-c41a-4944-9155-90b2c1a5a42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724338437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1724338437
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1192869079
Short name T286
Test name
Test status
Simulation time 229692760 ps
CPU time 3.17 seconds
Started Aug 07 06:18:44 PM PDT 24
Finished Aug 07 06:18:47 PM PDT 24
Peak memory 206048 kb
Host smart-2c7df0b8-cb1c-4919-b435-98df0fced5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192869079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1192869079
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2867842809
Short name T508
Test name
Test status
Simulation time 291052265 ps
CPU time 2.61 seconds
Started Aug 07 06:18:46 PM PDT 24
Finished Aug 07 06:18:49 PM PDT 24
Peak memory 206676 kb
Host smart-729f10ad-2bff-4f29-9535-c91761967a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867842809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2867842809
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1296772112
Short name T104
Test name
Test status
Simulation time 240033651 ps
CPU time 6.74 seconds
Started Aug 07 06:18:45 PM PDT 24
Finished Aug 07 06:18:52 PM PDT 24
Peak memory 214332 kb
Host smart-5631ba95-af8b-4ab4-a5d6-afacb3753daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296772112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1296772112
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.440826138
Short name T189
Test name
Test status
Simulation time 118958347 ps
CPU time 3.76 seconds
Started Aug 07 06:18:44 PM PDT 24
Finished Aug 07 06:18:48 PM PDT 24
Peak memory 206860 kb
Host smart-80afccbf-fd02-4a11-9a47-d3d1657b0cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440826138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.440826138
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.97131153
Short name T384
Test name
Test status
Simulation time 101078405 ps
CPU time 3.3 seconds
Started Aug 07 06:18:45 PM PDT 24
Finished Aug 07 06:18:49 PM PDT 24
Peak memory 206852 kb
Host smart-8643e0e1-08b9-4ae0-9c9a-ad51d89158da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97131153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.97131153
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1738440862
Short name T517
Test name
Test status
Simulation time 194882428 ps
CPU time 7.01 seconds
Started Aug 07 06:18:45 PM PDT 24
Finished Aug 07 06:18:52 PM PDT 24
Peak memory 208672 kb
Host smart-1b7c4dcd-fd5d-43ac-8566-e42726497b07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738440862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1738440862
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.883910234
Short name T679
Test name
Test status
Simulation time 45834137 ps
CPU time 2.67 seconds
Started Aug 07 06:18:46 PM PDT 24
Finished Aug 07 06:18:49 PM PDT 24
Peak memory 208816 kb
Host smart-7e2af53e-fc97-4f3c-85d4-500b223aa617
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883910234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.883910234
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3262599868
Short name T337
Test name
Test status
Simulation time 117279552 ps
CPU time 3.19 seconds
Started Aug 07 06:18:45 PM PDT 24
Finished Aug 07 06:18:48 PM PDT 24
Peak memory 209476 kb
Host smart-e13a29d5-f689-4333-ab5d-22220c183025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262599868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3262599868
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1518627526
Short name T500
Test name
Test status
Simulation time 192467318 ps
CPU time 3.73 seconds
Started Aug 07 06:18:45 PM PDT 24
Finished Aug 07 06:18:49 PM PDT 24
Peak memory 206840 kb
Host smart-ebde09f6-cc28-4118-a14f-bda68924bbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518627526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1518627526
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1462849472
Short name T279
Test name
Test status
Simulation time 374055869 ps
CPU time 12.37 seconds
Started Aug 07 06:18:44 PM PDT 24
Finished Aug 07 06:18:56 PM PDT 24
Peak memory 219812 kb
Host smart-4d54af4e-3932-4ca7-a487-1bc10e32ab0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462849472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1462849472
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.709653480
Short name T653
Test name
Test status
Simulation time 135267042 ps
CPU time 3.59 seconds
Started Aug 07 06:18:43 PM PDT 24
Finished Aug 07 06:18:47 PM PDT 24
Peak memory 207784 kb
Host smart-4b7bb947-9da3-442a-9fe5-379723e1924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709653480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.709653480
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.220775275
Short name T502
Test name
Test status
Simulation time 826805643 ps
CPU time 1.84 seconds
Started Aug 07 06:18:46 PM PDT 24
Finished Aug 07 06:18:48 PM PDT 24
Peak memory 210772 kb
Host smart-d49639f6-83ab-47ae-83b6-2dfe5c8e1364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220775275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.220775275
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3322069584
Short name T720
Test name
Test status
Simulation time 41886314 ps
CPU time 0.88 seconds
Started Aug 07 06:17:15 PM PDT 24
Finished Aug 07 06:17:16 PM PDT 24
Peak memory 206132 kb
Host smart-69caa734-6d2d-44fa-843f-7a021bb1309e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322069584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3322069584
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1095488523
Short name T333
Test name
Test status
Simulation time 231224947 ps
CPU time 11.78 seconds
Started Aug 07 06:17:09 PM PDT 24
Finished Aug 07 06:17:21 PM PDT 24
Peak memory 214948 kb
Host smart-1e4be471-5940-434e-b85f-1dfe02562dc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1095488523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1095488523
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.579212192
Short name T711
Test name
Test status
Simulation time 874593407 ps
CPU time 7.15 seconds
Started Aug 07 06:17:13 PM PDT 24
Finished Aug 07 06:17:20 PM PDT 24
Peak memory 214380 kb
Host smart-bb32dd4f-4d44-4393-9632-87e026fd9dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579212192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.579212192
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.688301045
Short name T877
Test name
Test status
Simulation time 25987924 ps
CPU time 1.27 seconds
Started Aug 07 06:17:10 PM PDT 24
Finished Aug 07 06:17:11 PM PDT 24
Peak memory 206928 kb
Host smart-c9888dfe-4386-45b3-9487-dcb68e73ce64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688301045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.688301045
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1903423364
Short name T320
Test name
Test status
Simulation time 87754809 ps
CPU time 3.36 seconds
Started Aug 07 06:17:07 PM PDT 24
Finished Aug 07 06:17:10 PM PDT 24
Peak memory 208940 kb
Host smart-b56af66c-f3bc-468b-b7e4-d03a00c03aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903423364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1903423364
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.823323016
Short name T53
Test name
Test status
Simulation time 76613421 ps
CPU time 3.69 seconds
Started Aug 07 06:17:10 PM PDT 24
Finished Aug 07 06:17:14 PM PDT 24
Peak memory 220024 kb
Host smart-26d5930e-d347-49d5-95b1-3a06a73e0273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823323016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.823323016
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3761864101
Short name T199
Test name
Test status
Simulation time 71399360 ps
CPU time 2.3 seconds
Started Aug 07 06:17:09 PM PDT 24
Finished Aug 07 06:17:11 PM PDT 24
Peak memory 218412 kb
Host smart-7057ad03-9ec5-4cb1-9f17-df0c3391f9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761864101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3761864101
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.468993141
Short name T499
Test name
Test status
Simulation time 140137929 ps
CPU time 3.3 seconds
Started Aug 07 06:17:06 PM PDT 24
Finished Aug 07 06:17:10 PM PDT 24
Peak memory 208140 kb
Host smart-14f43a49-6a51-4214-8e45-18719dca6f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468993141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.468993141
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.654957271
Short name T13
Test name
Test status
Simulation time 1557266483 ps
CPU time 9.75 seconds
Started Aug 07 06:17:16 PM PDT 24
Finished Aug 07 06:17:25 PM PDT 24
Peak memory 233836 kb
Host smart-c4004ce8-4de1-4fb7-ac31-f9dbf81a5d01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654957271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.654957271
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3234829479
Short name T700
Test name
Test status
Simulation time 492988055 ps
CPU time 4.21 seconds
Started Aug 07 06:17:05 PM PDT 24
Finished Aug 07 06:17:09 PM PDT 24
Peak memory 209128 kb
Host smart-2a9dae65-269b-4aef-81a4-fb59aac952bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234829479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3234829479
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2274422438
Short name T541
Test name
Test status
Simulation time 402101316 ps
CPU time 1.94 seconds
Started Aug 07 06:17:06 PM PDT 24
Finished Aug 07 06:17:08 PM PDT 24
Peak memory 207028 kb
Host smart-5fc62d5b-8ad9-4a8e-8d84-eaa08c0f6ccc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274422438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2274422438
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2531954029
Short name T851
Test name
Test status
Simulation time 6161633841 ps
CPU time 65.19 seconds
Started Aug 07 06:17:07 PM PDT 24
Finished Aug 07 06:18:12 PM PDT 24
Peak memory 208496 kb
Host smart-4f80f00b-4e5c-4341-8a4d-84730394cd3d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531954029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2531954029
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3830280935
Short name T782
Test name
Test status
Simulation time 348540157 ps
CPU time 7.38 seconds
Started Aug 07 06:17:07 PM PDT 24
Finished Aug 07 06:17:15 PM PDT 24
Peak memory 208632 kb
Host smart-8db43f6b-71a9-4146-a26c-741e7c35d8bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830280935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3830280935
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3530695854
Short name T781
Test name
Test status
Simulation time 443294577 ps
CPU time 3.07 seconds
Started Aug 07 06:17:13 PM PDT 24
Finished Aug 07 06:17:16 PM PDT 24
Peak memory 222464 kb
Host smart-668f5e6f-726d-4c5d-a1fe-834cb8f9ceef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530695854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3530695854
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1004688621
Short name T581
Test name
Test status
Simulation time 189487244 ps
CPU time 2.65 seconds
Started Aug 07 06:17:07 PM PDT 24
Finished Aug 07 06:17:10 PM PDT 24
Peak memory 207040 kb
Host smart-6e0c2508-8ee2-4dc6-a58b-df29d9e798c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004688621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1004688621
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1497971021
Short name T187
Test name
Test status
Simulation time 295242825 ps
CPU time 6.58 seconds
Started Aug 07 06:17:15 PM PDT 24
Finished Aug 07 06:17:22 PM PDT 24
Peak memory 218112 kb
Host smart-c8b17ad9-5add-4c50-839a-c857e0a64d9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497971021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1497971021
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.4037658955
Short name T339
Test name
Test status
Simulation time 99727698 ps
CPU time 4.68 seconds
Started Aug 07 06:17:05 PM PDT 24
Finished Aug 07 06:17:09 PM PDT 24
Peak memory 207000 kb
Host smart-310f7411-364e-4944-b841-04169b34d091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037658955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.4037658955
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1738881260
Short name T439
Test name
Test status
Simulation time 152901896 ps
CPU time 2.91 seconds
Started Aug 07 06:17:14 PM PDT 24
Finished Aug 07 06:17:17 PM PDT 24
Peak memory 209932 kb
Host smart-bfd1ea28-605f-4dbb-9a91-1ab9d34eee70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738881260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1738881260
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2373231233
Short name T473
Test name
Test status
Simulation time 11773788 ps
CPU time 0.91 seconds
Started Aug 07 06:18:47 PM PDT 24
Finished Aug 07 06:18:48 PM PDT 24
Peak memory 206048 kb
Host smart-6be81dd4-ba8b-47ee-ba84-a074c3058aff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373231233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2373231233
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2755111437
Short name T701
Test name
Test status
Simulation time 1706867207 ps
CPU time 5.41 seconds
Started Aug 07 06:18:44 PM PDT 24
Finished Aug 07 06:18:49 PM PDT 24
Peak memory 208568 kb
Host smart-37daa74b-5a17-48d2-b0ce-7048065d57ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755111437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2755111437
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.558511103
Short name T234
Test name
Test status
Simulation time 31372991 ps
CPU time 1.86 seconds
Started Aug 07 06:18:45 PM PDT 24
Finished Aug 07 06:18:47 PM PDT 24
Peak memory 214384 kb
Host smart-487c8b9d-ddd5-430c-8997-b04ccb676d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558511103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.558511103
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1224917728
Short name T546
Test name
Test status
Simulation time 104919093 ps
CPU time 5.33 seconds
Started Aug 07 06:18:48 PM PDT 24
Finished Aug 07 06:18:53 PM PDT 24
Peak memory 218148 kb
Host smart-d45ec8f5-52ce-48bf-acd8-6a14c1b6f7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224917728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1224917728
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1600337762
Short name T627
Test name
Test status
Simulation time 41912468 ps
CPU time 3.01 seconds
Started Aug 07 06:18:43 PM PDT 24
Finished Aug 07 06:18:47 PM PDT 24
Peak memory 214312 kb
Host smart-305716fc-7124-4361-ad35-f586ad91a048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600337762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1600337762
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1161692029
Short name T17
Test name
Test status
Simulation time 156538105 ps
CPU time 4.59 seconds
Started Aug 07 06:18:47 PM PDT 24
Finished Aug 07 06:18:51 PM PDT 24
Peak memory 208468 kb
Host smart-f40db1f3-736f-489f-a3b3-c755a2d3a33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161692029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1161692029
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3723798583
Short name T301
Test name
Test status
Simulation time 39646204 ps
CPU time 2.6 seconds
Started Aug 07 06:18:43 PM PDT 24
Finished Aug 07 06:18:45 PM PDT 24
Peak memory 208692 kb
Host smart-9ad18d41-6467-4521-a2f7-c411808a5c5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723798583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3723798583
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2722600807
Short name T470
Test name
Test status
Simulation time 420038600 ps
CPU time 5.06 seconds
Started Aug 07 06:18:46 PM PDT 24
Finished Aug 07 06:18:51 PM PDT 24
Peak memory 208648 kb
Host smart-55cc034e-1fb9-4ee6-bc7a-3f44f23a7429
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722600807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2722600807
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1009596643
Short name T467
Test name
Test status
Simulation time 272520392 ps
CPU time 3.85 seconds
Started Aug 07 06:18:44 PM PDT 24
Finished Aug 07 06:18:48 PM PDT 24
Peak memory 207020 kb
Host smart-63175bf2-73e4-47aa-b7f2-016664f0ed86
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009596643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1009596643
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2709071926
Short name T456
Test name
Test status
Simulation time 132174578 ps
CPU time 3.42 seconds
Started Aug 07 06:18:45 PM PDT 24
Finished Aug 07 06:18:48 PM PDT 24
Peak memory 216232 kb
Host smart-61923b0f-f7a8-4d7d-8eb6-c1c3a2c5e8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709071926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2709071926
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1712081664
Short name T433
Test name
Test status
Simulation time 201714682 ps
CPU time 4.21 seconds
Started Aug 07 06:18:44 PM PDT 24
Finished Aug 07 06:18:48 PM PDT 24
Peak memory 207984 kb
Host smart-fbcc1aa0-5a34-432a-86dd-ba92723d45b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712081664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1712081664
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2793278290
Short name T202
Test name
Test status
Simulation time 2637703771 ps
CPU time 32.37 seconds
Started Aug 07 06:18:45 PM PDT 24
Finished Aug 07 06:19:18 PM PDT 24
Peak memory 217004 kb
Host smart-56362089-69c7-4cf9-8463-4186f3090ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793278290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2793278290
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2780952332
Short name T689
Test name
Test status
Simulation time 276481761 ps
CPU time 15.78 seconds
Started Aug 07 06:18:45 PM PDT 24
Finished Aug 07 06:19:01 PM PDT 24
Peak memory 222584 kb
Host smart-cda527db-9cb6-4948-bc6f-70db641c48f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780952332 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2780952332
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1279139221
Short name T570
Test name
Test status
Simulation time 24213639534 ps
CPU time 61.16 seconds
Started Aug 07 06:18:44 PM PDT 24
Finished Aug 07 06:19:45 PM PDT 24
Peak memory 209512 kb
Host smart-23139f73-67cb-4610-a24f-dd74e9c325f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279139221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1279139221
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2462673790
Short name T185
Test name
Test status
Simulation time 66132704 ps
CPU time 2.77 seconds
Started Aug 07 06:18:46 PM PDT 24
Finished Aug 07 06:18:49 PM PDT 24
Peak memory 210172 kb
Host smart-e9fcd1dc-b9a0-4a75-a0aa-16ba0bbc6e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462673790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2462673790
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.837285572
Short name T860
Test name
Test status
Simulation time 56894327 ps
CPU time 0.77 seconds
Started Aug 07 06:18:50 PM PDT 24
Finished Aug 07 06:18:51 PM PDT 24
Peak memory 205948 kb
Host smart-cc7a62d6-8657-4c27-869b-fcbcc0bb0f82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837285572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.837285572
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2394617726
Short name T454
Test name
Test status
Simulation time 229259935 ps
CPU time 2.88 seconds
Started Aug 07 06:18:51 PM PDT 24
Finished Aug 07 06:18:54 PM PDT 24
Peak memory 214400 kb
Host smart-8340f9c9-0d1e-4619-8034-5bf00307e186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394617726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2394617726
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2956634621
Short name T833
Test name
Test status
Simulation time 307424103 ps
CPU time 7.12 seconds
Started Aug 07 06:18:49 PM PDT 24
Finished Aug 07 06:18:56 PM PDT 24
Peak memory 219692 kb
Host smart-c21122da-2d67-4608-a42e-53b62607456d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956634621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2956634621
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2626543781
Short name T664
Test name
Test status
Simulation time 283876857 ps
CPU time 2.11 seconds
Started Aug 07 06:18:52 PM PDT 24
Finished Aug 07 06:18:55 PM PDT 24
Peak memory 222548 kb
Host smart-18ef5bb6-0d57-4619-87e9-7b35dcef8aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626543781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2626543781
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1433006997
Short name T859
Test name
Test status
Simulation time 440102413 ps
CPU time 4.75 seconds
Started Aug 07 06:18:53 PM PDT 24
Finished Aug 07 06:18:58 PM PDT 24
Peak memory 214288 kb
Host smart-5b6a0b0e-86b8-4a34-877d-93c44c893863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433006997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1433006997
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2181840125
Short name T6
Test name
Test status
Simulation time 273855117 ps
CPU time 3.42 seconds
Started Aug 07 06:18:49 PM PDT 24
Finished Aug 07 06:18:53 PM PDT 24
Peak memory 219852 kb
Host smart-d10338f6-4f39-445d-8fe8-fb0c48d1972a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181840125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2181840125
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.401772503
Short name T244
Test name
Test status
Simulation time 412429819 ps
CPU time 4.98 seconds
Started Aug 07 06:18:48 PM PDT 24
Finished Aug 07 06:18:53 PM PDT 24
Peak memory 218396 kb
Host smart-d30a1553-c0ae-40ae-8ee9-9086bce03952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401772503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.401772503
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3449551612
Short name T611
Test name
Test status
Simulation time 82183507 ps
CPU time 1.83 seconds
Started Aug 07 06:18:49 PM PDT 24
Finished Aug 07 06:18:50 PM PDT 24
Peak memory 206996 kb
Host smart-b0770ff5-177a-4e65-b827-c5260effe480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449551612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3449551612
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3594009933
Short name T426
Test name
Test status
Simulation time 1975630114 ps
CPU time 7.17 seconds
Started Aug 07 06:18:49 PM PDT 24
Finished Aug 07 06:18:57 PM PDT 24
Peak memory 208264 kb
Host smart-a671479e-e90c-4035-a87e-f0b2fd00d9f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594009933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3594009933
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2052987742
Short name T712
Test name
Test status
Simulation time 220628163 ps
CPU time 3.56 seconds
Started Aug 07 06:18:51 PM PDT 24
Finished Aug 07 06:18:55 PM PDT 24
Peak memory 208520 kb
Host smart-23660cf0-3a9a-41a0-89c3-473db38106f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052987742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2052987742
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3371180339
Short name T537
Test name
Test status
Simulation time 43630268 ps
CPU time 2.77 seconds
Started Aug 07 06:18:50 PM PDT 24
Finished Aug 07 06:18:53 PM PDT 24
Peak memory 209008 kb
Host smart-93cc4dc7-0ee2-4d67-9fcb-b3f4b23f446d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371180339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3371180339
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.4136060655
Short name T449
Test name
Test status
Simulation time 74123244 ps
CPU time 2.34 seconds
Started Aug 07 06:18:48 PM PDT 24
Finished Aug 07 06:18:51 PM PDT 24
Peak memory 218232 kb
Host smart-272ebc28-f521-4aff-afd5-3bfa3a0b833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136060655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.4136060655
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.780806572
Short name T420
Test name
Test status
Simulation time 156984291 ps
CPU time 4.14 seconds
Started Aug 07 06:18:53 PM PDT 24
Finished Aug 07 06:18:57 PM PDT 24
Peak memory 208808 kb
Host smart-774b9415-8679-44d2-970f-c1fd060e2f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780806572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.780806572
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1862253993
Short name T842
Test name
Test status
Simulation time 902560017 ps
CPU time 34.24 seconds
Started Aug 07 06:18:49 PM PDT 24
Finished Aug 07 06:19:23 PM PDT 24
Peak memory 222180 kb
Host smart-8963cc7b-d786-4772-a1ea-c0d33000c4a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862253993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1862253993
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.942217134
Short name T5
Test name
Test status
Simulation time 187418926 ps
CPU time 8.1 seconds
Started Aug 07 06:18:49 PM PDT 24
Finished Aug 07 06:18:57 PM PDT 24
Peak memory 222672 kb
Host smart-26c5f7f8-ba61-4c4e-bf12-5f07967f7490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942217134 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.942217134
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2958454749
Short name T874
Test name
Test status
Simulation time 974549026 ps
CPU time 5.83 seconds
Started Aug 07 06:18:52 PM PDT 24
Finished Aug 07 06:18:58 PM PDT 24
Peak memory 214256 kb
Host smart-82e893f9-8710-48be-a517-8540f245d10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958454749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2958454749
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.347615672
Short name T831
Test name
Test status
Simulation time 130210319 ps
CPU time 2.62 seconds
Started Aug 07 06:18:50 PM PDT 24
Finished Aug 07 06:18:52 PM PDT 24
Peak memory 210208 kb
Host smart-9850623e-0932-4927-b8a1-9af94e3332f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347615672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.347615672
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1789785216
Short name T428
Test name
Test status
Simulation time 18823001 ps
CPU time 0.84 seconds
Started Aug 07 06:18:57 PM PDT 24
Finished Aug 07 06:18:58 PM PDT 24
Peak memory 205976 kb
Host smart-21f64255-aa05-4666-ae35-1feccbeb0654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789785216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1789785216
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2469205853
Short name T210
Test name
Test status
Simulation time 485047026 ps
CPU time 5.33 seconds
Started Aug 07 06:18:50 PM PDT 24
Finished Aug 07 06:18:56 PM PDT 24
Peak memory 210652 kb
Host smart-c216b4d8-6321-4b00-8a02-23f124084ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469205853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2469205853
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.732152935
Short name T532
Test name
Test status
Simulation time 286319660 ps
CPU time 4.3 seconds
Started Aug 07 06:18:51 PM PDT 24
Finished Aug 07 06:18:56 PM PDT 24
Peak memory 208252 kb
Host smart-c1f764be-7b29-4998-9dec-173b7b4b36d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732152935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.732152935
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3795478875
Short name T488
Test name
Test status
Simulation time 99610064 ps
CPU time 4.65 seconds
Started Aug 07 06:18:50 PM PDT 24
Finished Aug 07 06:18:55 PM PDT 24
Peak memory 219512 kb
Host smart-63682104-79f9-4271-94ce-70a75511027c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795478875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3795478875
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.212132534
Short name T331
Test name
Test status
Simulation time 806042905 ps
CPU time 3.52 seconds
Started Aug 07 06:18:49 PM PDT 24
Finished Aug 07 06:18:52 PM PDT 24
Peak memory 219536 kb
Host smart-e2429f36-2189-4274-b7d9-31c9bef8f6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212132534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.212132534
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2220364788
Short name T709
Test name
Test status
Simulation time 567856601 ps
CPU time 4.97 seconds
Started Aug 07 06:18:50 PM PDT 24
Finished Aug 07 06:18:55 PM PDT 24
Peak memory 214968 kb
Host smart-af7d692b-f7f8-4f0d-83c0-7d5a106729b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220364788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2220364788
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.225874389
Short name T803
Test name
Test status
Simulation time 1473036732 ps
CPU time 19.72 seconds
Started Aug 07 06:18:55 PM PDT 24
Finished Aug 07 06:19:15 PM PDT 24
Peak memory 208932 kb
Host smart-8dcdcf05-91c5-4eb7-ac96-a43b4d125e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225874389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.225874389
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1886551041
Short name T855
Test name
Test status
Simulation time 65774841 ps
CPU time 3.27 seconds
Started Aug 07 06:18:51 PM PDT 24
Finished Aug 07 06:18:55 PM PDT 24
Peak memory 208480 kb
Host smart-af6d1cea-3a15-476d-81af-55707f0568c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886551041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1886551041
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3993947577
Short name T773
Test name
Test status
Simulation time 68705442 ps
CPU time 2.83 seconds
Started Aug 07 06:18:51 PM PDT 24
Finished Aug 07 06:18:54 PM PDT 24
Peak memory 206960 kb
Host smart-936c0b99-d3ec-41c5-b904-45eed85c8c36
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993947577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3993947577
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3268361484
Short name T724
Test name
Test status
Simulation time 94786747 ps
CPU time 2.92 seconds
Started Aug 07 06:18:49 PM PDT 24
Finished Aug 07 06:18:52 PM PDT 24
Peak memory 207072 kb
Host smart-5665a23e-9e49-47cd-a71f-4eff575a5ac7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268361484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3268361484
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.573770902
Short name T529
Test name
Test status
Simulation time 176851430 ps
CPU time 3.21 seconds
Started Aug 07 06:18:51 PM PDT 24
Finished Aug 07 06:18:54 PM PDT 24
Peak memory 206908 kb
Host smart-2cd7b46b-8cab-46c2-a8d8-e7b850fa553a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573770902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.573770902
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1577557259
Short name T617
Test name
Test status
Simulation time 1036537222 ps
CPU time 10.05 seconds
Started Aug 07 06:18:50 PM PDT 24
Finished Aug 07 06:19:00 PM PDT 24
Peak memory 218528 kb
Host smart-9759a697-97bc-4106-9723-f1d94c6558df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577557259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1577557259
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2001671412
Short name T849
Test name
Test status
Simulation time 87523258 ps
CPU time 2.03 seconds
Started Aug 07 06:18:48 PM PDT 24
Finished Aug 07 06:18:50 PM PDT 24
Peak memory 208628 kb
Host smart-ae2ec116-5741-4a8e-9417-10c791d37bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001671412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2001671412
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3665023788
Short name T200
Test name
Test status
Simulation time 9320411954 ps
CPU time 97.56 seconds
Started Aug 07 06:18:51 PM PDT 24
Finished Aug 07 06:20:29 PM PDT 24
Peak memory 220556 kb
Host smart-22a86dc6-3408-4df1-bf5a-9ba03706786d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665023788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3665023788
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1909488115
Short name T318
Test name
Test status
Simulation time 168596146 ps
CPU time 5.6 seconds
Started Aug 07 06:18:51 PM PDT 24
Finished Aug 07 06:18:56 PM PDT 24
Peak memory 214336 kb
Host smart-28e2de60-a6ae-42b8-b891-013ca96644de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909488115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1909488115
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3644867386
Short name T494
Test name
Test status
Simulation time 15273737 ps
CPU time 0.92 seconds
Started Aug 07 06:18:56 PM PDT 24
Finished Aug 07 06:18:57 PM PDT 24
Peak memory 206144 kb
Host smart-7a0296bb-a7a9-4a16-967f-1f21b5eeb0ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644867386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3644867386
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3774632483
Short name T29
Test name
Test status
Simulation time 85162804 ps
CPU time 1.98 seconds
Started Aug 07 06:18:56 PM PDT 24
Finished Aug 07 06:18:58 PM PDT 24
Peak memory 221544 kb
Host smart-c146b0a6-f064-409b-87a0-da901fa5f462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774632483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3774632483
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.4026853859
Short name T498
Test name
Test status
Simulation time 111178593 ps
CPU time 3.76 seconds
Started Aug 07 06:18:56 PM PDT 24
Finished Aug 07 06:19:00 PM PDT 24
Peak memory 209876 kb
Host smart-cf10c4cd-8eb0-40bb-9310-d1a87523deca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026853859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.4026853859
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.320345490
Short name T472
Test name
Test status
Simulation time 73696497 ps
CPU time 2.67 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:03 PM PDT 24
Peak memory 214324 kb
Host smart-e49f14e1-33a0-4aea-a932-b4a3f48c7f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320345490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.320345490
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1070426358
Short name T852
Test name
Test status
Simulation time 38438449 ps
CPU time 2.38 seconds
Started Aug 07 06:18:57 PM PDT 24
Finished Aug 07 06:18:59 PM PDT 24
Peak memory 214948 kb
Host smart-1e7e1fcf-2953-4a6f-81e1-b65ab2afd9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070426358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1070426358
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.830344701
Short name T522
Test name
Test status
Simulation time 87269069 ps
CPU time 4.16 seconds
Started Aug 07 06:18:58 PM PDT 24
Finished Aug 07 06:19:03 PM PDT 24
Peak memory 210208 kb
Host smart-d039ad1d-d555-475e-9fc9-fec77c9e1400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830344701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.830344701
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1133215211
Short name T322
Test name
Test status
Simulation time 562362559 ps
CPU time 12.11 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:12 PM PDT 24
Peak memory 218260 kb
Host smart-beb77ff1-c0c4-4e30-a730-f01686486234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133215211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1133215211
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3333079216
Short name T280
Test name
Test status
Simulation time 277661532 ps
CPU time 2.83 seconds
Started Aug 07 06:18:55 PM PDT 24
Finished Aug 07 06:18:58 PM PDT 24
Peak memory 207576 kb
Host smart-1fbab5d4-f3a9-44e5-b417-1fe2aeaf1c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333079216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3333079216
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2927218820
Short name T676
Test name
Test status
Simulation time 373813928 ps
CPU time 6.99 seconds
Started Aug 07 06:18:56 PM PDT 24
Finished Aug 07 06:19:03 PM PDT 24
Peak memory 208004 kb
Host smart-c9d7cf50-b622-43b1-abd0-1c7d357b9008
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927218820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2927218820
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1199448757
Short name T620
Test name
Test status
Simulation time 8641017253 ps
CPU time 25.45 seconds
Started Aug 07 06:18:53 PM PDT 24
Finished Aug 07 06:19:18 PM PDT 24
Peak memory 208256 kb
Host smart-53944adc-6a6d-453a-b126-4bfa9bdb7ba1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199448757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1199448757
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2876591477
Short name T501
Test name
Test status
Simulation time 666772474 ps
CPU time 5.24 seconds
Started Aug 07 06:18:52 PM PDT 24
Finished Aug 07 06:18:58 PM PDT 24
Peak memory 208072 kb
Host smart-8848913e-a8b4-45f9-b399-65a4741dc4c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876591477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2876591477
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1287867159
Short name T715
Test name
Test status
Simulation time 128447015 ps
CPU time 2.09 seconds
Started Aug 07 06:18:58 PM PDT 24
Finished Aug 07 06:19:00 PM PDT 24
Peak memory 215668 kb
Host smart-8589d68f-ed71-4c4f-ab37-c90b6e75aa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287867159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1287867159
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.264886295
Short name T105
Test name
Test status
Simulation time 721717985 ps
CPU time 4.62 seconds
Started Aug 07 06:18:54 PM PDT 24
Finished Aug 07 06:18:59 PM PDT 24
Peak memory 206964 kb
Host smart-40fb68fa-e811-4f78-bccb-055b5d16102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264886295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.264886295
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1901993684
Short name T168
Test name
Test status
Simulation time 1481854113 ps
CPU time 19.76 seconds
Started Aug 07 06:18:58 PM PDT 24
Finished Aug 07 06:19:18 PM PDT 24
Peak memory 221460 kb
Host smart-1d9145d3-ef50-4d23-b560-e2159e1266da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901993684 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1901993684
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3455595251
Short name T239
Test name
Test status
Simulation time 161981229 ps
CPU time 4.28 seconds
Started Aug 07 06:18:58 PM PDT 24
Finished Aug 07 06:19:03 PM PDT 24
Peak memory 207548 kb
Host smart-6f8fe8df-9d0c-4b63-bb4d-f6a318bb2963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455595251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3455595251
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3535538619
Short name T465
Test name
Test status
Simulation time 107322612 ps
CPU time 2.54 seconds
Started Aug 07 06:18:54 PM PDT 24
Finished Aug 07 06:18:57 PM PDT 24
Peak memory 209816 kb
Host smart-6b963131-c22f-4e8a-97da-ccf73344544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535538619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3535538619
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.275271740
Short name T614
Test name
Test status
Simulation time 160783152 ps
CPU time 0.81 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:01 PM PDT 24
Peak memory 205988 kb
Host smart-acdc9f90-70a5-4360-af00-471a5b50de22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275271740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.275271740
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.625711709
Short name T754
Test name
Test status
Simulation time 441821051 ps
CPU time 4.86 seconds
Started Aug 07 06:18:56 PM PDT 24
Finished Aug 07 06:19:01 PM PDT 24
Peak memory 222156 kb
Host smart-8e440ae4-3701-4f97-987b-b9db7b34267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625711709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.625711709
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1425126329
Short name T762
Test name
Test status
Simulation time 71289591 ps
CPU time 2.72 seconds
Started Aug 07 06:18:57 PM PDT 24
Finished Aug 07 06:19:00 PM PDT 24
Peak memory 207432 kb
Host smart-9472bbc2-8380-414c-9bcb-d1a408f944b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425126329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1425126329
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2671458401
Short name T93
Test name
Test status
Simulation time 1643145046 ps
CPU time 3.7 seconds
Started Aug 07 06:18:56 PM PDT 24
Finished Aug 07 06:19:00 PM PDT 24
Peak memory 220464 kb
Host smart-60a58ec8-eb4e-4117-8208-f4ab12375eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671458401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2671458401
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.642733252
Short name T903
Test name
Test status
Simulation time 147048110 ps
CPU time 4.21 seconds
Started Aug 07 06:18:57 PM PDT 24
Finished Aug 07 06:19:01 PM PDT 24
Peak memory 215488 kb
Host smart-1c9ace8a-7ce9-431a-b869-df9dc6e9e095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642733252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.642733252
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.816299625
Short name T336
Test name
Test status
Simulation time 459521339 ps
CPU time 5.48 seconds
Started Aug 07 06:18:55 PM PDT 24
Finished Aug 07 06:19:00 PM PDT 24
Peak memory 210452 kb
Host smart-fc24f8b8-d9ea-42e4-8957-b90cbda469cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816299625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.816299625
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2608438588
Short name T477
Test name
Test status
Simulation time 906043922 ps
CPU time 21.13 seconds
Started Aug 07 06:18:56 PM PDT 24
Finished Aug 07 06:19:17 PM PDT 24
Peak memory 208240 kb
Host smart-828a9737-1f95-4040-8030-55bbddd8c1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608438588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2608438588
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.524859777
Short name T415
Test name
Test status
Simulation time 78843772 ps
CPU time 3.52 seconds
Started Aug 07 06:18:58 PM PDT 24
Finished Aug 07 06:19:02 PM PDT 24
Peak memory 208284 kb
Host smart-368a899c-33c2-4cd7-a16b-ad154e7ae735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524859777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.524859777
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.830497477
Short name T761
Test name
Test status
Simulation time 1455800891 ps
CPU time 11.09 seconds
Started Aug 07 06:18:56 PM PDT 24
Finished Aug 07 06:19:08 PM PDT 24
Peak memory 207496 kb
Host smart-1d2e5dae-13eb-4a4e-95e8-f96aab856cea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830497477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.830497477
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.382954969
Short name T560
Test name
Test status
Simulation time 642621599 ps
CPU time 4.5 seconds
Started Aug 07 06:18:58 PM PDT 24
Finished Aug 07 06:19:02 PM PDT 24
Peak memory 207224 kb
Host smart-1fe896a8-7250-4453-b06c-6a84e597a5b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382954969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.382954969
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.61266879
Short name T490
Test name
Test status
Simulation time 207094455 ps
CPU time 2.78 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:03 PM PDT 24
Peak memory 208808 kb
Host smart-aa6dea0f-7843-404e-887d-79bdbb8c1cce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61266879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.61266879
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1785671596
Short name T418
Test name
Test status
Simulation time 143651444 ps
CPU time 2.1 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:02 PM PDT 24
Peak memory 214624 kb
Host smart-8c9b25fc-70d2-4f1b-a41b-709123e1f80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785671596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1785671596
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1405131913
Short name T451
Test name
Test status
Simulation time 56871110 ps
CPU time 2.23 seconds
Started Aug 07 06:18:55 PM PDT 24
Finished Aug 07 06:18:57 PM PDT 24
Peak memory 207132 kb
Host smart-c1e23016-9c0f-4173-b05f-3cbe1d16a9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405131913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1405131913
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.978933065
Short name T180
Test name
Test status
Simulation time 1821806602 ps
CPU time 46.04 seconds
Started Aug 07 06:18:59 PM PDT 24
Finished Aug 07 06:19:45 PM PDT 24
Peak memory 215724 kb
Host smart-6bdd186c-0233-4c6e-907c-88305cde6ba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978933065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.978933065
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1751517669
Short name T312
Test name
Test status
Simulation time 376605069 ps
CPU time 4.73 seconds
Started Aug 07 06:18:57 PM PDT 24
Finished Aug 07 06:19:02 PM PDT 24
Peak memory 210456 kb
Host smart-a0eec689-98b0-4511-a720-47c2215f75df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751517669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1751517669
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2119796135
Short name T526
Test name
Test status
Simulation time 31263672 ps
CPU time 1.91 seconds
Started Aug 07 06:18:57 PM PDT 24
Finished Aug 07 06:18:59 PM PDT 24
Peak memory 210092 kb
Host smart-270ff098-9c8d-4803-b32a-0d51a489aa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119796135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2119796135
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.4165791637
Short name T697
Test name
Test status
Simulation time 22998029 ps
CPU time 0.95 seconds
Started Aug 07 06:19:02 PM PDT 24
Finished Aug 07 06:19:03 PM PDT 24
Peak memory 205980 kb
Host smart-d1ce9562-2eba-48d7-8427-412120939f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165791637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.4165791637
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.54765464
Short name T340
Test name
Test status
Simulation time 247223890 ps
CPU time 6.7 seconds
Started Aug 07 06:19:05 PM PDT 24
Finished Aug 07 06:19:11 PM PDT 24
Peak memory 215344 kb
Host smart-d6492625-44eb-45c4-8405-897e48ceee6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54765464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.54765464
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3179063555
Short name T457
Test name
Test status
Simulation time 99930295 ps
CPU time 3.13 seconds
Started Aug 07 06:19:03 PM PDT 24
Finished Aug 07 06:19:07 PM PDT 24
Peak memory 218500 kb
Host smart-44890d32-9b9d-4612-acee-432b911a4707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179063555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3179063555
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.557335865
Short name T270
Test name
Test status
Simulation time 1370529055 ps
CPU time 2.96 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:03 PM PDT 24
Peak memory 208324 kb
Host smart-4699bc9e-5609-461e-92ee-6eb5d9e6976c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557335865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.557335865
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.986931502
Short name T825
Test name
Test status
Simulation time 329576918 ps
CPU time 4.13 seconds
Started Aug 07 06:19:03 PM PDT 24
Finished Aug 07 06:19:07 PM PDT 24
Peak memory 214592 kb
Host smart-d616ddd1-0e73-40f3-b387-eb47b62c2aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986931502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.986931502
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2335607050
Short name T545
Test name
Test status
Simulation time 104805460 ps
CPU time 4.64 seconds
Started Aug 07 06:18:59 PM PDT 24
Finished Aug 07 06:19:04 PM PDT 24
Peak memory 221588 kb
Host smart-ebe397c3-789c-4ce2-a682-4260fe2535b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335607050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2335607050
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.490438133
Short name T125
Test name
Test status
Simulation time 788554435 ps
CPU time 7.46 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:07 PM PDT 24
Peak memory 209848 kb
Host smart-c207e64f-878c-4337-8072-2044e0a50108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490438133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.490438133
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1607161608
Short name T641
Test name
Test status
Simulation time 47953477 ps
CPU time 2.88 seconds
Started Aug 07 06:19:03 PM PDT 24
Finished Aug 07 06:19:06 PM PDT 24
Peak memory 208980 kb
Host smart-1fc1f764-2706-472b-a468-9c1b2d19b78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607161608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1607161608
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.440390168
Short name T235
Test name
Test status
Simulation time 190207238 ps
CPU time 5.48 seconds
Started Aug 07 06:19:03 PM PDT 24
Finished Aug 07 06:19:09 PM PDT 24
Peak memory 208448 kb
Host smart-7ac6c021-5a16-48e0-b383-10718c02330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440390168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.440390168
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3275816826
Short name T511
Test name
Test status
Simulation time 166234944 ps
CPU time 4.41 seconds
Started Aug 07 06:19:01 PM PDT 24
Finished Aug 07 06:19:06 PM PDT 24
Peak memory 208752 kb
Host smart-3abd92b5-5264-4779-bb14-b0bced70e3b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275816826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3275816826
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1567828077
Short name T197
Test name
Test status
Simulation time 1146019984 ps
CPU time 9.25 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:09 PM PDT 24
Peak memory 208820 kb
Host smart-eca52c28-e857-48fd-8547-b60806fbb675
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567828077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1567828077
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.541944786
Short name T705
Test name
Test status
Simulation time 387478729 ps
CPU time 8.37 seconds
Started Aug 07 06:19:03 PM PDT 24
Finished Aug 07 06:19:11 PM PDT 24
Peak memory 208716 kb
Host smart-fa7fa142-12f7-4aa5-9126-57a37d88c9f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541944786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.541944786
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3686560494
Short name T652
Test name
Test status
Simulation time 181565871 ps
CPU time 2.35 seconds
Started Aug 07 06:19:01 PM PDT 24
Finished Aug 07 06:19:04 PM PDT 24
Peak memory 208088 kb
Host smart-f2e7f748-2a58-4d3e-b630-3c5241abc2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686560494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3686560494
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2351220396
Short name T865
Test name
Test status
Simulation time 418982607 ps
CPU time 3.17 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:04 PM PDT 24
Peak memory 206912 kb
Host smart-b23761ce-26f2-4938-8953-80a4abe5674d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351220396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2351220396
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.841746716
Short name T567
Test name
Test status
Simulation time 1237322831 ps
CPU time 7.34 seconds
Started Aug 07 06:19:03 PM PDT 24
Finished Aug 07 06:19:10 PM PDT 24
Peak memory 209924 kb
Host smart-07e24342-f211-4df2-b4df-9d40791b38f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841746716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.841746716
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2838210867
Short name T45
Test name
Test status
Simulation time 300172566 ps
CPU time 5.64 seconds
Started Aug 07 06:18:58 PM PDT 24
Finished Aug 07 06:19:04 PM PDT 24
Peak memory 210884 kb
Host smart-c2e689ce-cbd8-461b-acf1-c5b1c2fc54ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838210867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2838210867
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.435270173
Short name T527
Test name
Test status
Simulation time 17759967 ps
CPU time 0.73 seconds
Started Aug 07 06:19:05 PM PDT 24
Finished Aug 07 06:19:06 PM PDT 24
Peak memory 205976 kb
Host smart-1d66536d-f865-4ec4-a71e-3c35f67b0d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435270173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.435270173
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3661071006
Short name T22
Test name
Test status
Simulation time 452811417 ps
CPU time 2.45 seconds
Started Aug 07 06:19:03 PM PDT 24
Finished Aug 07 06:19:06 PM PDT 24
Peak memory 222688 kb
Host smart-24a5dc7f-2182-4ddf-8f5f-f48f70a9521e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661071006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3661071006
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2759771648
Short name T345
Test name
Test status
Simulation time 184707304 ps
CPU time 4 seconds
Started Aug 07 06:19:02 PM PDT 24
Finished Aug 07 06:19:07 PM PDT 24
Peak memory 208164 kb
Host smart-82836829-d50c-44f3-95a5-4bd533d24444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759771648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2759771648
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2788211936
Short name T48
Test name
Test status
Simulation time 500651516 ps
CPU time 4.52 seconds
Started Aug 07 06:19:02 PM PDT 24
Finished Aug 07 06:19:07 PM PDT 24
Peak memory 207312 kb
Host smart-326a53cb-8dcb-4327-8942-a61c87eb9879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788211936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2788211936
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.778319928
Short name T424
Test name
Test status
Simulation time 35118109 ps
CPU time 2.01 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:02 PM PDT 24
Peak memory 214356 kb
Host smart-f163311f-e551-4bd0-bad8-9fb9862b7f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778319928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.778319928
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3582780642
Short name T218
Test name
Test status
Simulation time 114703848 ps
CPU time 3.25 seconds
Started Aug 07 06:19:01 PM PDT 24
Finished Aug 07 06:19:04 PM PDT 24
Peak memory 207644 kb
Host smart-3352f91b-b945-467d-b57b-102264e31bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582780642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3582780642
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2882107663
Short name T294
Test name
Test status
Simulation time 2043323444 ps
CPU time 13.91 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:14 PM PDT 24
Peak memory 218352 kb
Host smart-edc06cba-8dc8-4ffc-a5b5-c5710c278050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882107663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2882107663
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.155781859
Short name T408
Test name
Test status
Simulation time 218849683 ps
CPU time 3.7 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:04 PM PDT 24
Peak memory 206892 kb
Host smart-00ed7bf7-2350-4cfb-8a96-7ae11027f6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155781859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.155781859
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2320958391
Short name T729
Test name
Test status
Simulation time 22903919 ps
CPU time 1.94 seconds
Started Aug 07 06:19:01 PM PDT 24
Finished Aug 07 06:19:03 PM PDT 24
Peak memory 207004 kb
Host smart-f4bd5e60-f69d-4403-ae32-0162700b5b09
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320958391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2320958391
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1082085980
Short name T559
Test name
Test status
Simulation time 113049815 ps
CPU time 3.21 seconds
Started Aug 07 06:18:59 PM PDT 24
Finished Aug 07 06:19:03 PM PDT 24
Peak memory 208696 kb
Host smart-f8394f36-8448-4930-847e-21606333a66a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082085980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1082085980
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.566358187
Short name T342
Test name
Test status
Simulation time 1120310916 ps
CPU time 4.25 seconds
Started Aug 07 06:19:01 PM PDT 24
Finished Aug 07 06:19:05 PM PDT 24
Peak memory 207020 kb
Host smart-6d92224e-96fa-466b-913a-268560f719f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566358187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.566358187
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1343015078
Short name T293
Test name
Test status
Simulation time 488174994 ps
CPU time 6.49 seconds
Started Aug 07 06:19:06 PM PDT 24
Finished Aug 07 06:19:13 PM PDT 24
Peak memory 208668 kb
Host smart-023626af-66cc-4fc0-bb3e-0c976555425d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343015078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1343015078
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.254437656
Short name T671
Test name
Test status
Simulation time 60429268 ps
CPU time 2.15 seconds
Started Aug 07 06:19:00 PM PDT 24
Finished Aug 07 06:19:02 PM PDT 24
Peak memory 206868 kb
Host smart-db50b4c7-3799-4e02-a595-d965803174aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254437656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.254437656
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1833679933
Short name T486
Test name
Test status
Simulation time 1345880895 ps
CPU time 13.44 seconds
Started Aug 07 06:19:16 PM PDT 24
Finished Aug 07 06:19:29 PM PDT 24
Peak memory 221432 kb
Host smart-13ba8629-d270-4c55-8635-e252df296e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833679933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1833679933
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2322402504
Short name T807
Test name
Test status
Simulation time 273130476 ps
CPU time 9.58 seconds
Started Aug 07 06:19:07 PM PDT 24
Finished Aug 07 06:19:17 PM PDT 24
Peak memory 222596 kb
Host smart-4aa8896c-bc26-4ef4-8f47-cbb67f587c5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322402504 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2322402504
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3672257721
Short name T274
Test name
Test status
Simulation time 75651512 ps
CPU time 3.1 seconds
Started Aug 07 06:19:01 PM PDT 24
Finished Aug 07 06:19:04 PM PDT 24
Peak memory 214296 kb
Host smart-2b132802-4f65-4c47-9767-46f730eb8408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672257721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3672257721
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3448228039
Short name T373
Test name
Test status
Simulation time 423234541 ps
CPU time 2.47 seconds
Started Aug 07 06:19:12 PM PDT 24
Finished Aug 07 06:19:14 PM PDT 24
Peak memory 210152 kb
Host smart-4e8238c7-819c-467b-a404-01285f957518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448228039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3448228039
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.786991694
Short name T516
Test name
Test status
Simulation time 51681197 ps
CPU time 0.78 seconds
Started Aug 07 06:19:10 PM PDT 24
Finished Aug 07 06:19:11 PM PDT 24
Peak memory 205964 kb
Host smart-bf4a2831-5c06-4a2e-867f-7d9d58326018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786991694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.786991694
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2099974377
Short name T62
Test name
Test status
Simulation time 111505386 ps
CPU time 2.56 seconds
Started Aug 07 06:19:05 PM PDT 24
Finished Aug 07 06:19:08 PM PDT 24
Peak memory 217068 kb
Host smart-1b751130-a33c-40ab-b181-b930909357e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099974377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2099974377
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.593652970
Short name T678
Test name
Test status
Simulation time 134514917 ps
CPU time 3.51 seconds
Started Aug 07 06:19:08 PM PDT 24
Finished Aug 07 06:19:11 PM PDT 24
Peak memory 207612 kb
Host smart-5e2bc2a7-ed4c-41f9-a844-0c7f8e6205f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593652970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.593652970
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2832045808
Short name T894
Test name
Test status
Simulation time 250955145 ps
CPU time 3.22 seconds
Started Aug 07 06:19:09 PM PDT 24
Finished Aug 07 06:19:12 PM PDT 24
Peak memory 222404 kb
Host smart-49e77091-8577-4ad1-913a-803be2fbd050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832045808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2832045808
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3238520615
Short name T878
Test name
Test status
Simulation time 44001431 ps
CPU time 2.64 seconds
Started Aug 07 06:19:08 PM PDT 24
Finished Aug 07 06:19:10 PM PDT 24
Peak memory 209336 kb
Host smart-f4587d39-6e3f-4141-92e9-01e8e4fce8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238520615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3238520615
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1889612500
Short name T352
Test name
Test status
Simulation time 44949514 ps
CPU time 2.88 seconds
Started Aug 07 06:19:12 PM PDT 24
Finished Aug 07 06:19:15 PM PDT 24
Peak memory 210080 kb
Host smart-7ab56864-9513-4160-9935-2374880f503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889612500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1889612500
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.231904823
Short name T298
Test name
Test status
Simulation time 78709191 ps
CPU time 2.45 seconds
Started Aug 07 06:19:15 PM PDT 24
Finished Aug 07 06:19:18 PM PDT 24
Peak memory 207228 kb
Host smart-1baf7fa8-5d35-49fa-b7ab-66886e462248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231904823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.231904823
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.792224606
Short name T577
Test name
Test status
Simulation time 42204183 ps
CPU time 1.94 seconds
Started Aug 07 06:19:12 PM PDT 24
Finished Aug 07 06:19:14 PM PDT 24
Peak memory 208884 kb
Host smart-a95ad98c-30ad-43ae-8cf7-a9768a2eec3c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792224606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.792224606
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3166321113
Short name T241
Test name
Test status
Simulation time 57078504 ps
CPU time 2.44 seconds
Started Aug 07 06:19:15 PM PDT 24
Finished Aug 07 06:19:18 PM PDT 24
Peak memory 208768 kb
Host smart-d91898b5-b5e0-4fa1-a81f-19117c1f57f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166321113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3166321113
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1386405172
Short name T838
Test name
Test status
Simulation time 270091414 ps
CPU time 2.8 seconds
Started Aug 07 06:19:07 PM PDT 24
Finished Aug 07 06:19:10 PM PDT 24
Peak memory 207384 kb
Host smart-a55f0af9-4f4c-4053-bd43-f9e0d6830e31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386405172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1386405172
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.334144453
Short name T350
Test name
Test status
Simulation time 194493711 ps
CPU time 4.28 seconds
Started Aug 07 06:19:08 PM PDT 24
Finished Aug 07 06:19:13 PM PDT 24
Peak memory 209956 kb
Host smart-4ba794ea-5532-404c-8f16-dcc60f2403a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334144453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.334144453
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.4239498540
Short name T892
Test name
Test status
Simulation time 380981063 ps
CPU time 10.85 seconds
Started Aug 07 06:19:07 PM PDT 24
Finished Aug 07 06:19:18 PM PDT 24
Peak memory 208012 kb
Host smart-f2baa227-2af6-4cae-b871-f091064c624e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239498540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.4239498540
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3925139284
Short name T897
Test name
Test status
Simulation time 3289238991 ps
CPU time 67.88 seconds
Started Aug 07 06:19:15 PM PDT 24
Finished Aug 07 06:20:23 PM PDT 24
Peak memory 216204 kb
Host smart-9bca664e-04ff-454e-b360-3960e7918921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925139284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3925139284
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2905613221
Short name T504
Test name
Test status
Simulation time 2010581116 ps
CPU time 15.42 seconds
Started Aug 07 06:19:05 PM PDT 24
Finished Aug 07 06:19:21 PM PDT 24
Peak memory 222296 kb
Host smart-0449b2af-745d-40b8-a4a0-c27d820f1f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905613221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2905613221
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3731861956
Short name T602
Test name
Test status
Simulation time 74543192 ps
CPU time 2.77 seconds
Started Aug 07 06:19:07 PM PDT 24
Finished Aug 07 06:19:10 PM PDT 24
Peak memory 209880 kb
Host smart-2237e417-4282-43a2-b21d-594e265db984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731861956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3731861956
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2403730180
Short name T83
Test name
Test status
Simulation time 18534218 ps
CPU time 0.83 seconds
Started Aug 07 06:19:13 PM PDT 24
Finished Aug 07 06:19:14 PM PDT 24
Peak memory 205972 kb
Host smart-6ef6c338-4e7f-4006-9be7-732ce229d17c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403730180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2403730180
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.607306030
Short name T820
Test name
Test status
Simulation time 250055545 ps
CPU time 5.7 seconds
Started Aug 07 06:19:15 PM PDT 24
Finished Aug 07 06:19:21 PM PDT 24
Peak memory 214536 kb
Host smart-b5a4dfb1-f29a-4984-9748-2307f6c0ff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607306030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.607306030
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.4246431850
Short name T269
Test name
Test status
Simulation time 395923977 ps
CPU time 4.16 seconds
Started Aug 07 06:19:13 PM PDT 24
Finished Aug 07 06:19:17 PM PDT 24
Peak memory 214340 kb
Host smart-2573b2aa-3d0b-43c4-bd74-3ae106026fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246431850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4246431850
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2649057852
Short name T330
Test name
Test status
Simulation time 148484135 ps
CPU time 4.17 seconds
Started Aug 07 06:19:18 PM PDT 24
Finished Aug 07 06:19:22 PM PDT 24
Peak memory 214344 kb
Host smart-9c88c23d-d57a-46ee-8af4-70cadb913ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649057852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2649057852
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2957058757
Short name T332
Test name
Test status
Simulation time 441995985 ps
CPU time 5.2 seconds
Started Aug 07 06:19:11 PM PDT 24
Finished Aug 07 06:19:17 PM PDT 24
Peak memory 222492 kb
Host smart-4a10729b-7aa3-45d5-9179-ed5dc3ea1a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957058757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2957058757
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3121131707
Short name T217
Test name
Test status
Simulation time 122808949 ps
CPU time 3.81 seconds
Started Aug 07 06:19:11 PM PDT 24
Finished Aug 07 06:19:15 PM PDT 24
Peak memory 214428 kb
Host smart-f5f746d3-b95e-430b-aea8-9363d0e955ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121131707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3121131707
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2001582550
Short name T506
Test name
Test status
Simulation time 145023007 ps
CPU time 5.55 seconds
Started Aug 07 06:19:11 PM PDT 24
Finished Aug 07 06:19:17 PM PDT 24
Peak memory 209732 kb
Host smart-3c785e60-c51a-4ebd-86f7-973a292033a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001582550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2001582550
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.958693669
Short name T101
Test name
Test status
Simulation time 4015641021 ps
CPU time 17.64 seconds
Started Aug 07 06:19:07 PM PDT 24
Finished Aug 07 06:19:24 PM PDT 24
Peak memory 208664 kb
Host smart-17154db1-9417-4d6e-b586-bc853f63c366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958693669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.958693669
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2351981473
Short name T657
Test name
Test status
Simulation time 101402790 ps
CPU time 2.68 seconds
Started Aug 07 06:19:07 PM PDT 24
Finished Aug 07 06:19:09 PM PDT 24
Peak memory 206960 kb
Host smart-b5afd24b-37c2-4405-91cf-8f084ec60ad8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351981473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2351981473
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2713244582
Short name T413
Test name
Test status
Simulation time 1171410479 ps
CPU time 26.87 seconds
Started Aug 07 06:19:09 PM PDT 24
Finished Aug 07 06:19:36 PM PDT 24
Peak memory 208736 kb
Host smart-099e491a-be06-47b2-9830-a8d0074bc0b0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713244582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2713244582
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.4076066259
Short name T904
Test name
Test status
Simulation time 1035065490 ps
CPU time 4.46 seconds
Started Aug 07 06:19:13 PM PDT 24
Finished Aug 07 06:19:18 PM PDT 24
Peak memory 206912 kb
Host smart-6a0e1007-fdee-463b-9f23-9f3fa7ce0dd2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076066259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.4076066259
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2952842712
Short name T870
Test name
Test status
Simulation time 41746918 ps
CPU time 2.32 seconds
Started Aug 07 06:19:15 PM PDT 24
Finished Aug 07 06:19:18 PM PDT 24
Peak memory 215664 kb
Host smart-4c94f701-ba6a-4d72-9835-e50a3b28ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952842712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2952842712
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1301556206
Short name T619
Test name
Test status
Simulation time 132717414 ps
CPU time 2.68 seconds
Started Aug 07 06:19:10 PM PDT 24
Finished Aug 07 06:19:13 PM PDT 24
Peak memory 208292 kb
Host smart-89f2b357-676f-44a8-8abc-af5660e850bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301556206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1301556206
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3955592631
Short name T74
Test name
Test status
Simulation time 1092047039 ps
CPU time 6.94 seconds
Started Aug 07 06:19:13 PM PDT 24
Finished Aug 07 06:19:20 PM PDT 24
Peak memory 222404 kb
Host smart-bb626b25-c599-4efe-a2a9-64e7504a44ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955592631 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3955592631
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.548985557
Short name T27
Test name
Test status
Simulation time 305941956 ps
CPU time 11.3 seconds
Started Aug 07 06:19:11 PM PDT 24
Finished Aug 07 06:19:23 PM PDT 24
Peak memory 208756 kb
Host smart-e8fae0d6-61bd-4ea7-9b22-ee362e725ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548985557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.548985557
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.752802536
Short name T374
Test name
Test status
Simulation time 78389110 ps
CPU time 2.15 seconds
Started Aug 07 06:19:16 PM PDT 24
Finished Aug 07 06:19:18 PM PDT 24
Peak memory 210364 kb
Host smart-77f36697-edd8-498c-95b7-68139d2f845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752802536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.752802536
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2220872831
Short name T80
Test name
Test status
Simulation time 21443055 ps
CPU time 0.88 seconds
Started Aug 07 06:19:18 PM PDT 24
Finished Aug 07 06:19:19 PM PDT 24
Peak memory 205988 kb
Host smart-93243a65-c1d9-4583-bbcf-f1f7745a2c7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220872831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2220872831
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.4132771445
Short name T760
Test name
Test status
Simulation time 39354622 ps
CPU time 2.87 seconds
Started Aug 07 06:19:13 PM PDT 24
Finished Aug 07 06:19:16 PM PDT 24
Peak memory 214372 kb
Host smart-b1969a5a-0b06-4cf4-90b3-5e902b9d146b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4132771445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.4132771445
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.697631570
Short name T743
Test name
Test status
Simulation time 48281142 ps
CPU time 2.6 seconds
Started Aug 07 06:19:10 PM PDT 24
Finished Aug 07 06:19:13 PM PDT 24
Peak memory 210056 kb
Host smart-7a1c1bad-4fab-4558-8e8c-5bf06951f09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697631570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.697631570
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.788066207
Short name T367
Test name
Test status
Simulation time 48074396 ps
CPU time 2.16 seconds
Started Aug 07 06:19:14 PM PDT 24
Finished Aug 07 06:19:17 PM PDT 24
Peak memory 214452 kb
Host smart-cc764ae3-0eb8-4d3e-8894-5380ec1e132e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788066207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.788066207
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.658044719
Short name T273
Test name
Test status
Simulation time 406346607 ps
CPU time 3.17 seconds
Started Aug 07 06:19:13 PM PDT 24
Finished Aug 07 06:19:16 PM PDT 24
Peak memory 214252 kb
Host smart-4bfca509-7274-4d8a-bb4b-32c422e1d36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658044719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.658044719
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.103519090
Short name T207
Test name
Test status
Simulation time 494098816 ps
CPU time 4.15 seconds
Started Aug 07 06:19:17 PM PDT 24
Finished Aug 07 06:19:21 PM PDT 24
Peak memory 210656 kb
Host smart-b58a9800-623e-4f48-8cfc-63b97872147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103519090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.103519090
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2279488709
Short name T226
Test name
Test status
Simulation time 575223137 ps
CPU time 7.82 seconds
Started Aug 07 06:19:12 PM PDT 24
Finished Aug 07 06:19:20 PM PDT 24
Peak memory 218560 kb
Host smart-1314453f-ce29-4021-a567-f6b7e8121a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279488709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2279488709
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3984918673
Short name T869
Test name
Test status
Simulation time 588459421 ps
CPU time 6.65 seconds
Started Aug 07 06:19:12 PM PDT 24
Finished Aug 07 06:19:19 PM PDT 24
Peak memory 208372 kb
Host smart-ab567ea9-466b-4f29-8e6c-249bf68c99de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984918673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3984918673
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3475518122
Short name T665
Test name
Test status
Simulation time 604112482 ps
CPU time 14.86 seconds
Started Aug 07 06:19:15 PM PDT 24
Finished Aug 07 06:19:30 PM PDT 24
Peak memory 208788 kb
Host smart-37a2ae66-40d2-4925-9e1a-5ec7dc4af1e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475518122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3475518122
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3173195324
Short name T474
Test name
Test status
Simulation time 36899168 ps
CPU time 2.55 seconds
Started Aug 07 06:19:19 PM PDT 24
Finished Aug 07 06:19:22 PM PDT 24
Peak memory 208740 kb
Host smart-652e0a03-a8cf-4f7f-865e-c41b69e063d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173195324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3173195324
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1099013930
Short name T240
Test name
Test status
Simulation time 49627347 ps
CPU time 2.72 seconds
Started Aug 07 06:19:11 PM PDT 24
Finished Aug 07 06:19:14 PM PDT 24
Peak memory 207056 kb
Host smart-596a424a-455e-43fd-9d42-5fc1591f7742
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099013930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1099013930
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.11874893
Short name T819
Test name
Test status
Simulation time 45944209 ps
CPU time 1.82 seconds
Started Aug 07 06:19:15 PM PDT 24
Finished Aug 07 06:19:16 PM PDT 24
Peak memory 208292 kb
Host smart-d907d75d-9a0d-4d4d-8a94-b9994feea1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11874893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.11874893
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.4006921183
Short name T682
Test name
Test status
Simulation time 675928480 ps
CPU time 4.57 seconds
Started Aug 07 06:19:12 PM PDT 24
Finished Aug 07 06:19:17 PM PDT 24
Peak memory 206888 kb
Host smart-e141abd3-9850-493b-ba51-10013a92087e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006921183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.4006921183
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2282603962
Short name T215
Test name
Test status
Simulation time 1119355082 ps
CPU time 42.34 seconds
Started Aug 07 06:19:12 PM PDT 24
Finished Aug 07 06:19:55 PM PDT 24
Peak memory 215140 kb
Host smart-93b624e9-d56d-45c0-b497-14b5a221bf2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282603962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2282603962
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3021526633
Short name T728
Test name
Test status
Simulation time 388571727 ps
CPU time 5.89 seconds
Started Aug 07 06:19:14 PM PDT 24
Finished Aug 07 06:19:20 PM PDT 24
Peak memory 208312 kb
Host smart-7c2f5588-c63b-4d3f-ac22-ec0140f8d196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021526633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3021526633
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3803156369
Short name T82
Test name
Test status
Simulation time 72541431 ps
CPU time 0.79 seconds
Started Aug 07 06:17:17 PM PDT 24
Finished Aug 07 06:17:18 PM PDT 24
Peak memory 205976 kb
Host smart-2664cb76-db90-47b7-b229-5c20730716cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803156369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3803156369
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2073194599
Short name T369
Test name
Test status
Simulation time 253760666 ps
CPU time 13.45 seconds
Started Aug 07 06:17:10 PM PDT 24
Finished Aug 07 06:17:24 PM PDT 24
Peak memory 215352 kb
Host smart-5fe1c7f5-52f9-404e-bda3-795d5ca350bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2073194599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2073194599
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4067636595
Short name T725
Test name
Test status
Simulation time 177570826 ps
CPU time 4.1 seconds
Started Aug 07 06:17:13 PM PDT 24
Finished Aug 07 06:17:17 PM PDT 24
Peak memory 214332 kb
Host smart-ae303ff3-25cb-4ae4-891e-518c0a7ed349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067636595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4067636595
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.180162922
Short name T359
Test name
Test status
Simulation time 1557633238 ps
CPU time 6.82 seconds
Started Aug 07 06:17:10 PM PDT 24
Finished Aug 07 06:17:17 PM PDT 24
Peak memory 209704 kb
Host smart-2fc67419-54c0-42ae-a257-5f631729dc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180162922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.180162922
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2186282812
Short name T308
Test name
Test status
Simulation time 212263324 ps
CPU time 2.43 seconds
Started Aug 07 06:17:28 PM PDT 24
Finished Aug 07 06:17:31 PM PDT 24
Peak memory 220852 kb
Host smart-ef63a00a-f8c6-4a97-826f-f21c6184d108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186282812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2186282812
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2940621483
Short name T774
Test name
Test status
Simulation time 66978214 ps
CPU time 2.29 seconds
Started Aug 07 06:17:13 PM PDT 24
Finished Aug 07 06:17:15 PM PDT 24
Peak memory 219196 kb
Host smart-04b4a77c-1381-4ccc-b01f-e236a915950c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940621483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2940621483
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3260347565
Short name T866
Test name
Test status
Simulation time 420698036 ps
CPU time 5.54 seconds
Started Aug 07 06:17:12 PM PDT 24
Finished Aug 07 06:17:18 PM PDT 24
Peak memory 219800 kb
Host smart-54531c9a-4bcf-4057-a965-c0929a725ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260347565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3260347565
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1733542452
Short name T742
Test name
Test status
Simulation time 72530529 ps
CPU time 3.15 seconds
Started Aug 07 06:17:13 PM PDT 24
Finished Aug 07 06:17:16 PM PDT 24
Peak memory 207372 kb
Host smart-8df3fb09-e611-4788-923d-28d5a6eca13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733542452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1733542452
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.4216372001
Short name T662
Test name
Test status
Simulation time 44140790 ps
CPU time 2.52 seconds
Started Aug 07 06:17:15 PM PDT 24
Finished Aug 07 06:17:18 PM PDT 24
Peak memory 208436 kb
Host smart-ae0170d3-0cb1-4f82-83e2-786d02cb8251
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216372001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.4216372001
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3069324473
Short name T673
Test name
Test status
Simulation time 862426511 ps
CPU time 20.13 seconds
Started Aug 07 06:17:13 PM PDT 24
Finished Aug 07 06:17:34 PM PDT 24
Peak memory 208040 kb
Host smart-d80e90db-a1bf-4aa8-8c2a-125171d8d098
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069324473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3069324473
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2026770186
Short name T857
Test name
Test status
Simulation time 845554515 ps
CPU time 15.42 seconds
Started Aug 07 06:17:14 PM PDT 24
Finished Aug 07 06:17:30 PM PDT 24
Peak memory 207944 kb
Host smart-7a03ebc8-f5e3-411c-a6cf-606c8e1ec0e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026770186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2026770186
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2649054984
Short name T798
Test name
Test status
Simulation time 680223226 ps
CPU time 4.41 seconds
Started Aug 07 06:17:17 PM PDT 24
Finished Aug 07 06:17:22 PM PDT 24
Peak memory 218468 kb
Host smart-faaa5ac3-22dd-4c5d-9d0c-77ae8548a15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649054984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2649054984
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3307138602
Short name T184
Test name
Test status
Simulation time 394758955 ps
CPU time 4.55 seconds
Started Aug 07 06:17:12 PM PDT 24
Finished Aug 07 06:17:17 PM PDT 24
Peak memory 208588 kb
Host smart-03084ab3-2138-4a53-a07d-67e2f3a83ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307138602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3307138602
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.4161171710
Short name T283
Test name
Test status
Simulation time 274116337 ps
CPU time 16.99 seconds
Started Aug 07 06:17:21 PM PDT 24
Finished Aug 07 06:17:39 PM PDT 24
Peak memory 222476 kb
Host smart-0735f789-fc86-4164-ad49-0fa5595fe978
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161171710 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.4161171710
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1590851387
Short name T778
Test name
Test status
Simulation time 7209503687 ps
CPU time 24.7 seconds
Started Aug 07 06:17:12 PM PDT 24
Finished Aug 07 06:17:37 PM PDT 24
Peak memory 210828 kb
Host smart-6dc05223-bc99-471c-aaf9-69b8a1c00162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590851387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1590851387
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1464884513
Short name T372
Test name
Test status
Simulation time 162440036 ps
CPU time 2.25 seconds
Started Aug 07 06:17:18 PM PDT 24
Finished Aug 07 06:17:20 PM PDT 24
Peak memory 210416 kb
Host smart-61e89ee0-9943-43c8-a15e-8c9decfcc5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464884513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1464884513
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.4209723793
Short name T471
Test name
Test status
Simulation time 39673684 ps
CPU time 0.85 seconds
Started Aug 07 06:19:17 PM PDT 24
Finished Aug 07 06:19:18 PM PDT 24
Peak memory 205988 kb
Host smart-05b9f6e8-d4e7-43fe-add7-9591fbfa8ed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209723793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.4209723793
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1772294274
Short name T136
Test name
Test status
Simulation time 711022972 ps
CPU time 34.64 seconds
Started Aug 07 06:19:20 PM PDT 24
Finished Aug 07 06:19:55 PM PDT 24
Peak memory 214348 kb
Host smart-7574f946-927b-4765-80a6-09ca964dcb21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772294274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1772294274
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.98707482
Short name T704
Test name
Test status
Simulation time 617362075 ps
CPU time 6.69 seconds
Started Aug 07 06:19:20 PM PDT 24
Finished Aug 07 06:19:26 PM PDT 24
Peak memory 222616 kb
Host smart-862ee44b-84cb-4872-8cc4-db2293fddb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98707482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.98707482
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1353969243
Short name T72
Test name
Test status
Simulation time 296907355 ps
CPU time 2.05 seconds
Started Aug 07 06:19:18 PM PDT 24
Finished Aug 07 06:19:20 PM PDT 24
Peak memory 208876 kb
Host smart-23eafbae-1a90-48ca-839c-01694f5b1c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353969243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1353969243
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3888596490
Short name T688
Test name
Test status
Simulation time 100736843 ps
CPU time 1.95 seconds
Started Aug 07 06:19:20 PM PDT 24
Finished Aug 07 06:19:23 PM PDT 24
Peak memory 214344 kb
Host smart-956c559b-7885-4dd6-955d-1cf9e65673ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888596490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3888596490
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1695665977
Short name T348
Test name
Test status
Simulation time 63776768 ps
CPU time 2.31 seconds
Started Aug 07 06:19:21 PM PDT 24
Finished Aug 07 06:19:23 PM PDT 24
Peak memory 221500 kb
Host smart-f7d64b20-1bf4-43eb-ba97-eb961d059862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695665977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1695665977
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3838841731
Short name T582
Test name
Test status
Simulation time 195659024 ps
CPU time 2.69 seconds
Started Aug 07 06:19:22 PM PDT 24
Finished Aug 07 06:19:25 PM PDT 24
Peak memory 220204 kb
Host smart-024dbd7b-9f3e-473a-885e-4ff8b81a5fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838841731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3838841731
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1081761992
Short name T853
Test name
Test status
Simulation time 129096994 ps
CPU time 3.26 seconds
Started Aug 07 06:19:20 PM PDT 24
Finished Aug 07 06:19:23 PM PDT 24
Peak memory 208372 kb
Host smart-eafd1103-a90a-47a8-9d91-a24c28b2f46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081761992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1081761992
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1933222832
Short name T182
Test name
Test status
Simulation time 60000924 ps
CPU time 3.23 seconds
Started Aug 07 06:19:18 PM PDT 24
Finished Aug 07 06:19:22 PM PDT 24
Peak memory 209056 kb
Host smart-61e2513e-1b0e-4a96-b088-ea1153e5f3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933222832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1933222832
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1203375213
Short name T268
Test name
Test status
Simulation time 183791658 ps
CPU time 3.2 seconds
Started Aug 07 06:19:17 PM PDT 24
Finished Aug 07 06:19:20 PM PDT 24
Peak memory 206884 kb
Host smart-791af504-eb91-4053-9f76-e161529204ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203375213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1203375213
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2400301038
Short name T228
Test name
Test status
Simulation time 205171633 ps
CPU time 2.88 seconds
Started Aug 07 06:19:19 PM PDT 24
Finished Aug 07 06:19:23 PM PDT 24
Peak memory 208876 kb
Host smart-82d8f13c-a5cb-4bf3-81ec-a376f00cbc9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400301038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2400301038
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3031224481
Short name T227
Test name
Test status
Simulation time 116284439 ps
CPU time 4.65 seconds
Started Aug 07 06:19:22 PM PDT 24
Finished Aug 07 06:19:27 PM PDT 24
Peak memory 208644 kb
Host smart-89b91edd-e726-416d-8414-64843aeea2c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031224481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3031224481
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2416576392
Short name T576
Test name
Test status
Simulation time 429591944 ps
CPU time 4.06 seconds
Started Aug 07 06:19:20 PM PDT 24
Finished Aug 07 06:19:24 PM PDT 24
Peak memory 218284 kb
Host smart-276f7c60-128d-4ac4-a193-a65595649a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416576392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2416576392
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1198890130
Short name T578
Test name
Test status
Simulation time 2012446166 ps
CPU time 19.11 seconds
Started Aug 07 06:19:13 PM PDT 24
Finished Aug 07 06:19:32 PM PDT 24
Peak memory 207824 kb
Host smart-b63dd188-d718-47e3-9875-7642af0106af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198890130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1198890130
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2169205919
Short name T209
Test name
Test status
Simulation time 5303174406 ps
CPU time 33.23 seconds
Started Aug 07 06:19:18 PM PDT 24
Finished Aug 07 06:19:52 PM PDT 24
Peak memory 223396 kb
Host smart-7259939e-1671-4e7a-875c-ad4225bd3994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169205919 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2169205919
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.56094905
Short name T815
Test name
Test status
Simulation time 1029017520 ps
CPU time 8.28 seconds
Started Aug 07 06:19:20 PM PDT 24
Finished Aug 07 06:19:28 PM PDT 24
Peak memory 209132 kb
Host smart-01f98ed2-fe7c-48eb-bfc1-5ff2ebc89870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56094905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.56094905
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2154108087
Short name T52
Test name
Test status
Simulation time 104667547 ps
CPU time 2.23 seconds
Started Aug 07 06:19:19 PM PDT 24
Finished Aug 07 06:19:21 PM PDT 24
Peak memory 210284 kb
Host smart-4cb7dde2-2282-4f50-8526-bce2d3c9d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154108087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2154108087
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2625045180
Short name T604
Test name
Test status
Simulation time 61631640 ps
CPU time 0.96 seconds
Started Aug 07 06:19:29 PM PDT 24
Finished Aug 07 06:19:31 PM PDT 24
Peak memory 206116 kb
Host smart-cd750679-ebb9-4781-afe9-7b8584ce8f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625045180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2625045180
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3926541342
Short name T382
Test name
Test status
Simulation time 33395164 ps
CPU time 2.89 seconds
Started Aug 07 06:19:19 PM PDT 24
Finished Aug 07 06:19:22 PM PDT 24
Peak memory 214340 kb
Host smart-f0c6c2a6-c0f4-42e7-a429-9d9025545f60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926541342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3926541342
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.435206197
Short name T588
Test name
Test status
Simulation time 78177393 ps
CPU time 3.63 seconds
Started Aug 07 06:19:21 PM PDT 24
Finished Aug 07 06:19:25 PM PDT 24
Peak memory 209588 kb
Host smart-3032cd8b-7180-4843-a64a-5a012821d2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435206197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.435206197
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.418831181
Short name T362
Test name
Test status
Simulation time 150393197 ps
CPU time 3.33 seconds
Started Aug 07 06:19:17 PM PDT 24
Finished Aug 07 06:19:21 PM PDT 24
Peak memory 209828 kb
Host smart-e9b80c9e-b2ae-4877-9209-e4454a75562a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418831181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.418831181
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.789632788
Short name T94
Test name
Test status
Simulation time 776700357 ps
CPU time 5.63 seconds
Started Aug 07 06:19:20 PM PDT 24
Finished Aug 07 06:19:26 PM PDT 24
Peak memory 222212 kb
Host smart-c7fc13e3-07f3-4648-a215-064204cb2ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789632788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.789632788
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2618244623
Short name T783
Test name
Test status
Simulation time 117612577 ps
CPU time 2.37 seconds
Started Aug 07 06:19:21 PM PDT 24
Finished Aug 07 06:19:23 PM PDT 24
Peak memory 208404 kb
Host smart-a6899473-3f19-4aa4-b677-12f2e3b36cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618244623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2618244623
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2572895403
Short name T800
Test name
Test status
Simulation time 32686747 ps
CPU time 2.27 seconds
Started Aug 07 06:19:19 PM PDT 24
Finished Aug 07 06:19:22 PM PDT 24
Peak memory 207836 kb
Host smart-5f9edbbc-5383-47be-a40e-63fd4214644b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572895403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2572895403
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1008912045
Short name T84
Test name
Test status
Simulation time 47833678 ps
CPU time 2.26 seconds
Started Aug 07 06:19:19 PM PDT 24
Finished Aug 07 06:19:21 PM PDT 24
Peak memory 208468 kb
Host smart-2a80e475-9263-4523-a04e-78f6eebaac0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008912045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1008912045
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.4257710061
Short name T747
Test name
Test status
Simulation time 733790139 ps
CPU time 22.5 seconds
Started Aug 07 06:19:20 PM PDT 24
Finished Aug 07 06:19:42 PM PDT 24
Peak memory 207424 kb
Host smart-2cbced70-98b7-4d8d-8480-0e351f3ba7be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257710061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.4257710061
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3403127350
Short name T432
Test name
Test status
Simulation time 227580063 ps
CPU time 2.73 seconds
Started Aug 07 06:19:19 PM PDT 24
Finished Aug 07 06:19:22 PM PDT 24
Peak memory 208580 kb
Host smart-98e8291d-2996-4a30-bbd5-ddfd262c2a54
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403127350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3403127350
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3901894852
Short name T461
Test name
Test status
Simulation time 812858900 ps
CPU time 5.89 seconds
Started Aug 07 06:19:22 PM PDT 24
Finished Aug 07 06:19:28 PM PDT 24
Peak memory 208256 kb
Host smart-1d49f0b8-81e2-4f22-8f93-cbad1bbce665
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901894852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3901894852
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3238306891
Short name T717
Test name
Test status
Simulation time 120549238 ps
CPU time 2.33 seconds
Started Aug 07 06:19:19 PM PDT 24
Finished Aug 07 06:19:21 PM PDT 24
Peak memory 209944 kb
Host smart-2da245b8-5b52-499c-b97c-b001e2364a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238306891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3238306891
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3691732616
Short name T694
Test name
Test status
Simulation time 136728014 ps
CPU time 3.5 seconds
Started Aug 07 06:19:20 PM PDT 24
Finished Aug 07 06:19:24 PM PDT 24
Peak memory 208708 kb
Host smart-290c66a7-53f0-42da-a80b-989392f22c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691732616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3691732616
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.89574527
Short name T540
Test name
Test status
Simulation time 5001573789 ps
CPU time 34.07 seconds
Started Aug 07 06:19:20 PM PDT 24
Finished Aug 07 06:19:55 PM PDT 24
Peak memory 217092 kb
Host smart-7480c204-df84-40f9-bc26-89e90e735adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89574527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.89574527
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1985799700
Short name T398
Test name
Test status
Simulation time 143079656 ps
CPU time 6.26 seconds
Started Aug 07 06:19:19 PM PDT 24
Finished Aug 07 06:19:26 PM PDT 24
Peak memory 218296 kb
Host smart-52354399-c67d-4245-a679-825e39b086ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985799700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1985799700
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2350019623
Short name T165
Test name
Test status
Simulation time 165653764 ps
CPU time 3.11 seconds
Started Aug 07 06:19:18 PM PDT 24
Finished Aug 07 06:19:21 PM PDT 24
Peak memory 210452 kb
Host smart-84f7f047-0345-41d3-95b3-fe89c1ee0121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350019623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2350019623
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3600569085
Short name T458
Test name
Test status
Simulation time 17476001 ps
CPU time 0.94 seconds
Started Aug 07 06:19:27 PM PDT 24
Finished Aug 07 06:19:28 PM PDT 24
Peak memory 206108 kb
Host smart-0d9eb53a-b19f-4886-9250-f70fe3ba463f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600569085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3600569085
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.4253129460
Short name T65
Test name
Test status
Simulation time 1243160210 ps
CPU time 4.11 seconds
Started Aug 07 06:19:26 PM PDT 24
Finished Aug 07 06:19:30 PM PDT 24
Peak memory 221344 kb
Host smart-a43caa24-4749-4326-a9eb-6512de843c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253129460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.4253129460
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2850091368
Short name T600
Test name
Test status
Simulation time 341580148 ps
CPU time 2.28 seconds
Started Aug 07 06:19:27 PM PDT 24
Finished Aug 07 06:19:30 PM PDT 24
Peak memory 208460 kb
Host smart-b45ac1ff-a5af-43b3-abda-42d25079cf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850091368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2850091368
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1807815840
Short name T489
Test name
Test status
Simulation time 878952731 ps
CPU time 14.13 seconds
Started Aug 07 06:19:24 PM PDT 24
Finished Aug 07 06:19:38 PM PDT 24
Peak memory 222408 kb
Host smart-0928c30d-f98e-4f6c-b62f-e8ad14549642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807815840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1807815840
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2192529870
Short name T835
Test name
Test status
Simulation time 84211358 ps
CPU time 3.16 seconds
Started Aug 07 06:19:24 PM PDT 24
Finished Aug 07 06:19:27 PM PDT 24
Peak memory 222520 kb
Host smart-37477ca8-3bdb-4a4a-b881-464849b6ac5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192529870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2192529870
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1098797088
Short name T135
Test name
Test status
Simulation time 94358564 ps
CPU time 1.99 seconds
Started Aug 07 06:19:25 PM PDT 24
Finished Aug 07 06:19:27 PM PDT 24
Peak memory 206236 kb
Host smart-d765ef82-d2c7-40ff-9199-07fff84a8b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098797088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1098797088
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3044248419
Short name T900
Test name
Test status
Simulation time 63901111 ps
CPU time 3.03 seconds
Started Aug 07 06:19:24 PM PDT 24
Finished Aug 07 06:19:28 PM PDT 24
Peak memory 208704 kb
Host smart-6be0be22-10b6-44b4-be22-448794b36d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044248419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3044248419
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3273416378
Short name T544
Test name
Test status
Simulation time 804366058 ps
CPU time 4.23 seconds
Started Aug 07 06:19:25 PM PDT 24
Finished Aug 07 06:19:30 PM PDT 24
Peak memory 208408 kb
Host smart-62e14db7-5335-426d-b867-d9feacbfc37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273416378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3273416378
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3958709766
Short name T579
Test name
Test status
Simulation time 625814935 ps
CPU time 7.42 seconds
Started Aug 07 06:19:30 PM PDT 24
Finished Aug 07 06:19:37 PM PDT 24
Peak memory 209140 kb
Host smart-52afeab4-285f-4e4a-8ad5-05f261776477
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958709766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3958709766
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.259137856
Short name T427
Test name
Test status
Simulation time 61047595 ps
CPU time 2.35 seconds
Started Aug 07 06:19:26 PM PDT 24
Finished Aug 07 06:19:29 PM PDT 24
Peak memory 207580 kb
Host smart-d87a1108-5624-4530-9df4-97508f41f0a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259137856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.259137856
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3697506831
Short name T319
Test name
Test status
Simulation time 347148396 ps
CPU time 4.84 seconds
Started Aug 07 06:19:23 PM PDT 24
Finished Aug 07 06:19:28 PM PDT 24
Peak memory 207056 kb
Host smart-cfe87ae3-7845-4053-a346-8b8cb45ff78c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697506831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3697506831
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1726555807
Short name T751
Test name
Test status
Simulation time 231732269 ps
CPU time 3.1 seconds
Started Aug 07 06:19:25 PM PDT 24
Finished Aug 07 06:19:28 PM PDT 24
Peak memory 215944 kb
Host smart-b39c52a2-82d9-4326-9bdb-954dd8662087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726555807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1726555807
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1025611641
Short name T188
Test name
Test status
Simulation time 216260568 ps
CPU time 4.74 seconds
Started Aug 07 06:19:30 PM PDT 24
Finished Aug 07 06:19:35 PM PDT 24
Peak memory 206952 kb
Host smart-77d66ae6-6bec-4ae4-829f-3672a1d07110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025611641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1025611641
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1175320985
Short name T117
Test name
Test status
Simulation time 1263755006 ps
CPU time 15.74 seconds
Started Aug 07 06:19:26 PM PDT 24
Finished Aug 07 06:19:42 PM PDT 24
Peak memory 222504 kb
Host smart-409d8a14-fbc7-4331-94f0-538ed4aefb2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175320985 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1175320985
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.312048714
Short name T585
Test name
Test status
Simulation time 175007375 ps
CPU time 4.53 seconds
Started Aug 07 06:19:29 PM PDT 24
Finished Aug 07 06:19:33 PM PDT 24
Peak memory 218084 kb
Host smart-9d67f829-35ff-4e02-baca-bb7dafc92d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312048714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.312048714
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1815966975
Short name T58
Test name
Test status
Simulation time 94993833 ps
CPU time 3.08 seconds
Started Aug 07 06:19:25 PM PDT 24
Finished Aug 07 06:19:28 PM PDT 24
Peak memory 210416 kb
Host smart-6da94909-1bdd-4c1b-a165-11a916d206a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815966975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1815966975
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2143799734
Short name T81
Test name
Test status
Simulation time 34305861 ps
CPU time 0.86 seconds
Started Aug 07 06:19:24 PM PDT 24
Finished Aug 07 06:19:25 PM PDT 24
Peak memory 205964 kb
Host smart-8e674eba-2448-4f6c-97f6-7debeab6f63e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143799734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2143799734
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3837889372
Short name T222
Test name
Test status
Simulation time 303537164 ps
CPU time 4.76 seconds
Started Aug 07 06:19:24 PM PDT 24
Finished Aug 07 06:19:29 PM PDT 24
Peak memory 214236 kb
Host smart-dea40d3b-d0d3-4618-8b97-0c29b306d77d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3837889372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3837889372
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1780428096
Short name T640
Test name
Test status
Simulation time 39155175 ps
CPU time 2.23 seconds
Started Aug 07 06:19:27 PM PDT 24
Finished Aug 07 06:19:29 PM PDT 24
Peak memory 207064 kb
Host smart-bc0f9aaf-398b-4884-be9b-43ccb400e201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780428096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1780428096
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3405858170
Short name T699
Test name
Test status
Simulation time 992182701 ps
CPU time 3.87 seconds
Started Aug 07 06:19:23 PM PDT 24
Finished Aug 07 06:19:27 PM PDT 24
Peak memory 214356 kb
Host smart-99aaa907-76cb-4ee5-9c83-9e4b4cbaa631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405858170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3405858170
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2922863723
Short name T656
Test name
Test status
Simulation time 77666310 ps
CPU time 3.05 seconds
Started Aug 07 06:19:24 PM PDT 24
Finished Aug 07 06:19:27 PM PDT 24
Peak memory 222560 kb
Host smart-1590b755-cb80-42cb-b3de-975fdfabc9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922863723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2922863723
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.48612552
Short name T264
Test name
Test status
Simulation time 1386047661 ps
CPU time 8.13 seconds
Started Aug 07 06:19:28 PM PDT 24
Finished Aug 07 06:19:36 PM PDT 24
Peak memory 218300 kb
Host smart-51331e4b-8123-46f5-9c4b-fe42748e6197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48612552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.48612552
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.4254549178
Short name T533
Test name
Test status
Simulation time 50292694 ps
CPU time 2.74 seconds
Started Aug 07 06:19:24 PM PDT 24
Finished Aug 07 06:19:27 PM PDT 24
Peak memory 208744 kb
Host smart-58169f45-7ef5-4dee-b4ca-681d07c41430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254549178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.4254549178
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3713775480
Short name T558
Test name
Test status
Simulation time 204132369 ps
CPU time 6.62 seconds
Started Aug 07 06:19:30 PM PDT 24
Finished Aug 07 06:19:37 PM PDT 24
Peak memory 208628 kb
Host smart-caea2cfc-7bfd-485b-b66e-fd11a816dbf6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713775480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3713775480
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2200927240
Short name T661
Test name
Test status
Simulation time 79110533 ps
CPU time 3.66 seconds
Started Aug 07 06:19:25 PM PDT 24
Finished Aug 07 06:19:29 PM PDT 24
Peak memory 208876 kb
Host smart-72f2e4a7-7e37-4424-acd6-1136b00114c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200927240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2200927240
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2218465070
Short name T409
Test name
Test status
Simulation time 36224204 ps
CPU time 2.59 seconds
Started Aug 07 06:19:24 PM PDT 24
Finished Aug 07 06:19:27 PM PDT 24
Peak memory 206968 kb
Host smart-f9762471-36ce-4225-8599-d610cdd80ea1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218465070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2218465070
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3885228285
Short name T469
Test name
Test status
Simulation time 88049125 ps
CPU time 2.6 seconds
Started Aug 07 06:19:25 PM PDT 24
Finished Aug 07 06:19:28 PM PDT 24
Peak memory 209452 kb
Host smart-d6963faa-3a34-46db-b34d-15a84619a6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885228285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3885228285
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.304722045
Short name T463
Test name
Test status
Simulation time 248563484 ps
CPU time 6.7 seconds
Started Aug 07 06:19:28 PM PDT 24
Finished Aug 07 06:19:34 PM PDT 24
Peak memory 208360 kb
Host smart-af52243d-c701-418a-8ad6-8a104d55af07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304722045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.304722045
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1834352324
Short name T220
Test name
Test status
Simulation time 3038766985 ps
CPU time 10.76 seconds
Started Aug 07 06:19:25 PM PDT 24
Finished Aug 07 06:19:36 PM PDT 24
Peak memory 220504 kb
Host smart-a70df159-dc38-4b25-bab0-b2a14ed0239e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834352324 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1834352324
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3918799740
Short name T856
Test name
Test status
Simulation time 45227270 ps
CPU time 3.06 seconds
Started Aug 07 06:19:26 PM PDT 24
Finished Aug 07 06:19:29 PM PDT 24
Peak memory 218460 kb
Host smart-1a5dcc95-3f8e-4725-9e48-e9d9ef46e84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918799740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3918799740
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1029226766
Short name T786
Test name
Test status
Simulation time 76094909 ps
CPU time 2.73 seconds
Started Aug 07 06:19:31 PM PDT 24
Finished Aug 07 06:19:33 PM PDT 24
Peak memory 210484 kb
Host smart-1fde6352-565a-44d8-b10b-672e9d9c921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029226766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1029226766
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2237454276
Short name T412
Test name
Test status
Simulation time 84971795 ps
CPU time 0.91 seconds
Started Aug 07 06:19:33 PM PDT 24
Finished Aug 07 06:19:34 PM PDT 24
Peak memory 205992 kb
Host smart-a0e35307-cd1c-4050-895a-4cba6974eb7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237454276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2237454276
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3589377242
Short name T763
Test name
Test status
Simulation time 109315580 ps
CPU time 2.41 seconds
Started Aug 07 06:19:29 PM PDT 24
Finished Aug 07 06:19:32 PM PDT 24
Peak memory 214332 kb
Host smart-61b259cc-0ade-45a7-8c1c-ee85b7ab2539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589377242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3589377242
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.843050981
Short name T25
Test name
Test status
Simulation time 45369900 ps
CPU time 1.69 seconds
Started Aug 07 06:19:31 PM PDT 24
Finished Aug 07 06:19:33 PM PDT 24
Peak memory 215340 kb
Host smart-295bd3b5-d789-4990-bd1c-8e54aae400fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843050981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.843050981
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3541599578
Short name T263
Test name
Test status
Simulation time 195922101 ps
CPU time 2.64 seconds
Started Aug 07 06:19:32 PM PDT 24
Finished Aug 07 06:19:35 PM PDT 24
Peak memory 209120 kb
Host smart-a7187a64-b450-4a76-91c7-a2ceb4155ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541599578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3541599578
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3659069707
Short name T771
Test name
Test status
Simulation time 33432239 ps
CPU time 2.52 seconds
Started Aug 07 06:19:34 PM PDT 24
Finished Aug 07 06:19:37 PM PDT 24
Peak memory 209308 kb
Host smart-ec4a68ac-d756-4345-ac53-59f86bc67fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659069707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3659069707
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2386082618
Short name T482
Test name
Test status
Simulation time 76606827 ps
CPU time 1.72 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:19:37 PM PDT 24
Peak memory 214288 kb
Host smart-d0bd9b36-73dc-438c-b8ba-ea9e4ed77be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386082618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2386082618
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_random.3374727278
Short name T520
Test name
Test status
Simulation time 157802825 ps
CPU time 3.86 seconds
Started Aug 07 06:19:26 PM PDT 24
Finished Aug 07 06:19:30 PM PDT 24
Peak memory 207992 kb
Host smart-bd8cddec-bf4e-40e6-b8b3-55fd1cacc0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374727278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3374727278
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1175588016
Short name T292
Test name
Test status
Simulation time 120242635 ps
CPU time 4.3 seconds
Started Aug 07 06:19:24 PM PDT 24
Finished Aug 07 06:19:29 PM PDT 24
Peak memory 207848 kb
Host smart-2ee017a8-3dfa-431a-98eb-63a1c4a8da1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175588016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1175588016
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2448199021
Short name T311
Test name
Test status
Simulation time 132997629 ps
CPU time 3.36 seconds
Started Aug 07 06:19:26 PM PDT 24
Finished Aug 07 06:19:29 PM PDT 24
Peak memory 208612 kb
Host smart-7f43d1bf-5e44-4c15-b6d6-f689c630e5bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448199021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2448199021
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2539933219
Short name T196
Test name
Test status
Simulation time 1101485128 ps
CPU time 4.62 seconds
Started Aug 07 06:19:24 PM PDT 24
Finished Aug 07 06:19:28 PM PDT 24
Peak memory 208812 kb
Host smart-99a1dc8d-1928-47be-9b60-36790836f4fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539933219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2539933219
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1819894002
Short name T675
Test name
Test status
Simulation time 70980486 ps
CPU time 3.27 seconds
Started Aug 07 06:19:25 PM PDT 24
Finished Aug 07 06:19:28 PM PDT 24
Peak memory 208608 kb
Host smart-9dff8ffd-aafa-4e43-932d-0a51220f8a81
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819894002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1819894002
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1957178045
Short name T597
Test name
Test status
Simulation time 50353711 ps
CPU time 2.41 seconds
Started Aug 07 06:19:29 PM PDT 24
Finished Aug 07 06:19:32 PM PDT 24
Peak memory 209500 kb
Host smart-0d88554c-9e31-43ef-96ff-cab12662ba68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957178045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1957178045
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3264093926
Short name T512
Test name
Test status
Simulation time 113803601 ps
CPU time 4.09 seconds
Started Aug 07 06:19:25 PM PDT 24
Finished Aug 07 06:19:30 PM PDT 24
Peak memory 206912 kb
Host smart-1345da50-d9c9-4044-ae21-0a6ec9004fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264093926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3264093926
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1559095465
Short name T772
Test name
Test status
Simulation time 1187199256 ps
CPU time 24.36 seconds
Started Aug 07 06:19:32 PM PDT 24
Finished Aug 07 06:19:57 PM PDT 24
Peak memory 222692 kb
Host smart-8beb023c-105c-4d9c-921b-f16ac32f6e0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559095465 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1559095465
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1957511754
Short name T848
Test name
Test status
Simulation time 451541329 ps
CPU time 4.76 seconds
Started Aug 07 06:19:33 PM PDT 24
Finished Aug 07 06:19:38 PM PDT 24
Peak memory 208420 kb
Host smart-debba0ba-b24f-4342-9864-b3dd222a2529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957511754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1957511754
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2822087290
Short name T539
Test name
Test status
Simulation time 115052803 ps
CPU time 1.68 seconds
Started Aug 07 06:19:33 PM PDT 24
Finished Aug 07 06:19:35 PM PDT 24
Peak memory 208512 kb
Host smart-f351b3fd-cc7e-4577-b0d3-d8888c301f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822087290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2822087290
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.4032964545
Short name T399
Test name
Test status
Simulation time 47636304 ps
CPU time 0.86 seconds
Started Aug 07 06:19:34 PM PDT 24
Finished Aug 07 06:19:36 PM PDT 24
Peak memory 205812 kb
Host smart-87aa2e58-900d-4f6e-a1ac-aaa98523d324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032964545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.4032964545
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2096331777
Short name T127
Test name
Test status
Simulation time 260789980 ps
CPU time 5.12 seconds
Started Aug 07 06:19:34 PM PDT 24
Finished Aug 07 06:19:39 PM PDT 24
Peak memory 215720 kb
Host smart-3e3dfe27-3453-40c6-b575-81441e748357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2096331777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2096331777
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.670470131
Short name T9
Test name
Test status
Simulation time 650931403 ps
CPU time 5.07 seconds
Started Aug 07 06:19:31 PM PDT 24
Finished Aug 07 06:19:36 PM PDT 24
Peak memory 209576 kb
Host smart-eeb4758a-2f3b-486b-a172-bece6623824f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670470131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.670470131
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3088523507
Short name T328
Test name
Test status
Simulation time 77376335 ps
CPU time 3.37 seconds
Started Aug 07 06:19:31 PM PDT 24
Finished Aug 07 06:19:34 PM PDT 24
Peak memory 210212 kb
Host smart-578c38d6-75ce-4930-81bf-7aa634b67ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088523507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3088523507
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2444206797
Short name T329
Test name
Test status
Simulation time 247310770 ps
CPU time 2.66 seconds
Started Aug 07 06:19:30 PM PDT 24
Finished Aug 07 06:19:32 PM PDT 24
Peak memory 214348 kb
Host smart-2b12f2bf-1001-404c-8188-0a664552fd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444206797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2444206797
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.439117130
Short name T779
Test name
Test status
Simulation time 94383335 ps
CPU time 3.25 seconds
Started Aug 07 06:19:32 PM PDT 24
Finished Aug 07 06:19:35 PM PDT 24
Peak memory 220860 kb
Host smart-e8368013-bec2-4760-aaa4-6fbda243ecef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439117130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.439117130
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2767620609
Short name T462
Test name
Test status
Simulation time 240281545 ps
CPU time 3.29 seconds
Started Aug 07 06:19:33 PM PDT 24
Finished Aug 07 06:19:37 PM PDT 24
Peak memory 209828 kb
Host smart-668bb97a-2c03-4225-9f52-4ecce4a12cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767620609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2767620609
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1398564166
Short name T645
Test name
Test status
Simulation time 1021223676 ps
CPU time 32.41 seconds
Started Aug 07 06:19:31 PM PDT 24
Finished Aug 07 06:20:03 PM PDT 24
Peak memory 214384 kb
Host smart-852a6789-80fc-4718-bf89-beb0a929bc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398564166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1398564166
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.34244203
Short name T621
Test name
Test status
Simulation time 300052454 ps
CPU time 3.08 seconds
Started Aug 07 06:19:30 PM PDT 24
Finished Aug 07 06:19:33 PM PDT 24
Peak memory 208724 kb
Host smart-84379e11-8483-417c-a0e1-8f387342a395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34244203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.34244203
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.851921088
Short name T453
Test name
Test status
Simulation time 428855900 ps
CPU time 8.23 seconds
Started Aug 07 06:19:29 PM PDT 24
Finished Aug 07 06:19:38 PM PDT 24
Peak memory 208568 kb
Host smart-8dae229c-712f-4814-b635-941f73b7b486
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851921088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.851921088
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.122488121
Short name T886
Test name
Test status
Simulation time 1030532415 ps
CPU time 4.29 seconds
Started Aug 07 06:19:32 PM PDT 24
Finished Aug 07 06:19:36 PM PDT 24
Peak memory 208316 kb
Host smart-cce3f852-8453-4b3d-8b89-6e2bf181b7ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122488121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.122488121
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.456775303
Short name T103
Test name
Test status
Simulation time 1013365531 ps
CPU time 6.52 seconds
Started Aug 07 06:19:34 PM PDT 24
Finished Aug 07 06:19:41 PM PDT 24
Peak memory 207824 kb
Host smart-88791bfb-b917-4483-96af-606694e301ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456775303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.456775303
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3611421512
Short name T692
Test name
Test status
Simulation time 181004899 ps
CPU time 3.86 seconds
Started Aug 07 06:19:31 PM PDT 24
Finished Aug 07 06:19:35 PM PDT 24
Peak memory 218468 kb
Host smart-b4988eed-81e7-4979-a7df-743f18aa507f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611421512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3611421512
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3120594158
Short name T402
Test name
Test status
Simulation time 439587670 ps
CPU time 8.89 seconds
Started Aug 07 06:19:31 PM PDT 24
Finished Aug 07 06:19:40 PM PDT 24
Peak memory 208704 kb
Host smart-80a1f0b9-8c3c-436d-ac90-01562af52ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120594158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3120594158
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3043995172
Short name T310
Test name
Test status
Simulation time 4854789123 ps
CPU time 64.99 seconds
Started Aug 07 06:19:31 PM PDT 24
Finished Aug 07 06:20:36 PM PDT 24
Peak memory 222484 kb
Host smart-cdab2718-6ec1-48ac-9573-2a1b4fb87195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043995172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3043995172
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.628283623
Short name T880
Test name
Test status
Simulation time 572461215 ps
CPU time 6.71 seconds
Started Aug 07 06:19:31 PM PDT 24
Finished Aug 07 06:19:38 PM PDT 24
Peak memory 214448 kb
Host smart-121ba40f-3cd4-4ec6-acce-bd473c56d390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628283623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.628283623
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1533229213
Short name T719
Test name
Test status
Simulation time 124945467 ps
CPU time 2.97 seconds
Started Aug 07 06:19:31 PM PDT 24
Finished Aug 07 06:19:35 PM PDT 24
Peak memory 210272 kb
Host smart-be55a97d-219e-4e1b-81f2-ff921fbc6d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533229213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1533229213
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1776239336
Short name T524
Test name
Test status
Simulation time 85856725 ps
CPU time 0.86 seconds
Started Aug 07 06:19:37 PM PDT 24
Finished Aug 07 06:19:38 PM PDT 24
Peak memory 205892 kb
Host smart-d770dccc-a7dd-4615-a323-1055e222873e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776239336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1776239336
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.824563009
Short name T32
Test name
Test status
Simulation time 201364826 ps
CPU time 2.82 seconds
Started Aug 07 06:19:36 PM PDT 24
Finished Aug 07 06:19:38 PM PDT 24
Peak memory 207880 kb
Host smart-90b3011d-250d-496f-a25e-0e512c571adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824563009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.824563009
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2958927742
Short name T69
Test name
Test status
Simulation time 109284419 ps
CPU time 3.1 seconds
Started Aug 07 06:19:37 PM PDT 24
Finished Aug 07 06:19:41 PM PDT 24
Peak memory 208548 kb
Host smart-7ca8f75c-de18-4dbc-a175-c2268482dc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958927742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2958927742
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3532701073
Short name T307
Test name
Test status
Simulation time 146353127 ps
CPU time 3.88 seconds
Started Aug 07 06:19:34 PM PDT 24
Finished Aug 07 06:19:38 PM PDT 24
Peak memory 222360 kb
Host smart-35d7c7fe-e7bd-4f9b-9bb2-f319c62ea145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532701073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3532701073
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1506580395
Short name T764
Test name
Test status
Simulation time 1166795589 ps
CPU time 4.08 seconds
Started Aug 07 06:19:38 PM PDT 24
Finished Aug 07 06:19:42 PM PDT 24
Peak memory 214296 kb
Host smart-68ade870-4015-4fe1-ad65-89d6d744c8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506580395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1506580395
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2871256395
Short name T481
Test name
Test status
Simulation time 1006667622 ps
CPU time 3.75 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:19:39 PM PDT 24
Peak memory 219912 kb
Host smart-3a2ef00a-8e63-429b-9503-a1544d10ce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871256395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2871256395
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3168237788
Short name T326
Test name
Test status
Simulation time 700972136 ps
CPU time 5.47 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:19:40 PM PDT 24
Peak memory 209516 kb
Host smart-7801ee45-07e8-47e0-9cd2-ea50aa3ec244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168237788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3168237788
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2038828859
Short name T595
Test name
Test status
Simulation time 475082535 ps
CPU time 3.37 seconds
Started Aug 07 06:19:32 PM PDT 24
Finished Aug 07 06:19:36 PM PDT 24
Peak memory 206880 kb
Host smart-4b4fe480-7c42-499a-beed-c5ee4bef321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038828859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2038828859
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.748823763
Short name T385
Test name
Test status
Simulation time 40523036 ps
CPU time 2.41 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:19:37 PM PDT 24
Peak memory 208104 kb
Host smart-228f37e2-3fab-437e-b0d0-d16e4646c647
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748823763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.748823763
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3857734865
Short name T809
Test name
Test status
Simulation time 147344057 ps
CPU time 3.65 seconds
Started Aug 07 06:19:36 PM PDT 24
Finished Aug 07 06:19:40 PM PDT 24
Peak memory 209092 kb
Host smart-4459eece-72d7-4766-b150-2d234e54ac04
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857734865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3857734865
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3976372127
Short name T574
Test name
Test status
Simulation time 994936846 ps
CPU time 8.65 seconds
Started Aug 07 06:19:36 PM PDT 24
Finished Aug 07 06:19:45 PM PDT 24
Peak memory 208388 kb
Host smart-cf77ebb6-5773-4738-8068-87b861ffcc8a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976372127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3976372127
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1731902734
Short name T814
Test name
Test status
Simulation time 174162174 ps
CPU time 5.08 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:19:40 PM PDT 24
Peak memory 218288 kb
Host smart-ef818505-3bbf-46ae-b38e-4896c0133089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731902734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1731902734
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3227160581
Short name T812
Test name
Test status
Simulation time 282403306 ps
CPU time 2.39 seconds
Started Aug 07 06:19:32 PM PDT 24
Finished Aug 07 06:19:35 PM PDT 24
Peak memory 208592 kb
Host smart-c6007de5-4737-4222-81f1-2cf341579d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227160581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3227160581
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3464786851
Short name T299
Test name
Test status
Simulation time 435785201 ps
CPU time 24.76 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:20:00 PM PDT 24
Peak memory 216244 kb
Host smart-71610939-901c-47e3-8040-4f2b502a7cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464786851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3464786851
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.523617696
Short name T686
Test name
Test status
Simulation time 228326952 ps
CPU time 5.18 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:19:40 PM PDT 24
Peak memory 207408 kb
Host smart-9ba50ac8-b3be-4cdb-92be-84ed44e0b722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523617696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.523617696
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.774799002
Short name T829
Test name
Test status
Simulation time 1711498583 ps
CPU time 2.33 seconds
Started Aug 07 06:19:37 PM PDT 24
Finished Aug 07 06:19:39 PM PDT 24
Peak memory 210740 kb
Host smart-41dceb6d-be01-4152-a8dd-8ebe535c6a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774799002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.774799002
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.657152688
Short name T79
Test name
Test status
Simulation time 38679854 ps
CPU time 0.86 seconds
Started Aug 07 06:19:38 PM PDT 24
Finished Aug 07 06:19:39 PM PDT 24
Peak memory 205968 kb
Host smart-4c8a248c-4704-47d8-ad04-188c526fa223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657152688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.657152688
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3798567499
Short name T334
Test name
Test status
Simulation time 11721383272 ps
CPU time 93.63 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:21:09 PM PDT 24
Peak memory 222472 kb
Host smart-812b3cc0-eecd-45e0-aae4-245606662cb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798567499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3798567499
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3613728460
Short name T806
Test name
Test status
Simulation time 46648097 ps
CPU time 2.37 seconds
Started Aug 07 06:19:36 PM PDT 24
Finished Aug 07 06:19:38 PM PDT 24
Peak memory 208468 kb
Host smart-50815c5a-e0d7-4f8e-8ca5-4fdd3713bc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613728460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3613728460
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3592020833
Short name T284
Test name
Test status
Simulation time 113891175 ps
CPU time 1.94 seconds
Started Aug 07 06:19:37 PM PDT 24
Finished Aug 07 06:19:39 PM PDT 24
Peak memory 214336 kb
Host smart-86248236-6463-4039-bb02-267624d45601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592020833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3592020833
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3350717947
Short name T88
Test name
Test status
Simulation time 1661138532 ps
CPU time 4.04 seconds
Started Aug 07 06:19:39 PM PDT 24
Finished Aug 07 06:19:43 PM PDT 24
Peak memory 214296 kb
Host smart-f6aa3e7f-c878-4b43-8f88-d58f3b683d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350717947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3350717947
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.491286461
Short name T230
Test name
Test status
Simulation time 41049161 ps
CPU time 2.73 seconds
Started Aug 07 06:19:37 PM PDT 24
Finished Aug 07 06:19:40 PM PDT 24
Peak memory 214264 kb
Host smart-98f8bfd0-3a83-4f8e-9b19-85a92fa7c445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491286461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.491286461
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3060020336
Short name T847
Test name
Test status
Simulation time 49192498 ps
CPU time 3.28 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:19:39 PM PDT 24
Peak memory 220052 kb
Host smart-53b5c015-c6bb-43c4-9832-da9a6b7766e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060020336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3060020336
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1108099963
Short name T714
Test name
Test status
Simulation time 225299524 ps
CPU time 7 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:19:42 PM PDT 24
Peak memory 207672 kb
Host smart-6e53ae72-1719-44cc-9326-d3cc79a484ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108099963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1108099963
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.289048055
Short name T341
Test name
Test status
Simulation time 2879120014 ps
CPU time 36.12 seconds
Started Aug 07 06:19:38 PM PDT 24
Finished Aug 07 06:20:15 PM PDT 24
Peak memory 208208 kb
Host smart-ee6c6a19-c8b7-4fdf-b1f6-56b65eb696f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289048055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.289048055
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3052578644
Short name T85
Test name
Test status
Simulation time 484382140 ps
CPU time 12.38 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:19:47 PM PDT 24
Peak memory 208156 kb
Host smart-b8a11e09-3744-48ee-9307-93c6757a9289
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052578644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3052578644
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.893757545
Short name T523
Test name
Test status
Simulation time 219214011 ps
CPU time 3.29 seconds
Started Aug 07 06:19:36 PM PDT 24
Finished Aug 07 06:19:39 PM PDT 24
Peak memory 207068 kb
Host smart-3ce734c7-9f43-4e14-8e27-71cb8e203823
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893757545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.893757545
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3435069801
Short name T97
Test name
Test status
Simulation time 140581579 ps
CPU time 3.78 seconds
Started Aug 07 06:19:36 PM PDT 24
Finished Aug 07 06:19:40 PM PDT 24
Peak memory 208756 kb
Host smart-65990e15-c7e1-449c-80be-e583ce62aa67
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435069801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3435069801
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1846402591
Short name T634
Test name
Test status
Simulation time 52586356 ps
CPU time 2.15 seconds
Started Aug 07 06:19:34 PM PDT 24
Finished Aug 07 06:19:36 PM PDT 24
Peak memory 209288 kb
Host smart-448a377d-00af-4ae4-9dcf-74d4f357aa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846402591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1846402591
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.724677459
Short name T434
Test name
Test status
Simulation time 122727733 ps
CPU time 4.13 seconds
Started Aug 07 06:19:37 PM PDT 24
Finished Aug 07 06:19:41 PM PDT 24
Peak memory 208544 kb
Host smart-e9973120-b8e9-4316-aeda-16a5773da59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724677459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.724677459
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3258256715
Short name T302
Test name
Test status
Simulation time 1419815964 ps
CPU time 12.91 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:19:48 PM PDT 24
Peak memory 219616 kb
Host smart-7ab15a5b-9bf7-4660-abad-8964782458ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258256715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3258256715
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4055939566
Short name T830
Test name
Test status
Simulation time 575535333 ps
CPU time 6.56 seconds
Started Aug 07 06:19:35 PM PDT 24
Finished Aug 07 06:19:42 PM PDT 24
Peak memory 218204 kb
Host smart-48b238f0-0a6e-4f59-8e7a-b448eba35172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055939566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4055939566
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1947454393
Short name T612
Test name
Test status
Simulation time 90435303 ps
CPU time 1.9 seconds
Started Aug 07 06:19:37 PM PDT 24
Finished Aug 07 06:19:39 PM PDT 24
Peak memory 210428 kb
Host smart-70765a11-b633-4c76-81b1-82693d5bcd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947454393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1947454393
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1767234123
Short name T891
Test name
Test status
Simulation time 188165860 ps
CPU time 0.98 seconds
Started Aug 07 06:19:47 PM PDT 24
Finished Aug 07 06:19:48 PM PDT 24
Peak memory 206140 kb
Host smart-c50b0d10-189c-4562-a604-dbb56e40a6c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767234123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1767234123
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2654821861
Short name T338
Test name
Test status
Simulation time 140811713 ps
CPU time 7.49 seconds
Started Aug 07 06:19:41 PM PDT 24
Finished Aug 07 06:19:49 PM PDT 24
Peak memory 215364 kb
Host smart-a815b3be-2f52-4e12-8771-ec0497824dee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654821861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2654821861
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3875057916
Short name T39
Test name
Test status
Simulation time 131174842 ps
CPU time 3.18 seconds
Started Aug 07 06:19:46 PM PDT 24
Finished Aug 07 06:19:49 PM PDT 24
Peak memory 214292 kb
Host smart-af7ea9eb-fbfc-410c-b400-205f1f063997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875057916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3875057916
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.585940489
Short name T75
Test name
Test status
Simulation time 169962814 ps
CPU time 3.8 seconds
Started Aug 07 06:19:43 PM PDT 24
Finished Aug 07 06:19:47 PM PDT 24
Peak memory 210320 kb
Host smart-a9026a32-3094-4ab8-9821-d0e567e77bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585940489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.585940489
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1978840847
Short name T669
Test name
Test status
Simulation time 77728114 ps
CPU time 2.77 seconds
Started Aug 07 06:19:46 PM PDT 24
Finished Aug 07 06:19:49 PM PDT 24
Peak memory 214380 kb
Host smart-d938df91-f2d0-46e8-b095-dc463d04893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978840847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1978840847
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2844325761
Short name T769
Test name
Test status
Simulation time 41157406 ps
CPU time 2.62 seconds
Started Aug 07 06:19:45 PM PDT 24
Finished Aug 07 06:19:48 PM PDT 24
Peak memory 212064 kb
Host smart-2338501c-eea9-4822-bf74-701a478ba59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844325761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2844325761
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3073168045
Short name T555
Test name
Test status
Simulation time 130325937 ps
CPU time 3.92 seconds
Started Aug 07 06:19:45 PM PDT 24
Finished Aug 07 06:19:49 PM PDT 24
Peak memory 222396 kb
Host smart-1b67bdab-545d-405f-89d1-1ffbed6a066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073168045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3073168045
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3146413055
Short name T265
Test name
Test status
Simulation time 320433667 ps
CPU time 5.35 seconds
Started Aug 07 06:19:37 PM PDT 24
Finished Aug 07 06:19:42 PM PDT 24
Peak memory 209940 kb
Host smart-af9150ba-b733-455e-811f-ca2a40456f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146413055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3146413055
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2972155221
Short name T684
Test name
Test status
Simulation time 230060303 ps
CPU time 7.03 seconds
Started Aug 07 06:19:40 PM PDT 24
Finished Aug 07 06:19:47 PM PDT 24
Peak memory 208520 kb
Host smart-d1ac2c1e-cd02-437c-9275-90fcc10260b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972155221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2972155221
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1554889152
Short name T687
Test name
Test status
Simulation time 305398441 ps
CPU time 6.36 seconds
Started Aug 07 06:19:36 PM PDT 24
Finished Aug 07 06:19:43 PM PDT 24
Peak memory 207856 kb
Host smart-a307f546-d3c2-415b-9c2d-60685721acd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554889152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1554889152
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2953346707
Short name T827
Test name
Test status
Simulation time 41575118 ps
CPU time 2.31 seconds
Started Aug 07 06:19:37 PM PDT 24
Finished Aug 07 06:19:40 PM PDT 24
Peak memory 206900 kb
Host smart-fe0b2a2c-560c-42ff-99e2-f58667478f68
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953346707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2953346707
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.820776379
Short name T315
Test name
Test status
Simulation time 284058552 ps
CPU time 10.4 seconds
Started Aug 07 06:19:37 PM PDT 24
Finished Aug 07 06:19:48 PM PDT 24
Peak memory 208784 kb
Host smart-481ee193-4d6c-4c9c-ab79-5520a2a5107d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820776379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.820776379
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4216575553
Short name T796
Test name
Test status
Simulation time 176882537 ps
CPU time 2.82 seconds
Started Aug 07 06:19:44 PM PDT 24
Finished Aug 07 06:19:47 PM PDT 24
Peak memory 207720 kb
Host smart-cc8129c5-684a-46c8-917a-57079f6ec16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216575553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4216575553
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.837925723
Short name T388
Test name
Test status
Simulation time 1169758131 ps
CPU time 13.32 seconds
Started Aug 07 06:19:38 PM PDT 24
Finished Aug 07 06:19:51 PM PDT 24
Peak memory 206940 kb
Host smart-fdbc7c86-b1b7-459d-895d-8c1723c07976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837925723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.837925723
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1272034213
Short name T118
Test name
Test status
Simulation time 284977000 ps
CPU time 8.98 seconds
Started Aug 07 06:19:47 PM PDT 24
Finished Aug 07 06:19:56 PM PDT 24
Peak memory 222600 kb
Host smart-512744fd-2f4d-454a-8c90-73ce96656ebd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272034213 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1272034213
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1669967275
Short name T513
Test name
Test status
Simulation time 403559785 ps
CPU time 6.3 seconds
Started Aug 07 06:19:43 PM PDT 24
Finished Aug 07 06:19:50 PM PDT 24
Peak memory 209384 kb
Host smart-ab07f201-315c-422f-afea-3d96cc60d0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669967275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1669967275
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1599586236
Short name T483
Test name
Test status
Simulation time 348269096 ps
CPU time 6.77 seconds
Started Aug 07 06:19:45 PM PDT 24
Finished Aug 07 06:19:52 PM PDT 24
Peak memory 210556 kb
Host smart-e12162fc-d295-4b6c-8513-b49aacccaf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599586236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1599586236
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3605716467
Short name T603
Test name
Test status
Simulation time 21165614 ps
CPU time 0.93 seconds
Started Aug 07 06:19:46 PM PDT 24
Finished Aug 07 06:19:47 PM PDT 24
Peak memory 205984 kb
Host smart-2e19db54-d631-4c24-a73c-3bf3ce47fafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605716467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3605716467
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2226902850
Short name T381
Test name
Test status
Simulation time 1189289541 ps
CPU time 15.49 seconds
Started Aug 07 06:19:43 PM PDT 24
Finished Aug 07 06:19:58 PM PDT 24
Peak memory 222500 kb
Host smart-7a75c129-1e04-4d21-b13d-d0da0de45baf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226902850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2226902850
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4219739021
Short name T736
Test name
Test status
Simulation time 106369338 ps
CPU time 4.39 seconds
Started Aug 07 06:19:47 PM PDT 24
Finished Aug 07 06:19:52 PM PDT 24
Peak memory 208404 kb
Host smart-c17c294a-474a-4931-b3c9-09661cd08ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219739021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4219739021
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1954155433
Short name T895
Test name
Test status
Simulation time 255629588 ps
CPU time 4.82 seconds
Started Aug 07 06:19:46 PM PDT 24
Finished Aug 07 06:19:51 PM PDT 24
Peak memory 208316 kb
Host smart-428d87ff-0433-4b21-a73a-ec1048b8861d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954155433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1954155433
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1693894960
Short name T881
Test name
Test status
Simulation time 21092798 ps
CPU time 1.8 seconds
Started Aug 07 06:19:44 PM PDT 24
Finished Aug 07 06:19:46 PM PDT 24
Peak memory 214428 kb
Host smart-9355b00f-257f-4dcf-af49-2d19ab03f734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693894960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1693894960
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1280835732
Short name T201
Test name
Test status
Simulation time 127971766 ps
CPU time 5.66 seconds
Started Aug 07 06:19:44 PM PDT 24
Finished Aug 07 06:19:49 PM PDT 24
Peak memory 222428 kb
Host smart-d3e13802-aa7e-4062-9c8f-0b4db1e61bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280835732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1280835732
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3507413404
Short name T730
Test name
Test status
Simulation time 1410275353 ps
CPU time 9.95 seconds
Started Aug 07 06:19:47 PM PDT 24
Finished Aug 07 06:19:57 PM PDT 24
Peak memory 214348 kb
Host smart-28aacb44-cfdb-4926-9242-fc1b482b9938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507413404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3507413404
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2952541770
Short name T496
Test name
Test status
Simulation time 2314099560 ps
CPU time 14.04 seconds
Started Aug 07 06:19:45 PM PDT 24
Finished Aug 07 06:19:59 PM PDT 24
Peak memory 208544 kb
Host smart-a5963d86-f171-4157-b386-b57633014cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952541770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2952541770
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3982720003
Short name T787
Test name
Test status
Simulation time 259368790 ps
CPU time 3.36 seconds
Started Aug 07 06:19:44 PM PDT 24
Finished Aug 07 06:19:47 PM PDT 24
Peak memory 208044 kb
Host smart-67cb2b3d-5c00-44b9-8c2b-d1e8de63c9c5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982720003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3982720003
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2284323115
Short name T816
Test name
Test status
Simulation time 570461228 ps
CPU time 4.93 seconds
Started Aug 07 06:19:43 PM PDT 24
Finished Aug 07 06:19:48 PM PDT 24
Peak memory 208004 kb
Host smart-7c81c1e9-d11a-4014-989a-b1ff1dec4223
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284323115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2284323115
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1843369798
Short name T530
Test name
Test status
Simulation time 34662946 ps
CPU time 2.51 seconds
Started Aug 07 06:19:43 PM PDT 24
Finished Aug 07 06:19:46 PM PDT 24
Peak memory 208708 kb
Host smart-30cfd472-23fe-47df-b895-c686d5d7d437
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843369798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1843369798
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.9394930
Short name T818
Test name
Test status
Simulation time 265837662 ps
CPU time 2.93 seconds
Started Aug 07 06:19:44 PM PDT 24
Finished Aug 07 06:19:47 PM PDT 24
Peak memory 218320 kb
Host smart-7b7ca6f3-f2f0-4d40-bce6-c9cafa727279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9394930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.9394930
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.564224707
Short name T550
Test name
Test status
Simulation time 327564481 ps
CPU time 2.75 seconds
Started Aug 07 06:19:45 PM PDT 24
Finished Aug 07 06:19:48 PM PDT 24
Peak memory 208472 kb
Host smart-5031098b-3f1a-46aa-b55e-837ae9a551b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564224707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.564224707
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.730818436
Short name T317
Test name
Test status
Simulation time 51212375 ps
CPU time 3.35 seconds
Started Aug 07 06:19:48 PM PDT 24
Finished Aug 07 06:19:51 PM PDT 24
Peak memory 208652 kb
Host smart-e740130b-b0ab-441e-ae36-838463c29c0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730818436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.730818436
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3581727435
Short name T77
Test name
Test status
Simulation time 1753305224 ps
CPU time 18.75 seconds
Started Aug 07 06:19:43 PM PDT 24
Finished Aug 07 06:20:02 PM PDT 24
Peak memory 218156 kb
Host smart-cd35e7d8-d96f-4a03-bbf1-c04e57872e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581727435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3581727435
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3375740941
Short name T371
Test name
Test status
Simulation time 103914699 ps
CPU time 3.76 seconds
Started Aug 07 06:19:42 PM PDT 24
Finished Aug 07 06:19:45 PM PDT 24
Peak memory 210336 kb
Host smart-3e78ea01-d8d6-4d6d-9a33-927ae6790236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375740941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3375740941
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3350214987
Short name T893
Test name
Test status
Simulation time 161325652 ps
CPU time 0.81 seconds
Started Aug 07 06:17:20 PM PDT 24
Finished Aug 07 06:17:21 PM PDT 24
Peak memory 205964 kb
Host smart-85b03847-e0b5-4a2f-b5c7-936c847a32ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350214987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3350214987
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1589632349
Short name T316
Test name
Test status
Simulation time 6600512908 ps
CPU time 92.48 seconds
Started Aug 07 06:17:17 PM PDT 24
Finished Aug 07 06:18:50 PM PDT 24
Peak memory 215848 kb
Host smart-27557420-1600-41ba-800b-8857d4b3d8e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1589632349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1589632349
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.157195915
Short name T681
Test name
Test status
Simulation time 199797961 ps
CPU time 2.38 seconds
Started Aug 07 06:17:22 PM PDT 24
Finished Aug 07 06:17:24 PM PDT 24
Peak memory 214176 kb
Host smart-75c02516-3d2f-48a3-92aa-e6df95ebd89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157195915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.157195915
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3019605199
Short name T363
Test name
Test status
Simulation time 725961980 ps
CPU time 2.57 seconds
Started Aug 07 06:17:17 PM PDT 24
Finished Aug 07 06:17:20 PM PDT 24
Peak memory 218364 kb
Host smart-d7e33bde-8c41-4c80-8344-08b5d586e8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019605199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3019605199
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2826688339
Short name T171
Test name
Test status
Simulation time 63033943 ps
CPU time 3.22 seconds
Started Aug 07 06:17:28 PM PDT 24
Finished Aug 07 06:17:32 PM PDT 24
Peak memory 209280 kb
Host smart-acd25b11-8fd6-4065-a595-de99763c585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826688339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2826688339
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1408831678
Short name T368
Test name
Test status
Simulation time 241278287 ps
CPU time 2.87 seconds
Started Aug 07 06:17:18 PM PDT 24
Finished Aug 07 06:17:21 PM PDT 24
Peak memory 214364 kb
Host smart-96c86b20-40db-497f-a5b6-098a7d5aecec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408831678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1408831678
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_random.2337959822
Short name T492
Test name
Test status
Simulation time 558396295 ps
CPU time 4.88 seconds
Started Aug 07 06:17:16 PM PDT 24
Finished Aug 07 06:17:21 PM PDT 24
Peak memory 210396 kb
Host smart-259dfd84-f2de-4dee-90e9-1eddff485395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337959822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2337959822
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3312708857
Short name T591
Test name
Test status
Simulation time 60474899 ps
CPU time 1.72 seconds
Started Aug 07 06:17:21 PM PDT 24
Finished Aug 07 06:17:23 PM PDT 24
Peak memory 206828 kb
Host smart-ac69b102-4033-487e-9df1-ab102c549956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312708857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3312708857
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1214479858
Short name T790
Test name
Test status
Simulation time 315580635 ps
CPU time 3.78 seconds
Started Aug 07 06:17:28 PM PDT 24
Finished Aug 07 06:17:32 PM PDT 24
Peak memory 208948 kb
Host smart-1fa598e6-0ffe-474a-83c3-29a1f07e7335
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214479858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1214479858
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2246894956
Short name T281
Test name
Test status
Simulation time 96929410 ps
CPU time 2.81 seconds
Started Aug 07 06:17:17 PM PDT 24
Finished Aug 07 06:17:20 PM PDT 24
Peak memory 209000 kb
Host smart-12c49c2b-5b98-4040-83dd-a32bd215316e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246894956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2246894956
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.636306624
Short name T416
Test name
Test status
Simulation time 1146182071 ps
CPU time 23.17 seconds
Started Aug 07 06:17:17 PM PDT 24
Finished Aug 07 06:17:40 PM PDT 24
Peak memory 208760 kb
Host smart-7631ed22-abfd-470b-a59a-33218fe86772
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636306624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.636306624
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1837380903
Short name T174
Test name
Test status
Simulation time 99377669 ps
CPU time 3.02 seconds
Started Aug 07 06:17:20 PM PDT 24
Finished Aug 07 06:17:23 PM PDT 24
Peak memory 214328 kb
Host smart-725485d5-d8c4-47cc-9fd5-574f7d0ab703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837380903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1837380903
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.554762688
Short name T562
Test name
Test status
Simulation time 2306047917 ps
CPU time 13.78 seconds
Started Aug 07 06:17:19 PM PDT 24
Finished Aug 07 06:17:33 PM PDT 24
Peak memory 207964 kb
Host smart-0194e4e9-8198-4d29-a6fc-ed8d3faa3210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554762688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.554762688
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2348639473
Short name T126
Test name
Test status
Simulation time 709340608 ps
CPU time 7.95 seconds
Started Aug 07 06:17:18 PM PDT 24
Finished Aug 07 06:17:26 PM PDT 24
Peak memory 222436 kb
Host smart-5cad48d0-71ee-4bd3-81dc-5740065b662a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348639473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2348639473
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.671013034
Short name T510
Test name
Test status
Simulation time 514768118 ps
CPU time 5.65 seconds
Started Aug 07 06:17:17 PM PDT 24
Finished Aug 07 06:17:22 PM PDT 24
Peak memory 209296 kb
Host smart-6ed4b749-ab07-4fe8-8254-c4029054d56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671013034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.671013034
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1889341053
Short name T622
Test name
Test status
Simulation time 14789936 ps
CPU time 0.88 seconds
Started Aug 07 06:17:24 PM PDT 24
Finished Aug 07 06:17:25 PM PDT 24
Peak memory 205964 kb
Host smart-7625341f-a8d8-4ef9-9969-159806e19649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889341053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1889341053
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.751871366
Short name T100
Test name
Test status
Simulation time 233778052 ps
CPU time 3.18 seconds
Started Aug 07 06:17:24 PM PDT 24
Finished Aug 07 06:17:27 PM PDT 24
Peak memory 218004 kb
Host smart-46d1917d-70e4-405a-91be-115099d37750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751871366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.751871366
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1249243437
Short name T563
Test name
Test status
Simulation time 870623796 ps
CPU time 4.11 seconds
Started Aug 07 06:17:23 PM PDT 24
Finished Aug 07 06:17:27 PM PDT 24
Peak memory 208656 kb
Host smart-b2bf876d-fc38-4b82-b6be-951de0e56df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249243437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1249243437
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2177642553
Short name T885
Test name
Test status
Simulation time 251956771 ps
CPU time 3.83 seconds
Started Aug 07 06:17:23 PM PDT 24
Finished Aug 07 06:17:27 PM PDT 24
Peak memory 222520 kb
Host smart-5c994a19-0c6c-40c7-be85-cb7139ce6b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177642553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2177642553
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.623970179
Short name T744
Test name
Test status
Simulation time 321689918 ps
CPU time 2.65 seconds
Started Aug 07 06:17:23 PM PDT 24
Finished Aug 07 06:17:26 PM PDT 24
Peak memory 220140 kb
Host smart-70f8f124-474b-477c-89e9-cfb82cc7f47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623970179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.623970179
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.469323811
Short name T190
Test name
Test status
Simulation time 4111699734 ps
CPU time 22.24 seconds
Started Aug 07 06:17:25 PM PDT 24
Finished Aug 07 06:17:47 PM PDT 24
Peak memory 208944 kb
Host smart-d66df215-94bc-48a2-a15a-cd2ca283a59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469323811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.469323811
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1014400929
Short name T801
Test name
Test status
Simulation time 177707976 ps
CPU time 3.92 seconds
Started Aug 07 06:17:18 PM PDT 24
Finished Aug 07 06:17:22 PM PDT 24
Peak memory 208108 kb
Host smart-9813c4eb-f03a-484f-aab4-b893f65e1649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014400929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1014400929
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4233856809
Short name T633
Test name
Test status
Simulation time 129158344 ps
CPU time 2.48 seconds
Started Aug 07 06:17:28 PM PDT 24
Finished Aug 07 06:17:31 PM PDT 24
Peak memory 207452 kb
Host smart-b0b9073c-fd7e-49c6-9f71-d159f259169d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233856809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4233856809
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1531372370
Short name T354
Test name
Test status
Simulation time 171200714 ps
CPU time 5.17 seconds
Started Aug 07 06:17:28 PM PDT 24
Finished Aug 07 06:17:34 PM PDT 24
Peak memory 208536 kb
Host smart-05661705-7c41-42ec-850d-70d3c7f0e5dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531372370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1531372370
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.4115982881
Short name T650
Test name
Test status
Simulation time 130167539 ps
CPU time 2.45 seconds
Started Aug 07 06:17:22 PM PDT 24
Finished Aug 07 06:17:24 PM PDT 24
Peak memory 206864 kb
Host smart-4e75d821-ff7e-47bb-9b2c-5eab32ffe00b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115982881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4115982881
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.4282556278
Short name T411
Test name
Test status
Simulation time 196933771 ps
CPU time 3.6 seconds
Started Aug 07 06:17:23 PM PDT 24
Finished Aug 07 06:17:27 PM PDT 24
Peak memory 209020 kb
Host smart-bf23e753-7fb2-4d07-a329-3297ef036464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282556278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.4282556278
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3430104103
Short name T407
Test name
Test status
Simulation time 53172511 ps
CPU time 2.66 seconds
Started Aug 07 06:17:27 PM PDT 24
Finished Aug 07 06:17:30 PM PDT 24
Peak memory 206856 kb
Host smart-1754ac21-9a6f-4fdd-b6da-d071f3136dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430104103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3430104103
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.958973662
Short name T51
Test name
Test status
Simulation time 1559811884 ps
CPU time 22.9 seconds
Started Aug 07 06:17:27 PM PDT 24
Finished Aug 07 06:17:50 PM PDT 24
Peak memory 222456 kb
Host smart-72dfe47c-555f-4792-9ccf-e5da57c81f79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958973662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.958973662
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2638240583
Short name T410
Test name
Test status
Simulation time 850882743 ps
CPU time 9.92 seconds
Started Aug 07 06:17:23 PM PDT 24
Finished Aug 07 06:17:34 PM PDT 24
Peak memory 209196 kb
Host smart-132c467c-d7ec-4500-a5b1-c5e0e848ced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638240583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2638240583
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3930656201
Short name T148
Test name
Test status
Simulation time 39567180 ps
CPU time 1.56 seconds
Started Aug 07 06:17:25 PM PDT 24
Finished Aug 07 06:17:26 PM PDT 24
Peak memory 209600 kb
Host smart-ecce11de-bbfa-49df-b54e-35c1e2158869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930656201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3930656201
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.897083521
Short name T748
Test name
Test status
Simulation time 11234968 ps
CPU time 0.73 seconds
Started Aug 07 06:17:33 PM PDT 24
Finished Aug 07 06:17:33 PM PDT 24
Peak memory 205980 kb
Host smart-5f2c223b-5b5b-4f07-bea1-63cbcbf76e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897083521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.897083521
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1387886422
Short name T20
Test name
Test status
Simulation time 30915912 ps
CPU time 1.65 seconds
Started Aug 07 06:17:30 PM PDT 24
Finished Aug 07 06:17:32 PM PDT 24
Peak memory 222608 kb
Host smart-a510ff83-5e0d-47d9-a55e-17647ffd4acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387886422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1387886422
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2246869036
Short name T594
Test name
Test status
Simulation time 245246958 ps
CPU time 2.81 seconds
Started Aug 07 06:17:31 PM PDT 24
Finished Aug 07 06:17:34 PM PDT 24
Peak memory 207496 kb
Host smart-1cc3c756-a59b-4894-ac4e-70140c86392d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246869036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2246869036
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2772167947
Short name T844
Test name
Test status
Simulation time 32978244 ps
CPU time 2.42 seconds
Started Aug 07 06:17:27 PM PDT 24
Finished Aug 07 06:17:30 PM PDT 24
Peak memory 214344 kb
Host smart-b2854da1-4f14-4033-b012-7f1134419b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772167947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2772167947
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3438398154
Short name T767
Test name
Test status
Simulation time 423141749 ps
CPU time 2.38 seconds
Started Aug 07 06:17:31 PM PDT 24
Finished Aug 07 06:17:34 PM PDT 24
Peak memory 214428 kb
Host smart-62f2f45e-3f0c-4f65-9cb1-ebbc77737f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438398154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3438398154
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.907966358
Short name T444
Test name
Test status
Simulation time 93038622 ps
CPU time 3.17 seconds
Started Aug 07 06:17:27 PM PDT 24
Finished Aug 07 06:17:31 PM PDT 24
Peak memory 220208 kb
Host smart-eb3b7a7f-2c9f-4992-8737-ce2e50ce2ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907966358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.907966358
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2383851480
Short name T605
Test name
Test status
Simulation time 179871137 ps
CPU time 5.95 seconds
Started Aug 07 06:17:23 PM PDT 24
Finished Aug 07 06:17:29 PM PDT 24
Peak memory 214332 kb
Host smart-389eafb6-7c34-4c89-ad39-3a671d212ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383851480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2383851480
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2981672234
Short name T566
Test name
Test status
Simulation time 392046184 ps
CPU time 4.75 seconds
Started Aug 07 06:17:24 PM PDT 24
Finished Aug 07 06:17:29 PM PDT 24
Peak memory 208088 kb
Host smart-ec07a3ad-8a93-4cff-929d-4af24bf5f8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981672234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2981672234
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1023398472
Short name T784
Test name
Test status
Simulation time 78543962 ps
CPU time 3.57 seconds
Started Aug 07 06:17:21 PM PDT 24
Finished Aug 07 06:17:25 PM PDT 24
Peak memory 208024 kb
Host smart-d6b5e851-b894-42a0-ad4d-e864ce896e2f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023398472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1023398472
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1602946205
Short name T14
Test name
Test status
Simulation time 447154582 ps
CPU time 4.93 seconds
Started Aug 07 06:17:23 PM PDT 24
Finished Aug 07 06:17:28 PM PDT 24
Peak memory 208756 kb
Host smart-9a2550a4-ac78-410e-b9a4-9b1447ce45d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602946205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1602946205
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.409921309
Short name T629
Test name
Test status
Simulation time 216789487 ps
CPU time 3.17 seconds
Started Aug 07 06:17:29 PM PDT 24
Finished Aug 07 06:17:32 PM PDT 24
Peak memory 209140 kb
Host smart-6b142a41-c906-4da7-9ff3-662426cc7bb5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409921309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.409921309
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3688186188
Short name T177
Test name
Test status
Simulation time 406087336 ps
CPU time 5.53 seconds
Started Aug 07 06:17:28 PM PDT 24
Finished Aug 07 06:17:34 PM PDT 24
Peak memory 218520 kb
Host smart-c98d5143-50dc-4daf-a5dd-1517d69c2d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688186188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3688186188
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1933485250
Short name T703
Test name
Test status
Simulation time 63248003 ps
CPU time 2.08 seconds
Started Aug 07 06:17:22 PM PDT 24
Finished Aug 07 06:17:25 PM PDT 24
Peak memory 206836 kb
Host smart-f7a5be54-caf7-4f6b-8569-a533896fa1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933485250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1933485250
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1982264291
Short name T613
Test name
Test status
Simulation time 936064460 ps
CPU time 31.28 seconds
Started Aug 07 06:17:30 PM PDT 24
Finished Aug 07 06:18:02 PM PDT 24
Peak memory 214828 kb
Host smart-8d5b3d98-91d4-45bf-9374-904d1a0d57b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982264291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1982264291
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.690481656
Short name T572
Test name
Test status
Simulation time 573015016 ps
CPU time 10.25 seconds
Started Aug 07 06:17:26 PM PDT 24
Finished Aug 07 06:17:37 PM PDT 24
Peak memory 220188 kb
Host smart-f23fde7e-0e81-478f-b293-ab4b78f69023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690481656 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.690481656
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.4031860302
Short name T569
Test name
Test status
Simulation time 562157233 ps
CPU time 5.46 seconds
Started Aug 07 06:17:30 PM PDT 24
Finished Aug 07 06:17:35 PM PDT 24
Peak memory 207928 kb
Host smart-fbb026fb-45f4-405e-9810-20fc3b5f28ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031860302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.4031860302
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2931037651
Short name T378
Test name
Test status
Simulation time 89407844 ps
CPU time 1.93 seconds
Started Aug 07 06:17:29 PM PDT 24
Finished Aug 07 06:17:31 PM PDT 24
Peak memory 210244 kb
Host smart-d6acf0df-75b2-4c38-bf5f-af46b4b9a05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931037651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2931037651
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1611717206
Short name T435
Test name
Test status
Simulation time 22604596 ps
CPU time 0.81 seconds
Started Aug 07 06:17:29 PM PDT 24
Finished Aug 07 06:17:30 PM PDT 24
Peak memory 205980 kb
Host smart-e01a8ed6-bb22-4088-b6ee-50d4e91531e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611717206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1611717206
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.116835222
Short name T740
Test name
Test status
Simulation time 64425814 ps
CPU time 3.03 seconds
Started Aug 07 06:17:31 PM PDT 24
Finished Aug 07 06:17:35 PM PDT 24
Peak memory 214632 kb
Host smart-03a76171-d321-473f-9398-e242bcfdfe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116835222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.116835222
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1696478818
Short name T655
Test name
Test status
Simulation time 118128956 ps
CPU time 2.95 seconds
Started Aug 07 06:17:28 PM PDT 24
Finished Aug 07 06:17:32 PM PDT 24
Peak memory 209504 kb
Host smart-24fb1b90-d5c9-4f67-ae01-5010cf96c208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696478818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1696478818
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3066727748
Short name T353
Test name
Test status
Simulation time 1107661898 ps
CPU time 5.37 seconds
Started Aug 07 06:17:27 PM PDT 24
Finished Aug 07 06:17:32 PM PDT 24
Peak memory 208696 kb
Host smart-453c9bdf-6e84-463f-ae40-87339500ff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066727748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3066727748
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2295342376
Short name T233
Test name
Test status
Simulation time 422729147 ps
CPU time 3.54 seconds
Started Aug 07 06:17:30 PM PDT 24
Finished Aug 07 06:17:33 PM PDT 24
Peak memory 220300 kb
Host smart-af4c7588-24f9-4761-9ef7-92b4972889cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295342376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2295342376
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2689083121
Short name T102
Test name
Test status
Simulation time 308391504 ps
CPU time 1.87 seconds
Started Aug 07 06:17:33 PM PDT 24
Finished Aug 07 06:17:35 PM PDT 24
Peak memory 206216 kb
Host smart-d11a51d0-4636-4ddb-9fc5-e017352a9e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689083121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2689083121
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.625908137
Short name T15
Test name
Test status
Simulation time 330312994 ps
CPU time 3.37 seconds
Started Aug 07 06:17:32 PM PDT 24
Finished Aug 07 06:17:35 PM PDT 24
Peak memory 207832 kb
Host smart-ef0c993f-3731-4e0f-b581-6f36d5c7defe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625908137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.625908137
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3551666807
Short name T430
Test name
Test status
Simulation time 153466736 ps
CPU time 2.38 seconds
Started Aug 07 06:17:30 PM PDT 24
Finished Aug 07 06:17:33 PM PDT 24
Peak memory 206852 kb
Host smart-51e295c9-a477-450b-817f-34d6f305cc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551666807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3551666807
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3207800568
Short name T596
Test name
Test status
Simulation time 1613783712 ps
CPU time 33.27 seconds
Started Aug 07 06:17:29 PM PDT 24
Finished Aug 07 06:18:02 PM PDT 24
Peak memory 208356 kb
Host smart-d69cc572-e16e-4b72-843b-89612cf315fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207800568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3207800568
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2751393936
Short name T325
Test name
Test status
Simulation time 534827675 ps
CPU time 12.18 seconds
Started Aug 07 06:17:29 PM PDT 24
Finished Aug 07 06:17:42 PM PDT 24
Peak memory 207960 kb
Host smart-c14ecace-8a93-43c0-b4a8-8a1cc9406ead
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751393936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2751393936
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3024426700
Short name T867
Test name
Test status
Simulation time 810182438 ps
CPU time 19.8 seconds
Started Aug 07 06:17:30 PM PDT 24
Finished Aug 07 06:17:50 PM PDT 24
Peak memory 208892 kb
Host smart-303cc681-221d-4811-b46d-621ba6e15878
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024426700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3024426700
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1563353014
Short name T768
Test name
Test status
Simulation time 17151467700 ps
CPU time 34.2 seconds
Started Aug 07 06:17:30 PM PDT 24
Finished Aug 07 06:18:04 PM PDT 24
Peak memory 218392 kb
Host smart-f41b3a7f-a171-4e4d-a3ee-07dea4dcdd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563353014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1563353014
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.319831997
Short name T441
Test name
Test status
Simulation time 270764724 ps
CPU time 3.03 seconds
Started Aug 07 06:17:27 PM PDT 24
Finished Aug 07 06:17:30 PM PDT 24
Peak memory 208296 kb
Host smart-438d46d1-1ae8-454e-bf31-a6a110394fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319831997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.319831997
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.735071720
Short name T423
Test name
Test status
Simulation time 617875229 ps
CPU time 13.98 seconds
Started Aug 07 06:17:28 PM PDT 24
Finished Aug 07 06:17:42 PM PDT 24
Peak memory 209256 kb
Host smart-a329693d-2fdf-43b9-844f-2402686861b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735071720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.735071720
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1450484249
Short name T810
Test name
Test status
Simulation time 84723753 ps
CPU time 1.63 seconds
Started Aug 07 06:17:33 PM PDT 24
Finished Aug 07 06:17:34 PM PDT 24
Peak memory 209840 kb
Host smart-3dad7e77-bcdd-4243-9737-eade2c3a6fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450484249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1450484249
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1667709938
Short name T659
Test name
Test status
Simulation time 54431693 ps
CPU time 0.79 seconds
Started Aug 07 06:17:35 PM PDT 24
Finished Aug 07 06:17:35 PM PDT 24
Peak memory 205884 kb
Host smart-dfd607b9-cbd1-449e-88fd-f8046b60b2d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667709938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1667709938
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2856966026
Short name T236
Test name
Test status
Simulation time 145744341 ps
CPU time 6.85 seconds
Started Aug 07 06:17:29 PM PDT 24
Finished Aug 07 06:17:36 PM PDT 24
Peak memory 214464 kb
Host smart-7cac81d5-8e2b-46a5-8469-31cefcac7ff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2856966026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2856966026
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1267065912
Short name T304
Test name
Test status
Simulation time 250941274 ps
CPU time 3.36 seconds
Started Aug 07 06:17:29 PM PDT 24
Finished Aug 07 06:17:33 PM PDT 24
Peak memory 214324 kb
Host smart-09c2825f-925e-4bd7-9e91-3b916d202ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267065912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1267065912
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3768550583
Short name T861
Test name
Test status
Simulation time 230124256 ps
CPU time 5.46 seconds
Started Aug 07 06:17:33 PM PDT 24
Finished Aug 07 06:17:39 PM PDT 24
Peak memory 214316 kb
Host smart-ea24d355-86e2-4df7-a7cc-5887513720dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768550583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3768550583
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1213434919
Short name T251
Test name
Test status
Simulation time 851128134 ps
CPU time 5.26 seconds
Started Aug 07 06:17:33 PM PDT 24
Finished Aug 07 06:17:38 PM PDT 24
Peak memory 214592 kb
Host smart-095dcbe3-b826-4c34-9bed-dbb668a60fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213434919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1213434919
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.4293424102
Short name T198
Test name
Test status
Simulation time 72481493 ps
CPU time 3.09 seconds
Started Aug 07 06:17:29 PM PDT 24
Finished Aug 07 06:17:32 PM PDT 24
Peak memory 214584 kb
Host smart-ef7db028-d927-456a-86b7-25c5ede37c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293424102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.4293424102
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3584334525
Short name T387
Test name
Test status
Simulation time 4731775382 ps
CPU time 83.58 seconds
Started Aug 07 06:17:29 PM PDT 24
Finished Aug 07 06:18:53 PM PDT 24
Peak memory 209684 kb
Host smart-0f0ed7fd-b0fb-4336-8812-207d6fcc01eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584334525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3584334525
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3306981381
Short name T519
Test name
Test status
Simulation time 474385865 ps
CPU time 5.97 seconds
Started Aug 07 06:17:28 PM PDT 24
Finished Aug 07 06:17:34 PM PDT 24
Peak memory 208524 kb
Host smart-b538f724-1701-4df8-90d8-5bfef63680b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306981381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3306981381
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.4000851217
Short name T690
Test name
Test status
Simulation time 417574272 ps
CPU time 3.67 seconds
Started Aug 07 06:17:30 PM PDT 24
Finished Aug 07 06:17:34 PM PDT 24
Peak memory 208600 kb
Host smart-e2c9d9ff-345a-498d-8c0c-f4cf1da213d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000851217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.4000851217
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1734348789
Short name T658
Test name
Test status
Simulation time 71679331 ps
CPU time 2.59 seconds
Started Aug 07 06:17:28 PM PDT 24
Finished Aug 07 06:17:31 PM PDT 24
Peak memory 208740 kb
Host smart-b12aabda-1dd0-41f3-b086-52d40dc334e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734348789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1734348789
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1756977
Short name T176
Test name
Test status
Simulation time 171938301 ps
CPU time 2.59 seconds
Started Aug 07 06:17:29 PM PDT 24
Finished Aug 07 06:17:32 PM PDT 24
Peak memory 208752 kb
Host smart-f837f68e-14f0-43f4-ad84-a8fed222743a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1756977
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.407531533
Short name T780
Test name
Test status
Simulation time 266887529 ps
CPU time 3.44 seconds
Started Aug 07 06:17:34 PM PDT 24
Finished Aug 07 06:17:38 PM PDT 24
Peak memory 208940 kb
Host smart-42996b81-6c4c-42f5-bc25-16d863634c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407531533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.407531533
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3820339893
Short name T601
Test name
Test status
Simulation time 46265446 ps
CPU time 2.22 seconds
Started Aug 07 06:17:32 PM PDT 24
Finished Aug 07 06:17:34 PM PDT 24
Peak memory 206760 kb
Host smart-7ac7c8d4-71ca-4659-9f08-427d9c3ed2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820339893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3820339893
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.4038220244
Short name T221
Test name
Test status
Simulation time 701943509 ps
CPU time 27.36 seconds
Started Aug 07 06:17:31 PM PDT 24
Finished Aug 07 06:17:59 PM PDT 24
Peak memory 222244 kb
Host smart-8e1b5d76-6d42-498e-a9bf-fd8b719fd9f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038220244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.4038220244
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.787212797
Short name T551
Test name
Test status
Simulation time 124770129 ps
CPU time 5.3 seconds
Started Aug 07 06:17:28 PM PDT 24
Finished Aug 07 06:17:34 PM PDT 24
Peak memory 218216 kb
Host smart-dbfef149-8f62-4d9a-8ec2-71e1c47f2fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787212797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.787212797
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1993065568
Short name T440
Test name
Test status
Simulation time 353247015 ps
CPU time 1.58 seconds
Started Aug 07 06:17:34 PM PDT 24
Finished Aug 07 06:17:36 PM PDT 24
Peak memory 209912 kb
Host smart-0c2e6994-eabd-45a3-8b0d-c584790ba675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993065568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1993065568
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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