Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4611

1

T1

5

T2

8

T4

1

auto[1]

554

1

T16

1

T43

6

T190

3

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4611

1

T1

5

T2

8

T4

1

auto[1]

554

1

T16

1

T43

6

T190

3

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4587

1

T1

2

T2

5

T4

1

auto[1]

578

1

T1

3

T2

3

T16

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4587

1

T1

2

T2

5

T4

1

auto[1]

578

1

T1

3

T2

3

T16

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	370	1			T18	2		T19	6		T35	1
auto[OpGenId]	1100	1			T1	1		T15	1		T16	2
auto[OpGenSwOut]	1089	1			T1	2		T4	1		T15	2
auto[OpGenHwOut]	2539	1			T1	2		T2	8		T15	2
auto[OpDisable]	67	1			T34	1		T44	1		T46	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	370	1			T18	2		T19	6		T35	1
auto[OpGenId]	1100	1			T1	1		T15	1		T16	2
auto[OpGenSwOut]	1089	1			T1	2		T4	1		T15	2
auto[OpGenHwOut]	2539	1			T1	2		T2	8		T15	2
auto[OpDisable]	67	1			T34	1		T44	1		T46	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4678

1

T1

5

T2

8

T4

1

auto[1]

487

1

T16

3

T19

1

T44

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4678

1

T1

5

T2

8

T4

1

auto[1]

487

1

T16

3

T19

1

T44

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4902

1

T1

5

T2

8

T4

1

auto[1]

263

1

T19

5

T113

7

T135

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1771	1			T1	4		T2	2		T4	1
auto[1]	682	1			T2	1		T15	1		T16	1
auto[2]	695	1			T2	1		T16	2		T18	1
auto[3]	698	1			T2	1		T19	3		T43	4
auto[4]	315	1			T2	1		T19	3		T43	3
auto[5]	318	1			T1	1		T2	1		T43	3
auto[6]	346	1			T2	1		T15	1		T35	1
auto[7]	340	1			T15	1		T18	1		T43	4

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1319	1			T1	1		T2	3		T15	2
clear_one[1]	682	1			T2	1		T15	1		T16	1
clear_one[2]	695	1			T2	1		T16	2		T18	1
clear_one[3]	698	1			T2	1		T19	3		T43	4
clear_none	1771	1			T1	4		T2	2		T4	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1005	1			T15	1		T16	2		T18	1
auto[StInit]	651	1			T1	1		T2	1		T19	2
auto[StCreatorRootKey]	559	1			T2	1		T4	1		T19	1
auto[StOwnerIntKey]	525	1			T1	1		T2	1		T16	1
auto[StOwnerKey]	419	1			T2	1		T43	5		T133	1
auto[StDisabled]	1723	1			T1	3		T2	4		T16	2
auto[StInvalid]	283	1			T15	4		T18	4		T35	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1005	1			T15	1		T16	2		T18	1
auto[StInit]	651	1			T1	1		T2	1		T19	2
auto[StCreatorRootKey]	559	1			T2	1		T4	1		T19	1
auto[StOwnerIntKey]	525	1			T1	1		T2	1		T16	1
auto[StOwnerKey]	419	1			T2	1		T43	5		T133	1
auto[StDisabled]	1723	1			T1	3		T2	4		T16	2
auto[StInvalid]	283	1			T15	4		T18	4		T35	2

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	15
[auto[0] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[3] - auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	4
[auto[3] - auto[6]]	[auto[StReset]]	[auto[OpDisable]]	--	--	4
[auto[3] - auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	16
[auto[3] - auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[7]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	5	1			T136	1		T223	1		T224	1
auto[0]	auto[StReset]	auto[OpGenId]	150	1			T35	2		T43	1		T30	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	154	1			T15	1		T16	1		T43	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	270	1			T18	1		T43	1		T190	1
auto[0]	auto[StInit]	auto[OpAdvance]	40	1			T19	1		T43	1		T44	1
auto[0]	auto[StInit]	auto[OpGenId]	101	1			T46	3		T225	1		T23	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	100	1			T34	1		T36	1		T52	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	179	1			T1	1		T2	1		T133	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	17	1			T43	1		T6	1		T204	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	45	1			T77	2		T192	1		T70	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	53	1			T4	1		T44	1		T77	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	85	1			T43	1		T133	1		T113	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	16	1			T77	1		T204	1		T64	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T16	1		T135	1		T226	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	29	1			T62	1		T227	1		T102	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	52	1			T26	1		T43	1		T42	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T135	1		T64	1		T228	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	17	1			T77	2		T229	1		T8	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T44	1		T77	1		T8	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	31	1			T126	1		T230	1		T60	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	20	1			T113	1		T86	1		T192	1
auto[0]	auto[StDisabled]	auto[OpGenId]	62	1			T1	1		T26	1		T43	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T1	2		T43	2		T46	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	155	1			T2	1		T133	1		T130	1
auto[0]	auto[StDisabled]	auto[OpDisable]	16	1			T70	1		T6	1		T68	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	7	1			T81	1		T231	1		T232	1
auto[0]	auto[StInvalid]	auto[OpGenId]	19	1			T36	1		T48	1		T233	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	26	1			T18	1		T48	1		T87	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	21	1			T15	1		T87	1		T85	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T234	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	14	1			T128	1		T6	1		T121	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	19	1			T35	1		T43	1		T6	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	38	1			T35	1		T44	1		T129	1
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T123	1		T235	2		-	-
auto[1]	auto[StInit]	auto[OpGenId]	6	1			T66	1		T229	1		T236	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	7	1			T67	1		T234	1		T108	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	28	1			T230	1		T71	1		T201	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T128	1		T237	1		T187	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T46	1		T53	1		T72	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T43	1		T189	1		T238	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T2	1		T134	1		T126	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T79	1		T239	1		T137	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T23	1		T24	1		T240	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	21	1			T62	1		T198	1		T241	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T133	1		T126	1		T242	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T113	1		T137	1		T10	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	12	1			T42	1		T60	1		T243	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T43	1		T86	1		T225	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T190	1		T128	1		T197	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	18	1			T135	1		T46	1		T77	1
auto[1]	auto[StDisabled]	auto[OpGenId]	65	1			T44	1		T113	2		T82	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	44	1			T42	1		T46	1		T82	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	143	1			T16	1		T43	2		T133	1
auto[1]	auto[StDisabled]	auto[OpDisable]	12	1			T34	1		T44	1		T244	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	6	1			T18	1		T35	1		T245	1
auto[1]	auto[StInvalid]	auto[OpGenId]	10	1			T36	1		T80	1		T55	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T80	1		T246	1		T247	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T15	1		T233	1		T248	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T239	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	27	1			T16	1		T81	1		T249	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	25	1			T42	1		T53	1		T39	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	44	1			T242	1		T250	1		T251	1
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T252	1		T214	1		T253	1
auto[2]	auto[StInit]	auto[OpGenId]	14	1			T189	1		T239	1		T254	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	9	1			T43	1		T46	2		T179	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	22	1			T129	1		T251	1		T255	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T256	1		T257	1		-	-
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T46	1		T8	1		T24	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T34	1		T44	1		T127	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	47	1			T190	1		T129	1		T250	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T43	1		T192	1		T124	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T46	2		T67	1		T64	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T60	1		T137	1		T258	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T19	2		T44	1		T46	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T259	1		T260	1		T93	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	12	1			T135	1		T226	1		T184	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T43	1		T67	1		T204	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	36	1			T196	1		T78	1		T255	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	22	1			T19	2		T259	1		T261	1
auto[2]	auto[StDisabled]	auto[OpGenId]	56	1			T43	1		T86	1		T46	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T16	1		T225	1		T262	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T2	1		T190	2		T44	2
auto[2]	auto[StDisabled]	auto[OpDisable]	5	1			T178	1		T214	1		T263	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	7	1			T233	1		T81	1		T248	1
auto[2]	auto[StInvalid]	auto[OpGenId]	6	1			T264	1		T265	1		T232	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T18	1		T36	1		T87	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T35	1		T87	1		T266	1
auto[3]	auto[StReset]	auto[OpGenId]	21	1			T53	1		T102	1		T63	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	22	1			T42	1		T60	2		T239	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	49	1			T130	1		T27	1		T242	1
auto[3]	auto[StInit]	auto[OpAdvance]	9	1			T19	1		T144	1		T239	1
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T267	1		T64	1		T108	2
auto[3]	auto[StInit]	auto[OpGenSwOut]	10	1			T46	1		T63	1		T123	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	24	1			T128	1		T242	1		T250	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T213	1		T268	1		T260	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T44	1		T27	1		T82	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T144	2		T137	2		T6	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	33	1			T19	1		T195	1		T242	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T260	3		T269	1		T220	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T239	5		T63	1		T124	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T113	1		T239	1		T201	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	48	1			T130	1		T82	1		T270	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T204	1		T260	1		T271	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	14	1			T46	1		T123	1		T84	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T189	1		T113	1		T57	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T2	1		T43	1		T44	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	19	1			T189	1		T82	1		T88	1
auto[3]	auto[StDisabled]	auto[OpGenId]	51	1			T42	1		T46	1		T144	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	41	1			T19	1		T43	1		T86	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T43	2		T47	1		T126	1
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T46	1		T74	1		T272	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	7	1			T273	1		T85	1		T245	1
auto[3]	auto[StInvalid]	auto[OpGenId]	14	1			T87	1		T248	1		T273	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T36	1		T81	1		T248	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T274	1		T275	2		T231	1
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T39	1		T276	1		T234	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	12	1			T6	1		T67	1		T241	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	23	1			T44	1		T242	1		T277	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T278	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	5	1			T46	1		T64	1		T279	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T67	1		T185	1		T280	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	7	1			T130	1		T281	1		T282	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T283	1		T176	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T86	1		T69	1		T284	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T45	1		T46	2		T75	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T60	1		T285	1		T101	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T286	1		T287	1		T185	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T63	1		T288	1		T289	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T234	1		T73	1		T290	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T2	1		T129	1		T291	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T236	1		T292	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	2	1			T267	1		T293	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T46	1		T124	1		T294	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T251	1		T295	1		T296	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	6	1			T19	2		T267	1		T8	1
auto[4]	auto[StDisabled]	auto[OpGenId]	28	1			T192	1		T258	1		T73	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	18	1			T43	1		T73	2		T108	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T19	1		T43	2		T133	1
auto[4]	auto[StDisabled]	auto[OpDisable]	8	1			T53	1		T67	1		T268	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T52	1		T297	1		T298	1
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T36	1		T299	1		T300	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T266	1		T301	1		T302	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T264	1		T303	1		T304	1
auto[5]	auto[StReset]	auto[OpGenId]	7	1			T239	1		T305	1		T216	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	9	1			T6	2		T300	1		T75	2
auto[5]	auto[StReset]	auto[OpGenHwOut]	25	1			T43	1		T251	1		T254	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T200	1		T89	1		T175	1
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T127	1		T305	1		T216	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T71	1		T218	1		T306	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	7	1			T126	1		T78	1		T67	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T274	1		T123	1		T172	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T46	1		T23	1		T102	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T276	1		T307	1		T216	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T197	1		T308	1		T309	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T214	1		T310	1		T311	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T216	1		T224	1		T312	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T249	1		T313	1		T314	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	12	1			T1	1		T196	1		T296	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T185	1		-	-		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	12	1			T43	1		T102	1		T315	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T67	1		T64	1		T268	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	13	1			T242	1		T270	1		T6	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	12	1			T23	1		T63	1		T201	2
auto[5]	auto[StDisabled]	auto[OpGenId]	26	1			T43	1		T53	1		T71	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	14	1			T226	1		T63	1		T64	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T2	1		T190	1		T129	1
auto[5]	auto[StDisabled]	auto[OpDisable]	7	1			T71	1		T72	1		T63	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T87	1		T316	1		T297	1
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T80	1		T273	1		T303	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T317	1		T318	1		T319	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T299	1		T320	1		T297	1
auto[6]	auto[StReset]	auto[OpGenId]	14	1			T35	1		T60	1		T268	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	12	1			T42	1		T68	1		T63	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	17	1			T277	2		T230	1		T282	1
auto[6]	auto[StInit]	auto[OpAdvance]	4	1			T260	1		T252	1		T321	1
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T46	1		T322	1		T186	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	6	1			T182	1		T323	1		T217	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	7	1			T42	1		T324	1		T325	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T6	1		T252	1		T326	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T10	1		T323	1		T327	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T46	1		T63	1		T64	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T255	1		T328	1		T53	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T252	1		T329	1		T330	2
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T43	1		T46	2		T60	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T42	1		T256	1		T279	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	27	1			T30	1		T195	1		T58	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T305	1		T331	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T102	1		T73	1		T240	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T332	1		T120	1		T333	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T133	1		T324	1		T63	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	8	1			T43	1		T269	1		T256	1
auto[6]	auto[StDisabled]	auto[OpGenId]	22	1			T128	1		T259	1		T64	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T26	1		T201	1		T334	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T2	1		T133	1		T126	1
auto[6]	auto[StDisabled]	auto[OpDisable]	3	1			T102	1		T186	1		T335	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	5	1			T336	1		T337	1		T338	1
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T15	1		T339	1		T316	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T48	1		T273	1		T275	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T299	1		T340	1		T304	1
auto[7]	auto[StReset]	auto[OpGenId]	5	1			T8	1		T89	1		T341	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	10	1			T43	1		T46	1		T248	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T130	1		T277	1		T250	1
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T53	1		T124	1		T217	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T30	1		T183	1		T311	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	16	1			T190	1		T277	1		T276	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T326	1		-	-		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T47	1		T249	1		T240	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T215	1		T342	1		T343	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T291	1		T196	1		T230	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T344	1		T292	1		T345	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T64	1		T228	1		T346	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T43	1		T39	1		T63	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	29	1			T190	1		T197	1		T78	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T43	1		T347	2		T209	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	3	1			T79	1		T63	1		T201	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T244	1		T216	2		T348	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T291	1		T103	1		T349	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	11	1			T70	1		T8	1		T269	1
auto[7]	auto[StDisabled]	auto[OpGenId]	30	1			T77	1		T62	1		T347	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T43	1		T86	1		T46	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	66	1			T44	1		T291	1		T196	2
auto[7]	auto[StDisabled]	auto[OpDisable]	7	1			T262	1		T67	1		T8	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T18	1		T85	1		T317	1
auto[7]	auto[StInvalid]	auto[OpGenId]	6	1			T87	1		T81	1		T85	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T15	1		T52	2		T301	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T245	1		T350	1		T338	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1319

1

T1

1

T2

3

T15

2

clear_one[1]

auto[0]

auto[0]

auto[0]

407

1

T15

1

T18

1

T34

1

clear_one[1]

auto[0]

auto[0]

auto[1]

104

1

T44

1

T126

2

T195

2

clear_one[1]

auto[0]

auto[1]

auto[0]

130

1

T2

1

T43

2

T133

2

clear_one[1]

auto[0]

auto[1]

auto[1]

41

1

T16

1

T79

1

T66

1

clear_one[2]

auto[0]

auto[0]

auto[0]

421

1

T2

1

T16

1

T18

1

clear_one[2]

auto[0]

auto[0]

auto[1]

105

1

T19

1

T44

1

T126

1

clear_one[2]

auto[1]

auto[0]

auto[0]

129

1

T43

1

T190

3

T44

1

clear_one[2]

auto[1]

auto[0]

auto[1]

40

1

T16

1

T44

1

T136

1

clear_one[3]

auto[0]

auto[0]

auto[0]

398

1

T19

3

T47

1

T189

2

clear_one[3]

auto[0]

auto[1]

auto[0]

139

1

T2

1

T130

2

T46

1

clear_one[3]

auto[1]

auto[0]

auto[0]

120

1

T43

2

T42

1

T44

1

clear_one[3]

auto[1]

auto[1]

auto[0]

41

1

T43

2

T128

1

T113

3

clear_none

auto[0]

auto[0]

auto[0]

1281

1

T1

1

T2

1

T4

1

clear_none

auto[0]

auto[0]

auto[1]

99

1

T16

1

T44

1

T126

1

clear_none

auto[0]

auto[1]

auto[0]

132

1

T1

3

T2

1

T26

2

clear_none

auto[0]

auto[1]

auto[1]

35

1

T46

1

T60

3

T88

1

clear_none

auto[1]

auto[0]

auto[0]

133

1

T43

1

T42

1

T46

4

clear_none

auto[1]

auto[0]

auto[1]

31

1

T46

1

T192

1

T227

1

clear_none

auto[1]

auto[1]

auto[0]

28

1

T113

1

T70

1

T6

2

clear_none

auto[1]

auto[1]

auto[1]

32

1

T46

1

T79

1

T6

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1281	1			T1	1		T2	3		T15	2
clear_all	auto[1]	38	1			T19	2		T347	2		T252	5
clear_one[1]	auto[0]	630	1			T2	1		T15	1		T16	1
clear_one[1]	auto[1]	52	1			T113	2		T135	1		T77	1
clear_one[2]	auto[0]	660	1			T2	1		T16	2		T18	1
clear_one[2]	auto[1]	35	1			T19	2		T239	1		T137	1
clear_one[3]	auto[0]	653	1			T2	1		T19	2		T43	4
clear_one[3]	auto[1]	45	1			T19	1		T113	2		T82	1
clear_none	auto[0]	1678	1			T1	4		T2	2		T4	1
clear_none	auto[1]	93	1			T113	3		T135	1		T77	10