Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10955

1

T1

15

T2

4

T3

8

auto[Attestation]

7269

1

T1

10

T2

4

T4

12

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2639	1			T1	5		T3	1		T4	7
auto[Aes]	3356	1			T1	5		T3	1		T5	1
auto[Kmac]	3344	1			T1	4		T2	8		T3	3
auto[Otbn]	3164	1			T1	6		T4	3		T15	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7454	1			T1	8		T2	8		T3	8
auto[OpGenId]	5721	1			T1	5		T3	3		T5	4
auto[OpGenSwOut]	5655	1			T1	14		T3	5		T4	12
auto[OpGenHwOut]	6848	1			T1	6		T2	8		T5	1
auto[OpDisable]	135	1			T34	1		T47	1		T44	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10240

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

15573

1

T1

25

T2

8

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6562	1			T1	6		T2	1		T3	1
auto[StInit]	3663	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3023	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2679	1			T1	2		T2	2		T3	2
auto[StOwnerKey]	2328	1			T1	2		T2	2		T3	2
auto[StDisabled]	7558	1			T1	19		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	352	1			T1	1		T15	3		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	94	1			T3	1		T16	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	89	1			T4	1		T34	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T19	2		T44	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T43	3		T135	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	201	1			T17	1		T26	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	347	1			T15	2		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	103	1			T188	1		T189	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T43	2		T47	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	66	1			T3	1		T42	2		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	53	1			T43	1		T44	1		T144	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	217	1			T1	3		T4	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	379	1			T1	1		T15	4		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	96	1			T43	1		T42	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	76	1			T16	1		T43	2		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	68	1			T4	1		T19	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	63	1			T1	1		T3	1		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	196	1			T3	2		T4	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	327	1			T1	1		T15	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	95	1			T43	1		T42	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	65	1			T4	1		T43	1		T46	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T134	1		T113	1		T46	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	62	1			T86	1		T77	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	212	1			T1	3		T43	5		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	71	1			T42	1		T46	2		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	110	1			T34	1		T42	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T43	1		T134	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	71	1			T4	2		T43	3		T134	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	53	1			T44	1		T113	1		T46	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	214	1			T1	1		T43	3		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	56	1			T42	2		T62	2		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	88	1			T47	1		T44	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	64	1			T43	1		T77	2		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	61	1			T43	1		T189	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	55	1			T43	1		T189	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	195	1			T1	1		T4	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	60	1			T42	1		T46	1		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	110	1			T83	1		T43	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T83	1		T43	2		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	63	1			T4	1		T17	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	54	1			T189	1		T76	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	185	1			T4	1		T26	1		T43	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	77	1			T42	3		T46	5		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	106	1			T30	1		T127	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	73	1			T34	1		T44	2		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	63	1			T46	1		T77	1		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	57	1			T43	1		T46	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	186	1			T1	2		T4	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	265	1			T1	1		T15	2		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	99	1			T1	1		T43	2		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	78	1			T26	1		T43	2		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	70	1			T4	1		T26	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	40	1			T43	1		T30	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	171	1			T4	1		T19	1		T43	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	553	1			T5	1		T15	1		T43	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	122	1			T34	1		T190	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	107	1			T43	2		T42	1		T46	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	101	1			T129	1		T46	1		T77	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	69	1			T30	1		T79	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	259	1			T16	2		T43	2		T190	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	475	1			T15	1		T18	2		T35	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	134	1			T26	1		T133	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T2	1		T134	1		T127	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T134	2		T42	2		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	70	1			T43	1		T30	1		T113	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	273	1			T1	1		T2	3		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	425	1			T15	1		T16	3		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	116	1			T43	1		T195	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T43	1		T126	1		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	94	1			T19	1		T43	2		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	57	1			T195	1		T196	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	236	1			T43	2		T126	2		T113	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	53	1			T42	2		T46	2		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	85	1			T44	2		T135	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	68	1			T16	1		T19	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	60	1			T43	3		T42	1		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	42	1			T43	1		T60	1		T8	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	166	1			T1	1		T4	2		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	70	1			T42	1		T46	3		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	115	1			T43	1		T47	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	98	1			T190	1		T129	1		T113	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	87	1			T1	1		T190	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	92	1			T16	1		T43	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	287	1			T43	1		T190	2		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	63	1			T46	3		T60	1		T62	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	104	1			T2	1		T43	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	113	1			T26	1		T133	1		T127	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	109	1			T2	1		T26	1		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	100	1			T2	1		T26	1		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	282	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	58	1			T44	1		T46	2		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	117	1			T47	1		T126	1		T113	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T16	1		T43	1		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	97	1			T134	1		T27	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	103	1			T26	1		T43	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	277	1			T4	1		T43	1		T47	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	189	1			T4	1		T19	2		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	661	1			T1	1		T3	1		T15	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	197	1			T3	1		T43	3		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	680	1			T1	3		T4	2		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	184	1			T1	1		T3	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	694	1			T1	1		T3	2		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	185	1			T4	1		T43	1		T134	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	646	1			T1	4		T15	1		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	185	1			T4	2		T43	3		T134	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	407	1			T1	1		T34	1		T43	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	170	1			T43	3		T189	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	349	1			T1	1		T4	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	180	1			T4	1		T17	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	366	1			T4	1		T26	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	180	1			T34	1		T43	1		T44	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	382	1			T1	2		T4	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	175	1			T4	1		T26	1		T43	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	548	1			T1	2		T4	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	266	1			T43	2		T30	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	945	1			T5	1		T15	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	252	1			T2	1		T43	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	897	1			T1	1		T2	3		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	240	1			T19	1		T43	3		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	792	1			T15	1		T16	3		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	158	1			T16	1		T19	1		T43	5
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	316	1			T1	1		T4	2		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	259	1			T1	1		T16	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	490	1			T43	2		T47	1		T190	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	313	1			T2	2		T26	2		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	458	1			T1	1		T2	2		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	274	1			T16	1		T43	2		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	465	1			T4	1		T26	1		T43	1