Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31855

1

T1

39

T2

21

T3

21

auto[1]

282

1

T19

1

T113

8

T135

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31860	1			T1	39		T2	21		T3	21
auto[134217728:268435455]	7	1			T369	1		T370	1		T237	2
auto[268435456:402653183]	12	1			T113	1		T135	1		T77	1
auto[402653184:536870911]	9	1			T113	2		T82	1		T371	1
auto[536870912:671088639]	5	1			T260	1		T372	1		T271	2
auto[671088640:805306367]	13	1			T137	1		T315	1		T369	1
auto[805306368:939524095]	8	1			T113	1		T261	1		T260	2
auto[939524096:1073741823]	9	1			T113	2		T261	2		T260	1
auto[1073741824:1207959551]	7	1			T239	1		T260	2		T369	1
auto[1207959552:1342177279]	6	1			T19	1		T271	2		T294	1
auto[1342177280:1476395007]	12	1			T239	2		T137	1		T252	1
auto[1476395008:1610612735]	6	1			T239	1		T261	2		T315	1
auto[1610612736:1744830463]	10	1			T261	1		T260	2		T252	1
auto[1744830464:1879048191]	8	1			T137	1		T373	1		T343	1
auto[1879048192:2013265919]	12	1			T77	1		T239	1		T260	1
auto[2013265920:2147483647]	11	1			T77	1		T137	1		T371	1
auto[2147483648:2281701375]	9	1			T113	1		T261	1		T371	1
auto[2281701376:2415919103]	5	1			T239	1		T371	1		T223	1
auto[2415919104:2550136831]	5	1			T144	2		T343	1		T374	1
auto[2550136832:2684354559]	7	1			T260	1		T224	1		T237	1
auto[2684354560:2818572287]	7	1			T371	1		T372	1		T375	1
auto[2818572288:2952790015]	5	1			T77	1		T260	1		T223	1
auto[2952790016:3087007743]	15	1			T261	1		T371	1		T372	1
auto[3087007744:3221225471]	9	1			T77	1		T144	1		T234	1
auto[3221225472:3355443199]	13	1			T239	1		T260	1		T224	1
auto[3355443200:3489660927]	9	1			T239	1		T136	1		T223	1
auto[3489660928:3623878655]	5	1			T77	1		T315	1		T252	1
auto[3623878656:3758096383]	9	1			T77	1		T239	1		T234	1
auto[3758096384:3892314111]	12	1			T113	1		T144	1		T252	1
auto[3892314112:4026531839]	11	1			T135	1		T77	1		T82	1
auto[4026531840:4160749567]	11	1			T239	1		T259	1		T315	1
auto[4160749568:4294967295]	10	1			T239	1		T261	1		T252	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31855	1			T1	39		T2	21		T3	21
auto[0:134217727]	auto[1]	5	1			T137	2		T347	1		T376	1
auto[134217728:268435455]	auto[1]	7	1			T369	1		T370	1		T237	2
auto[268435456:402653183]	auto[1]	12	1			T113	1		T135	1		T77	1
auto[402653184:536870911]	auto[1]	9	1			T113	2		T82	1		T371	1
auto[536870912:671088639]	auto[1]	5	1			T260	1		T372	1		T271	2
auto[671088640:805306367]	auto[1]	13	1			T137	1		T315	1		T369	1
auto[805306368:939524095]	auto[1]	8	1			T113	1		T261	1		T260	2
auto[939524096:1073741823]	auto[1]	9	1			T113	2		T261	2		T260	1
auto[1073741824:1207959551]	auto[1]	7	1			T239	1		T260	2		T369	1
auto[1207959552:1342177279]	auto[1]	6	1			T19	1		T271	2		T294	1
auto[1342177280:1476395007]	auto[1]	12	1			T239	2		T137	1		T252	1
auto[1476395008:1610612735]	auto[1]	6	1			T239	1		T261	2		T315	1
auto[1610612736:1744830463]	auto[1]	10	1			T261	1		T260	2		T252	1
auto[1744830464:1879048191]	auto[1]	8	1			T137	1		T373	1		T343	1
auto[1879048192:2013265919]	auto[1]	12	1			T77	1		T239	1		T260	1
auto[2013265920:2147483647]	auto[1]	11	1			T77	1		T137	1		T371	1
auto[2147483648:2281701375]	auto[1]	9	1			T113	1		T261	1		T371	1
auto[2281701376:2415919103]	auto[1]	5	1			T239	1		T371	1		T223	1
auto[2415919104:2550136831]	auto[1]	5	1			T144	2		T343	1		T374	1
auto[2550136832:2684354559]	auto[1]	7	1			T260	1		T224	1		T237	1
auto[2684354560:2818572287]	auto[1]	7	1			T371	1		T372	1		T375	1
auto[2818572288:2952790015]	auto[1]	5	1			T77	1		T260	1		T223	1
auto[2952790016:3087007743]	auto[1]	15	1			T261	1		T371	1		T372	1
auto[3087007744:3221225471]	auto[1]	9	1			T77	1		T144	1		T234	1
auto[3221225472:3355443199]	auto[1]	13	1			T239	1		T260	1		T224	1
auto[3355443200:3489660927]	auto[1]	9	1			T239	1		T136	1		T223	1
auto[3489660928:3623878655]	auto[1]	5	1			T77	1		T315	1		T252	1
auto[3623878656:3758096383]	auto[1]	9	1			T77	1		T239	1		T234	1
auto[3758096384:3892314111]	auto[1]	12	1			T113	1		T144	1		T252	1
auto[3892314112:4026531839]	auto[1]	11	1			T135	1		T77	1		T82	1
auto[4026531840:4160749567]	auto[1]	11	1			T239	1		T259	1		T315	1
auto[4160749568:4294967295]	auto[1]	10	1			T239	1		T261	1		T252	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1521

1

T4

2

T15

5

T16

2

auto[1]

1659

1

T1

3

T4

2

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T35	1		T26	1		T44	2
auto[134217728:268435455]	97	1			T18	1		T189	1		T79	1
auto[268435456:402653183]	102	1			T18	1		T43	1		T47	1
auto[402653184:536870911]	88	1			T15	1		T43	1		T86	1
auto[536870912:671088639]	107	1			T42	1		T44	1		T128	1
auto[671088640:805306367]	109	1			T15	1		T34	1		T113	1
auto[805306368:939524095]	89	1			T1	1		T16	1		T18	1
auto[939524096:1073741823]	110	1			T1	1		T134	1		T42	1
auto[1073741824:1207959551]	95	1			T1	1		T30	1		T42	1
auto[1207959552:1342177279]	95	1			T4	1		T43	1		T189	1
auto[1342177280:1476395007]	82	1			T43	1		T44	1		T46	1
auto[1476395008:1610612735]	101	1			T18	1		T19	1		T35	1
auto[1610612736:1744830463]	97	1			T16	1		T44	2		T128	1
auto[1744830464:1879048191]	98	1			T43	2		T30	1		T42	1
auto[1879048192:2013265919]	103	1			T43	3		T189	1		T233	1
auto[2013265920:2147483647]	104	1			T18	1		T43	1		T134	1
auto[2147483648:2281701375]	103	1			T15	2		T19	1		T43	1
auto[2281701376:2415919103]	110	1			T19	1		T189	1		T44	1
auto[2415919104:2550136831]	97	1			T4	2		T16	2		T35	1
auto[2550136832:2684354559]	104	1			T35	1		T43	2		T189	1
auto[2684354560:2818572287]	105	1			T18	1		T34	1		T44	1
auto[2818572288:2952790015]	110	1			T43	1		T189	2		T44	1
auto[2952790016:3087007743]	87	1			T18	1		T35	1		T43	1
auto[3087007744:3221225471]	84	1			T35	2		T113	1		T45	1
auto[3221225472:3355443199]	93	1			T18	1		T19	1		T44	1
auto[3355443200:3489660927]	98	1			T42	1		T44	1		T113	1
auto[3489660928:3623878655]	95	1			T4	1		T15	2		T18	1
auto[3623878656:3758096383]	106	1			T43	1		T42	1		T127	1
auto[3758096384:3892314111]	108	1			T87	1		T233	1		T77	1
auto[3892314112:4026531839]	104	1			T16	1		T26	1		T43	1
auto[4026531840:4160749567]	98	1			T15	1		T35	1		T43	2
auto[4160749568:4294967295]	93	1			T47	1		T44	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	57	1			T44	1		T87	1		T233	1
auto[0:134217727]	auto[1]	51	1			T35	1		T26	1		T44	1
auto[134217728:268435455]	auto[0]	39	1			T18	1		T189	1		T79	1
auto[134217728:268435455]	auto[1]	58	1			T144	1		T60	1		T70	1
auto[268435456:402653183]	auto[0]	48	1			T18	1		T44	2		T128	1
auto[268435456:402653183]	auto[1]	54	1			T43	1		T47	1		T44	1
auto[402653184:536870911]	auto[0]	40	1			T15	1		T57	1		T53	1
auto[402653184:536870911]	auto[1]	48	1			T43	1		T86	1		T82	1
auto[536870912:671088639]	auto[0]	50	1			T44	1		T128	1		T135	1
auto[536870912:671088639]	auto[1]	57	1			T42	1		T45	1		T77	1
auto[671088640:805306367]	auto[0]	39	1			T15	1		T82	1		T60	1
auto[671088640:805306367]	auto[1]	70	1			T34	1		T113	1		T46	1
auto[805306368:939524095]	auto[0]	44	1			T16	1		T18	1		T135	1
auto[805306368:939524095]	auto[1]	45	1			T1	1		T47	1		T128	1
auto[939524096:1073741823]	auto[0]	60	1			T134	1		T233	1		T55	1
auto[939524096:1073741823]	auto[1]	50	1			T1	1		T42	1		T48	1
auto[1073741824:1207959551]	auto[0]	38	1			T30	1		T46	1		T144	1
auto[1073741824:1207959551]	auto[1]	57	1			T1	1		T42	1		T44	1
auto[1207959552:1342177279]	auto[0]	44	1			T42	1		T44	1		T45	1
auto[1207959552:1342177279]	auto[1]	51	1			T4	1		T43	1		T189	1
auto[1342177280:1476395007]	auto[0]	40	1			T43	1		T44	1		T46	1
auto[1342177280:1476395007]	auto[1]	42	1			T82	1		T192	1		T362	1
auto[1476395008:1610612735]	auto[0]	55	1			T18	1		T35	1		T46	1
auto[1476395008:1610612735]	auto[1]	46	1			T19	1		T36	1		T77	1
auto[1610612736:1744830463]	auto[0]	43	1			T44	1		T128	1		T56	1
auto[1610612736:1744830463]	auto[1]	54	1			T16	1		T44	1		T192	1
auto[1744830464:1879048191]	auto[0]	42	1			T43	1		T30	1		T36	1
auto[1744830464:1879048191]	auto[1]	56	1			T43	1		T42	1		T46	1
auto[1879048192:2013265919]	auto[0]	51	1			T43	1		T189	1		T80	1
auto[1879048192:2013265919]	auto[1]	52	1			T43	2		T233	1		T46	2
auto[2013265920:2147483647]	auto[0]	51	1			T134	1		T44	1		T113	1
auto[2013265920:2147483647]	auto[1]	53	1			T18	1		T43	1		T80	1
auto[2147483648:2281701375]	auto[0]	52	1			T15	1		T19	1		T44	1
auto[2147483648:2281701375]	auto[1]	51	1			T15	1		T43	1		T44	1
auto[2281701376:2415919103]	auto[0]	51	1			T44	1		T46	2		T81	1
auto[2281701376:2415919103]	auto[1]	59	1			T19	1		T189	1		T87	1
auto[2415919104:2550136831]	auto[0]	42	1			T4	2		T35	1		T189	1
auto[2415919104:2550136831]	auto[1]	55	1			T16	2		T46	2		T254	1
auto[2550136832:2684354559]	auto[0]	52	1			T35	1		T43	1		T189	1
auto[2550136832:2684354559]	auto[1]	52	1			T43	1		T135	1		T71	1
auto[2684354560:2818572287]	auto[0]	55	1			T18	1		T34	1		T128	1
auto[2684354560:2818572287]	auto[1]	50	1			T44	1		T27	1		T60	2
auto[2818572288:2952790015]	auto[0]	61	1			T44	1		T233	2		T45	1
auto[2818572288:2952790015]	auto[1]	49	1			T43	1		T189	2		T113	1
auto[2952790016:3087007743]	auto[0]	46	1			T18	1		T43	1		T42	1
auto[2952790016:3087007743]	auto[1]	41	1			T35	1		T189	1		T42	1
auto[3087007744:3221225471]	auto[0]	42	1			T35	1		T113	1		T45	1
auto[3087007744:3221225471]	auto[1]	42	1			T35	1		T46	1		T58	1
auto[3221225472:3355443199]	auto[0]	47	1			T44	1		T128	1		T87	1
auto[3221225472:3355443199]	auto[1]	46	1			T18	1		T19	1		T27	1
auto[3355443200:3489660927]	auto[0]	42	1			T44	1		T45	1		T79	1
auto[3355443200:3489660927]	auto[1]	56	1			T42	1		T113	1		T86	1
auto[3489660928:3623878655]	auto[0]	58	1			T15	1		T81	1		T55	1
auto[3489660928:3623878655]	auto[1]	37	1			T4	1		T15	1		T18	1
auto[3623878656:3758096383]	auto[0]	45	1			T127	1		T52	1		T248	1
auto[3623878656:3758096383]	auto[1]	61	1			T43	1		T42	1		T46	1
auto[3758096384:3892314111]	auto[0]	56	1			T87	1		T233	1		T80	1
auto[3758096384:3892314111]	auto[1]	52	1			T77	1		T53	1		T266	1
auto[3892314112:4026531839]	auto[0]	43	1			T16	1		T42	1		T46	1
auto[3892314112:4026531839]	auto[1]	61	1			T26	1		T43	1		T77	1
auto[4026531840:4160749567]	auto[0]	44	1			T15	1		T43	2		T52	1
auto[4026531840:4160749567]	auto[1]	54	1			T35	1		T46	2		T62	1
auto[4160749568:4294967295]	auto[0]	44	1			T44	1		T48	1		T52	1
auto[4160749568:4294967295]	auto[1]	49	1			T47	1		T46	1		T70	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1544

1

T4

2

T15

4

T16

1

auto[1]

1636

1

T1

3

T4

2

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T43	1		T87	1		T45	1
auto[134217728:268435455]	90	1			T16	1		T18	1		T36	1
auto[268435456:402653183]	106	1			T1	1		T233	1		T46	1
auto[402653184:536870911]	102	1			T4	1		T15	1		T43	1
auto[536870912:671088639]	92	1			T30	1		T189	1		T135	1
auto[671088640:805306367]	108	1			T4	1		T34	1		T43	1
auto[805306368:939524095]	91	1			T43	1		T189	1		T87	1
auto[939524096:1073741823]	112	1			T18	1		T19	1		T43	1
auto[1073741824:1207959551]	98	1			T16	1		T19	1		T43	1
auto[1207959552:1342177279]	102	1			T18	1		T43	2		T44	1
auto[1342177280:1476395007]	100	1			T1	1		T35	1		T43	1
auto[1476395008:1610612735]	103	1			T189	1		T44	2		T36	1
auto[1610612736:1744830463]	107	1			T43	1		T42	1		T44	1
auto[1744830464:1879048191]	95	1			T15	1		T35	1		T43	1
auto[1879048192:2013265919]	93	1			T19	1		T135	1		T46	2
auto[2013265920:2147483647]	98	1			T15	1		T43	1		T42	1
auto[2147483648:2281701375]	91	1			T16	1		T44	1		T113	1
auto[2281701376:2415919103]	95	1			T15	1		T43	1		T42	1
auto[2415919104:2550136831]	90	1			T26	1		T43	1		T134	1
auto[2550136832:2684354559]	90	1			T16	1		T35	1		T26	1
auto[2684354560:2818572287]	110	1			T15	1		T42	1		T44	1
auto[2818572288:2952790015]	101	1			T18	1		T189	1		T44	2
auto[2952790016:3087007743]	107	1			T15	1		T35	1		T42	1
auto[3087007744:3221225471]	104	1			T19	1		T43	3		T44	1
auto[3221225472:3355443199]	103	1			T15	1		T44	1		T113	1
auto[3355443200:3489660927]	94	1			T4	1		T35	1		T43	1
auto[3489660928:3623878655]	101	1			T18	1		T34	1		T43	1
auto[3623878656:3758096383]	88	1			T189	1		T42	1		T44	1
auto[3758096384:3892314111]	106	1			T1	1		T16	1		T18	2
auto[3892314112:4026531839]	96	1			T4	1		T18	1		T35	1
auto[4026531840:4160749567]	107	1			T35	2		T43	1		T30	1
auto[4160749568:4294967295]	106	1			T18	1		T42	1		T44	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	36	1			T43	1		T87	1		T45	1
auto[0:134217727]	auto[1]	58	1			T46	2		T79	1		T81	1
auto[134217728:268435455]	auto[0]	43	1			T18	1		T36	1		T46	1
auto[134217728:268435455]	auto[1]	47	1			T16	1		T55	1		T6	1
auto[268435456:402653183]	auto[0]	56	1			T46	1		T144	1		T70	1
auto[268435456:402653183]	auto[1]	50	1			T1	1		T233	1		T192	1
auto[402653184:536870911]	auto[0]	49	1			T43	1		T233	1		T46	2
auto[402653184:536870911]	auto[1]	53	1			T4	1		T15	1		T86	1
auto[536870912:671088639]	auto[0]	48	1			T30	1		T46	1		T66	1
auto[536870912:671088639]	auto[1]	44	1			T189	1		T135	1		T23	1
auto[671088640:805306367]	auto[0]	57	1			T4	1		T34	1		T43	1
auto[671088640:805306367]	auto[1]	51	1			T189	1		T44	1		T52	1
auto[805306368:939524095]	auto[0]	43	1			T43	1		T189	1		T79	1
auto[805306368:939524095]	auto[1]	48	1			T87	1		T45	1		T46	2
auto[939524096:1073741823]	auto[0]	56	1			T43	1		T42	1		T44	1
auto[939524096:1073741823]	auto[1]	56	1			T18	1		T19	1		T47	1
auto[1073741824:1207959551]	auto[0]	47	1			T46	2		T57	1		T88	1
auto[1073741824:1207959551]	auto[1]	51	1			T16	1		T19	1		T43	1
auto[1207959552:1342177279]	auto[0]	46	1			T18	1		T44	1		T82	1
auto[1207959552:1342177279]	auto[1]	56	1			T43	2		T46	1		T359	1
auto[1342177280:1476395007]	auto[0]	44	1			T43	1		T79	1		T23	1
auto[1342177280:1476395007]	auto[1]	56	1			T1	1		T35	1		T46	2
auto[1476395008:1610612735]	auto[0]	47	1			T189	1		T44	1		T81	1
auto[1476395008:1610612735]	auto[1]	56	1			T44	1		T36	1		T46	2
auto[1610612736:1744830463]	auto[0]	53	1			T44	1		T60	1		T227	1
auto[1610612736:1744830463]	auto[1]	54	1			T43	1		T42	1		T27	1
auto[1744830464:1879048191]	auto[0]	54	1			T15	1		T35	1		T44	1
auto[1744830464:1879048191]	auto[1]	41	1			T43	1		T47	1		T239	1
auto[1879048192:2013265919]	auto[0]	45	1			T135	1		T46	1		T53	1
auto[1879048192:2013265919]	auto[1]	48	1			T19	1		T46	1		T77	1
auto[2013265920:2147483647]	auto[0]	47	1			T15	1		T42	1		T44	1
auto[2013265920:2147483647]	auto[1]	51	1			T43	1		T44	1		T128	1
auto[2147483648:2281701375]	auto[0]	57	1			T16	1		T44	1		T113	1
auto[2147483648:2281701375]	auto[1]	34	1			T6	1		T254	1		T105	1
auto[2281701376:2415919103]	auto[0]	46	1			T48	1		T38	1		T53	1
auto[2281701376:2415919103]	auto[1]	49	1			T15	1		T43	1		T42	1
auto[2415919104:2550136831]	auto[0]	40	1			T26	1		T43	1		T134	1
auto[2415919104:2550136831]	auto[1]	50	1			T128	1		T87	1		T233	1
auto[2550136832:2684354559]	auto[0]	46	1			T134	1		T79	1		T262	1
auto[2550136832:2684354559]	auto[1]	44	1			T16	1		T35	1		T26	1
auto[2684354560:2818572287]	auto[0]	55	1			T48	1		T135	1		T52	1
auto[2684354560:2818572287]	auto[1]	55	1			T15	1		T42	1		T44	1
auto[2818572288:2952790015]	auto[0]	44	1			T44	2		T79	1		T39	1
auto[2818572288:2952790015]	auto[1]	57	1			T18	1		T189	1		T20	1
auto[2952790016:3087007743]	auto[0]	49	1			T15	1		T35	1		T23	1
auto[2952790016:3087007743]	auto[1]	58	1			T42	1		T27	1		T45	1
auto[3087007744:3221225471]	auto[0]	57	1			T82	1		T243	1		T85	1
auto[3087007744:3221225471]	auto[1]	47	1			T19	1		T43	3		T44	1
auto[3221225472:3355443199]	auto[0]	47	1			T15	1		T113	1		T87	1
auto[3221225472:3355443199]	auto[1]	56	1			T44	1		T27	1		T86	1
auto[3355443200:3489660927]	auto[0]	53	1			T4	1		T35	1		T189	1
auto[3355443200:3489660927]	auto[1]	41	1			T43	1		T144	1		T62	1
auto[3489660928:3623878655]	auto[0]	55	1			T18	1		T34	1		T43	1
auto[3489660928:3623878655]	auto[1]	46	1			T46	2		T70	1		T53	1
auto[3623878656:3758096383]	auto[0]	37	1			T44	1		T128	1		T67	1
auto[3623878656:3758096383]	auto[1]	51	1			T189	1		T42	1		T46	1
auto[3758096384:3892314111]	auto[0]	44	1			T18	2		T189	1		T127	1
auto[3758096384:3892314111]	auto[1]	62	1			T1	1		T16	1		T113	1
auto[3892314112:4026531839]	auto[0]	41	1			T18	1		T35	1		T51	1
auto[3892314112:4026531839]	auto[1]	55	1			T4	1		T47	1		T42	1
auto[4026531840:4160749567]	auto[0]	53	1			T35	1		T43	1		T30	1
auto[4026531840:4160749567]	auto[1]	54	1			T35	1		T189	1		T46	1
auto[4160749568:4294967295]	auto[0]	49	1			T42	1		T44	1		T52	1
auto[4160749568:4294967295]	auto[1]	57	1			T18	1		T86	1		T144	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1510

1

T4

3

T15

5

T16

2

auto[1]

1670

1

T1

3

T4

1

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T19	1		T134	1		T44	2
auto[134217728:268435455]	86	1			T44	1		T52	1		T46	1
auto[268435456:402653183]	88	1			T26	1		T47	1		T44	1
auto[402653184:536870911]	87	1			T1	1		T43	1		T128	1
auto[536870912:671088639]	101	1			T16	1		T44	1		T128	1
auto[671088640:805306367]	103	1			T16	1		T18	1		T19	1
auto[805306368:939524095]	97	1			T43	1		T42	1		T87	1
auto[939524096:1073741823]	96	1			T4	1		T43	1		T42	1
auto[1073741824:1207959551]	100	1			T16	1		T19	1		T43	1
auto[1207959552:1342177279]	110	1			T128	1		T113	1		T46	2
auto[1342177280:1476395007]	101	1			T43	2		T42	1		T44	2
auto[1476395008:1610612735]	104	1			T16	2		T18	2		T189	3
auto[1610612736:1744830463]	96	1			T43	1		T189	1		T44	1
auto[1744830464:1879048191]	106	1			T30	1		T44	1		T56	1
auto[1879048192:2013265919]	91	1			T42	1		T44	2		T27	1
auto[2013265920:2147483647]	86	1			T15	1		T35	1		T47	1
auto[2147483648:2281701375]	107	1			T1	1		T18	1		T34	1
auto[2281701376:2415919103]	106	1			T4	1		T15	1		T43	1
auto[2415919104:2550136831]	108	1			T35	1		T26	1		T43	1
auto[2550136832:2684354559]	99	1			T1	1		T15	1		T18	1
auto[2684354560:2818572287]	88	1			T35	1		T44	1		T48	1
auto[2818572288:2952790015]	85	1			T35	1		T43	1		T189	1
auto[2952790016:3087007743]	111	1			T15	1		T43	1		T30	1
auto[3087007744:3221225471]	116	1			T4	1		T18	1		T35	1
auto[3221225472:3355443199]	90	1			T34	1		T43	1		T44	1
auto[3355443200:3489660927]	89	1			T18	1		T43	1		T135	1
auto[3489660928:3623878655]	114	1			T15	1		T19	1		T35	2
auto[3623878656:3758096383]	90	1			T43	3		T44	1		T135	1
auto[3758096384:3892314111]	117	1			T4	1		T35	1		T43	1
auto[3892314112:4026531839]	117	1			T18	2		T42	1		T27	1
auto[4026531840:4160749567]	94	1			T15	1		T43	1		T44	1
auto[4160749568:4294967295]	90	1			T15	1		T43	1		T189	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	57	1			T134	1		T44	2		T135	1
auto[0:134217727]	auto[1]	50	1			T19	1		T113	1		T52	1
auto[134217728:268435455]	auto[0]	36	1			T44	1		T52	1		T144	1
auto[134217728:268435455]	auto[1]	50	1			T46	1		T53	1		T67	4
auto[268435456:402653183]	auto[0]	46	1			T44	1		T113	1		T88	1
auto[268435456:402653183]	auto[1]	42	1			T26	1		T47	1		T46	1
auto[402653184:536870911]	auto[0]	43	1			T60	1		T6	2		T67	1
auto[402653184:536870911]	auto[1]	44	1			T1	1		T43	1		T128	1
auto[536870912:671088639]	auto[0]	50	1			T16	1		T44	1		T128	1
auto[536870912:671088639]	auto[1]	51	1			T27	1		T60	1		T62	1
auto[671088640:805306367]	auto[0]	55	1			T18	1		T36	1		T46	1
auto[671088640:805306367]	auto[1]	48	1			T16	1		T19	1		T48	1
auto[805306368:939524095]	auto[0]	46	1			T243	1		T53	2		T6	1
auto[805306368:939524095]	auto[1]	51	1			T43	1		T42	1		T87	1
auto[939524096:1073741823]	auto[0]	40	1			T4	1		T43	1		T42	1
auto[939524096:1073741823]	auto[1]	56	1			T36	1		T46	4		T55	1
auto[1073741824:1207959551]	auto[0]	53	1			T16	1		T44	1		T45	1
auto[1073741824:1207959551]	auto[1]	47	1			T19	1		T43	1		T42	1
auto[1207959552:1342177279]	auto[0]	50	1			T128	1		T57	1		T60	1
auto[1207959552:1342177279]	auto[1]	60	1			T113	1		T46	2		T60	1
auto[1342177280:1476395007]	auto[0]	44	1			T44	2		T87	1		T46	1
auto[1342177280:1476395007]	auto[1]	57	1			T43	2		T42	1		T46	2
auto[1476395008:1610612735]	auto[0]	54	1			T18	2		T53	1		T85	1
auto[1476395008:1610612735]	auto[1]	50	1			T16	2		T189	3		T42	1
auto[1610612736:1744830463]	auto[0]	47	1			T43	1		T44	1		T233	1
auto[1610612736:1744830463]	auto[1]	49	1			T189	1		T144	1		T192	1
auto[1744830464:1879048191]	auto[0]	56	1			T30	1		T56	1		T359	1
auto[1744830464:1879048191]	auto[1]	50	1			T44	1		T58	1		T248	1
auto[1879048192:2013265919]	auto[0]	43	1			T44	1		T81	1		T60	1
auto[1879048192:2013265919]	auto[1]	48	1			T42	1		T44	1		T27	1
auto[2013265920:2147483647]	auto[0]	48	1			T35	1		T189	1		T81	1
auto[2013265920:2147483647]	auto[1]	38	1			T15	1		T47	1		T42	1
auto[2147483648:2281701375]	auto[0]	60	1			T34	1		T134	1		T44	1
auto[2147483648:2281701375]	auto[1]	47	1			T1	1		T18	1		T43	1
auto[2281701376:2415919103]	auto[0]	50	1			T4	1		T189	1		T45	1
auto[2281701376:2415919103]	auto[1]	56	1			T15	1		T43	1		T46	1
auto[2415919104:2550136831]	auto[0]	49	1			T35	1		T26	1		T87	2
auto[2415919104:2550136831]	auto[1]	59	1			T43	1		T42	1		T135	1
auto[2550136832:2684354559]	auto[0]	42	1			T15	1		T18	1		T52	1
auto[2550136832:2684354559]	auto[1]	57	1			T1	1		T44	1		T82	1
auto[2684354560:2818572287]	auto[0]	42	1			T48	1		T233	1		T79	1
auto[2684354560:2818572287]	auto[1]	46	1			T35	1		T44	1		T62	1
auto[2818572288:2952790015]	auto[0]	32	1			T189	1		T46	1		T53	1
auto[2818572288:2952790015]	auto[1]	53	1			T35	1		T43	1		T27	1
auto[2952790016:3087007743]	auto[0]	51	1			T15	1		T43	1		T30	1
auto[2952790016:3087007743]	auto[1]	60	1			T86	1		T233	1		T77	2
auto[3087007744:3221225471]	auto[0]	48	1			T18	1		T35	1		T6	2
auto[3087007744:3221225471]	auto[1]	68	1			T4	1		T135	1		T233	1
auto[3221225472:3355443199]	auto[0]	34	1			T34	1		T43	1		T233	1
auto[3221225472:3355443199]	auto[1]	56	1			T44	1		T127	1		T128	1
auto[3355443200:3489660927]	auto[0]	48	1			T18	1		T43	1		T135	1
auto[3355443200:3489660927]	auto[1]	41	1			T46	1		T60	2		T229	1
auto[3489660928:3623878655]	auto[0]	52	1			T15	1		T35	1		T128	1
auto[3489660928:3623878655]	auto[1]	62	1			T19	1		T35	1		T47	1
auto[3623878656:3758096383]	auto[0]	39	1			T43	2		T135	1		T52	1
auto[3623878656:3758096383]	auto[1]	51	1			T43	1		T44	1		T38	1
auto[3758096384:3892314111]	auto[0]	60	1			T4	1		T189	1		T44	1
auto[3758096384:3892314111]	auto[1]	57	1			T35	1		T43	1		T79	1
auto[3892314112:4026531839]	auto[0]	51	1			T18	2		T46	1		T51	1
auto[3892314112:4026531839]	auto[1]	66	1			T42	1		T27	1		T192	1
auto[4026531840:4160749567]	auto[0]	44	1			T15	1		T44	1		T45	1
auto[4026531840:4160749567]	auto[1]	50	1			T43	1		T86	1		T46	2
auto[4160749568:4294967295]	auto[0]	40	1			T15	1		T233	1		T45	1
auto[4160749568:4294967295]	auto[1]	50	1			T43	1		T189	1		T46	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1541

1

T1

1

T4

2

T15

5

auto[1]

1639

1

T1

2

T4

2

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T4	1		T18	1		T19	1
auto[134217728:268435455]	97	1			T18	1		T42	1		T113	1
auto[268435456:402653183]	86	1			T27	1		T81	1		T82	1
auto[402653184:536870911]	96	1			T15	2		T47	1		T189	1
auto[536870912:671088639]	88	1			T34	1		T43	2		T44	1
auto[671088640:805306367]	93	1			T134	1		T189	1		T44	2
auto[805306368:939524095]	95	1			T189	1		T42	1		T44	1
auto[939524096:1073741823]	107	1			T1	1		T35	1		T113	1
auto[1073741824:1207959551]	109	1			T43	2		T44	1		T135	1
auto[1207959552:1342177279]	96	1			T19	1		T42	1		T44	1
auto[1342177280:1476395007]	103	1			T18	1		T44	1		T113	2
auto[1476395008:1610612735]	111	1			T1	1		T16	1		T47	1
auto[1610612736:1744830463]	96	1			T1	1		T189	1		T42	1
auto[1744830464:1879048191]	110	1			T43	1		T44	1		T77	1
auto[1879048192:2013265919]	87	1			T18	2		T34	1		T35	1
auto[2013265920:2147483647]	110	1			T35	1		T43	2		T44	1
auto[2147483648:2281701375]	104	1			T18	1		T35	1		T43	1
auto[2281701376:2415919103]	97	1			T86	1		T87	1		T46	1
auto[2415919104:2550136831]	109	1			T18	1		T19	1		T35	1
auto[2550136832:2684354559]	98	1			T35	1		T30	2		T44	1
auto[2684354560:2818572287]	120	1			T43	1		T47	1		T128	1
auto[2818572288:2952790015]	99	1			T19	1		T43	1		T233	1
auto[2952790016:3087007743]	91	1			T15	2		T80	1		T60	1
auto[3087007744:3221225471]	96	1			T16	1		T189	1		T44	2
auto[3221225472:3355443199]	96	1			T4	1		T16	1		T35	1
auto[3355443200:3489660927]	88	1			T16	2		T26	1		T43	1
auto[3489660928:3623878655]	98	1			T189	1		T42	1		T45	1
auto[3623878656:3758096383]	90	1			T43	3		T128	1		T86	1
auto[3758096384:3892314111]	105	1			T15	2		T128	1		T36	1
auto[3892314112:4026531839]	103	1			T4	1		T15	1		T18	1
auto[4026531840:4160749567]	105	1			T18	1		T44	1		T46	2
auto[4160749568:4294967295]	101	1			T4	1		T189	1		T48	1