Unified Coverage Report :: Group Instance : salt_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2746

1

T1

3

T4

4

T15

7

auto[1]

286

1

T19

8

T113

7

T77

14

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T35	1		T44	2		T128	2
auto[134217728:268435455]	99	1			T15	1		T16	1		T44	1
auto[268435456:402653183]	91	1			T44	1		T36	1		T52	1
auto[402653184:536870911]	93	1			T43	2		T189	1		T128	1
auto[536870912:671088639]	115	1			T15	1		T16	1		T19	1
auto[671088640:805306367]	100	1			T18	1		T43	1		T189	1
auto[805306368:939524095]	107	1			T15	1		T18	1		T19	2
auto[939524096:1073741823]	108	1			T1	1		T43	1		T47	1
auto[1073741824:1207959551]	102	1			T18	1		T19	2		T43	1
auto[1207959552:1342177279]	98	1			T35	1		T47	1		T134	1
auto[1342177280:1476395007]	103	1			T4	1		T15	1		T18	2
auto[1476395008:1610612735]	84	1			T113	1		T46	2		T77	1
auto[1610612736:1744830463]	95	1			T46	1		T57	1		T70	1
auto[1744830464:1879048191]	103	1			T15	1		T42	2		T128	1
auto[1879048192:2013265919]	93	1			T18	2		T35	1		T43	1
auto[2013265920:2147483647]	89	1			T16	1		T19	3		T26	1
auto[2147483648:2281701375]	79	1			T189	1		T44	1		T48	1
auto[2281701376:2415919103]	79	1			T1	1		T4	1		T18	1
auto[2415919104:2550136831]	90	1			T4	1		T35	2		T47	1
auto[2550136832:2684354559]	95	1			T4	1		T19	1		T43	1
auto[2684354560:2818572287]	78	1			T1	1		T42	3		T128	1
auto[2818572288:2952790015]	105	1			T15	1		T19	1		T113	1
auto[2952790016:3087007743]	96	1			T43	2		T42	2		T113	3
auto[3087007744:3221225471]	105	1			T15	1		T42	1		T48	1
auto[3221225472:3355443199]	103	1			T35	1		T43	1		T189	1
auto[3355443200:3489660927]	91	1			T46	1		T81	1		T60	1
auto[3489660928:3623878655]	86	1			T26	1		T189	2		T135	1
auto[3623878656:3758096383]	74	1			T43	2		T113	1		T135	1
auto[3758096384:3892314111]	96	1			T19	2		T43	1		T128	1
auto[3892314112:4026531839]	97	1			T127	1		T48	1		T52	1
auto[4026531840:4160749567]	87	1			T16	2		T18	1		T43	1
auto[4160749568:4294967295]	87	1			T35	1		T30	1		T44	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	93	1			T35	1		T44	2		T128	2
auto[0:134217727]	auto[1]	11	1			T77	1		T347	1		T371	1
auto[134217728:268435455]	auto[0]	85	1			T15	1		T16	1		T44	1
auto[134217728:268435455]	auto[1]	14	1			T239	2		T260	1		T384	1
auto[268435456:402653183]	auto[0]	76	1			T44	1		T36	1		T52	1
auto[268435456:402653183]	auto[1]	15	1			T77	2		T239	1		T234	1
auto[402653184:536870911]	auto[0]	87	1			T43	2		T189	1		T128	1
auto[402653184:536870911]	auto[1]	6	1			T315	1		T224	1		T370	1
auto[536870912:671088639]	auto[0]	104	1			T15	1		T16	1		T35	1
auto[536870912:671088639]	auto[1]	11	1			T19	1		T113	1		T315	1
auto[671088640:805306367]	auto[0]	85	1			T18	1		T43	1		T189	1
auto[671088640:805306367]	auto[1]	15	1			T113	1		T239	3		T137	1
auto[805306368:939524095]	auto[0]	95	1			T15	1		T18	1		T19	2
auto[805306368:939524095]	auto[1]	12	1			T77	3		T223	1		T224	1
auto[939524096:1073741823]	auto[0]	98	1			T1	1		T43	1		T47	1
auto[939524096:1073741823]	auto[1]	10	1			T113	2		T77	1		T371	1
auto[1073741824:1207959551]	auto[0]	92	1			T18	1		T43	1		T87	1
auto[1073741824:1207959551]	auto[1]	10	1			T19	2		T239	1		T137	1
auto[1207959552:1342177279]	auto[0]	92	1			T35	1		T47	1		T134	1
auto[1207959552:1342177279]	auto[1]	6	1			T315	1		T271	1		T330	1
auto[1342177280:1476395007]	auto[0]	100	1			T4	1		T15	1		T18	2
auto[1342177280:1476395007]	auto[1]	3	1			T371	1		T235	2		-	-
auto[1476395008:1610612735]	auto[0]	77	1			T46	2		T248	1		T70	1
auto[1476395008:1610612735]	auto[1]	7	1			T113	1		T77	1		T239	1
auto[1610612736:1744830463]	auto[0]	87	1			T46	1		T57	1		T70	1
auto[1610612736:1744830463]	auto[1]	8	1			T260	1		T237	2		T373	1
auto[1744830464:1879048191]	auto[0]	94	1			T15	1		T42	2		T128	1
auto[1744830464:1879048191]	auto[1]	9	1			T137	2		T260	1		T369	1
auto[1879048192:2013265919]	auto[0]	83	1			T18	2		T35	1		T43	1
auto[1879048192:2013265919]	auto[1]	10	1			T77	1		T137	1		T260	1
auto[2013265920:2147483647]	auto[0]	81	1			T16	1		T19	1		T26	1
auto[2013265920:2147483647]	auto[1]	8	1			T19	2		T234	1		T260	1
auto[2147483648:2281701375]	auto[0]	75	1			T189	1		T44	1		T48	1
auto[2147483648:2281701375]	auto[1]	4	1			T259	1		T224	1		T388	1
auto[2281701376:2415919103]	auto[0]	73	1			T1	1		T4	1		T18	1
auto[2281701376:2415919103]	auto[1]	6	1			T371	1		T260	1		T223	1
auto[2415919104:2550136831]	auto[0]	82	1			T4	1		T35	2		T47	1
auto[2415919104:2550136831]	auto[1]	8	1			T77	1		T261	1		T237	1
auto[2550136832:2684354559]	auto[0]	84	1			T4	1		T43	1		T113	1
auto[2550136832:2684354559]	auto[1]	11	1			T19	1		T144	1		T137	1
auto[2684354560:2818572287]	auto[0]	73	1			T1	1		T42	3		T128	1
auto[2684354560:2818572287]	auto[1]	5	1			T77	1		T144	1		T137	1
auto[2818572288:2952790015]	auto[0]	89	1			T15	1		T113	1		T79	1
auto[2818572288:2952790015]	auto[1]	16	1			T19	1		T239	1		T137	1
auto[2952790016:3087007743]	auto[0]	86	1			T43	2		T42	2		T113	2
auto[2952790016:3087007743]	auto[1]	10	1			T113	1		T260	2		T224	1
auto[3087007744:3221225471]	auto[0]	94	1			T15	1		T42	1		T48	1
auto[3087007744:3221225471]	auto[1]	11	1			T77	1		T137	1		T234	1
auto[3221225472:3355443199]	auto[0]	99	1			T35	1		T43	1		T189	1
auto[3221225472:3355443199]	auto[1]	4	1			T371	1		T286	1		T376	1
auto[3355443200:3489660927]	auto[0]	84	1			T46	1		T81	1		T60	1
auto[3355443200:3489660927]	auto[1]	7	1			T261	1		T260	1		T382	1
auto[3489660928:3623878655]	auto[0]	76	1			T26	1		T189	2		T135	1
auto[3489660928:3623878655]	auto[1]	10	1			T260	1		T369	1		T271	1
auto[3623878656:3758096383]	auto[0]	66	1			T43	2		T135	1		T233	1
auto[3623878656:3758096383]	auto[1]	8	1			T113	1		T239	1		T271	1
auto[3758096384:3892314111]	auto[0]	89	1			T19	1		T43	1		T128	1
auto[3758096384:3892314111]	auto[1]	7	1			T19	1		T82	1		T239	1
auto[3892314112:4026531839]	auto[0]	88	1			T127	1		T48	1		T52	1
auto[3892314112:4026531839]	auto[1]	9	1			T77	1		T347	1		T286	1
auto[4026531840:4160749567]	auto[0]	80	1			T16	2		T18	1		T43	1
auto[4026531840:4160749567]	auto[1]	7	1			T239	1		T223	2		T372	2
auto[4160749568:4294967295]	auto[0]	79	1			T35	1		T30	1		T44	1
auto[4160749568:4294967295]	auto[1]	8	1			T77	1		T239	1		T371	1