Unified Coverage Report :: Group Instance : sealing_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1511

1

T4

3

T15

4

T16

2

auto[1]

1669

1

T1

3

T4

1

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T42	2		T128	1		T48	1
auto[134217728:268435455]	107	1			T4	1		T18	1		T189	1
auto[268435456:402653183]	114	1			T19	1		T189	1		T44	1
auto[402653184:536870911]	110	1			T16	1		T35	1		T43	2
auto[536870912:671088639]	102	1			T35	1		T127	1		T27	1
auto[671088640:805306367]	102	1			T18	1		T43	1		T42	1
auto[805306368:939524095]	90	1			T1	1		T16	1		T19	1
auto[939524096:1073741823]	112	1			T43	1		T42	1		T44	1
auto[1073741824:1207959551]	102	1			T35	1		T42	1		T233	1
auto[1207959552:1342177279]	104	1			T34	1		T35	1		T47	1
auto[1342177280:1476395007]	94	1			T35	1		T43	3		T189	2
auto[1476395008:1610612735]	97	1			T1	1		T16	1		T35	1
auto[1610612736:1744830463]	93	1			T43	1		T134	1		T46	1
auto[1744830464:1879048191]	103	1			T113	1		T87	1		T233	1
auto[1879048192:2013265919]	95	1			T44	1		T36	1		T45	1
auto[2013265920:2147483647]	99	1			T15	1		T18	1		T189	1
auto[2147483648:2281701375]	99	1			T1	1		T18	1		T189	1
auto[2281701376:2415919103]	95	1			T43	1		T135	1		T87	2
auto[2415919104:2550136831]	87	1			T4	1		T18	1		T34	1
auto[2550136832:2684354559]	99	1			T18	1		T43	1		T42	1
auto[2684354560:2818572287]	107	1			T43	1		T44	1		T45	1
auto[2818572288:2952790015]	101	1			T15	1		T35	2		T43	1
auto[2952790016:3087007743]	105	1			T42	1		T128	1		T86	1
auto[3087007744:3221225471]	95	1			T26	1		T48	1		T46	1
auto[3221225472:3355443199]	86	1			T15	2		T18	1		T43	2
auto[3355443200:3489660927]	98	1			T18	1		T189	1		T44	2
auto[3489660928:3623878655]	103	1			T15	2		T16	1		T44	1
auto[3623878656:3758096383]	84	1			T18	1		T26	1		T43	1
auto[3758096384:3892314111]	100	1			T42	1		T44	1		T36	1
auto[3892314112:4026531839]	91	1			T47	2		T189	1		T52	1
auto[4026531840:4160749567]	97	1			T16	1		T19	1		T30	1
auto[4160749568:4294967295]	114	1			T4	2		T15	1		T19	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T42	1		T48	1		T46	1
auto[0:134217727]	auto[1]	47	1			T42	1		T128	1		T46	1
auto[134217728:268435455]	auto[0]	46	1			T4	1		T18	1		T189	1
auto[134217728:268435455]	auto[1]	61	1			T42	1		T57	1		T6	1
auto[268435456:402653183]	auto[0]	62	1			T189	1		T46	1		T57	1
auto[268435456:402653183]	auto[1]	52	1			T19	1		T44	1		T113	1
auto[402653184:536870911]	auto[0]	52	1			T30	1		T45	1		T79	1
auto[402653184:536870911]	auto[1]	58	1			T16	1		T35	1		T43	2
auto[536870912:671088639]	auto[0]	56	1			T127	1		T57	1		T60	1
auto[536870912:671088639]	auto[1]	46	1			T35	1		T27	1		T46	1
auto[671088640:805306367]	auto[0]	40	1			T44	1		T46	1		T56	1
auto[671088640:805306367]	auto[1]	62	1			T18	1		T43	1		T42	1
auto[805306368:939524095]	auto[0]	39	1			T16	1		T43	1		T144	2
auto[805306368:939524095]	auto[1]	51	1			T1	1		T19	1		T43	1
auto[939524096:1073741823]	auto[0]	52	1			T44	1		T46	1		T23	1
auto[939524096:1073741823]	auto[1]	60	1			T43	1		T42	1		T27	1
auto[1073741824:1207959551]	auto[0]	46	1			T35	1		T42	1		T233	1
auto[1073741824:1207959551]	auto[1]	56	1			T82	1		T58	1		T248	1
auto[1207959552:1342177279]	auto[0]	44	1			T34	1		T135	1		T52	1
auto[1207959552:1342177279]	auto[1]	60	1			T35	1		T47	1		T113	1
auto[1342177280:1476395007]	auto[0]	44	1			T43	2		T44	1		T46	2
auto[1342177280:1476395007]	auto[1]	50	1			T35	1		T43	1		T189	2
auto[1476395008:1610612735]	auto[0]	42	1			T35	1		T113	1		T264	1
auto[1476395008:1610612735]	auto[1]	55	1			T1	1		T16	1		T42	1
auto[1610612736:1744830463]	auto[0]	41	1			T134	1		T46	1		T71	1
auto[1610612736:1744830463]	auto[1]	52	1			T43	1		T60	2		T53	1
auto[1744830464:1879048191]	auto[0]	51	1			T233	1		T82	1		T248	1
auto[1744830464:1879048191]	auto[1]	52	1			T113	1		T87	1		T192	1
auto[1879048192:2013265919]	auto[0]	43	1			T44	1		T62	1		T6	2
auto[1879048192:2013265919]	auto[1]	52	1			T36	1		T45	1		T77	1
auto[2013265920:2147483647]	auto[0]	50	1			T15	1		T18	1		T46	1
auto[2013265920:2147483647]	auto[1]	49	1			T189	1		T46	2		T144	1
auto[2147483648:2281701375]	auto[0]	40	1			T18	1		T128	1		T48	1
auto[2147483648:2281701375]	auto[1]	59	1			T1	1		T189	1		T45	1
auto[2281701376:2415919103]	auto[0]	33	1			T87	2		T57	1		T53	1
auto[2281701376:2415919103]	auto[1]	62	1			T43	1		T135	1		T46	2
auto[2415919104:2550136831]	auto[0]	48	1			T4	1		T44	1		T52	1
auto[2415919104:2550136831]	auto[1]	39	1			T18	1		T34	1		T189	1
auto[2550136832:2684354559]	auto[0]	47	1			T266	1		T6	3		T67	1
auto[2550136832:2684354559]	auto[1]	52	1			T18	1		T43	1		T42	1
auto[2684354560:2818572287]	auto[0]	47	1			T43	1		T44	1		T45	1
auto[2684354560:2818572287]	auto[1]	60	1			T37	1		T82	1		T273	2
auto[2818572288:2952790015]	auto[0]	52	1			T15	1		T35	2		T135	1
auto[2818572288:2952790015]	auto[1]	49	1			T43	1		T46	1		T58	1
auto[2952790016:3087007743]	auto[0]	52	1			T128	1		T81	1		T53	1
auto[2952790016:3087007743]	auto[1]	53	1			T42	1		T86	1		T46	1
auto[3087007744:3221225471]	auto[0]	45	1			T81	1		T53	1		T67	1
auto[3087007744:3221225471]	auto[1]	50	1			T26	1		T48	1		T46	1
auto[3221225472:3355443199]	auto[0]	38	1			T15	1		T18	1		T43	1
auto[3221225472:3355443199]	auto[1]	48	1			T15	1		T43	1		T44	1
auto[3355443200:3489660927]	auto[0]	53	1			T18	1		T189	1		T44	2
auto[3355443200:3489660927]	auto[1]	45	1			T86	1		T66	1		T58	1
auto[3489660928:3623878655]	auto[0]	57	1			T15	1		T16	1		T44	1
auto[3489660928:3623878655]	auto[1]	46	1			T15	1		T58	1		T67	1
auto[3623878656:3758096383]	auto[0]	38	1			T18	1		T233	1		T81	1
auto[3623878656:3758096383]	auto[1]	46	1			T26	1		T43	1		T44	1
auto[3758096384:3892314111]	auto[0]	52	1			T44	1		T36	1		T52	1
auto[3758096384:3892314111]	auto[1]	48	1			T42	1		T46	2		T239	1
auto[3892314112:4026531839]	auto[0]	49	1			T189	1		T52	1		T82	1
auto[3892314112:4026531839]	auto[1]	42	1			T47	2		T46	1		T55	1
auto[4026531840:4160749567]	auto[0]	51	1			T30	1		T44	2		T87	1
auto[4026531840:4160749567]	auto[1]	46	1			T16	1		T19	1		T135	1
auto[4160749568:4294967295]	auto[0]	53	1			T4	1		T43	1		T44	2
auto[4160749568:4294967295]	auto[1]	61	1			T4	1		T15	1		T19	1