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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6434 1 T1 13 T4 15 T15 19
auto[1] 253 1 T19 2 T113 2 T77 4


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 2701 1 T1 6 T4 6 T15 9
auto[134217728:268435455] 159 1 T16 1 T18 1 T26 2
auto[268435456:402653183] 149 1 T1 1 T19 1 T189 2
auto[402653184:536870911] 132 1 T15 1 T43 1 T44 1
auto[536870912:671088639] 142 1 T4 2 T15 2 T35 1
auto[671088640:805306367] 124 1 T1 2 T4 1 T48 1
auto[805306368:939524095] 121 1 T42 2 T36 1 T135 1
auto[939524096:1073741823] 136 1 T15 1 T18 1 T35 1
auto[1073741824:1207959551] 116 1 T1 1 T34 1 T127 1
auto[1207959552:1342177279] 139 1 T4 1 T15 1 T19 1
auto[1342177280:1476395007] 111 1 T15 1 T47 1 T44 1
auto[1476395008:1610612735] 133 1 T4 1 T16 1 T18 1
auto[1610612736:1744830463] 143 1 T1 1 T16 1 T18 1
auto[1744830464:1879048191] 114 1 T15 1 T26 1 T189 1
auto[1879048192:2013265919] 143 1 T35 1 T43 2 T189 1
auto[2013265920:2147483647] 137 1 T15 1 T18 1 T19 1
auto[2147483648:2281701375] 139 1 T1 1 T18 1 T35 1
auto[2281701376:2415919103] 142 1 T35 1 T43 2 T87 1
auto[2415919104:2550136831] 119 1 T19 1 T35 1 T44 2
auto[2550136832:2684354559] 120 1 T4 1 T15 1 T18 1
auto[2684354560:2818572287] 132 1 T18 1 T35 2 T43 1
auto[2818572288:2952790015] 125 1 T35 1 T43 2 T135 1
auto[2952790016:3087007743] 108 1 T4 1 T16 1 T43 1
auto[3087007744:3221225471] 119 1 T19 1 T43 3 T86 2
auto[3221225472:3355443199] 142 1 T4 1 T16 1 T43 2
auto[3355443200:3489660927] 98 1 T15 1 T26 1 T45 1
auto[3489660928:3623878655] 124 1 T18 1 T26 1 T128 1
auto[3623878656:3758096383] 106 1 T1 1 T4 1 T35 1
auto[3758096384:3892314111] 122 1 T189 1 T42 1 T86 2
auto[3892314112:4026531839] 119 1 T18 1 T128 1 T48 1
auto[4026531840:4160749567] 136 1 T26 1 T43 2 T134 1
auto[4160749568:4294967295] 136 1 T16 1 T19 1 T43 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 2697 1 T1 6 T4 6 T15 9
auto[0:134217727] auto[1] 4 1 T260 1 T377 1 T235 1
auto[134217728:268435455] auto[0] 150 1 T16 1 T18 1 T26 2
auto[134217728:268435455] auto[1] 9 1 T137 2 T315 1 T260 1
auto[268435456:402653183] auto[0] 143 1 T1 1 T19 1 T189 2
auto[268435456:402653183] auto[1] 6 1 T252 1 T271 1 T373 1
auto[402653184:536870911] auto[0] 124 1 T15 1 T43 1 T44 1
auto[402653184:536870911] auto[1] 8 1 T239 1 T315 1 T223 1
auto[536870912:671088639] auto[0] 139 1 T4 2 T15 2 T35 1
auto[536870912:671088639] auto[1] 3 1 T223 1 T378 1 T379 1
auto[671088640:805306367] auto[0] 117 1 T1 2 T4 1 T48 1
auto[671088640:805306367] auto[1] 7 1 T372 1 T380 1 T370 1
auto[805306368:939524095] auto[0] 109 1 T42 2 T36 1 T135 1
auto[805306368:939524095] auto[1] 12 1 T239 1 T252 1 T271 1
auto[939524096:1073741823] auto[0] 126 1 T15 1 T18 1 T35 1
auto[939524096:1073741823] auto[1] 10 1 T77 1 T261 1 T315 1
auto[1073741824:1207959551] auto[0] 111 1 T1 1 T34 1 T127 1
auto[1073741824:1207959551] auto[1] 5 1 T113 1 T224 1 T237 1
auto[1207959552:1342177279] auto[0] 126 1 T4 1 T15 1 T19 1
auto[1207959552:1342177279] auto[1] 13 1 T137 2 T347 1 T315 1
auto[1342177280:1476395007] auto[0] 106 1 T15 1 T47 1 T44 1
auto[1342177280:1476395007] auto[1] 5 1 T260 1 T223 1 T372 1
auto[1476395008:1610612735] auto[0] 123 1 T4 1 T16 1 T18 1
auto[1476395008:1610612735] auto[1] 10 1 T77 1 T82 1 T371 1
auto[1610612736:1744830463] auto[0] 134 1 T1 1 T16 1 T18 1
auto[1610612736:1744830463] auto[1] 9 1 T347 1 T223 1 T224 1
auto[1744830464:1879048191] auto[0] 104 1 T15 1 T26 1 T189 1
auto[1744830464:1879048191] auto[1] 10 1 T239 1 T137 2 T371 1
auto[1879048192:2013265919] auto[0] 131 1 T35 1 T43 2 T189 1
auto[1879048192:2013265919] auto[1] 12 1 T144 1 T234 1 T223 1
auto[2013265920:2147483647] auto[0] 126 1 T15 1 T18 1 T19 1
auto[2013265920:2147483647] auto[1] 11 1 T239 2 T381 1 T315 1
auto[2147483648:2281701375] auto[0] 132 1 T1 1 T18 1 T35 1
auto[2147483648:2281701375] auto[1] 7 1 T77 1 T252 1 T224 1
auto[2281701376:2415919103] auto[0] 132 1 T35 1 T43 2 T87 1
auto[2281701376:2415919103] auto[1] 10 1 T82 1 T137 1 T234 1
auto[2415919104:2550136831] auto[0] 104 1 T35 1 T44 2 T113 1
auto[2415919104:2550136831] auto[1] 15 1 T19 1 T113 1 T77 1
auto[2550136832:2684354559] auto[0] 109 1 T4 1 T15 1 T18 1
auto[2550136832:2684354559] auto[1] 11 1 T239 1 T137 1 T234 1
auto[2684354560:2818572287] auto[0] 126 1 T18 1 T35 2 T43 1
auto[2684354560:2818572287] auto[1] 6 1 T259 1 T261 1 T260 1
auto[2818572288:2952790015] auto[0] 120 1 T35 1 T43 2 T135 1
auto[2818572288:2952790015] auto[1] 5 1 T260 1 T382 1 T237 1
auto[2952790016:3087007743] auto[0] 106 1 T4 1 T16 1 T43 1
auto[2952790016:3087007743] auto[1] 2 1 T137 1 T381 1 - -
auto[3087007744:3221225471] auto[0] 112 1 T43 3 T86 2 T46 1
auto[3087007744:3221225471] auto[1] 7 1 T19 1 T82 1 T315 1
auto[3221225472:3355443199] auto[0] 136 1 T4 1 T16 1 T43 2
auto[3221225472:3355443199] auto[1] 6 1 T260 1 T383 1 T373 1
auto[3355443200:3489660927] auto[0] 89 1 T15 1 T26 1 T45 1
auto[3355443200:3489660927] auto[1] 9 1 T315 1 T382 1 T237 1
auto[3489660928:3623878655] auto[0] 113 1 T18 1 T26 1 T128 1
auto[3489660928:3623878655] auto[1] 11 1 T137 1 T261 2 T384 1
auto[3623878656:3758096383] auto[0] 102 1 T1 1 T4 1 T35 1
auto[3623878656:3758096383] auto[1] 4 1 T82 1 T260 1 T223 1
auto[3758096384:3892314111] auto[0] 116 1 T189 1 T42 1 T86 2
auto[3758096384:3892314111] auto[1] 6 1 T371 1 T372 1 T286 1
auto[3892314112:4026531839] auto[0] 116 1 T18 1 T128 1 T48 1
auto[3892314112:4026531839] auto[1] 3 1 T343 1 T235 1 T385 1
auto[4026531840:4160749567] auto[0] 128 1 T26 1 T43 2 T134 1
auto[4026531840:4160749567] auto[1] 8 1 T82 1 T315 1 T260 1
auto[4160749568:4294967295] auto[0] 127 1 T16 1 T19 1 T43 2
auto[4160749568:4294967295] auto[1] 9 1 T347 1 T381 1 T223 1

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