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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.04 98.11 98.40 100.00 99.02 98.41 91.17


Total test records in report: 1081
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T1003 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4189091026 Aug 08 04:49:14 PM PDT 24 Aug 08 04:49:20 PM PDT 24 279138967 ps
T1004 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3006411606 Aug 08 04:49:25 PM PDT 24 Aug 08 04:49:28 PM PDT 24 436181276 ps
T1005 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2529842587 Aug 08 04:49:05 PM PDT 24 Aug 08 04:49:07 PM PDT 24 41933982 ps
T1006 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.467069516 Aug 08 04:49:23 PM PDT 24 Aug 08 04:49:27 PM PDT 24 110243064 ps
T1007 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3893741099 Aug 08 04:49:25 PM PDT 24 Aug 08 04:49:28 PM PDT 24 380343668 ps
T1008 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2142055006 Aug 08 04:49:09 PM PDT 24 Aug 08 04:49:10 PM PDT 24 17141002 ps
T1009 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1027507151 Aug 08 04:49:03 PM PDT 24 Aug 08 04:49:04 PM PDT 24 19058211 ps
T1010 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1398754679 Aug 08 04:49:16 PM PDT 24 Aug 08 04:49:18 PM PDT 24 82323771 ps
T1011 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2508363740 Aug 08 04:49:17 PM PDT 24 Aug 08 04:49:20 PM PDT 24 262832460 ps
T1012 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1905930976 Aug 08 04:49:07 PM PDT 24 Aug 08 04:49:11 PM PDT 24 176128194 ps
T1013 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.437052173 Aug 08 04:49:27 PM PDT 24 Aug 08 04:49:29 PM PDT 24 123754243 ps
T1014 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3543492506 Aug 08 04:49:18 PM PDT 24 Aug 08 04:49:19 PM PDT 24 19323172 ps
T1015 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3462897410 Aug 08 04:49:30 PM PDT 24 Aug 08 04:49:31 PM PDT 24 13224139 ps
T1016 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.43941635 Aug 08 04:49:16 PM PDT 24 Aug 08 04:49:20 PM PDT 24 116432208 ps
T1017 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.627999128 Aug 08 04:49:35 PM PDT 24 Aug 08 04:49:36 PM PDT 24 120347908 ps
T1018 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1919144794 Aug 08 04:49:18 PM PDT 24 Aug 08 04:49:19 PM PDT 24 15588505 ps
T1019 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.4294317189 Aug 08 04:48:59 PM PDT 24 Aug 08 04:49:01 PM PDT 24 31968553 ps
T1020 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.954297541 Aug 08 04:49:40 PM PDT 24 Aug 08 04:49:41 PM PDT 24 17579861 ps
T1021 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2038028820 Aug 08 04:49:14 PM PDT 24 Aug 08 04:49:16 PM PDT 24 28891162 ps
T1022 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.958807788 Aug 08 04:49:30 PM PDT 24 Aug 08 04:49:33 PM PDT 24 122221210 ps
T1023 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3061423447 Aug 08 04:49:41 PM PDT 24 Aug 08 04:49:42 PM PDT 24 30968851 ps
T1024 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2706797890 Aug 08 04:48:58 PM PDT 24 Aug 08 04:48:59 PM PDT 24 25636921 ps
T1025 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3662709575 Aug 08 04:49:17 PM PDT 24 Aug 08 04:49:18 PM PDT 24 17959483 ps
T1026 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.372326951 Aug 08 04:49:20 PM PDT 24 Aug 08 04:49:21 PM PDT 24 12248509 ps
T1027 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.524225823 Aug 08 04:49:15 PM PDT 24 Aug 08 04:49:17 PM PDT 24 488010872 ps
T1028 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1348312890 Aug 08 04:49:12 PM PDT 24 Aug 08 04:49:19 PM PDT 24 60290553 ps
T1029 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3064545665 Aug 08 04:49:25 PM PDT 24 Aug 08 04:49:32 PM PDT 24 241081141 ps
T1030 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.4066436686 Aug 08 04:49:18 PM PDT 24 Aug 08 04:49:22 PM PDT 24 170660833 ps
T1031 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2702309255 Aug 08 04:49:02 PM PDT 24 Aug 08 04:49:04 PM PDT 24 71992404 ps
T1032 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1668964255 Aug 08 04:49:05 PM PDT 24 Aug 08 04:49:08 PM PDT 24 390274438 ps
T1033 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1463235191 Aug 08 04:48:58 PM PDT 24 Aug 08 04:49:00 PM PDT 24 646731972 ps
T1034 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.4115711931 Aug 08 04:49:29 PM PDT 24 Aug 08 04:49:30 PM PDT 24 43135312 ps
T1035 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3495803018 Aug 08 04:49:34 PM PDT 24 Aug 08 04:49:35 PM PDT 24 32505726 ps
T1036 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2224444761 Aug 08 04:49:28 PM PDT 24 Aug 08 04:49:29 PM PDT 24 19324693 ps
T1037 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3205284325 Aug 08 04:49:00 PM PDT 24 Aug 08 04:49:04 PM PDT 24 81390988 ps
T1038 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1372122471 Aug 08 04:48:59 PM PDT 24 Aug 08 04:49:00 PM PDT 24 89308154 ps
T1039 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1989244577 Aug 08 04:49:19 PM PDT 24 Aug 08 04:49:23 PM PDT 24 526688240 ps
T1040 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.393492373 Aug 08 04:49:31 PM PDT 24 Aug 08 04:49:37 PM PDT 24 168448991 ps
T1041 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1326855019 Aug 08 04:49:49 PM PDT 24 Aug 08 04:49:50 PM PDT 24 38265030 ps
T1042 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.139550432 Aug 08 04:49:28 PM PDT 24 Aug 08 04:49:33 PM PDT 24 476608190 ps
T1043 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.958740158 Aug 08 04:49:01 PM PDT 24 Aug 08 04:49:05 PM PDT 24 372440878 ps
T1044 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3632018357 Aug 08 04:49:13 PM PDT 24 Aug 08 04:49:15 PM PDT 24 45001046 ps
T1045 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1731450621 Aug 08 04:49:25 PM PDT 24 Aug 08 04:49:28 PM PDT 24 236434590 ps
T1046 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3856539783 Aug 08 04:49:02 PM PDT 24 Aug 08 04:49:03 PM PDT 24 20208042 ps
T1047 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.759968755 Aug 08 04:49:18 PM PDT 24 Aug 08 04:49:19 PM PDT 24 42646445 ps
T1048 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1412096288 Aug 08 04:49:26 PM PDT 24 Aug 08 04:49:27 PM PDT 24 21047365 ps
T1049 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2812364390 Aug 08 04:49:08 PM PDT 24 Aug 08 04:49:09 PM PDT 24 174562424 ps
T1050 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1601516607 Aug 08 04:48:55 PM PDT 24 Aug 08 04:48:57 PM PDT 24 94597155 ps
T1051 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3900499355 Aug 08 04:49:13 PM PDT 24 Aug 08 04:49:15 PM PDT 24 235711287 ps
T1052 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.502683364 Aug 08 04:49:20 PM PDT 24 Aug 08 04:49:35 PM PDT 24 1008179246 ps
T1053 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.172968585 Aug 08 04:49:16 PM PDT 24 Aug 08 04:49:19 PM PDT 24 157991187 ps
T1054 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.997269331 Aug 08 04:49:40 PM PDT 24 Aug 08 04:49:40 PM PDT 24 26734528 ps
T1055 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1618740974 Aug 08 04:49:02 PM PDT 24 Aug 08 04:49:04 PM PDT 24 74102140 ps
T1056 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3235362495 Aug 08 04:49:19 PM PDT 24 Aug 08 04:49:20 PM PDT 24 115385031 ps
T1057 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4017895603 Aug 08 04:49:31 PM PDT 24 Aug 08 04:49:37 PM PDT 24 456387163 ps
T1058 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3917100437 Aug 08 04:49:26 PM PDT 24 Aug 08 04:49:28 PM PDT 24 51930796 ps
T1059 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3735230252 Aug 08 04:49:47 PM PDT 24 Aug 08 04:49:48 PM PDT 24 18565264 ps
T1060 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1022654293 Aug 08 04:49:25 PM PDT 24 Aug 08 04:49:27 PM PDT 24 59039539 ps
T1061 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.4113092567 Aug 08 04:49:06 PM PDT 24 Aug 08 04:49:11 PM PDT 24 155735057 ps
T1062 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2025253072 Aug 08 04:49:26 PM PDT 24 Aug 08 04:49:27 PM PDT 24 17379442 ps
T1063 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.193790081 Aug 08 04:49:28 PM PDT 24 Aug 08 04:49:29 PM PDT 24 14717381 ps
T1064 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.980382297 Aug 08 04:49:24 PM PDT 24 Aug 08 04:49:25 PM PDT 24 22818064 ps
T1065 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2535821675 Aug 08 04:49:20 PM PDT 24 Aug 08 04:49:26 PM PDT 24 130773375 ps
T154 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4081473154 Aug 08 04:49:35 PM PDT 24 Aug 08 04:49:41 PM PDT 24 838845649 ps
T1066 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.390298451 Aug 08 04:49:08 PM PDT 24 Aug 08 04:49:11 PM PDT 24 59954380 ps
T1067 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.757391981 Aug 08 04:48:57 PM PDT 24 Aug 08 04:49:00 PM PDT 24 243330778 ps
T1068 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1263176879 Aug 08 04:49:18 PM PDT 24 Aug 08 04:49:23 PM PDT 24 135246281 ps
T1069 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3072190780 Aug 08 04:49:14 PM PDT 24 Aug 08 04:49:16 PM PDT 24 13121810 ps
T1070 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3831205217 Aug 08 04:49:25 PM PDT 24 Aug 08 04:49:31 PM PDT 24 161186947 ps
T1071 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3250615812 Aug 08 04:49:15 PM PDT 24 Aug 08 04:49:22 PM PDT 24 158847739 ps
T1072 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3759983763 Aug 08 04:49:24 PM PDT 24 Aug 08 04:49:26 PM PDT 24 28178274 ps
T1073 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3043543768 Aug 08 04:49:05 PM PDT 24 Aug 08 04:49:11 PM PDT 24 871033338 ps
T1074 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.821437081 Aug 08 04:49:17 PM PDT 24 Aug 08 04:49:20 PM PDT 24 85236647 ps
T1075 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2282864932 Aug 08 04:49:19 PM PDT 24 Aug 08 04:49:21 PM PDT 24 478016292 ps
T1076 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2302827509 Aug 08 04:48:55 PM PDT 24 Aug 08 04:48:57 PM PDT 24 36508088 ps
T1077 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.832785596 Aug 08 04:49:06 PM PDT 24 Aug 08 04:49:07 PM PDT 24 56852969 ps
T1078 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1320826939 Aug 08 04:49:09 PM PDT 24 Aug 08 04:49:11 PM PDT 24 112376237 ps
T1079 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.125865377 Aug 08 04:49:22 PM PDT 24 Aug 08 04:49:24 PM PDT 24 94885136 ps
T1080 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1015996852 Aug 08 04:49:25 PM PDT 24 Aug 08 04:49:26 PM PDT 24 12911986 ps
T1081 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2073736839 Aug 08 04:48:58 PM PDT 24 Aug 08 04:49:06 PM PDT 24 246266713 ps
T167 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1535315014 Aug 08 04:49:27 PM PDT 24 Aug 08 04:49:32 PM PDT 24 297321026 ps

Test location /workspace/coverage/default/0.keymgr_random.287470195
Short name T16
Test name
Test status
Simulation time 446502521 ps
CPU time 13.98 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:29:11 PM PDT 24
Peak memory 219648 kb
Host smart-c9911146-569a-4f6a-ba01-8467eeafad76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287470195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.287470195
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3347105010
Short name T46
Test name
Test status
Simulation time 5531066066 ps
CPU time 56.12 seconds
Started Aug 08 05:31:38 PM PDT 24
Finished Aug 08 05:32:34 PM PDT 24
Peak memory 222640 kb
Host smart-9976e34c-9d4f-41ae-a936-20d23bcc5d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347105010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3347105010
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2906253540
Short name T18
Test name
Test status
Simulation time 482342064 ps
CPU time 5.36 seconds
Started Aug 08 05:31:19 PM PDT 24
Finished Aug 08 05:31:25 PM PDT 24
Peak memory 222448 kb
Host smart-8977c6a8-1eb5-41d8-8112-561769b6161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906253540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2906253540
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.127605967
Short name T6
Test name
Test status
Simulation time 9476231493 ps
CPU time 62.16 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:31:24 PM PDT 24
Peak memory 222456 kb
Host smart-e2684db6-86e4-4ac8-ad7c-a136bcb4c9f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127605967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.127605967
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2070995913
Short name T12
Test name
Test status
Simulation time 2785007803 ps
CPU time 12.32 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:29:09 PM PDT 24
Peak memory 238972 kb
Host smart-19837c0a-b97d-4c3a-8738-1859bd5b8d61
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070995913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2070995913
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1345227244
Short name T62
Test name
Test status
Simulation time 292133270 ps
CPU time 15.77 seconds
Started Aug 08 05:30:34 PM PDT 24
Finished Aug 08 05:30:50 PM PDT 24
Peak memory 221256 kb
Host smart-c0459f91-6186-48f7-b789-31ed3f7d01bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345227244 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1345227244
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3124719749
Short name T151
Test name
Test status
Simulation time 331035074 ps
CPU time 7.22 seconds
Started Aug 08 04:49:24 PM PDT 24
Finished Aug 08 04:49:31 PM PDT 24
Peak memory 216600 kb
Host smart-874e221d-9501-41a9-971e-4409c7166570
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124719749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3124719749
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3139391304
Short name T60
Test name
Test status
Simulation time 882438205 ps
CPU time 16.57 seconds
Started Aug 08 05:31:26 PM PDT 24
Finished Aug 08 05:31:43 PM PDT 24
Peak memory 219980 kb
Host smart-1e3b90cb-448d-4379-be3f-636e2c7bb4dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139391304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3139391304
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2723689839
Short name T35
Test name
Test status
Simulation time 159801289 ps
CPU time 2.85 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:20 PM PDT 24
Peak memory 204600 kb
Host smart-caca1ed7-ebd8-47f9-b355-ba07bebd7d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723689839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2723689839
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3565771361
Short name T239
Test name
Test status
Simulation time 895986207 ps
CPU time 44.63 seconds
Started Aug 08 05:31:47 PM PDT 24
Finished Aug 08 05:32:32 PM PDT 24
Peak memory 215496 kb
Host smart-7cb36c5c-e6a6-496f-92a0-026ca40d42d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3565771361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3565771361
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3182996953
Short name T9
Test name
Test status
Simulation time 395073932 ps
CPU time 5.78 seconds
Started Aug 08 05:31:03 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 209764 kb
Host smart-ad7e7838-d0b0-4f94-9938-d0a6b67aaaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182996953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3182996953
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1053287717
Short name T43
Test name
Test status
Simulation time 1886327680 ps
CPU time 46.09 seconds
Started Aug 08 05:30:36 PM PDT 24
Finished Aug 08 05:31:22 PM PDT 24
Peak memory 220440 kb
Host smart-c7840e11-6a0d-48bf-9316-d7f9f9d703de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053287717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1053287717
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1146896745
Short name T111
Test name
Test status
Simulation time 549707281 ps
CPU time 8.13 seconds
Started Aug 08 04:49:12 PM PDT 24
Finished Aug 08 04:49:20 PM PDT 24
Peak memory 220756 kb
Host smart-57f33ac5-9093-48a4-9bff-44644f3053b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146896745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1146896745
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3986049208
Short name T373
Test name
Test status
Simulation time 631739760 ps
CPU time 16.56 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:24 PM PDT 24
Peak memory 215544 kb
Host smart-54a0eefa-b8d7-4960-b87a-07373dc13599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986049208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3986049208
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.223544688
Short name T63
Test name
Test status
Simulation time 392333915 ps
CPU time 19.7 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:27 PM PDT 24
Peak memory 222472 kb
Host smart-70774730-ff1e-42ba-9b72-8deeb99f4151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223544688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.223544688
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.4109034212
Short name T260
Test name
Test status
Simulation time 240738893 ps
CPU time 13.08 seconds
Started Aug 08 05:31:07 PM PDT 24
Finished Aug 08 05:31:20 PM PDT 24
Peak memory 215180 kb
Host smart-afa97e02-ab7e-401e-92f0-47560f534965
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4109034212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.4109034212
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3417025119
Short name T93
Test name
Test status
Simulation time 121179305 ps
CPU time 5.16 seconds
Started Aug 08 05:30:17 PM PDT 24
Finished Aug 08 05:30:22 PM PDT 24
Peak memory 220836 kb
Host smart-1ff6a0ce-af50-402c-9eab-d6951edae120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417025119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3417025119
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.4189969695
Short name T64
Test name
Test status
Simulation time 3614417494 ps
CPU time 36.77 seconds
Started Aug 08 05:30:27 PM PDT 24
Finished Aug 08 05:31:04 PM PDT 24
Peak memory 222596 kb
Host smart-901e163e-cbed-4396-8875-ec02678f9a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189969695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4189969695
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.922820317
Short name T113
Test name
Test status
Simulation time 1048337687 ps
CPU time 5.14 seconds
Started Aug 08 05:30:27 PM PDT 24
Finished Aug 08 05:30:33 PM PDT 24
Peak memory 214292 kb
Host smart-333cc245-e38f-45df-986d-cdc8f40eb655
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922820317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.922820317
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1806342879
Short name T370
Test name
Test status
Simulation time 71672614 ps
CPU time 4.24 seconds
Started Aug 08 05:30:29 PM PDT 24
Finished Aug 08 05:30:33 PM PDT 24
Peak memory 214212 kb
Host smart-3234d037-9b5a-4304-a69f-282c626a6459
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1806342879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1806342879
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.4270750668
Short name T56
Test name
Test status
Simulation time 265430419 ps
CPU time 3.76 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:45 PM PDT 24
Peak memory 222596 kb
Host smart-a96467e1-a102-40b9-871e-772baed55030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270750668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.4270750668
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.151394534
Short name T44
Test name
Test status
Simulation time 741821817 ps
CPU time 18.7 seconds
Started Aug 08 05:32:00 PM PDT 24
Finished Aug 08 05:32:19 PM PDT 24
Peak memory 214336 kb
Host smart-9154b1f7-218b-4eac-a318-795a875d615d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151394534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.151394534
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.13093486
Short name T22
Test name
Test status
Simulation time 94007077 ps
CPU time 1.84 seconds
Started Aug 08 05:29:39 PM PDT 24
Finished Aug 08 05:29:41 PM PDT 24
Peak memory 216932 kb
Host smart-bdb916ee-45fe-423c-bcc2-113e45bd65ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13093486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.13093486
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3925098725
Short name T806
Test name
Test status
Simulation time 53968163 ps
CPU time 2.66 seconds
Started Aug 08 05:32:06 PM PDT 24
Finished Aug 08 05:32:09 PM PDT 24
Peak memory 216932 kb
Host smart-279a3862-16f7-45ef-9181-e59fd4d6e83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925098725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3925098725
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2143951494
Short name T372
Test name
Test status
Simulation time 188281832 ps
CPU time 9.06 seconds
Started Aug 08 05:31:46 PM PDT 24
Finished Aug 08 05:31:55 PM PDT 24
Peak memory 214324 kb
Host smart-ea416d80-47bf-49b6-8831-a045248db987
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2143951494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2143951494
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2362598476
Short name T30
Test name
Test status
Simulation time 48011698 ps
CPU time 2.79 seconds
Started Aug 08 05:31:14 PM PDT 24
Finished Aug 08 05:31:17 PM PDT 24
Peak memory 218296 kb
Host smart-e71f9402-5d47-4643-bc96-3717cff25461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362598476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2362598476
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.993702834
Short name T137
Test name
Test status
Simulation time 178104826 ps
CPU time 8.48 seconds
Started Aug 08 05:28:56 PM PDT 24
Finished Aug 08 05:29:04 PM PDT 24
Peak memory 214380 kb
Host smart-3ad773d2-d629-4f07-bf85-f7d04044881b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=993702834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.993702834
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.921967613
Short name T960
Test name
Test status
Simulation time 502715392 ps
CPU time 2.03 seconds
Started Aug 08 04:49:19 PM PDT 24
Finished Aug 08 04:49:21 PM PDT 24
Peak memory 214520 kb
Host smart-c8b9e7c7-ccbd-41bf-857a-bd78913e887a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921967613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.921967613
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.564966850
Short name T90
Test name
Test status
Simulation time 357461738 ps
CPU time 9.04 seconds
Started Aug 08 05:31:21 PM PDT 24
Finished Aug 08 05:31:30 PM PDT 24
Peak memory 214492 kb
Host smart-cb7d7e5d-963b-4004-8306-b9763cbc9ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564966850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.564966850
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3202107930
Short name T67
Test name
Test status
Simulation time 10764999308 ps
CPU time 36.96 seconds
Started Aug 08 05:29:10 PM PDT 24
Finished Aug 08 05:29:47 PM PDT 24
Peak memory 215912 kb
Host smart-247e88f8-577b-48bd-b9de-62d0c36ed04e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202107930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3202107930
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3867793976
Short name T170
Test name
Test status
Simulation time 643375169 ps
CPU time 3.86 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:12 PM PDT 24
Peak memory 210152 kb
Host smart-0432a2f5-4921-48c6-a6d2-45a079affc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867793976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3867793976
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1994032161
Short name T73
Test name
Test status
Simulation time 3591257022 ps
CPU time 47 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 215588 kb
Host smart-f25585c5-4657-499a-a922-b7970f5bb021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994032161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1994032161
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2784624258
Short name T23
Test name
Test status
Simulation time 701464576 ps
CPU time 8.56 seconds
Started Aug 08 05:31:32 PM PDT 24
Finished Aug 08 05:31:40 PM PDT 24
Peak memory 209272 kb
Host smart-5866cb7f-016a-4b82-8f15-0e927321e9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784624258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2784624258
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3240999149
Short name T124
Test name
Test status
Simulation time 541811736 ps
CPU time 24.89 seconds
Started Aug 08 05:31:45 PM PDT 24
Finished Aug 08 05:32:10 PM PDT 24
Peak memory 221116 kb
Host smart-ec89c17f-978e-46d2-8ebc-6ee2b7d273ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240999149 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3240999149
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1756447901
Short name T95
Test name
Test status
Simulation time 36596965 ps
CPU time 0.75 seconds
Started Aug 08 05:29:38 PM PDT 24
Finished Aug 08 05:29:39 PM PDT 24
Peak memory 206016 kb
Host smart-66706592-cc76-4aac-81e6-7573f96e82f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756447901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1756447901
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.525306327
Short name T343
Test name
Test status
Simulation time 602706505 ps
CPU time 16.26 seconds
Started Aug 08 05:29:39 PM PDT 24
Finished Aug 08 05:29:55 PM PDT 24
Peak memory 214468 kb
Host smart-38d1db48-27cd-419f-8ba3-f57b30777beb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525306327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.525306327
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3849601593
Short name T252
Test name
Test status
Simulation time 343311167 ps
CPU time 5.47 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:13 PM PDT 24
Peak memory 215236 kb
Host smart-86d72e21-7299-4947-91f4-e277778786aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849601593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3849601593
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4081473154
Short name T154
Test name
Test status
Simulation time 838845649 ps
CPU time 6.12 seconds
Started Aug 08 04:49:35 PM PDT 24
Finished Aug 08 04:49:41 PM PDT 24
Peak memory 214192 kb
Host smart-839072c7-74a2-4d13-b02e-298a4266b584
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081473154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.4081473154
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.881062616
Short name T268
Test name
Test status
Simulation time 146104126817 ps
CPU time 540.08 seconds
Started Aug 08 05:29:33 PM PDT 24
Finished Aug 08 05:38:33 PM PDT 24
Peak memory 222500 kb
Host smart-47bc3f80-d30f-44d1-b50a-1309cbc20d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881062616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.881062616
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3061249839
Short name T385
Test name
Test status
Simulation time 511714061 ps
CPU time 6.8 seconds
Started Aug 08 05:29:43 PM PDT 24
Finished Aug 08 05:29:50 PM PDT 24
Peak memory 214424 kb
Host smart-9c4d7c70-b894-469b-97f3-7aed8648475c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3061249839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3061249839
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3575606702
Short name T216
Test name
Test status
Simulation time 766827215 ps
CPU time 29.14 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:31:53 PM PDT 24
Peak memory 222132 kb
Host smart-536f5e10-cc2b-4e19-a184-00b431c00f3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575606702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3575606702
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1567862112
Short name T316
Test name
Test status
Simulation time 49076914 ps
CPU time 1.79 seconds
Started Aug 08 05:29:29 PM PDT 24
Finished Aug 08 05:29:31 PM PDT 24
Peak memory 214536 kb
Host smart-7d3718e7-7b8b-4294-963a-164b4cd43fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567862112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1567862112
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.482235554
Short name T531
Test name
Test status
Simulation time 544209904 ps
CPU time 4.06 seconds
Started Aug 08 05:28:58 PM PDT 24
Finished Aug 08 05:29:02 PM PDT 24
Peak memory 217460 kb
Host smart-006daed2-04dd-496a-95ba-114c8f6e72bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482235554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.482235554
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1656109800
Short name T146
Test name
Test status
Simulation time 52524180 ps
CPU time 3.49 seconds
Started Aug 08 05:31:19 PM PDT 24
Finished Aug 08 05:31:23 PM PDT 24
Peak memory 222632 kb
Host smart-ce7859f3-0599-4071-a139-4b6f131db1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656109800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1656109800
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3533657787
Short name T186
Test name
Test status
Simulation time 1286581975 ps
CPU time 33.3 seconds
Started Aug 08 05:29:53 PM PDT 24
Finished Aug 08 05:30:27 PM PDT 24
Peak memory 214960 kb
Host smart-b2a76b04-b3d1-4c2c-a995-e1ab040ed9be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533657787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3533657787
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1139222759
Short name T701
Test name
Test status
Simulation time 161720969 ps
CPU time 2.67 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 214284 kb
Host smart-98ecd5a8-0160-4899-8663-5ca2b1e62c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139222759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1139222759
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2966343168
Short name T388
Test name
Test status
Simulation time 434674714 ps
CPU time 6.45 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:31:01 PM PDT 24
Peak memory 214276 kb
Host smart-dab06d0e-751e-412d-8a3d-35a0afc8ce4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966343168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2966343168
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2995911913
Short name T161
Test name
Test status
Simulation time 190633630 ps
CPU time 2.71 seconds
Started Aug 08 04:49:09 PM PDT 24
Finished Aug 08 04:49:12 PM PDT 24
Peak memory 206060 kb
Host smart-eb59c1d8-f50e-42b3-a59f-b1bdaadaf6e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995911913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2995911913
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2077671032
Short name T152
Test name
Test status
Simulation time 66440298 ps
CPU time 2.96 seconds
Started Aug 08 04:49:39 PM PDT 24
Finished Aug 08 04:49:42 PM PDT 24
Peak memory 214300 kb
Host smart-e21b4e5e-a358-4961-bc5f-e9c9c851f08e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077671032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2077671032
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2972319088
Short name T147
Test name
Test status
Simulation time 252607062 ps
CPU time 4.35 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:12 PM PDT 24
Peak memory 222512 kb
Host smart-ec4bb9a4-70e4-48a4-9a6d-b96683c00a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972319088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2972319088
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3726579666
Short name T282
Test name
Test status
Simulation time 167415973 ps
CPU time 3.9 seconds
Started Aug 08 05:29:29 PM PDT 24
Finished Aug 08 05:29:33 PM PDT 24
Peak memory 208460 kb
Host smart-ca1e1be0-53f9-4e8a-b747-3f7306fcad20
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726579666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3726579666
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3807177547
Short name T612
Test name
Test status
Simulation time 973389320 ps
CPU time 4.66 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:45 PM PDT 24
Peak memory 221652 kb
Host smart-5ae5b5a2-8426-4afc-926e-d786c5487752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807177547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3807177547
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.489715455
Short name T8
Test name
Test status
Simulation time 1375453206 ps
CPU time 26.46 seconds
Started Aug 08 05:30:22 PM PDT 24
Finished Aug 08 05:30:49 PM PDT 24
Peak memory 216296 kb
Host smart-2d7b6a34-6bc0-43ef-96e8-1269039e15f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489715455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.489715455
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1185974374
Short name T107
Test name
Test status
Simulation time 62430922 ps
CPU time 1.65 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:07 PM PDT 24
Peak memory 209940 kb
Host smart-3da15f3e-1901-4b09-a18b-84f661f17a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185974374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1185974374
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2499728841
Short name T50
Test name
Test status
Simulation time 49082288 ps
CPU time 2.72 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:12 PM PDT 24
Peak memory 213880 kb
Host smart-ed681595-9c24-4c30-8ab5-cf3da53fafa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499728841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2499728841
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2188589886
Short name T14
Test name
Test status
Simulation time 675528963 ps
CPU time 13.36 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:23 PM PDT 24
Peak memory 231976 kb
Host smart-e8204ed0-f058-4f83-8f90-d42ec6fe77b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188589886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2188589886
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.935884224
Short name T150
Test name
Test status
Simulation time 62849260 ps
CPU time 3.5 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:30:57 PM PDT 24
Peak memory 215072 kb
Host smart-e492aebc-423f-4897-ab24-2a07484ebaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935884224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.935884224
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2042727620
Short name T301
Test name
Test status
Simulation time 422605422 ps
CPU time 3.36 seconds
Started Aug 08 05:28:58 PM PDT 24
Finished Aug 08 05:29:02 PM PDT 24
Peak memory 214332 kb
Host smart-164e9d55-9ff9-4780-9dce-3a1b760e2434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042727620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2042727620
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.377996280
Short name T81
Test name
Test status
Simulation time 43931813 ps
CPU time 1.88 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:21 PM PDT 24
Peak memory 220768 kb
Host smart-3ab7dbf3-807d-4e7e-ab8c-e52ba59835fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377996280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.377996280
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.4084302183
Short name T144
Test name
Test status
Simulation time 339836465 ps
CPU time 4.43 seconds
Started Aug 08 05:30:17 PM PDT 24
Finished Aug 08 05:30:21 PM PDT 24
Peak memory 215076 kb
Host smart-81a8533b-77c8-4e2b-b66b-6041df390764
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084302183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.4084302183
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.194430284
Short name T251
Test name
Test status
Simulation time 2533193000 ps
CPU time 15.2 seconds
Started Aug 08 05:30:33 PM PDT 24
Finished Aug 08 05:30:48 PM PDT 24
Peak memory 208840 kb
Host smart-9bcfe097-e50f-4d30-be46-913f618d8046
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194430284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.194430284
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1416961769
Short name T298
Test name
Test status
Simulation time 76887294 ps
CPU time 3.68 seconds
Started Aug 08 05:30:52 PM PDT 24
Finished Aug 08 05:30:56 PM PDT 24
Peak memory 222384 kb
Host smart-7de2ef59-1112-4126-a65e-9db7f25b171f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416961769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1416961769
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.212529311
Short name T218
Test name
Test status
Simulation time 5998861389 ps
CPU time 39.73 seconds
Started Aug 08 05:31:07 PM PDT 24
Finished Aug 08 05:31:47 PM PDT 24
Peak memory 214284 kb
Host smart-9296969b-64e2-40f3-b295-79014b458d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212529311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.212529311
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.4236755580
Short name T371
Test name
Test status
Simulation time 648231376 ps
CPU time 5.41 seconds
Started Aug 08 05:31:36 PM PDT 24
Finished Aug 08 05:31:41 PM PDT 24
Peak memory 215380 kb
Host smart-d40cc1d9-9631-4afc-8c42-f30144b3fc4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236755580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.4236755580
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1475210894
Short name T157
Test name
Test status
Simulation time 103161683 ps
CPU time 1.75 seconds
Started Aug 08 05:29:11 PM PDT 24
Finished Aug 08 05:29:13 PM PDT 24
Peak memory 209776 kb
Host smart-3c70521c-c060-4f37-8b60-1cb9e4da2c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475210894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1475210894
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3272840499
Short name T149
Test name
Test status
Simulation time 82364802 ps
CPU time 3.89 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:10 PM PDT 24
Peak memory 217864 kb
Host smart-30aa39d7-a7a7-49d4-ac9f-4f4c654290b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272840499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3272840499
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2684497041
Short name T796
Test name
Test status
Simulation time 269675197 ps
CPU time 4.26 seconds
Started Aug 08 05:29:31 PM PDT 24
Finished Aug 08 05:29:36 PM PDT 24
Peak memory 222440 kb
Host smart-f2c603ec-61d8-4a63-b471-4a6f2a47d920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684497041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2684497041
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2198653599
Short name T897
Test name
Test status
Simulation time 361982502 ps
CPU time 14.64 seconds
Started Aug 08 05:29:43 PM PDT 24
Finished Aug 08 05:29:57 PM PDT 24
Peak memory 222576 kb
Host smart-82e7d6b4-9a89-48e0-b6db-c3469cf5e8fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198653599 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2198653599
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.213070818
Short name T208
Test name
Test status
Simulation time 1073173078 ps
CPU time 13.45 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:21 PM PDT 24
Peak memory 222492 kb
Host smart-27eace23-dfc7-42c6-833b-fe5eb94da369
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213070818 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.213070818
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1250455351
Short name T292
Test name
Test status
Simulation time 803051300 ps
CPU time 18.23 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:24 PM PDT 24
Peak memory 216672 kb
Host smart-e0b88c88-34d8-447f-a928-ebe0c364298a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250455351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1250455351
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.4165781996
Short name T267
Test name
Test status
Simulation time 150276415 ps
CPU time 3.06 seconds
Started Aug 08 05:30:18 PM PDT 24
Finished Aug 08 05:30:21 PM PDT 24
Peak memory 214380 kb
Host smart-1d54cbd7-902c-4198-82e9-14af87a68714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165781996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.4165781996
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.203175803
Short name T405
Test name
Test status
Simulation time 119293930 ps
CPU time 2.63 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:44 PM PDT 24
Peak memory 207744 kb
Host smart-d1f2d201-1912-4d34-9948-c2e90cc1f471
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203175803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.203175803
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2909235530
Short name T214
Test name
Test status
Simulation time 1712676082 ps
CPU time 55.07 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:31:49 PM PDT 24
Peak memory 215232 kb
Host smart-62b14ac7-168f-4cda-8e62-538122e5ac00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909235530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2909235530
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2123464732
Short name T313
Test name
Test status
Simulation time 157296290 ps
CPU time 4.38 seconds
Started Aug 08 05:31:03 PM PDT 24
Finished Aug 08 05:31:07 PM PDT 24
Peak memory 209680 kb
Host smart-78dfff22-b3a2-4bc0-a19e-cc5a17384b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123464732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2123464732
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1938332752
Short name T256
Test name
Test status
Simulation time 613558898 ps
CPU time 15.85 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:22 PM PDT 24
Peak memory 216584 kb
Host smart-37170159-c484-4fdf-8c34-af2d29fac2fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938332752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1938332752
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2452631817
Short name T223
Test name
Test status
Simulation time 745022981 ps
CPU time 38.81 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:48 PM PDT 24
Peak memory 214360 kb
Host smart-1175c01e-333c-4cb3-9043-04fd31c48fbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452631817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2452631817
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2700039829
Short name T25
Test name
Test status
Simulation time 351334854 ps
CPU time 3.7 seconds
Started Aug 08 05:29:11 PM PDT 24
Finished Aug 08 05:29:15 PM PDT 24
Peak memory 209444 kb
Host smart-c7620f13-0a72-4190-a8ef-51f5ef88a670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700039829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2700039829
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.148485922
Short name T185
Test name
Test status
Simulation time 4887621073 ps
CPU time 74.77 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:32:39 PM PDT 24
Peak memory 222544 kb
Host smart-aa2b4701-698e-465e-9449-2a6ffa432a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148485922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.148485922
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_random.1622948532
Short name T331
Test name
Test status
Simulation time 511255695 ps
CPU time 9.99 seconds
Started Aug 08 05:31:27 PM PDT 24
Finished Aug 08 05:31:37 PM PDT 24
Peak memory 214280 kb
Host smart-267b6855-d083-49cf-8550-bc2d3fea1de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622948532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1622948532
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3055571644
Short name T155
Test name
Test status
Simulation time 149527120 ps
CPU time 3.5 seconds
Started Aug 08 04:48:56 PM PDT 24
Finished Aug 08 04:49:00 PM PDT 24
Peak memory 215336 kb
Host smart-ab9e0767-0a7e-4ae8-935f-83ce8296de1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055571644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3055571644
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2717880113
Short name T158
Test name
Test status
Simulation time 272113179 ps
CPU time 4.41 seconds
Started Aug 08 04:49:14 PM PDT 24
Finished Aug 08 04:49:19 PM PDT 24
Peak memory 214276 kb
Host smart-fcf2c61c-f16d-442c-a55d-2d81b7e32dd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717880113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2717880113
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1535315014
Short name T167
Test name
Test status
Simulation time 297321026 ps
CPU time 4.42 seconds
Started Aug 08 04:49:27 PM PDT 24
Finished Aug 08 04:49:32 PM PDT 24
Peak memory 205976 kb
Host smart-bb9dc9cb-4d44-43fc-b67c-5ca9dd8d3d34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535315014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1535315014
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.792259396
Short name T160
Test name
Test status
Simulation time 75475034 ps
CPU time 2 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:30:57 PM PDT 24
Peak memory 209900 kb
Host smart-ce1e3b8d-7d86-44b5-8cb3-19bbf32e3e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792259396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.792259396
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.390570594
Short name T13
Test name
Test status
Simulation time 1085765141 ps
CPU time 17.04 seconds
Started Aug 08 05:29:10 PM PDT 24
Finished Aug 08 05:29:28 PM PDT 24
Peak memory 238768 kb
Host smart-9da20a17-e8d4-4471-9c0d-33a4720b915c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390570594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.390570594
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3322731153
Short name T120
Test name
Test status
Simulation time 530718185 ps
CPU time 14.07 seconds
Started Aug 08 05:28:58 PM PDT 24
Finished Aug 08 05:29:12 PM PDT 24
Peak memory 222500 kb
Host smart-807c7f97-ebd1-4122-a60f-0a1aebe66a3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322731153 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3322731153
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1580626345
Short name T761
Test name
Test status
Simulation time 7419809473 ps
CPU time 41.22 seconds
Started Aug 08 05:29:31 PM PDT 24
Finished Aug 08 05:30:13 PM PDT 24
Peak memory 208796 kb
Host smart-6f87a15d-99e9-49fd-83bb-7eea3f79824f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580626345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1580626345
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3866711330
Short name T539
Test name
Test status
Simulation time 52114251 ps
CPU time 2.59 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:43 PM PDT 24
Peak memory 208756 kb
Host smart-bf8617ed-d2b2-45a6-a4c9-98706b0360f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866711330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3866711330
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.131014446
Short name T714
Test name
Test status
Simulation time 45132780 ps
CPU time 2.77 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:29:44 PM PDT 24
Peak memory 222312 kb
Host smart-20798649-5a86-4e98-ac1c-e3b767eebd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131014446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.131014446
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1996781431
Short name T347
Test name
Test status
Simulation time 104707126 ps
CPU time 2.27 seconds
Started Aug 08 05:29:52 PM PDT 24
Finished Aug 08 05:29:54 PM PDT 24
Peak memory 214352 kb
Host smart-cdb640fa-8bf5-4c66-836a-8ee5571b5c4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996781431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1996781431
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2502879154
Short name T853
Test name
Test status
Simulation time 132769265 ps
CPU time 2.62 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 222504 kb
Host smart-ba91a064-984d-43fe-a169-ed485ffacdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502879154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2502879154
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1422267800
Short name T211
Test name
Test status
Simulation time 1340648706 ps
CPU time 34.91 seconds
Started Aug 08 05:30:06 PM PDT 24
Finished Aug 08 05:30:41 PM PDT 24
Peak memory 216580 kb
Host smart-406db852-65e0-45e9-95f0-2b13bcbe006f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422267800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1422267800
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.659091076
Short name T75
Test name
Test status
Simulation time 3274617071 ps
CPU time 34.06 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:42 PM PDT 24
Peak memory 222556 kb
Host smart-80103882-0cc3-4478-aee6-c52afcc545c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659091076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.659091076
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sideload.4288381669
Short name T506
Test name
Test status
Simulation time 127256096 ps
CPU time 3.12 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 208488 kb
Host smart-ff2c085e-e797-4f27-b451-47d8e992d78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288381669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.4288381669
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2195782675
Short name T176
Test name
Test status
Simulation time 1037191118 ps
CPU time 18.84 seconds
Started Aug 08 05:29:08 PM PDT 24
Finished Aug 08 05:29:27 PM PDT 24
Peak memory 222504 kb
Host smart-4ad71ca4-e2c5-4c22-a51d-466852aeb220
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195782675 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2195782675
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.813540030
Short name T234
Test name
Test status
Simulation time 37347442 ps
CPU time 2.92 seconds
Started Aug 08 05:30:20 PM PDT 24
Finished Aug 08 05:30:23 PM PDT 24
Peak memory 215428 kb
Host smart-cc16c460-1453-4902-b73c-44d9dc674f6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813540030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.813540030
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1475781728
Short name T381
Test name
Test status
Simulation time 48959021 ps
CPU time 2.17 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 214276 kb
Host smart-cbf9f26c-2796-4398-8218-d3a07550958c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1475781728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1475781728
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.912235793
Short name T200
Test name
Test status
Simulation time 396978458 ps
CPU time 3.36 seconds
Started Aug 08 05:30:27 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 215612 kb
Host smart-7bcaa8b0-50eb-4866-b869-347b43da37b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912235793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.912235793
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2014261261
Short name T123
Test name
Test status
Simulation time 2505536034 ps
CPU time 14.67 seconds
Started Aug 08 05:29:10 PM PDT 24
Finished Aug 08 05:29:25 PM PDT 24
Peak memory 219320 kb
Host smart-c1db3f81-2e09-4dc2-978d-c797f9c397d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014261261 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2014261261
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.751660940
Short name T278
Test name
Test status
Simulation time 310790894 ps
CPU time 5.29 seconds
Started Aug 08 05:31:00 PM PDT 24
Finished Aug 08 05:31:05 PM PDT 24
Peak memory 209576 kb
Host smart-974bd202-d241-480f-93bf-22230129bcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751660940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.751660940
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.817080627
Short name T212
Test name
Test status
Simulation time 150829572 ps
CPU time 2.99 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:20 PM PDT 24
Peak memory 210020 kb
Host smart-bc5b6e9c-4b6e-4e3e-b1ad-56f8274e6c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817080627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.817080627
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3888829286
Short name T382
Test name
Test status
Simulation time 658712705 ps
CPU time 10.58 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:28 PM PDT 24
Peak memory 214316 kb
Host smart-8b9f9b20-61f8-468d-9cf5-a4394b7b83bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888829286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3888829286
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3092290549
Short name T326
Test name
Test status
Simulation time 1610507386 ps
CPU time 59.15 seconds
Started Aug 08 05:29:21 PM PDT 24
Finished Aug 08 05:30:20 PM PDT 24
Peak memory 216196 kb
Host smart-e66eef9b-593f-4531-85e3-d09623ab9cf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092290549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3092290549
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.511327652
Short name T148
Test name
Test status
Simulation time 713100480 ps
CPU time 6.51 seconds
Started Aug 08 05:30:06 PM PDT 24
Finished Aug 08 05:30:13 PM PDT 24
Peak memory 222468 kb
Host smart-6f887c12-659d-424a-8f5b-2dad4e508571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511327652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.511327652
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2471125328
Short name T145
Test name
Test status
Simulation time 144094660 ps
CPU time 2.96 seconds
Started Aug 08 05:30:36 PM PDT 24
Finished Aug 08 05:30:40 PM PDT 24
Peak memory 216940 kb
Host smart-bb55e875-eaa0-499a-91ee-e18fb1c57f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471125328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2471125328
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.4113092567
Short name T1061
Test name
Test status
Simulation time 155735057 ps
CPU time 4.78 seconds
Started Aug 08 04:49:06 PM PDT 24
Finished Aug 08 04:49:11 PM PDT 24
Peak memory 206112 kb
Host smart-9b24ed89-cca3-41ad-8f71-f52fda285e41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113092567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.4
113092567
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2515358892
Short name T925
Test name
Test status
Simulation time 2860273747 ps
CPU time 24.6 seconds
Started Aug 08 04:49:17 PM PDT 24
Finished Aug 08 04:49:42 PM PDT 24
Peak memory 206084 kb
Host smart-4e4d1cc2-4b64-499d-8797-d0e4decf6cc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515358892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
515358892
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2302827509
Short name T1076
Test name
Test status
Simulation time 36508088 ps
CPU time 0.96 seconds
Started Aug 08 04:48:55 PM PDT 24
Finished Aug 08 04:48:57 PM PDT 24
Peak memory 205908 kb
Host smart-d89699c9-6e53-4534-a945-3522de688724
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302827509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
302827509
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2702309255
Short name T1031
Test name
Test status
Simulation time 71992404 ps
CPU time 1.61 seconds
Started Aug 08 04:49:02 PM PDT 24
Finished Aug 08 04:49:04 PM PDT 24
Peak memory 214348 kb
Host smart-03ceea95-6539-477d-b739-47e3a2ce933f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702309255 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2702309255
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1047909408
Short name T940
Test name
Test status
Simulation time 27705801 ps
CPU time 1.17 seconds
Started Aug 08 04:48:56 PM PDT 24
Finished Aug 08 04:48:57 PM PDT 24
Peak memory 205864 kb
Host smart-3b83188a-4798-4fac-a388-28ceb8e0c11e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047909408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1047909408
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2478988137
Short name T971
Test name
Test status
Simulation time 40907467 ps
CPU time 0.72 seconds
Started Aug 08 04:48:53 PM PDT 24
Finished Aug 08 04:48:54 PM PDT 24
Peak memory 205880 kb
Host smart-0981c3ca-5ca0-4c4b-9be4-3dc1b1203d8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478988137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2478988137
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.958740158
Short name T1043
Test name
Test status
Simulation time 372440878 ps
CPU time 3.97 seconds
Started Aug 08 04:49:01 PM PDT 24
Finished Aug 08 04:49:05 PM PDT 24
Peak memory 206036 kb
Host smart-65e0dd20-f59d-48aa-86dc-16d984c846d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958740158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.958740158
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1463235191
Short name T1033
Test name
Test status
Simulation time 646731972 ps
CPU time 2.15 seconds
Started Aug 08 04:48:58 PM PDT 24
Finished Aug 08 04:49:00 PM PDT 24
Peak memory 214400 kb
Host smart-9e1859d2-adad-4bb6-825f-741e8f746f00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463235191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1463235191
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1905930976
Short name T1012
Test name
Test status
Simulation time 176128194 ps
CPU time 4.53 seconds
Started Aug 08 04:49:07 PM PDT 24
Finished Aug 08 04:49:11 PM PDT 24
Peak memory 214488 kb
Host smart-46fd5135-941a-48c8-96ec-55d243f5c4ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905930976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1905930976
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1601516607
Short name T1050
Test name
Test status
Simulation time 94597155 ps
CPU time 1.74 seconds
Started Aug 08 04:48:55 PM PDT 24
Finished Aug 08 04:48:57 PM PDT 24
Peak memory 214408 kb
Host smart-eac200f8-0a88-40b2-a0aa-4d7c9c7a0092
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601516607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1601516607
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3043543768
Short name T1073
Test name
Test status
Simulation time 871033338 ps
CPU time 5.38 seconds
Started Aug 08 04:49:05 PM PDT 24
Finished Aug 08 04:49:11 PM PDT 24
Peak memory 206084 kb
Host smart-cace143f-b0a2-4d98-9f1d-0c040a71c878
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043543768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
043543768
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.125693969
Short name T917
Test name
Test status
Simulation time 5152726800 ps
CPU time 23.67 seconds
Started Aug 08 04:49:11 PM PDT 24
Finished Aug 08 04:49:35 PM PDT 24
Peak memory 206096 kb
Host smart-82259e85-73a1-49a4-a806-1756e387e74c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125693969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.125693969
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3632018357
Short name T1044
Test name
Test status
Simulation time 45001046 ps
CPU time 1.13 seconds
Started Aug 08 04:49:13 PM PDT 24
Finished Aug 08 04:49:15 PM PDT 24
Peak memory 206076 kb
Host smart-f42abb77-01e7-4928-b6fc-fc509f3bd144
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632018357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
632018357
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1795859588
Short name T998
Test name
Test status
Simulation time 84704307 ps
CPU time 1.35 seconds
Started Aug 08 04:49:17 PM PDT 24
Finished Aug 08 04:49:19 PM PDT 24
Peak memory 214328 kb
Host smart-748cb449-1870-4945-894e-b89747fee9d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795859588 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1795859588
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1027507151
Short name T1009
Test name
Test status
Simulation time 19058211 ps
CPU time 1.08 seconds
Started Aug 08 04:49:03 PM PDT 24
Finished Aug 08 04:49:04 PM PDT 24
Peak memory 206124 kb
Host smart-05e5c576-81f8-4112-a207-5997fda9ed57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027507151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1027507151
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4143946139
Short name T913
Test name
Test status
Simulation time 23637509 ps
CPU time 0.8 seconds
Started Aug 08 04:49:18 PM PDT 24
Finished Aug 08 04:49:19 PM PDT 24
Peak memory 205820 kb
Host smart-13499da1-511e-4717-ba63-537bcbdfd2e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143946139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4143946139
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.294426629
Short name T143
Test name
Test status
Simulation time 72132446 ps
CPU time 2.46 seconds
Started Aug 08 04:49:22 PM PDT 24
Finished Aug 08 04:49:25 PM PDT 24
Peak memory 214568 kb
Host smart-3c18f996-bbac-428d-9e2a-1b85ed45e421
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294426629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.294426629
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1668964255
Short name T1032
Test name
Test status
Simulation time 390274438 ps
CPU time 2.94 seconds
Started Aug 08 04:49:05 PM PDT 24
Finished Aug 08 04:49:08 PM PDT 24
Peak memory 214500 kb
Host smart-2a29a25b-4ab0-4d08-90de-b9f6775e94cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668964255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1668964255
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1731450621
Short name T1045
Test name
Test status
Simulation time 236434590 ps
CPU time 3.09 seconds
Started Aug 08 04:49:25 PM PDT 24
Finished Aug 08 04:49:28 PM PDT 24
Peak memory 214432 kb
Host smart-8fa4c736-1df0-4adf-aff9-6d29afe0aff1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731450621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1731450621
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1266019378
Short name T930
Test name
Test status
Simulation time 251568644 ps
CPU time 6.69 seconds
Started Aug 08 04:49:11 PM PDT 24
Finished Aug 08 04:49:18 PM PDT 24
Peak memory 214260 kb
Host smart-63059993-1923-4919-8ef0-fa904e924d26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266019378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1266019378
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2529842587
Short name T1005
Test name
Test status
Simulation time 41933982 ps
CPU time 1.5 seconds
Started Aug 08 04:49:05 PM PDT 24
Finished Aug 08 04:49:07 PM PDT 24
Peak memory 214440 kb
Host smart-765abe6f-de45-460c-a459-fee8e1a14126
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529842587 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2529842587
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.832785596
Short name T1077
Test name
Test status
Simulation time 56852969 ps
CPU time 1.07 seconds
Started Aug 08 04:49:06 PM PDT 24
Finished Aug 08 04:49:07 PM PDT 24
Peak memory 206008 kb
Host smart-e4a34c9a-025d-4a51-8d6c-fe724828b55e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832785596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.832785596
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3970226454
Short name T908
Test name
Test status
Simulation time 15747879 ps
CPU time 0.75 seconds
Started Aug 08 04:49:26 PM PDT 24
Finished Aug 08 04:49:26 PM PDT 24
Peak memory 205744 kb
Host smart-5fd8503c-b939-493c-b814-c88018582ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970226454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3970226454
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.744681520
Short name T942
Test name
Test status
Simulation time 42071512 ps
CPU time 1.37 seconds
Started Aug 08 04:49:07 PM PDT 24
Finished Aug 08 04:49:09 PM PDT 24
Peak memory 206068 kb
Host smart-cca617b3-d4b5-4f98-b53b-ad914f0c05a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744681520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.744681520
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3900499355
Short name T1051
Test name
Test status
Simulation time 235711287 ps
CPU time 2.63 seconds
Started Aug 08 04:49:13 PM PDT 24
Finished Aug 08 04:49:15 PM PDT 24
Peak memory 214584 kb
Host smart-8490fd15-04a3-4c8f-bc2e-c375103c6332
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900499355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3900499355
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2963524381
Short name T109
Test name
Test status
Simulation time 211637888 ps
CPU time 9.29 seconds
Started Aug 08 04:49:00 PM PDT 24
Finished Aug 08 04:49:09 PM PDT 24
Peak memory 220488 kb
Host smart-629ca803-4c75-409b-b521-95f538a263ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963524381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2963524381
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1899466727
Short name T949
Test name
Test status
Simulation time 390373582 ps
CPU time 3.86 seconds
Started Aug 08 04:49:00 PM PDT 24
Finished Aug 08 04:49:04 PM PDT 24
Peak memory 214420 kb
Host smart-d3596685-e0c3-42c4-b03a-50e3fefd71b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899466727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1899466727
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.365444814
Short name T159
Test name
Test status
Simulation time 728745098 ps
CPU time 4.24 seconds
Started Aug 08 04:49:18 PM PDT 24
Finished Aug 08 04:49:22 PM PDT 24
Peak memory 205984 kb
Host smart-f736ddb0-23a2-41ab-8981-0974bc6b6c58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365444814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.365444814
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1064866126
Short name T999
Test name
Test status
Simulation time 306842796 ps
CPU time 2.39 seconds
Started Aug 08 04:49:32 PM PDT 24
Finished Aug 08 04:49:34 PM PDT 24
Peak memory 222396 kb
Host smart-e4c5933f-eaab-4557-8805-6417afc1d66c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064866126 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1064866126
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.28885887
Short name T969
Test name
Test status
Simulation time 155860034 ps
CPU time 1.16 seconds
Started Aug 08 04:49:24 PM PDT 24
Finished Aug 08 04:49:25 PM PDT 24
Peak memory 206208 kb
Host smart-20ede4b4-e685-4cc3-9e3f-415e3bc2f4fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28885887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.28885887
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3961329480
Short name T965
Test name
Test status
Simulation time 14016113 ps
CPU time 0.78 seconds
Started Aug 08 04:49:22 PM PDT 24
Finished Aug 08 04:49:23 PM PDT 24
Peak memory 205784 kb
Host smart-546fb86e-57f1-47fa-a8fd-bb94df3b0f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961329480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3961329480
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1977512126
Short name T963
Test name
Test status
Simulation time 104481366 ps
CPU time 2.4 seconds
Started Aug 08 04:49:08 PM PDT 24
Finished Aug 08 04:49:10 PM PDT 24
Peak memory 206064 kb
Host smart-65430ca3-5029-4c36-830d-2d521027c41a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977512126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1977512126
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3852386483
Short name T958
Test name
Test status
Simulation time 2564697286 ps
CPU time 15.44 seconds
Started Aug 08 04:49:10 PM PDT 24
Finished Aug 08 04:49:25 PM PDT 24
Peak memory 214712 kb
Host smart-a3a73d98-24e1-4798-9d52-6c265e9b04be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852386483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3852386483
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.172968585
Short name T1053
Test name
Test status
Simulation time 157991187 ps
CPU time 3.02 seconds
Started Aug 08 04:49:16 PM PDT 24
Finished Aug 08 04:49:19 PM PDT 24
Peak memory 214252 kb
Host smart-9f1868b9-abce-4dab-9fa1-ac61dde20d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172968585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.172968585
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1294150112
Short name T936
Test name
Test status
Simulation time 250830822 ps
CPU time 3.74 seconds
Started Aug 08 04:49:14 PM PDT 24
Finished Aug 08 04:49:18 PM PDT 24
Peak memory 214128 kb
Host smart-672f0dd8-24bc-4091-b631-c336e8228da2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294150112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1294150112
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.412446121
Short name T921
Test name
Test status
Simulation time 141842128 ps
CPU time 1.4 seconds
Started Aug 08 04:49:15 PM PDT 24
Finished Aug 08 04:49:17 PM PDT 24
Peak memory 214380 kb
Host smart-2b3d1675-7a7f-4da3-9de4-3316f68ae1cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412446121 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.412446121
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2142055006
Short name T1008
Test name
Test status
Simulation time 17141002 ps
CPU time 1.11 seconds
Started Aug 08 04:49:09 PM PDT 24
Finished Aug 08 04:49:10 PM PDT 24
Peak memory 206040 kb
Host smart-9e443e9d-584e-44a4-89a4-434d36d20ce5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142055006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2142055006
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3235362495
Short name T1056
Test name
Test status
Simulation time 115385031 ps
CPU time 0.85 seconds
Started Aug 08 04:49:19 PM PDT 24
Finished Aug 08 04:49:20 PM PDT 24
Peak memory 205780 kb
Host smart-1e5cdd39-507e-471d-8af2-3fdaeefcbae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235362495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3235362495
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2830635008
Short name T140
Test name
Test status
Simulation time 65249215 ps
CPU time 2.77 seconds
Started Aug 08 04:49:07 PM PDT 24
Finished Aug 08 04:49:10 PM PDT 24
Peak memory 205940 kb
Host smart-81eff439-d50e-4c38-97fc-7590b82e88c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830635008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2830635008
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1398754679
Short name T1010
Test name
Test status
Simulation time 82323771 ps
CPU time 1.75 seconds
Started Aug 08 04:49:16 PM PDT 24
Finished Aug 08 04:49:18 PM PDT 24
Peak memory 214548 kb
Host smart-f7072239-a7f6-4453-9135-f5c627a59253
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398754679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1398754679
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3393256396
Short name T118
Test name
Test status
Simulation time 301243972 ps
CPU time 6.76 seconds
Started Aug 08 04:49:22 PM PDT 24
Finished Aug 08 04:49:29 PM PDT 24
Peak memory 220544 kb
Host smart-c175edef-8d3a-4459-bca8-f080322281e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393256396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3393256396
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.43941635
Short name T1016
Test name
Test status
Simulation time 116432208 ps
CPU time 3.29 seconds
Started Aug 08 04:49:16 PM PDT 24
Finished Aug 08 04:49:20 PM PDT 24
Peak memory 222460 kb
Host smart-3511824d-4d6b-40a4-ab0e-26c3c4cca252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43941635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.43941635
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2502319979
Short name T909
Test name
Test status
Simulation time 115992386 ps
CPU time 1.36 seconds
Started Aug 08 04:49:16 PM PDT 24
Finished Aug 08 04:49:17 PM PDT 24
Peak memory 206184 kb
Host smart-f046abb8-4f9c-49a1-88e1-25ed8bb2a911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502319979 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2502319979
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.863349769
Short name T932
Test name
Test status
Simulation time 10394202 ps
CPU time 1.02 seconds
Started Aug 08 04:49:27 PM PDT 24
Finished Aug 08 04:49:28 PM PDT 24
Peak memory 205936 kb
Host smart-bc61401b-ae3a-47ea-8ee8-8eda0ddfd266
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863349769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.863349769
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2249242747
Short name T928
Test name
Test status
Simulation time 41226800 ps
CPU time 0.72 seconds
Started Aug 08 04:49:13 PM PDT 24
Finished Aug 08 04:49:15 PM PDT 24
Peak memory 205920 kb
Host smart-4a23325e-c4ce-4051-a32c-9fd1f3081db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249242747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2249242747
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.147182315
Short name T992
Test name
Test status
Simulation time 117397439 ps
CPU time 4.12 seconds
Started Aug 08 04:49:28 PM PDT 24
Finished Aug 08 04:49:32 PM PDT 24
Peak memory 206036 kb
Host smart-1801ac0d-2a2c-4f60-80ee-dcfd9eab4f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147182315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.147182315
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2149413422
Short name T117
Test name
Test status
Simulation time 122506399 ps
CPU time 1.53 seconds
Started Aug 08 04:49:16 PM PDT 24
Finished Aug 08 04:49:17 PM PDT 24
Peak memory 214580 kb
Host smart-56178940-d63c-4e93-9810-c4417942e096
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149413422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2149413422
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4017895603
Short name T1057
Test name
Test status
Simulation time 456387163 ps
CPU time 6.36 seconds
Started Aug 08 04:49:31 PM PDT 24
Finished Aug 08 04:49:37 PM PDT 24
Peak memory 214568 kb
Host smart-b8dc85a4-ddfd-4748-b226-b03a192a2f47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017895603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.4017895603
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.958807788
Short name T1022
Test name
Test status
Simulation time 122221210 ps
CPU time 2.36 seconds
Started Aug 08 04:49:30 PM PDT 24
Finished Aug 08 04:49:33 PM PDT 24
Peak memory 217252 kb
Host smart-e446c804-46e5-4528-86d3-f8421652f055
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958807788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.958807788
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2282864932
Short name T1075
Test name
Test status
Simulation time 478016292 ps
CPU time 2.27 seconds
Started Aug 08 04:49:19 PM PDT 24
Finished Aug 08 04:49:21 PM PDT 24
Peak memory 214272 kb
Host smart-747d5f06-ba16-44b9-b2d8-a4a4066913e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282864932 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2282864932
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.344557336
Short name T944
Test name
Test status
Simulation time 89046252 ps
CPU time 0.98 seconds
Started Aug 08 04:49:21 PM PDT 24
Finished Aug 08 04:49:22 PM PDT 24
Peak memory 205964 kb
Host smart-fb396d30-c7bd-4a3d-8c64-c27db3123bab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344557336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.344557336
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2932526267
Short name T931
Test name
Test status
Simulation time 19662366 ps
CPU time 0.74 seconds
Started Aug 08 04:49:12 PM PDT 24
Finished Aug 08 04:49:18 PM PDT 24
Peak memory 205772 kb
Host smart-f472617e-62a6-41a4-a1bd-4b1b21e41a6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932526267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2932526267
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3006411606
Short name T1004
Test name
Test status
Simulation time 436181276 ps
CPU time 3.59 seconds
Started Aug 08 04:49:25 PM PDT 24
Finished Aug 08 04:49:28 PM PDT 24
Peak memory 206236 kb
Host smart-805fb5de-1a9f-4c40-80f2-a126721b2fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006411606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3006411606
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.524225823
Short name T1027
Test name
Test status
Simulation time 488010872 ps
CPU time 1.87 seconds
Started Aug 08 04:49:15 PM PDT 24
Finished Aug 08 04:49:17 PM PDT 24
Peak memory 214536 kb
Host smart-45b76669-5e96-465c-9c46-dc99fe27eec4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524225823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.524225823
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3789552151
Short name T934
Test name
Test status
Simulation time 555005965 ps
CPU time 5.03 seconds
Started Aug 08 04:49:09 PM PDT 24
Finished Aug 08 04:49:14 PM PDT 24
Peak memory 220588 kb
Host smart-daea9e3d-d374-40b1-a137-cd6a47188bf8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789552151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3789552151
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.816840128
Short name T910
Test name
Test status
Simulation time 214870440 ps
CPU time 3.17 seconds
Started Aug 08 04:49:14 PM PDT 24
Finished Aug 08 04:49:18 PM PDT 24
Peak memory 214328 kb
Host smart-5b69c98f-d209-4afb-9ec3-348061ad573a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816840128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.816840128
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.584207416
Short name T990
Test name
Test status
Simulation time 125354450 ps
CPU time 4.88 seconds
Started Aug 08 04:49:28 PM PDT 24
Finished Aug 08 04:49:33 PM PDT 24
Peak memory 214244 kb
Host smart-e2652062-2567-43ab-9e68-8e801f019936
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584207416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.584207416
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3250615812
Short name T1071
Test name
Test status
Simulation time 158847739 ps
CPU time 2.1 seconds
Started Aug 08 04:49:15 PM PDT 24
Finished Aug 08 04:49:22 PM PDT 24
Peak memory 214376 kb
Host smart-418424f2-5796-4055-8abd-0e284e4eafe8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250615812 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3250615812
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2048052852
Short name T946
Test name
Test status
Simulation time 69567461 ps
CPU time 1.28 seconds
Started Aug 08 04:49:20 PM PDT 24
Finished Aug 08 04:49:21 PM PDT 24
Peak memory 206148 kb
Host smart-1a2da87e-6bfe-4328-a2d0-9806645cbea5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048052852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2048052852
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3594156310
Short name T995
Test name
Test status
Simulation time 47859704 ps
CPU time 0.86 seconds
Started Aug 08 04:49:16 PM PDT 24
Finished Aug 08 04:49:17 PM PDT 24
Peak memory 205912 kb
Host smart-532b654a-6651-4401-9bd2-f2b9b9626f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594156310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3594156310
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1287484371
Short name T142
Test name
Test status
Simulation time 21958414 ps
CPU time 1.65 seconds
Started Aug 08 04:49:18 PM PDT 24
Finished Aug 08 04:49:20 PM PDT 24
Peak memory 205988 kb
Host smart-cb423839-e0ba-4fa2-b462-5bd76539217c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287484371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1287484371
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.467069516
Short name T1006
Test name
Test status
Simulation time 110243064 ps
CPU time 3.4 seconds
Started Aug 08 04:49:23 PM PDT 24
Finished Aug 08 04:49:27 PM PDT 24
Peak memory 218772 kb
Host smart-4cbd8560-bced-4c6e-bef5-6effc24fbf80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467069516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.467069516
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1356588382
Short name T935
Test name
Test status
Simulation time 723904359 ps
CPU time 13.11 seconds
Started Aug 08 04:49:12 PM PDT 24
Finished Aug 08 04:49:25 PM PDT 24
Peak memory 214636 kb
Host smart-3974d428-c048-44dd-a39c-1a83c26e6f07
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356588382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1356588382
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2509069553
Short name T1002
Test name
Test status
Simulation time 84930801 ps
CPU time 1.61 seconds
Started Aug 08 04:49:25 PM PDT 24
Finished Aug 08 04:49:27 PM PDT 24
Peak memory 214300 kb
Host smart-9f3a8691-5185-4b5f-8b0d-464463fbd8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509069553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2509069553
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1119443698
Short name T166
Test name
Test status
Simulation time 511370511 ps
CPU time 5.03 seconds
Started Aug 08 04:49:20 PM PDT 24
Finished Aug 08 04:49:25 PM PDT 24
Peak memory 214364 kb
Host smart-12beb24c-3873-4b71-90af-7dd297f841b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119443698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1119443698
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3233079698
Short name T912
Test name
Test status
Simulation time 477603740 ps
CPU time 1.72 seconds
Started Aug 08 04:49:24 PM PDT 24
Finished Aug 08 04:49:26 PM PDT 24
Peak memory 214448 kb
Host smart-d3a18999-fbe6-4e6c-b30e-e6e1720d5058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233079698 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3233079698
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.759968755
Short name T1047
Test name
Test status
Simulation time 42646445 ps
CPU time 0.88 seconds
Started Aug 08 04:49:18 PM PDT 24
Finished Aug 08 04:49:19 PM PDT 24
Peak memory 205820 kb
Host smart-cda38692-615e-4ea9-89fc-b3a754c79b27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759968755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.759968755
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.4194105895
Short name T907
Test name
Test status
Simulation time 12537411 ps
CPU time 0.87 seconds
Started Aug 08 04:49:16 PM PDT 24
Finished Aug 08 04:49:17 PM PDT 24
Peak memory 205836 kb
Host smart-6b67828d-d74b-4faa-9356-ad18123b326a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194105895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.4194105895
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.786846524
Short name T961
Test name
Test status
Simulation time 238667282 ps
CPU time 2.34 seconds
Started Aug 08 04:49:24 PM PDT 24
Finished Aug 08 04:49:26 PM PDT 24
Peak memory 206164 kb
Host smart-e0a8481c-9ff3-4a5e-91f2-8959ac8661d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786846524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.786846524
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.461049786
Short name T997
Test name
Test status
Simulation time 160143083 ps
CPU time 1.4 seconds
Started Aug 08 04:49:22 PM PDT 24
Finished Aug 08 04:49:24 PM PDT 24
Peak memory 214544 kb
Host smart-200f7a3f-efc3-4853-b4de-331bfa32930d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461049786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.461049786
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.139550432
Short name T1042
Test name
Test status
Simulation time 476608190 ps
CPU time 4.22 seconds
Started Aug 08 04:49:28 PM PDT 24
Finished Aug 08 04:49:33 PM PDT 24
Peak memory 214488 kb
Host smart-9512da53-1dd6-44ad-bb81-f01f959a314e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139550432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.139550432
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.120706957
Short name T967
Test name
Test status
Simulation time 590073509 ps
CPU time 3.58 seconds
Started Aug 08 04:49:30 PM PDT 24
Finished Aug 08 04:49:33 PM PDT 24
Peak memory 216568 kb
Host smart-0a5715ff-d41f-44ed-a91e-95b531676140
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120706957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.120706957
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1127686381
Short name T918
Test name
Test status
Simulation time 90888023 ps
CPU time 1.18 seconds
Started Aug 08 04:49:19 PM PDT 24
Finished Aug 08 04:49:20 PM PDT 24
Peak memory 206068 kb
Host smart-8dd7c7da-e6fc-4b85-aca4-de941a25a518
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127686381 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1127686381
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1015996852
Short name T1080
Test name
Test status
Simulation time 12911986 ps
CPU time 0.83 seconds
Started Aug 08 04:49:25 PM PDT 24
Finished Aug 08 04:49:26 PM PDT 24
Peak memory 205756 kb
Host smart-8e8e09e9-fb79-432f-9eeb-b99206ab6545
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015996852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1015996852
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3417815573
Short name T968
Test name
Test status
Simulation time 32629947 ps
CPU time 0.81 seconds
Started Aug 08 04:49:25 PM PDT 24
Finished Aug 08 04:49:26 PM PDT 24
Peak memory 205772 kb
Host smart-709e7cbe-9a06-481a-9fa2-a460030564bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417815573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3417815573
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3917100437
Short name T1058
Test name
Test status
Simulation time 51930796 ps
CPU time 1.66 seconds
Started Aug 08 04:49:26 PM PDT 24
Finished Aug 08 04:49:28 PM PDT 24
Peak memory 206192 kb
Host smart-d7ba2a60-ab7c-48ab-8a6f-a5d9711fa25f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917100437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3917100437
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1933872749
Short name T976
Test name
Test status
Simulation time 160696633 ps
CPU time 4.38 seconds
Started Aug 08 04:49:26 PM PDT 24
Finished Aug 08 04:49:30 PM PDT 24
Peak memory 214596 kb
Host smart-2111758b-ccac-4506-8ab2-a82148b54fa4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933872749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1933872749
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.671580385
Short name T994
Test name
Test status
Simulation time 189762873 ps
CPU time 7.86 seconds
Started Aug 08 04:49:18 PM PDT 24
Finished Aug 08 04:49:26 PM PDT 24
Peak memory 214556 kb
Host smart-be528081-6ee2-4c72-9e9f-182b487ccbe2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671580385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.671580385
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1022654293
Short name T1060
Test name
Test status
Simulation time 59039539 ps
CPU time 2.25 seconds
Started Aug 08 04:49:25 PM PDT 24
Finished Aug 08 04:49:27 PM PDT 24
Peak memory 214432 kb
Host smart-a732ff67-a85e-4bec-a443-7b47f6d549d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022654293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1022654293
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3759983763
Short name T1072
Test name
Test status
Simulation time 28178274 ps
CPU time 2 seconds
Started Aug 08 04:49:24 PM PDT 24
Finished Aug 08 04:49:26 PM PDT 24
Peak memory 214292 kb
Host smart-916f4526-fd47-42e7-83f5-a11291b4dcd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759983763 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3759983763
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.437052173
Short name T1013
Test name
Test status
Simulation time 123754243 ps
CPU time 1.13 seconds
Started Aug 08 04:49:27 PM PDT 24
Finished Aug 08 04:49:29 PM PDT 24
Peak memory 206192 kb
Host smart-0e5a418d-10a3-46c5-a203-ec73ee70afe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437052173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.437052173
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.372326951
Short name T1026
Test name
Test status
Simulation time 12248509 ps
CPU time 0.83 seconds
Started Aug 08 04:49:20 PM PDT 24
Finished Aug 08 04:49:21 PM PDT 24
Peak memory 205696 kb
Host smart-7b61abbc-5fcc-4c93-a357-6a80e31948c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372326951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.372326951
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2458284387
Short name T952
Test name
Test status
Simulation time 88313695 ps
CPU time 2.48 seconds
Started Aug 08 04:49:36 PM PDT 24
Finished Aug 08 04:49:39 PM PDT 24
Peak memory 206056 kb
Host smart-929471d6-75a8-4bc5-8e0d-bead21a093c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458284387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2458284387
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3893741099
Short name T1007
Test name
Test status
Simulation time 380343668 ps
CPU time 2.08 seconds
Started Aug 08 04:49:25 PM PDT 24
Finished Aug 08 04:49:28 PM PDT 24
Peak memory 214504 kb
Host smart-320a4f24-e5ba-4f05-9718-8be4cdf12b69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893741099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3893741099
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.605738657
Short name T115
Test name
Test status
Simulation time 757483994 ps
CPU time 9.82 seconds
Started Aug 08 04:49:43 PM PDT 24
Finished Aug 08 04:49:53 PM PDT 24
Peak memory 214556 kb
Host smart-ebdb33d0-c160-492a-b6de-8f63b8d39680
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605738657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.605738657
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3152767409
Short name T191
Test name
Test status
Simulation time 154025488 ps
CPU time 4.08 seconds
Started Aug 08 04:49:15 PM PDT 24
Finished Aug 08 04:49:19 PM PDT 24
Peak memory 214420 kb
Host smart-30b8265b-3e5e-47b2-910f-f8aaa421c74c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152767409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3152767409
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2099841684
Short name T911
Test name
Test status
Simulation time 197289321 ps
CPU time 4.39 seconds
Started Aug 08 04:49:29 PM PDT 24
Finished Aug 08 04:49:33 PM PDT 24
Peak memory 215412 kb
Host smart-e1d0b199-2263-4eed-b239-0419a37440c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099841684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2099841684
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.445523222
Short name T948
Test name
Test status
Simulation time 74975363 ps
CPU time 2.36 seconds
Started Aug 08 04:49:19 PM PDT 24
Finished Aug 08 04:49:22 PM PDT 24
Peak memory 214372 kb
Host smart-1bc85a66-6f78-4380-a788-1041345d5dc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445523222 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.445523222
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3268857407
Short name T929
Test name
Test status
Simulation time 26622899 ps
CPU time 1.33 seconds
Started Aug 08 04:49:43 PM PDT 24
Finished Aug 08 04:49:44 PM PDT 24
Peak memory 205948 kb
Host smart-204a261e-2022-41fd-886c-eff2df18a6d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268857407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3268857407
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1655491076
Short name T938
Test name
Test status
Simulation time 8815892 ps
CPU time 0.82 seconds
Started Aug 08 04:49:19 PM PDT 24
Finished Aug 08 04:49:20 PM PDT 24
Peak memory 205816 kb
Host smart-2d2efccf-3858-45ea-abca-2cba3ebd91a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655491076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1655491076
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1755380959
Short name T984
Test name
Test status
Simulation time 79408332 ps
CPU time 1.94 seconds
Started Aug 08 04:49:31 PM PDT 24
Finished Aug 08 04:49:33 PM PDT 24
Peak memory 206064 kb
Host smart-59d29a72-67ed-4d3f-b228-fe91581947f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755380959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1755380959
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3310553072
Short name T959
Test name
Test status
Simulation time 72627252 ps
CPU time 2.43 seconds
Started Aug 08 04:49:25 PM PDT 24
Finished Aug 08 04:49:28 PM PDT 24
Peak memory 214532 kb
Host smart-bcfc2183-9e01-4453-9474-d72343d35718
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310553072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3310553072
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.4124179416
Short name T933
Test name
Test status
Simulation time 87925450 ps
CPU time 3.77 seconds
Started Aug 08 04:49:17 PM PDT 24
Finished Aug 08 04:49:21 PM PDT 24
Peak memory 222732 kb
Host smart-43ab117a-54ab-4192-89b3-4e173c47af86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124179416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.4124179416
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.125865377
Short name T1079
Test name
Test status
Simulation time 94885136 ps
CPU time 1.84 seconds
Started Aug 08 04:49:22 PM PDT 24
Finished Aug 08 04:49:24 PM PDT 24
Peak memory 214308 kb
Host smart-9c7210ae-70b6-471d-a6a4-8f00a54ec8fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125865377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.125865377
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3205284325
Short name T1037
Test name
Test status
Simulation time 81390988 ps
CPU time 4.29 seconds
Started Aug 08 04:49:00 PM PDT 24
Finished Aug 08 04:49:04 PM PDT 24
Peak memory 206096 kb
Host smart-865c63e6-9e7b-4c3d-975f-b9c7c757eea4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205284325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
205284325
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1762510859
Short name T956
Test name
Test status
Simulation time 2272453607 ps
CPU time 16.22 seconds
Started Aug 08 04:49:04 PM PDT 24
Finished Aug 08 04:49:20 PM PDT 24
Peak memory 206060 kb
Host smart-f0a8efd0-81af-492c-94fc-c010ce3ed4f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762510859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
762510859
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1075581389
Short name T1000
Test name
Test status
Simulation time 25558700 ps
CPU time 1.23 seconds
Started Aug 08 04:49:12 PM PDT 24
Finished Aug 08 04:49:13 PM PDT 24
Peak memory 206364 kb
Host smart-98c68603-b1be-4932-b8b3-3f49986eda35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075581389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
075581389
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1904550291
Short name T924
Test name
Test status
Simulation time 73628748 ps
CPU time 1.38 seconds
Started Aug 08 04:49:03 PM PDT 24
Finished Aug 08 04:49:05 PM PDT 24
Peak memory 214260 kb
Host smart-d37271d5-da79-494e-9469-ab507d229e2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904550291 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1904550291
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2956080888
Short name T138
Test name
Test status
Simulation time 17913120 ps
CPU time 1.12 seconds
Started Aug 08 04:49:11 PM PDT 24
Finished Aug 08 04:49:12 PM PDT 24
Peak memory 206020 kb
Host smart-6f52ce9e-10df-4b3f-b75f-cffb6b9978ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956080888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2956080888
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4153652244
Short name T978
Test name
Test status
Simulation time 31969573 ps
CPU time 0.8 seconds
Started Aug 08 04:49:03 PM PDT 24
Finished Aug 08 04:49:04 PM PDT 24
Peak memory 205692 kb
Host smart-f77a9074-39ab-46ff-8475-cd214cb78ed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153652244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4153652244
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3051531490
Short name T957
Test name
Test status
Simulation time 898443942 ps
CPU time 3.67 seconds
Started Aug 08 04:49:02 PM PDT 24
Finished Aug 08 04:49:06 PM PDT 24
Peak memory 206128 kb
Host smart-4ffbbbd2-7abc-4bc8-a206-8976acfc39d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051531490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3051531490
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4277657413
Short name T939
Test name
Test status
Simulation time 88545210 ps
CPU time 2.16 seconds
Started Aug 08 04:49:18 PM PDT 24
Finished Aug 08 04:49:20 PM PDT 24
Peak memory 214560 kb
Host smart-0b1f179a-c213-43a9-afa1-58fda0ffbf23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277657413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.4277657413
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3064545665
Short name T1029
Test name
Test status
Simulation time 241081141 ps
CPU time 7.05 seconds
Started Aug 08 04:49:25 PM PDT 24
Finished Aug 08 04:49:32 PM PDT 24
Peak memory 214560 kb
Host smart-53c4e469-a42f-4b20-8d19-699f7ac76fbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064545665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3064545665
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2345215506
Short name T937
Test name
Test status
Simulation time 396455717 ps
CPU time 2.44 seconds
Started Aug 08 04:49:18 PM PDT 24
Finished Aug 08 04:49:21 PM PDT 24
Peak memory 214452 kb
Host smart-38e9cfa1-aa78-484f-b289-a354c8e4d6b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345215506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2345215506
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2829936666
Short name T162
Test name
Test status
Simulation time 277560663 ps
CPU time 6.77 seconds
Started Aug 08 04:49:00 PM PDT 24
Finished Aug 08 04:49:07 PM PDT 24
Peak memory 214684 kb
Host smart-373a7f3a-902d-4b61-acd6-0f0b5f2cf695
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829936666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2829936666
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.725024447
Short name T916
Test name
Test status
Simulation time 22910333 ps
CPU time 0.69 seconds
Started Aug 08 04:49:30 PM PDT 24
Finished Aug 08 04:49:31 PM PDT 24
Peak memory 205792 kb
Host smart-466f0259-b548-4601-bc38-4da2dec2c5af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725024447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.725024447
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1154889770
Short name T914
Test name
Test status
Simulation time 57213809 ps
CPU time 0.78 seconds
Started Aug 08 04:49:28 PM PDT 24
Finished Aug 08 04:49:29 PM PDT 24
Peak memory 205832 kb
Host smart-975ce136-c1cd-475d-9fd7-7f25ca3d9d08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154889770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1154889770
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.954297541
Short name T1020
Test name
Test status
Simulation time 17579861 ps
CPU time 0.78 seconds
Started Aug 08 04:49:40 PM PDT 24
Finished Aug 08 04:49:41 PM PDT 24
Peak memory 205748 kb
Host smart-5b0e7d09-0e16-4210-b9f8-1d482c910066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954297541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.954297541
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2472669601
Short name T966
Test name
Test status
Simulation time 19681758 ps
CPU time 0.7 seconds
Started Aug 08 04:49:47 PM PDT 24
Finished Aug 08 04:49:48 PM PDT 24
Peak memory 205748 kb
Host smart-629d6aa8-2f69-4435-a112-4fe00327a0a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472669601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2472669601
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.193790081
Short name T1063
Test name
Test status
Simulation time 14717381 ps
CPU time 0.92 seconds
Started Aug 08 04:49:28 PM PDT 24
Finished Aug 08 04:49:29 PM PDT 24
Peak memory 206012 kb
Host smart-9be0c2d3-709a-41b3-bc4c-e019cbc5c57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193790081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.193790081
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2225594902
Short name T972
Test name
Test status
Simulation time 11598086 ps
CPU time 0.77 seconds
Started Aug 08 04:49:39 PM PDT 24
Finished Aug 08 04:49:40 PM PDT 24
Peak memory 205748 kb
Host smart-f07de2cd-1e3f-48e4-85c1-da723eaac7c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225594902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2225594902
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1887138597
Short name T983
Test name
Test status
Simulation time 16374677 ps
CPU time 0.8 seconds
Started Aug 08 04:49:22 PM PDT 24
Finished Aug 08 04:49:23 PM PDT 24
Peak memory 206144 kb
Host smart-2acd4f67-6e04-4010-a3d3-873c774b0119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887138597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1887138597
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.4115711931
Short name T1034
Test name
Test status
Simulation time 43135312 ps
CPU time 0.88 seconds
Started Aug 08 04:49:29 PM PDT 24
Finished Aug 08 04:49:30 PM PDT 24
Peak memory 205868 kb
Host smart-f9cdab26-03bc-4968-8d10-fd88ba52d84c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115711931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4115711931
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2025253072
Short name T1062
Test name
Test status
Simulation time 17379442 ps
CPU time 0.68 seconds
Started Aug 08 04:49:26 PM PDT 24
Finished Aug 08 04:49:27 PM PDT 24
Peak memory 205732 kb
Host smart-5a39c8fe-945e-4f7f-82bf-acb74aa35b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025253072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2025253072
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3462897410
Short name T1015
Test name
Test status
Simulation time 13224139 ps
CPU time 0.86 seconds
Started Aug 08 04:49:30 PM PDT 24
Finished Aug 08 04:49:31 PM PDT 24
Peak memory 205784 kb
Host smart-d1044a53-be69-4501-9d02-9caaf50881ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462897410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3462897410
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2073736839
Short name T1081
Test name
Test status
Simulation time 246266713 ps
CPU time 7.97 seconds
Started Aug 08 04:48:58 PM PDT 24
Finished Aug 08 04:49:06 PM PDT 24
Peak memory 205992 kb
Host smart-2db43d43-e94a-42dc-a106-8a949f7cccb5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073736839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
073736839
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2246885522
Short name T991
Test name
Test status
Simulation time 145466294 ps
CPU time 6.02 seconds
Started Aug 08 04:49:20 PM PDT 24
Finished Aug 08 04:49:26 PM PDT 24
Peak memory 206096 kb
Host smart-7be40c76-c8e3-46c8-a3c2-910226840b25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246885522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
246885522
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3295575025
Short name T951
Test name
Test status
Simulation time 139759649 ps
CPU time 1.53 seconds
Started Aug 08 04:49:21 PM PDT 24
Finished Aug 08 04:49:22 PM PDT 24
Peak memory 206044 kb
Host smart-226af7ff-e514-4f4e-9d2b-b9a1e0b4cd48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295575025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
295575025
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1372122471
Short name T1038
Test name
Test status
Simulation time 89308154 ps
CPU time 1.4 seconds
Started Aug 08 04:48:59 PM PDT 24
Finished Aug 08 04:49:00 PM PDT 24
Peak memory 216928 kb
Host smart-d5ca2bb9-8e65-4649-844e-fd21bc883cea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372122471 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1372122471
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3817560849
Short name T139
Test name
Test status
Simulation time 268107454 ps
CPU time 1.62 seconds
Started Aug 08 04:49:15 PM PDT 24
Finished Aug 08 04:49:17 PM PDT 24
Peak memory 205892 kb
Host smart-fb18864a-97f8-4c4e-9cbe-f7a6fa2903a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817560849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3817560849
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.815789633
Short name T941
Test name
Test status
Simulation time 17511712 ps
CPU time 0.89 seconds
Started Aug 08 04:49:13 PM PDT 24
Finished Aug 08 04:49:14 PM PDT 24
Peak memory 205792 kb
Host smart-5ab14078-2111-4c43-bc56-a8e5e9dee5b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815789633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.815789633
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.390298451
Short name T1066
Test name
Test status
Simulation time 59954380 ps
CPU time 2.44 seconds
Started Aug 08 04:49:08 PM PDT 24
Finished Aug 08 04:49:11 PM PDT 24
Peak memory 205896 kb
Host smart-bc351a55-35d4-4f8d-81ae-9d8953270111
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390298451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.390298451
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.869423752
Short name T114
Test name
Test status
Simulation time 171175099 ps
CPU time 2.15 seconds
Started Aug 08 04:49:04 PM PDT 24
Finished Aug 08 04:49:06 PM PDT 24
Peak memory 214504 kb
Host smart-9e9d50cc-acef-48be-8c5f-e8b71ed39b1e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869423752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.869423752
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3820182987
Short name T110
Test name
Test status
Simulation time 357352214 ps
CPU time 6.92 seconds
Started Aug 08 04:49:13 PM PDT 24
Finished Aug 08 04:49:21 PM PDT 24
Peak memory 220740 kb
Host smart-53a6ecea-9ad9-46aa-b01d-9c5e70056d8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820182987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3820182987
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1757713903
Short name T982
Test name
Test status
Simulation time 108752341 ps
CPU time 2.72 seconds
Started Aug 08 04:49:05 PM PDT 24
Finished Aug 08 04:49:08 PM PDT 24
Peak memory 214196 kb
Host smart-06952bf1-d21d-4066-8c87-5092dc685bac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757713903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1757713903
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1989244577
Short name T1039
Test name
Test status
Simulation time 526688240 ps
CPU time 4.05 seconds
Started Aug 08 04:49:19 PM PDT 24
Finished Aug 08 04:49:23 PM PDT 24
Peak memory 214232 kb
Host smart-0c815fa7-fb0e-44a5-8660-5a258eb173d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989244577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1989244577
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3323162531
Short name T1001
Test name
Test status
Simulation time 21861807 ps
CPU time 0.75 seconds
Started Aug 08 04:49:19 PM PDT 24
Finished Aug 08 04:49:20 PM PDT 24
Peak memory 205836 kb
Host smart-f5d4062c-83e7-4c80-b43a-9769c4b797ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323162531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3323162531
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3495803018
Short name T1035
Test name
Test status
Simulation time 32505726 ps
CPU time 0.83 seconds
Started Aug 08 04:49:34 PM PDT 24
Finished Aug 08 04:49:35 PM PDT 24
Peak memory 205924 kb
Host smart-6ea11ad6-c614-4fda-817d-ae885e4c8bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495803018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3495803018
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2188489846
Short name T926
Test name
Test status
Simulation time 47852756 ps
CPU time 0.85 seconds
Started Aug 08 04:49:39 PM PDT 24
Finished Aug 08 04:49:40 PM PDT 24
Peak memory 205848 kb
Host smart-f5806a14-fa02-45ec-95e5-c9da74d4a206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188489846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2188489846
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.4088605987
Short name T988
Test name
Test status
Simulation time 14890409 ps
CPU time 0.87 seconds
Started Aug 08 04:49:36 PM PDT 24
Finished Aug 08 04:49:37 PM PDT 24
Peak memory 206036 kb
Host smart-1c28ad89-762e-481e-952b-063309a4e54e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088605987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.4088605987
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.997269331
Short name T1054
Test name
Test status
Simulation time 26734528 ps
CPU time 0.76 seconds
Started Aug 08 04:49:40 PM PDT 24
Finished Aug 08 04:49:40 PM PDT 24
Peak memory 205796 kb
Host smart-7008e0b0-358c-4dc4-a360-7f13f8717ec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997269331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.997269331
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1428129941
Short name T920
Test name
Test status
Simulation time 22641444 ps
CPU time 0.71 seconds
Started Aug 08 04:49:24 PM PDT 24
Finished Aug 08 04:49:25 PM PDT 24
Peak memory 205768 kb
Host smart-dbe3ecb5-2164-4295-9851-2fb89f1d95ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428129941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1428129941
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.980382297
Short name T1064
Test name
Test status
Simulation time 22818064 ps
CPU time 0.74 seconds
Started Aug 08 04:49:24 PM PDT 24
Finished Aug 08 04:49:25 PM PDT 24
Peak memory 205824 kb
Host smart-680b6cdd-c28f-460b-b9bf-57a2c269264b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980382297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.980382297
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2224444761
Short name T1036
Test name
Test status
Simulation time 19324693 ps
CPU time 0.73 seconds
Started Aug 08 04:49:28 PM PDT 24
Finished Aug 08 04:49:29 PM PDT 24
Peak memory 205920 kb
Host smart-9d4cc70a-af30-4160-8095-cfe4d97ca5b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224444761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2224444761
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.174519454
Short name T979
Test name
Test status
Simulation time 46862623 ps
CPU time 0.78 seconds
Started Aug 08 04:49:26 PM PDT 24
Finished Aug 08 04:49:27 PM PDT 24
Peak memory 205792 kb
Host smart-4b7fa219-0e2d-4524-9c0b-4e2bf7abeaa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174519454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.174519454
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2681328388
Short name T943
Test name
Test status
Simulation time 48307063 ps
CPU time 0.87 seconds
Started Aug 08 04:49:47 PM PDT 24
Finished Aug 08 04:49:48 PM PDT 24
Peak memory 205748 kb
Host smart-ffe258c8-f6c3-4c1e-aabd-6ec07cc6dfe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681328388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2681328388
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.235685525
Short name T955
Test name
Test status
Simulation time 9131379274 ps
CPU time 18.75 seconds
Started Aug 08 04:49:18 PM PDT 24
Finished Aug 08 04:49:37 PM PDT 24
Peak memory 206116 kb
Host smart-20b0a938-45b4-4c4b-b63a-d94a48a58b55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235685525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.235685525
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.502683364
Short name T1052
Test name
Test status
Simulation time 1008179246 ps
CPU time 14.34 seconds
Started Aug 08 04:49:20 PM PDT 24
Finished Aug 08 04:49:35 PM PDT 24
Peak memory 206012 kb
Host smart-d5cbdf50-aedc-45be-b3cd-0aa5e184b1f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502683364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.502683364
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.4294317189
Short name T1019
Test name
Test status
Simulation time 31968553 ps
CPU time 1.42 seconds
Started Aug 08 04:48:59 PM PDT 24
Finished Aug 08 04:49:01 PM PDT 24
Peak memory 206092 kb
Host smart-7de83575-60d9-4f26-a672-505ddc914d21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294317189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.4
294317189
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1009003003
Short name T996
Test name
Test status
Simulation time 66234821 ps
CPU time 1.42 seconds
Started Aug 08 04:49:13 PM PDT 24
Finished Aug 08 04:49:15 PM PDT 24
Peak memory 214352 kb
Host smart-3fc6266e-7704-4202-a47a-ce49dbbfbe75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009003003 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1009003003
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1919144794
Short name T1018
Test name
Test status
Simulation time 15588505 ps
CPU time 1.03 seconds
Started Aug 08 04:49:18 PM PDT 24
Finished Aug 08 04:49:19 PM PDT 24
Peak memory 206100 kb
Host smart-7268b54e-fd17-4b32-91a5-07a962ba146c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919144794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1919144794
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1054801178
Short name T964
Test name
Test status
Simulation time 16862872 ps
CPU time 0.73 seconds
Started Aug 08 04:49:12 PM PDT 24
Finished Aug 08 04:49:13 PM PDT 24
Peak memory 205720 kb
Host smart-8e6e27e9-a3a2-4a2b-99a3-369445e846c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054801178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1054801178
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1348312890
Short name T1028
Test name
Test status
Simulation time 60290553 ps
CPU time 2.09 seconds
Started Aug 08 04:49:12 PM PDT 24
Finished Aug 08 04:49:19 PM PDT 24
Peak memory 205876 kb
Host smart-1769ecd8-cbef-4bde-a2cf-4864a841649c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348312890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1348312890
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2931077827
Short name T974
Test name
Test status
Simulation time 486527660 ps
CPU time 3.58 seconds
Started Aug 08 04:49:17 PM PDT 24
Finished Aug 08 04:49:21 PM PDT 24
Peak memory 214436 kb
Host smart-4f4b7ba3-b9d6-485d-b77f-f5c3af48550a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931077827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2931077827
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4189091026
Short name T1003
Test name
Test status
Simulation time 279138967 ps
CPU time 6.36 seconds
Started Aug 08 04:49:14 PM PDT 24
Finished Aug 08 04:49:20 PM PDT 24
Peak memory 214552 kb
Host smart-327b5e49-2b89-44d8-ac69-e40153e2398b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189091026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.4189091026
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3360076435
Short name T919
Test name
Test status
Simulation time 150928996 ps
CPU time 3.14 seconds
Started Aug 08 04:49:00 PM PDT 24
Finished Aug 08 04:49:03 PM PDT 24
Peak memory 216672 kb
Host smart-d0b09329-79ba-4009-8841-fdb24406cb91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360076435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3360076435
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1156936170
Short name T164
Test name
Test status
Simulation time 98375863 ps
CPU time 3.97 seconds
Started Aug 08 04:49:14 PM PDT 24
Finished Aug 08 04:49:19 PM PDT 24
Peak memory 205968 kb
Host smart-c22eddb8-7a51-4dcd-be68-6004c1704d73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156936170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1156936170
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2187695933
Short name T922
Test name
Test status
Simulation time 39064842 ps
CPU time 0.74 seconds
Started Aug 08 04:49:42 PM PDT 24
Finished Aug 08 04:49:48 PM PDT 24
Peak memory 205868 kb
Host smart-f8417411-21b5-4d15-aac6-76535f47781f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187695933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2187695933
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3061423447
Short name T1023
Test name
Test status
Simulation time 30968851 ps
CPU time 0.81 seconds
Started Aug 08 04:49:41 PM PDT 24
Finished Aug 08 04:49:42 PM PDT 24
Peak memory 205768 kb
Host smart-c8c318a7-f914-40ce-b861-54a83a519258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061423447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3061423447
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.363913623
Short name T954
Test name
Test status
Simulation time 18389927 ps
CPU time 0.94 seconds
Started Aug 08 04:49:23 PM PDT 24
Finished Aug 08 04:49:24 PM PDT 24
Peak memory 205984 kb
Host smart-17891154-0a3a-4f58-a5ce-af02da9c1703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363913623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.363913623
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.364362233
Short name T906
Test name
Test status
Simulation time 43066295 ps
CPU time 0.67 seconds
Started Aug 08 04:49:29 PM PDT 24
Finished Aug 08 04:49:30 PM PDT 24
Peak memory 205860 kb
Host smart-ccdfed61-6f3d-4808-9b90-cab959bf972b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364362233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.364362233
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1412096288
Short name T1048
Test name
Test status
Simulation time 21047365 ps
CPU time 0.86 seconds
Started Aug 08 04:49:26 PM PDT 24
Finished Aug 08 04:49:27 PM PDT 24
Peak memory 205940 kb
Host smart-470a393b-d52c-4d99-a743-85539b4e55f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412096288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1412096288
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3306379651
Short name T945
Test name
Test status
Simulation time 15308585 ps
CPU time 0.68 seconds
Started Aug 08 04:49:26 PM PDT 24
Finished Aug 08 04:49:26 PM PDT 24
Peak memory 205840 kb
Host smart-e9971535-cf54-435c-80b9-c4e3f0ed546f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306379651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3306379651
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3735230252
Short name T1059
Test name
Test status
Simulation time 18565264 ps
CPU time 0.71 seconds
Started Aug 08 04:49:47 PM PDT 24
Finished Aug 08 04:49:48 PM PDT 24
Peak memory 205836 kb
Host smart-62048b35-cdbb-4f56-97f4-b61a52cbafac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735230252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3735230252
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1326855019
Short name T1041
Test name
Test status
Simulation time 38265030 ps
CPU time 0.68 seconds
Started Aug 08 04:49:49 PM PDT 24
Finished Aug 08 04:49:50 PM PDT 24
Peak memory 205748 kb
Host smart-4afc3f66-5760-4b02-8f9e-7a5bbd1b071a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326855019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1326855019
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1672004784
Short name T970
Test name
Test status
Simulation time 13125393 ps
CPU time 0.91 seconds
Started Aug 08 04:49:34 PM PDT 24
Finished Aug 08 04:49:35 PM PDT 24
Peak memory 205792 kb
Host smart-474a2ee1-e412-455e-9173-0f952b3bba8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672004784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1672004784
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.627999128
Short name T1017
Test name
Test status
Simulation time 120347908 ps
CPU time 0.86 seconds
Started Aug 08 04:49:35 PM PDT 24
Finished Aug 08 04:49:36 PM PDT 24
Peak memory 205772 kb
Host smart-b19c7cff-1a7e-448c-a463-540cd5c20d51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627999128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.627999128
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.4268262037
Short name T927
Test name
Test status
Simulation time 31555652 ps
CPU time 1.26 seconds
Started Aug 08 04:49:13 PM PDT 24
Finished Aug 08 04:49:15 PM PDT 24
Peak memory 214448 kb
Host smart-e06674d4-0379-459e-acd8-a35446adaa53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268262037 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.4268262037
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3404819259
Short name T141
Test name
Test status
Simulation time 25854252 ps
CPU time 1.09 seconds
Started Aug 08 04:49:10 PM PDT 24
Finished Aug 08 04:49:12 PM PDT 24
Peak memory 206064 kb
Host smart-cafcc8af-6980-498b-b936-02f5a15182a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404819259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3404819259
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3543492506
Short name T1014
Test name
Test status
Simulation time 19323172 ps
CPU time 0.76 seconds
Started Aug 08 04:49:18 PM PDT 24
Finished Aug 08 04:49:19 PM PDT 24
Peak memory 205728 kb
Host smart-f2267840-89ba-4a7e-9755-f143aa39e8a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543492506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3543492506
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.757391981
Short name T1067
Test name
Test status
Simulation time 243330778 ps
CPU time 2.4 seconds
Started Aug 08 04:48:57 PM PDT 24
Finished Aug 08 04:49:00 PM PDT 24
Peak memory 204932 kb
Host smart-fec78bf8-fc26-4857-800e-b39ab0ab7718
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757391981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.757391981
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.4066436686
Short name T1030
Test name
Test status
Simulation time 170660833 ps
CPU time 2.9 seconds
Started Aug 08 04:49:18 PM PDT 24
Finished Aug 08 04:49:22 PM PDT 24
Peak memory 214568 kb
Host smart-60519cf3-8b65-4962-8b43-7c50e0b61191
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066436686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.4066436686
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1033789247
Short name T987
Test name
Test status
Simulation time 88064103 ps
CPU time 3.9 seconds
Started Aug 08 04:49:24 PM PDT 24
Finished Aug 08 04:49:28 PM PDT 24
Peak memory 214576 kb
Host smart-243b28d4-4906-4762-9e60-7442ae374604
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033789247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1033789247
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2899364230
Short name T962
Test name
Test status
Simulation time 56986999 ps
CPU time 2.38 seconds
Started Aug 08 04:49:14 PM PDT 24
Finished Aug 08 04:49:16 PM PDT 24
Peak memory 217444 kb
Host smart-a217fe63-5374-414e-8fc0-b3dc42952c97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899364230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2899364230
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.659749855
Short name T985
Test name
Test status
Simulation time 248635734 ps
CPU time 3.53 seconds
Started Aug 08 04:49:29 PM PDT 24
Finished Aug 08 04:49:32 PM PDT 24
Peak memory 214272 kb
Host smart-160302a7-82d4-47d6-bf5c-f0d941cb58db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659749855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
659749855
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.775139010
Short name T156
Test name
Test status
Simulation time 337772156 ps
CPU time 1.74 seconds
Started Aug 08 04:49:05 PM PDT 24
Finished Aug 08 04:49:07 PM PDT 24
Peak memory 217072 kb
Host smart-affe7236-4524-4dba-8a1c-b3ea4918f025
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775139010 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.775139010
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3856539783
Short name T1046
Test name
Test status
Simulation time 20208042 ps
CPU time 0.88 seconds
Started Aug 08 04:49:02 PM PDT 24
Finished Aug 08 04:49:03 PM PDT 24
Peak memory 205772 kb
Host smart-fef6fdde-08a2-4215-a0b5-0f898ed08d42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856539783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3856539783
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2706797890
Short name T1024
Test name
Test status
Simulation time 25636921 ps
CPU time 0.75 seconds
Started Aug 08 04:48:58 PM PDT 24
Finished Aug 08 04:48:59 PM PDT 24
Peak memory 204692 kb
Host smart-1f5b2d0e-ff5c-42fc-95ec-a390c46962d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706797890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2706797890
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.821437081
Short name T1074
Test name
Test status
Simulation time 85236647 ps
CPU time 2.3 seconds
Started Aug 08 04:49:17 PM PDT 24
Finished Aug 08 04:49:20 PM PDT 24
Peak memory 206032 kb
Host smart-80133480-c3b9-43db-a402-af7c4fe30557
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821437081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.821437081
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3928621823
Short name T980
Test name
Test status
Simulation time 121238584 ps
CPU time 1.47 seconds
Started Aug 08 04:49:14 PM PDT 24
Finished Aug 08 04:49:16 PM PDT 24
Peak memory 214444 kb
Host smart-6ea0a98c-b55b-44bc-8b22-108bc48243ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928621823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3928621823
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3831205217
Short name T1070
Test name
Test status
Simulation time 161186947 ps
CPU time 6.53 seconds
Started Aug 08 04:49:25 PM PDT 24
Finished Aug 08 04:49:31 PM PDT 24
Peak memory 214484 kb
Host smart-c6688f28-21dc-4505-867b-ef2ee1a4f56b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831205217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3831205217
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1263176879
Short name T1068
Test name
Test status
Simulation time 135246281 ps
CPU time 4.62 seconds
Started Aug 08 04:49:18 PM PDT 24
Finished Aug 08 04:49:23 PM PDT 24
Peak memory 214384 kb
Host smart-13e15425-a592-41cf-9788-e13ea7a42a33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263176879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1263176879
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2535821675
Short name T1065
Test name
Test status
Simulation time 130773375 ps
CPU time 5.16 seconds
Started Aug 08 04:49:20 PM PDT 24
Finished Aug 08 04:49:26 PM PDT 24
Peak memory 214160 kb
Host smart-f7d0b23b-0c0f-44d5-b947-0186866ae471
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535821675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2535821675
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.445115211
Short name T950
Test name
Test status
Simulation time 86829562 ps
CPU time 1.51 seconds
Started Aug 08 04:49:17 PM PDT 24
Finished Aug 08 04:49:18 PM PDT 24
Peak memory 214320 kb
Host smart-55fbf235-0404-4918-a1c8-cc3076df01c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445115211 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.445115211
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1469244600
Short name T975
Test name
Test status
Simulation time 22464895 ps
CPU time 1.28 seconds
Started Aug 08 04:49:13 PM PDT 24
Finished Aug 08 04:49:15 PM PDT 24
Peak memory 206088 kb
Host smart-266bb2eb-0190-4711-a8a3-2ab53c874589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469244600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1469244600
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2360000677
Short name T947
Test name
Test status
Simulation time 25305502 ps
CPU time 0.92 seconds
Started Aug 08 04:49:21 PM PDT 24
Finished Aug 08 04:49:22 PM PDT 24
Peak memory 205848 kb
Host smart-db94f3ea-ac8a-4fbf-8ba4-aafc770d4530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360000677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2360000677
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1618740974
Short name T1055
Test name
Test status
Simulation time 74102140 ps
CPU time 1.63 seconds
Started Aug 08 04:49:02 PM PDT 24
Finished Aug 08 04:49:04 PM PDT 24
Peak memory 206172 kb
Host smart-4bc5ba04-bbc0-4ee9-804d-4da298e701f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618740974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1618740974
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3959485021
Short name T989
Test name
Test status
Simulation time 85854735 ps
CPU time 2.63 seconds
Started Aug 08 04:49:14 PM PDT 24
Finished Aug 08 04:49:17 PM PDT 24
Peak memory 214580 kb
Host smart-a6d097a2-a899-4935-be2a-dfe088829a5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959485021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3959485021
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.393492373
Short name T1040
Test name
Test status
Simulation time 168448991 ps
CPU time 6.49 seconds
Started Aug 08 04:49:31 PM PDT 24
Finished Aug 08 04:49:37 PM PDT 24
Peak memory 214520 kb
Host smart-7bfdac47-0d2a-48f6-8d18-c54ea01068cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393492373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.393492373
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3302513035
Short name T973
Test name
Test status
Simulation time 98500098 ps
CPU time 2.14 seconds
Started Aug 08 04:49:09 PM PDT 24
Finished Aug 08 04:49:11 PM PDT 24
Peak memory 214328 kb
Host smart-89ff820d-8ad4-49bb-b336-d6ac1d506fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302513035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3302513035
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3620973321
Short name T153
Test name
Test status
Simulation time 279312649 ps
CPU time 9.1 seconds
Started Aug 08 04:49:24 PM PDT 24
Finished Aug 08 04:49:33 PM PDT 24
Peak memory 214288 kb
Host smart-9b7325f7-6ad1-40b3-a2aa-280739f55944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620973321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3620973321
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2038028820
Short name T1021
Test name
Test status
Simulation time 28891162 ps
CPU time 1.76 seconds
Started Aug 08 04:49:14 PM PDT 24
Finished Aug 08 04:49:16 PM PDT 24
Peak memory 214344 kb
Host smart-c5c22de5-29f2-4020-baff-6ea43975fb20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038028820 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2038028820
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3072190780
Short name T1069
Test name
Test status
Simulation time 13121810 ps
CPU time 1 seconds
Started Aug 08 04:49:14 PM PDT 24
Finished Aug 08 04:49:16 PM PDT 24
Peak memory 206028 kb
Host smart-b1248c8b-70ba-490f-af29-58b21dfd6c44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072190780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3072190780
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2727029049
Short name T923
Test name
Test status
Simulation time 10054500 ps
CPU time 0.71 seconds
Started Aug 08 04:49:06 PM PDT 24
Finished Aug 08 04:49:07 PM PDT 24
Peak memory 205836 kb
Host smart-e9ed373c-69be-4bc3-b195-e92c08a1d88c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727029049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2727029049
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1320826939
Short name T1078
Test name
Test status
Simulation time 112376237 ps
CPU time 2.16 seconds
Started Aug 08 04:49:09 PM PDT 24
Finished Aug 08 04:49:11 PM PDT 24
Peak memory 206016 kb
Host smart-58fe3c4f-5c2c-42de-9d26-91430199fa5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320826939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1320826939
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2508363740
Short name T1011
Test name
Test status
Simulation time 262832460 ps
CPU time 3.08 seconds
Started Aug 08 04:49:17 PM PDT 24
Finished Aug 08 04:49:20 PM PDT 24
Peak memory 214500 kb
Host smart-362d74e8-7793-4fa5-a52a-b1740b3653c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508363740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2508363740
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1920967756
Short name T953
Test name
Test status
Simulation time 325778938 ps
CPU time 3.86 seconds
Started Aug 08 04:49:09 PM PDT 24
Finished Aug 08 04:49:18 PM PDT 24
Peak memory 214464 kb
Host smart-b4041ec0-fbab-4fff-8697-c19076c4829b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920967756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1920967756
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3042786445
Short name T915
Test name
Test status
Simulation time 481508439 ps
CPU time 2.65 seconds
Started Aug 08 04:49:05 PM PDT 24
Finished Aug 08 04:49:08 PM PDT 24
Peak memory 215136 kb
Host smart-cffe7de7-576e-4c35-b63a-b60b309a5a2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042786445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3042786445
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1376516518
Short name T993
Test name
Test status
Simulation time 82463236 ps
CPU time 1.73 seconds
Started Aug 08 04:49:25 PM PDT 24
Finished Aug 08 04:49:27 PM PDT 24
Peak memory 222508 kb
Host smart-9187787f-ec64-4ee7-aab6-3f91ccef4561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376516518 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1376516518
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2812364390
Short name T1049
Test name
Test status
Simulation time 174562424 ps
CPU time 1.22 seconds
Started Aug 08 04:49:08 PM PDT 24
Finished Aug 08 04:49:09 PM PDT 24
Peak memory 206044 kb
Host smart-040c68e6-a689-469f-ad27-759df3b0882f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812364390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2812364390
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3662709575
Short name T1025
Test name
Test status
Simulation time 17959483 ps
CPU time 0.78 seconds
Started Aug 08 04:49:17 PM PDT 24
Finished Aug 08 04:49:18 PM PDT 24
Peak memory 205904 kb
Host smart-05cb9ff5-6598-4b13-876d-40eaaa14f8d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662709575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3662709575
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2982985059
Short name T986
Test name
Test status
Simulation time 358285200 ps
CPU time 3.31 seconds
Started Aug 08 04:49:12 PM PDT 24
Finished Aug 08 04:49:15 PM PDT 24
Peak memory 206184 kb
Host smart-8242dba4-e194-4df5-9ae4-07beabed5b40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982985059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2982985059
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1557527604
Short name T981
Test name
Test status
Simulation time 407013663 ps
CPU time 2.14 seconds
Started Aug 08 04:49:24 PM PDT 24
Finished Aug 08 04:49:26 PM PDT 24
Peak memory 214600 kb
Host smart-02d4f82e-e654-46a9-8b28-ff5d27799fa0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557527604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1557527604
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2107226238
Short name T116
Test name
Test status
Simulation time 224280199 ps
CPU time 5.23 seconds
Started Aug 08 04:49:14 PM PDT 24
Finished Aug 08 04:49:19 PM PDT 24
Peak memory 220732 kb
Host smart-ad5ebf72-fc6f-4fd1-9332-73dbbe3637bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107226238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2107226238
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3314463310
Short name T977
Test name
Test status
Simulation time 20071578 ps
CPU time 1.54 seconds
Started Aug 08 04:49:17 PM PDT 24
Finished Aug 08 04:49:19 PM PDT 24
Peak memory 216588 kb
Host smart-017661d8-d9ad-46e6-b866-b7dea9bb7eaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314463310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3314463310
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.305348735
Short name T163
Test name
Test status
Simulation time 216851576 ps
CPU time 4.87 seconds
Started Aug 08 04:49:08 PM PDT 24
Finished Aug 08 04:49:13 PM PDT 24
Peak memory 214376 kb
Host smart-e355dfed-8ccf-4376-af16-70915072f53b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305348735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
305348735
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3968083001
Short name T692
Test name
Test status
Simulation time 52097979 ps
CPU time 0.88 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:28:58 PM PDT 24
Peak memory 205968 kb
Host smart-677ff801-e2df-43f2-99c5-d63c1a4186b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968083001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3968083001
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.815671597
Short name T11
Test name
Test status
Simulation time 99795588 ps
CPU time 1.88 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:28:59 PM PDT 24
Peak memory 214504 kb
Host smart-52f18f74-473a-4bff-b35b-948764010661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815671597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.815671597
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1333771381
Short name T792
Test name
Test status
Simulation time 87165692 ps
CPU time 3.1 seconds
Started Aug 08 05:28:58 PM PDT 24
Finished Aug 08 05:29:01 PM PDT 24
Peak memory 209692 kb
Host smart-e6b74337-3658-482f-9839-855e29b8f86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333771381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1333771381
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.4085883718
Short name T297
Test name
Test status
Simulation time 226053159 ps
CPU time 2.44 seconds
Started Aug 08 05:28:56 PM PDT 24
Finished Aug 08 05:28:58 PM PDT 24
Peak memory 214228 kb
Host smart-92f65e4e-0689-4f2d-bbc6-8dba8f91c9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085883718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4085883718
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1519218542
Short name T632
Test name
Test status
Simulation time 149598097 ps
CPU time 4.15 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:29:01 PM PDT 24
Peak memory 220264 kb
Host smart-83bc02be-6f11-4058-9c6d-edece842e03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519218542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1519218542
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.896783002
Short name T100
Test name
Test status
Simulation time 1034563686 ps
CPU time 16.11 seconds
Started Aug 08 05:28:55 PM PDT 24
Finished Aug 08 05:29:11 PM PDT 24
Peak memory 235508 kb
Host smart-00e45e01-6caa-418d-bad8-074b117515b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896783002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.896783002
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1040048005
Short name T599
Test name
Test status
Simulation time 733500641 ps
CPU time 7.09 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:29:04 PM PDT 24
Peak memory 208136 kb
Host smart-df40bdb9-698b-420d-8164-9e2f76b8582f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040048005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1040048005
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2301291858
Short name T576
Test name
Test status
Simulation time 451095069 ps
CPU time 2.63 seconds
Started Aug 08 05:28:59 PM PDT 24
Finished Aug 08 05:29:01 PM PDT 24
Peak memory 206836 kb
Host smart-3a17e045-b986-45c4-837e-ec05644c8410
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301291858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2301291858
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3682944168
Short name T621
Test name
Test status
Simulation time 2092543580 ps
CPU time 4.93 seconds
Started Aug 08 05:28:58 PM PDT 24
Finished Aug 08 05:29:03 PM PDT 24
Peak memory 207052 kb
Host smart-52cdf490-cb4d-4094-b841-82ee9ed359f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682944168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3682944168
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.4176456427
Short name T557
Test name
Test status
Simulation time 155430789 ps
CPU time 3.69 seconds
Started Aug 08 05:28:58 PM PDT 24
Finished Aug 08 05:29:02 PM PDT 24
Peak memory 208856 kb
Host smart-c2a3604b-3912-4c81-8b08-88ce09f79c8c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176456427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.4176456427
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1759322607
Short name T879
Test name
Test status
Simulation time 98948791 ps
CPU time 2.31 seconds
Started Aug 08 05:28:56 PM PDT 24
Finished Aug 08 05:28:59 PM PDT 24
Peak memory 209820 kb
Host smart-06b12525-8c27-46a4-b339-f07ffddbaa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759322607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1759322607
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.855580912
Short name T847
Test name
Test status
Simulation time 24245773 ps
CPU time 1.97 seconds
Started Aug 08 05:28:59 PM PDT 24
Finished Aug 08 05:29:01 PM PDT 24
Peak memory 208648 kb
Host smart-acfe3f5f-059a-4f7a-89bb-ec8015375554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855580912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.855580912
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2854909999
Short name T344
Test name
Test status
Simulation time 218386677 ps
CPU time 9.21 seconds
Started Aug 08 05:28:56 PM PDT 24
Finished Aug 08 05:29:05 PM PDT 24
Peak memory 220808 kb
Host smart-55018cbc-0247-4276-97f2-74fd29b0cf2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854909999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2854909999
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.123648105
Short name T386
Test name
Test status
Simulation time 2282012699 ps
CPU time 35.2 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:29:32 PM PDT 24
Peak memory 209128 kb
Host smart-f6449c01-1da9-4bf4-aa93-1aa437f2f407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123648105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.123648105
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1942765132
Short name T112
Test name
Test status
Simulation time 89868904 ps
CPU time 2.23 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:28:59 PM PDT 24
Peak memory 210236 kb
Host smart-3dda0688-3b6d-43a5-813e-0414ec8177a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942765132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1942765132
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1884073590
Short name T872
Test name
Test status
Simulation time 14759959 ps
CPU time 0.74 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:28:57 PM PDT 24
Peak memory 205916 kb
Host smart-f6dbc65a-8b31-4450-bed6-d248cd184daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884073590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1884073590
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.4006802191
Short name T261
Test name
Test status
Simulation time 55373504 ps
CPU time 3.86 seconds
Started Aug 08 05:28:58 PM PDT 24
Finished Aug 08 05:29:02 PM PDT 24
Peak memory 214336 kb
Host smart-ef922c44-ce6d-45de-a94a-f703a361c9f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006802191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.4006802191
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.298858141
Short name T540
Test name
Test status
Simulation time 148207626 ps
CPU time 1.65 seconds
Started Aug 08 05:28:55 PM PDT 24
Finished Aug 08 05:28:57 PM PDT 24
Peak memory 208292 kb
Host smart-574104a5-f548-4b51-af22-e911364fac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298858141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.298858141
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1944459898
Short name T299
Test name
Test status
Simulation time 374220388 ps
CPU time 4.77 seconds
Started Aug 08 05:28:58 PM PDT 24
Finished Aug 08 05:29:02 PM PDT 24
Peak memory 222512 kb
Host smart-0114bc2f-3425-4a04-8516-7fe25104d7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944459898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1944459898
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3363218400
Short name T693
Test name
Test status
Simulation time 48921617 ps
CPU time 2.25 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:28:59 PM PDT 24
Peak memory 214180 kb
Host smart-2c37d04c-b0a4-4459-b2a8-0e6f4ea0d0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363218400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3363218400
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.856347263
Short name T202
Test name
Test status
Simulation time 186489560 ps
CPU time 2.94 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:29:00 PM PDT 24
Peak memory 214920 kb
Host smart-fcc14dad-5378-4427-b50d-7659f443e836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856347263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.856347263
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2939555624
Short name T181
Test name
Test status
Simulation time 315375863 ps
CPU time 4.07 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:29:01 PM PDT 24
Peak memory 207388 kb
Host smart-9184f04f-9b20-41ac-92f2-5f8324df3b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939555624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2939555624
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2345630332
Short name T590
Test name
Test status
Simulation time 167029376 ps
CPU time 3.17 seconds
Started Aug 08 05:28:56 PM PDT 24
Finished Aug 08 05:29:00 PM PDT 24
Peak memory 206768 kb
Host smart-79a285dd-95b8-49d8-b817-f385fcababc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345630332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2345630332
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1881643998
Short name T513
Test name
Test status
Simulation time 133385551 ps
CPU time 3.94 seconds
Started Aug 08 05:28:55 PM PDT 24
Finished Aug 08 05:28:59 PM PDT 24
Peak memory 207032 kb
Host smart-c875b018-1a67-4ef3-88bd-5cff0a336c8e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881643998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1881643998
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3207561170
Short name T511
Test name
Test status
Simulation time 210767684 ps
CPU time 2.43 seconds
Started Aug 08 05:28:56 PM PDT 24
Finished Aug 08 05:28:58 PM PDT 24
Peak memory 206972 kb
Host smart-ceb9152e-5288-4bf6-a3d5-44f393c85369
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207561170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3207561170
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.872071910
Short name T827
Test name
Test status
Simulation time 2212944523 ps
CPU time 41.62 seconds
Started Aug 08 05:28:56 PM PDT 24
Finished Aug 08 05:29:38 PM PDT 24
Peak memory 207836 kb
Host smart-70f7aea5-59a2-4c09-92df-002161facb96
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872071910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.872071910
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4184910877
Short name T472
Test name
Test status
Simulation time 42155411 ps
CPU time 2.15 seconds
Started Aug 08 05:28:59 PM PDT 24
Finished Aug 08 05:29:01 PM PDT 24
Peak memory 208064 kb
Host smart-0e3a5d8a-03e0-4c7e-9a18-071cf40628c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184910877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4184910877
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2568770628
Short name T637
Test name
Test status
Simulation time 209361369 ps
CPU time 4.75 seconds
Started Aug 08 05:28:58 PM PDT 24
Finished Aug 08 05:29:03 PM PDT 24
Peak memory 206656 kb
Host smart-5d51a9ef-2d8b-4e7d-98ad-675e43f62f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568770628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2568770628
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3262216520
Short name T70
Test name
Test status
Simulation time 12177044109 ps
CPU time 17.38 seconds
Started Aug 08 05:29:01 PM PDT 24
Finished Aug 08 05:29:19 PM PDT 24
Peak memory 217048 kb
Host smart-91037c70-f34e-49bc-aa70-c89bd46945a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262216520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3262216520
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.225881249
Short name T184
Test name
Test status
Simulation time 124176921 ps
CPU time 3.49 seconds
Started Aug 08 05:28:59 PM PDT 24
Finished Aug 08 05:29:02 PM PDT 24
Peak memory 207356 kb
Host smart-060da34e-0b3a-4f6d-bc63-0bf3058991fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225881249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.225881249
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2987293189
Short name T493
Test name
Test status
Simulation time 64050833 ps
CPU time 2.68 seconds
Started Aug 08 05:28:58 PM PDT 24
Finished Aug 08 05:29:01 PM PDT 24
Peak memory 210296 kb
Host smart-d103b610-9028-417c-9595-2e3e2184167e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987293189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2987293189
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.11773120
Short name T779
Test name
Test status
Simulation time 40510793 ps
CPU time 0.86 seconds
Started Aug 08 05:29:43 PM PDT 24
Finished Aug 08 05:29:44 PM PDT 24
Peak memory 205984 kb
Host smart-1614aa83-b343-43f7-bf64-0266f2170ade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11773120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.11773120
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.402816536
Short name T392
Test name
Test status
Simulation time 497753118 ps
CPU time 3.71 seconds
Started Aug 08 05:29:31 PM PDT 24
Finished Aug 08 05:29:34 PM PDT 24
Peak memory 215392 kb
Host smart-d263cf64-371e-478f-927c-140dddb69296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402816536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.402816536
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1929390929
Short name T890
Test name
Test status
Simulation time 66559891 ps
CPU time 3.41 seconds
Started Aug 08 05:29:31 PM PDT 24
Finished Aug 08 05:29:34 PM PDT 24
Peak memory 208420 kb
Host smart-517c1851-2117-4078-8a6d-f15eb09df572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929390929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1929390929
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3108019392
Short name T57
Test name
Test status
Simulation time 194498421 ps
CPU time 2.92 seconds
Started Aug 08 05:29:31 PM PDT 24
Finished Aug 08 05:29:34 PM PDT 24
Peak memory 218132 kb
Host smart-57008c1e-cd3a-4cf2-9b9d-cce9e6cb8728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108019392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3108019392
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1041619699
Short name T257
Test name
Test status
Simulation time 1354525921 ps
CPU time 3.96 seconds
Started Aug 08 05:29:30 PM PDT 24
Finished Aug 08 05:29:34 PM PDT 24
Peak memory 220108 kb
Host smart-6664a57a-d63e-4257-8f89-5705b40a211b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041619699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1041619699
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1316984331
Short name T549
Test name
Test status
Simulation time 149299892 ps
CPU time 5.41 seconds
Started Aug 08 05:29:34 PM PDT 24
Finished Aug 08 05:29:40 PM PDT 24
Peak memory 207184 kb
Host smart-e5b8afc4-e9f9-4438-861d-fdcde82059bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316984331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1316984331
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3154184497
Short name T510
Test name
Test status
Simulation time 3543167887 ps
CPU time 28.1 seconds
Started Aug 08 05:29:29 PM PDT 24
Finished Aug 08 05:29:58 PM PDT 24
Peak memory 208432 kb
Host smart-d391e846-85b0-4827-b866-8bb22b81878b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154184497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3154184497
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.170844691
Short name T417
Test name
Test status
Simulation time 115714515 ps
CPU time 3.05 seconds
Started Aug 08 05:29:30 PM PDT 24
Finished Aug 08 05:29:33 PM PDT 24
Peak memory 206936 kb
Host smart-06ce7d91-cfb0-43f3-a5f9-17806c94dede
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170844691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.170844691
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2704248485
Short name T463
Test name
Test status
Simulation time 385179121 ps
CPU time 6.52 seconds
Started Aug 08 05:29:30 PM PDT 24
Finished Aug 08 05:29:36 PM PDT 24
Peak memory 208784 kb
Host smart-1a29c389-c2d3-4702-a8a0-275f8ad41e1e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704248485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2704248485
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.952778957
Short name T583
Test name
Test status
Simulation time 1484555389 ps
CPU time 14.59 seconds
Started Aug 08 05:29:34 PM PDT 24
Finished Aug 08 05:29:49 PM PDT 24
Peak memory 208516 kb
Host smart-b839a888-22a7-4990-bf0b-5b030f7131b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952778957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.952778957
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2172032348
Short name T76
Test name
Test status
Simulation time 748268399 ps
CPU time 19.17 seconds
Started Aug 08 05:29:42 PM PDT 24
Finished Aug 08 05:30:01 PM PDT 24
Peak memory 208456 kb
Host smart-2aad0d0c-2da1-403b-8d7f-c6272fa03505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172032348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2172032348
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2581069745
Short name T849
Test name
Test status
Simulation time 1185027657 ps
CPU time 8.46 seconds
Started Aug 08 05:29:31 PM PDT 24
Finished Aug 08 05:29:39 PM PDT 24
Peak memory 208432 kb
Host smart-a63c1eaf-5bbe-44de-a870-f1c6e6e46186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581069745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2581069745
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3837776865
Short name T276
Test name
Test status
Simulation time 1570122346 ps
CPU time 22.48 seconds
Started Aug 08 05:29:33 PM PDT 24
Finished Aug 08 05:29:55 PM PDT 24
Peak memory 218436 kb
Host smart-d56f587d-8a94-4015-9a60-7b18992a01ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837776865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3837776865
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.4056580865
Short name T54
Test name
Test status
Simulation time 50703296 ps
CPU time 1.9 seconds
Started Aug 08 05:29:31 PM PDT 24
Finished Aug 08 05:29:33 PM PDT 24
Peak memory 210136 kb
Host smart-cf1ac35b-303c-44fc-839d-fae1d2585e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056580865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.4056580865
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3282880331
Short name T457
Test name
Test status
Simulation time 652067434 ps
CPU time 4.9 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:29:46 PM PDT 24
Peak memory 208728 kb
Host smart-d64bff6d-59fc-4569-8dd7-8fedfddb7303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282880331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3282880331
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.351045138
Short name T246
Test name
Test status
Simulation time 95765762 ps
CPU time 2.85 seconds
Started Aug 08 05:29:42 PM PDT 24
Finished Aug 08 05:29:45 PM PDT 24
Peak memory 214332 kb
Host smart-63c3205e-7686-4097-a16a-1c3ca44418df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351045138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.351045138
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.4270490630
Short name T588
Test name
Test status
Simulation time 1222674030 ps
CPU time 12.27 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:52 PM PDT 24
Peak memory 222464 kb
Host smart-e1c88b3e-6d56-4997-b8ab-28bd6b0e6466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270490630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.4270490630
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1195513868
Short name T603
Test name
Test status
Simulation time 154769309 ps
CPU time 2.76 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:43 PM PDT 24
Peak memory 221132 kb
Host smart-d74c7cbb-b5ee-44a7-b61b-9bfffb5f5c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195513868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1195513868
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3550989672
Short name T807
Test name
Test status
Simulation time 545791880 ps
CPU time 5.05 seconds
Started Aug 08 05:29:32 PM PDT 24
Finished Aug 08 05:29:37 PM PDT 24
Peak memory 208360 kb
Host smart-0d05f2b6-3414-403f-b4eb-e6a9830f706e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550989672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3550989672
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.925198883
Short name T473
Test name
Test status
Simulation time 389523016 ps
CPU time 6.07 seconds
Started Aug 08 05:29:43 PM PDT 24
Finished Aug 08 05:29:49 PM PDT 24
Peak memory 208008 kb
Host smart-2a6a8313-15a5-4009-bc35-31152d002a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925198883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.925198883
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.4259826401
Short name T719
Test name
Test status
Simulation time 187720674 ps
CPU time 4.84 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:29:46 PM PDT 24
Peak memory 208628 kb
Host smart-e9916c3c-44e8-47c2-a288-6a833021ac59
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259826401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4259826401
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.645863084
Short name T709
Test name
Test status
Simulation time 67691944 ps
CPU time 3.37 seconds
Started Aug 08 05:29:35 PM PDT 24
Finished Aug 08 05:29:38 PM PDT 24
Peak memory 208688 kb
Host smart-9a5151d5-e742-455d-9012-334b0e968764
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645863084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.645863084
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.4243642071
Short name T502
Test name
Test status
Simulation time 304486812 ps
CPU time 3.43 seconds
Started Aug 08 05:29:38 PM PDT 24
Finished Aug 08 05:29:41 PM PDT 24
Peak memory 208712 kb
Host smart-b294e9fe-13eb-49b4-9a44-dd247f3de046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243642071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.4243642071
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.454311979
Short name T836
Test name
Test status
Simulation time 1730913116 ps
CPU time 5.1 seconds
Started Aug 08 05:29:29 PM PDT 24
Finished Aug 08 05:29:35 PM PDT 24
Peak memory 206892 kb
Host smart-6b12f976-eaa2-4f77-81fb-9f4bc7651d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454311979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.454311979
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2973774924
Short name T71
Test name
Test status
Simulation time 1695649822 ps
CPU time 49.48 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:30:30 PM PDT 24
Peak memory 216824 kb
Host smart-f8331b77-d9a9-4c47-ad4c-2efdc0a10ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973774924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2973774924
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3686054864
Short name T801
Test name
Test status
Simulation time 1907788216 ps
CPU time 18.84 seconds
Started Aug 08 05:29:39 PM PDT 24
Finished Aug 08 05:29:58 PM PDT 24
Peak memory 221100 kb
Host smart-5d7a2e12-49da-4177-bf9a-a4dc6035ce3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686054864 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3686054864
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2750185798
Short name T521
Test name
Test status
Simulation time 223766699 ps
CPU time 4.2 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:29:45 PM PDT 24
Peak memory 210340 kb
Host smart-83cbfbb5-9671-45a1-8cf4-7c5b3ae89bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750185798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2750185798
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2090461739
Short name T351
Test name
Test status
Simulation time 112132329 ps
CPU time 1.82 seconds
Started Aug 08 05:29:39 PM PDT 24
Finished Aug 08 05:29:41 PM PDT 24
Peak memory 210260 kb
Host smart-6884db2f-1951-4873-baaa-de9ddd6ee4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090461739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2090461739
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.4191117113
Short name T753
Test name
Test status
Simulation time 9625364 ps
CPU time 0.81 seconds
Started Aug 08 05:29:42 PM PDT 24
Finished Aug 08 05:29:42 PM PDT 24
Peak memory 205964 kb
Host smart-0740aff8-900f-4394-b315-84f8a09af9b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191117113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.4191117113
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3821566305
Short name T38
Test name
Test status
Simulation time 135288674 ps
CPU time 3.44 seconds
Started Aug 08 05:29:39 PM PDT 24
Finished Aug 08 05:29:43 PM PDT 24
Peak memory 214184 kb
Host smart-4cafd989-6d8f-46a3-9260-37d5998eaefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821566305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3821566305
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1444617894
Short name T58
Test name
Test status
Simulation time 286258410 ps
CPU time 6.31 seconds
Started Aug 08 05:29:39 PM PDT 24
Finished Aug 08 05:29:45 PM PDT 24
Peak memory 222520 kb
Host smart-7fc1861b-5ecf-4648-a76e-c8115481d48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444617894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1444617894
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.879249310
Short name T91
Test name
Test status
Simulation time 141170989 ps
CPU time 4.6 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:44 PM PDT 24
Peak memory 208696 kb
Host smart-31803add-f3a2-4b86-b87f-86dd12025d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879249310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.879249310
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1279254613
Short name T543
Test name
Test status
Simulation time 112703797 ps
CPU time 2.36 seconds
Started Aug 08 05:29:39 PM PDT 24
Finished Aug 08 05:29:42 PM PDT 24
Peak memory 214288 kb
Host smart-902442c2-3876-4b4b-aff9-0c2c21b2bc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279254613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1279254613
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3711744469
Short name T828
Test name
Test status
Simulation time 2211953463 ps
CPU time 55.46 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:30:36 PM PDT 24
Peak memory 209244 kb
Host smart-5c383fec-1d88-49d1-bc7f-f28e7048094e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711744469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3711744469
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2276491423
Short name T333
Test name
Test status
Simulation time 986496983 ps
CPU time 4.77 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:29:46 PM PDT 24
Peak memory 207036 kb
Host smart-a6200f33-daba-48d5-ae2a-5aa2ec2945d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276491423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2276491423
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2106701741
Short name T514
Test name
Test status
Simulation time 341060493 ps
CPU time 2.47 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:29:44 PM PDT 24
Peak memory 207472 kb
Host smart-442be4fe-0b23-4555-b08d-c8744f15aa63
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106701741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2106701741
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3151509758
Short name T591
Test name
Test status
Simulation time 117494861 ps
CPU time 3.08 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:29:44 PM PDT 24
Peak memory 206984 kb
Host smart-3e3f0220-383b-47b8-a5e2-5bfd397e4a22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151509758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3151509758
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2816527334
Short name T895
Test name
Test status
Simulation time 22467559 ps
CPU time 1.61 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:42 PM PDT 24
Peak memory 208184 kb
Host smart-e6894313-a19d-474c-846a-8ce860d75521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816527334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2816527334
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2926890946
Short name T730
Test name
Test status
Simulation time 217025722 ps
CPU time 2.88 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:43 PM PDT 24
Peak memory 208424 kb
Host smart-b0ae674c-d3f6-4003-bcb4-b6c84adc5c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926890946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2926890946
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.306004575
Short name T577
Test name
Test status
Simulation time 11372562201 ps
CPU time 51.46 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:30:32 PM PDT 24
Peak memory 215120 kb
Host smart-3f8dd893-2f95-4815-94d6-8cd34212148f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306004575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.306004575
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3482593175
Short name T556
Test name
Test status
Simulation time 3223701944 ps
CPU time 10.18 seconds
Started Aug 08 05:29:38 PM PDT 24
Finished Aug 08 05:29:49 PM PDT 24
Peak memory 222536 kb
Host smart-3b49b6e5-1717-47eb-86cf-b0068306e2d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482593175 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3482593175
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3357039997
Short name T623
Test name
Test status
Simulation time 221858823 ps
CPU time 3.9 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:29:45 PM PDT 24
Peak memory 208756 kb
Host smart-439a8b28-741c-4074-9ef5-3a709264506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357039997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3357039997
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2429627476
Short name T165
Test name
Test status
Simulation time 1606323785 ps
CPU time 8.63 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:49 PM PDT 24
Peak memory 210384 kb
Host smart-9a22c2b4-9078-4673-be1d-c3c57362bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429627476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2429627476
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.333514721
Short name T553
Test name
Test status
Simulation time 81197854 ps
CPU time 0.83 seconds
Started Aug 08 05:29:53 PM PDT 24
Finished Aug 08 05:29:54 PM PDT 24
Peak memory 205952 kb
Host smart-578e56da-9dc5-4312-ba1e-823a1062595c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333514721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.333514721
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1403015251
Short name T379
Test name
Test status
Simulation time 2433700044 ps
CPU time 60.7 seconds
Started Aug 08 05:29:39 PM PDT 24
Finished Aug 08 05:30:40 PM PDT 24
Peak memory 215848 kb
Host smart-89cef4e7-6e1b-49d2-a8f9-60ebd5932383
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403015251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1403015251
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2064621778
Short name T664
Test name
Test status
Simulation time 246318996 ps
CPU time 5.08 seconds
Started Aug 08 05:29:44 PM PDT 24
Finished Aug 08 05:29:49 PM PDT 24
Peak memory 208216 kb
Host smart-777ad5dc-104e-41bb-a449-5aefc81de795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064621778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2064621778
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.955356719
Short name T625
Test name
Test status
Simulation time 123866259 ps
CPU time 2.81 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:43 PM PDT 24
Peak memory 210168 kb
Host smart-4fc17a4d-da92-41a4-85b8-7c900e4dc4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955356719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.955356719
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1009118030
Short name T80
Test name
Test status
Simulation time 327492333 ps
CPU time 4.63 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:29:46 PM PDT 24
Peak memory 214324 kb
Host smart-6f3511c3-6ebe-40a6-a296-cf2f4d469c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009118030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1009118030
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1263981437
Short name T420
Test name
Test status
Simulation time 517932866 ps
CPU time 3.65 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:44 PM PDT 24
Peak memory 214224 kb
Host smart-c2068cc5-6496-4891-a692-655c237379ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263981437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1263981437
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2981109561
Short name T826
Test name
Test status
Simulation time 252952394 ps
CPU time 5.39 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:45 PM PDT 24
Peak memory 209184 kb
Host smart-ab470241-714f-499d-b693-061bfe64ef66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981109561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2981109561
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1228808715
Short name T367
Test name
Test status
Simulation time 359175144 ps
CPU time 4.62 seconds
Started Aug 08 05:29:42 PM PDT 24
Finished Aug 08 05:29:47 PM PDT 24
Peak memory 208588 kb
Host smart-d58fcaab-ed9f-435f-a370-6bb2b88a6077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228808715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1228808715
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.911370694
Short name T518
Test name
Test status
Simulation time 45043514 ps
CPU time 2.48 seconds
Started Aug 08 05:29:39 PM PDT 24
Finished Aug 08 05:29:42 PM PDT 24
Peak memory 207448 kb
Host smart-4afb9e5e-ed6c-4e54-9c1c-9adf7d7026f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911370694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.911370694
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3797804202
Short name T548
Test name
Test status
Simulation time 68782560 ps
CPU time 2.7 seconds
Started Aug 08 05:29:42 PM PDT 24
Finished Aug 08 05:29:44 PM PDT 24
Peak memory 206976 kb
Host smart-351a76f3-af77-4520-9410-53bc82d32eb2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797804202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3797804202
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2060389429
Short name T281
Test name
Test status
Simulation time 62475742 ps
CPU time 2.34 seconds
Started Aug 08 05:29:44 PM PDT 24
Finished Aug 08 05:29:47 PM PDT 24
Peak memory 207444 kb
Host smart-b79e9227-4d2a-44f8-b559-64ac193b920a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060389429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2060389429
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3981449755
Short name T568
Test name
Test status
Simulation time 86912840 ps
CPU time 3.69 seconds
Started Aug 08 05:29:39 PM PDT 24
Finished Aug 08 05:29:43 PM PDT 24
Peak memory 209348 kb
Host smart-1cd6fa68-c5c1-4f29-83f3-ac6a25cca554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981449755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3981449755
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1533371041
Short name T188
Test name
Test status
Simulation time 204162789 ps
CPU time 2.54 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:42 PM PDT 24
Peak memory 206888 kb
Host smart-7cf4e468-fe72-45f2-bad8-36905558fc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533371041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1533371041
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2895758628
Short name T574
Test name
Test status
Simulation time 978326721 ps
CPU time 26.11 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:30:07 PM PDT 24
Peak memory 216836 kb
Host smart-bbef34c7-c5a9-41f9-a47a-070d99b8a961
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895758628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2895758628
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.4237872617
Short name T177
Test name
Test status
Simulation time 2678703896 ps
CPU time 25.03 seconds
Started Aug 08 05:29:53 PM PDT 24
Finished Aug 08 05:30:18 PM PDT 24
Peak memory 220436 kb
Host smart-93e5b71a-5edf-48b6-9623-89db303f495b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237872617 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.4237872617
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2568890063
Short name T649
Test name
Test status
Simulation time 132232030 ps
CPU time 3.5 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:29:44 PM PDT 24
Peak memory 208760 kb
Host smart-5d107412-1b82-4853-a445-e9287d12075d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568890063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2568890063
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.673922492
Short name T560
Test name
Test status
Simulation time 121492851 ps
CPU time 2.26 seconds
Started Aug 08 05:29:43 PM PDT 24
Finished Aug 08 05:29:45 PM PDT 24
Peak memory 209760 kb
Host smart-860e1dbf-d970-45ca-bd13-9330203e3671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673922492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.673922492
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.34071177
Short name T462
Test name
Test status
Simulation time 43970664 ps
CPU time 0.75 seconds
Started Aug 08 05:29:51 PM PDT 24
Finished Aug 08 05:29:52 PM PDT 24
Peak memory 206024 kb
Host smart-b21dfc71-b94c-485e-b37d-d3c3fb44ea6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34071177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.34071177
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.542923800
Short name T871
Test name
Test status
Simulation time 34433268 ps
CPU time 2.36 seconds
Started Aug 08 05:29:53 PM PDT 24
Finished Aug 08 05:29:55 PM PDT 24
Peak memory 217056 kb
Host smart-31dd6d7f-64e2-4454-9947-1317c2e83567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542923800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.542923800
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3664176457
Short name T244
Test name
Test status
Simulation time 406903213 ps
CPU time 2.81 seconds
Started Aug 08 05:29:55 PM PDT 24
Finished Aug 08 05:29:58 PM PDT 24
Peak memory 208880 kb
Host smart-56ee7bdb-c2d8-4a7e-9959-5c7a7190892b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664176457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3664176457
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3230491372
Short name T183
Test name
Test status
Simulation time 108756236 ps
CPU time 5.29 seconds
Started Aug 08 05:29:53 PM PDT 24
Finished Aug 08 05:29:59 PM PDT 24
Peak memory 221612 kb
Host smart-1cf83f4f-f8ac-4e54-a2dd-4da543aff8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230491372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3230491372
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1728078938
Short name T247
Test name
Test status
Simulation time 132572443 ps
CPU time 2.31 seconds
Started Aug 08 05:29:51 PM PDT 24
Finished Aug 08 05:29:54 PM PDT 24
Peak memory 214224 kb
Host smart-d6f13909-0506-4423-b1b7-3f4df47e1c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728078938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1728078938
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.713311992
Short name T602
Test name
Test status
Simulation time 35724863 ps
CPU time 2.37 seconds
Started Aug 08 05:29:54 PM PDT 24
Finished Aug 08 05:29:56 PM PDT 24
Peak memory 220392 kb
Host smart-aae0dc95-3bf5-41f6-979b-b0954c5db537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713311992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.713311992
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.468631163
Short name T799
Test name
Test status
Simulation time 100282246 ps
CPU time 4.73 seconds
Started Aug 08 05:29:52 PM PDT 24
Finished Aug 08 05:29:57 PM PDT 24
Peak memory 209168 kb
Host smart-7ec6dacd-2357-4523-b772-920efd1b527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468631163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.468631163
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3095610710
Short name T886
Test name
Test status
Simulation time 230911589 ps
CPU time 3.3 seconds
Started Aug 08 05:29:55 PM PDT 24
Finished Aug 08 05:29:58 PM PDT 24
Peak memory 208628 kb
Host smart-24807f84-5359-4bec-a2b7-c32b94641dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095610710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3095610710
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2506208384
Short name T524
Test name
Test status
Simulation time 233433191 ps
CPU time 6.05 seconds
Started Aug 08 05:29:58 PM PDT 24
Finished Aug 08 05:30:04 PM PDT 24
Peak memory 208952 kb
Host smart-1b0e600e-e217-46f0-b2f1-5752bb390289
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506208384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2506208384
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2850509227
Short name T406
Test name
Test status
Simulation time 27749646 ps
CPU time 2.14 seconds
Started Aug 08 05:29:52 PM PDT 24
Finished Aug 08 05:29:54 PM PDT 24
Peak memory 208652 kb
Host smart-1c321fe6-e111-4740-8049-425b873ce719
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850509227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2850509227
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3802705632
Short name T773
Test name
Test status
Simulation time 110864288 ps
CPU time 3.47 seconds
Started Aug 08 05:29:52 PM PDT 24
Finished Aug 08 05:29:56 PM PDT 24
Peak memory 206952 kb
Host smart-b709b61c-c974-4401-a410-19881aa6d22a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802705632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3802705632
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1559414177
Short name T822
Test name
Test status
Simulation time 95435793 ps
CPU time 4.4 seconds
Started Aug 08 05:29:52 PM PDT 24
Finished Aug 08 05:29:57 PM PDT 24
Peak memory 209888 kb
Host smart-d217a785-c844-4223-851a-8964225b96ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559414177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1559414177
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.647419737
Short name T666
Test name
Test status
Simulation time 1885663774 ps
CPU time 10.46 seconds
Started Aug 08 05:29:57 PM PDT 24
Finished Aug 08 05:30:07 PM PDT 24
Peak memory 207920 kb
Host smart-d2052fb2-af7f-41a8-9db4-a6319d28adb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647419737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.647419737
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3254140019
Short name T121
Test name
Test status
Simulation time 3786349892 ps
CPU time 21.84 seconds
Started Aug 08 05:29:54 PM PDT 24
Finished Aug 08 05:30:16 PM PDT 24
Peak memory 222664 kb
Host smart-fef6c12c-aaf6-4f83-8c01-a034fb930040
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254140019 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3254140019
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3310000426
Short name T284
Test name
Test status
Simulation time 294493708 ps
CPU time 4.4 seconds
Started Aug 08 05:29:52 PM PDT 24
Finished Aug 08 05:29:56 PM PDT 24
Peak memory 222464 kb
Host smart-b6429051-5612-4407-9735-40fcabe97f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310000426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3310000426
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1276059710
Short name T499
Test name
Test status
Simulation time 264092749 ps
CPU time 2.31 seconds
Started Aug 08 05:29:53 PM PDT 24
Finished Aug 08 05:29:55 PM PDT 24
Peak memory 210912 kb
Host smart-5858e7aa-ed63-4fce-8cbf-49f566b433dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276059710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1276059710
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1960272841
Short name T395
Test name
Test status
Simulation time 13984118 ps
CPU time 0.94 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:06 PM PDT 24
Peak memory 206092 kb
Host smart-16420fde-64ab-4fe1-bfdf-a3d3fba50732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960272841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1960272841
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2669381730
Short name T286
Test name
Test status
Simulation time 23141651 ps
CPU time 2.06 seconds
Started Aug 08 05:29:52 PM PDT 24
Finished Aug 08 05:29:55 PM PDT 24
Peak memory 214436 kb
Host smart-d7798cfd-be3f-4970-a87d-a6b51816880f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669381730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2669381730
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1918332859
Short name T10
Test name
Test status
Simulation time 128344734 ps
CPU time 3.56 seconds
Started Aug 08 05:29:53 PM PDT 24
Finished Aug 08 05:29:56 PM PDT 24
Peak memory 207980 kb
Host smart-d913c23a-dadc-4e3f-b364-494a3bb1ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918332859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1918332859
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1941761092
Short name T562
Test name
Test status
Simulation time 48701395 ps
CPU time 2.43 seconds
Started Aug 08 05:29:53 PM PDT 24
Finished Aug 08 05:29:56 PM PDT 24
Peak memory 214364 kb
Host smart-29d167cd-4136-4ee7-83a3-2ebe51650f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941761092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1941761092
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1598485848
Short name T85
Test name
Test status
Simulation time 77788567 ps
CPU time 3.29 seconds
Started Aug 08 05:29:53 PM PDT 24
Finished Aug 08 05:29:57 PM PDT 24
Peak memory 214780 kb
Host smart-1a4c33f2-3884-43cc-82a5-49acc80112cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598485848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1598485848
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.500578328
Short name T248
Test name
Test status
Simulation time 120292925 ps
CPU time 3.24 seconds
Started Aug 08 05:29:53 PM PDT 24
Finished Aug 08 05:29:56 PM PDT 24
Peak memory 205964 kb
Host smart-cdaab227-fd9e-42e9-b37a-f9f61bf58449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500578328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.500578328
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.4128206705
Short name T708
Test name
Test status
Simulation time 459342608 ps
CPU time 3.85 seconds
Started Aug 08 05:29:53 PM PDT 24
Finished Aug 08 05:29:57 PM PDT 24
Peak memory 219604 kb
Host smart-edd381d0-5d45-4800-bdde-d90eeecc88eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128206705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.4128206705
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1402835955
Short name T289
Test name
Test status
Simulation time 66116630 ps
CPU time 4.16 seconds
Started Aug 08 05:29:52 PM PDT 24
Finished Aug 08 05:29:57 PM PDT 24
Peak memory 218392 kb
Host smart-760bc011-922f-4b8b-9f40-04c3c3bc0201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402835955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1402835955
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.283220624
Short name T225
Test name
Test status
Simulation time 39241925 ps
CPU time 1.65 seconds
Started Aug 08 05:29:58 PM PDT 24
Finished Aug 08 05:29:59 PM PDT 24
Peak memory 206748 kb
Host smart-f16ed7d4-780b-494a-a34d-4b17dd605a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283220624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.283220624
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1031662102
Short name T810
Test name
Test status
Simulation time 41869581 ps
CPU time 1.79 seconds
Started Aug 08 05:29:50 PM PDT 24
Finished Aug 08 05:29:52 PM PDT 24
Peak memory 206804 kb
Host smart-2d2f3369-7fa2-44ff-bfad-950aace37807
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031662102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1031662102
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.524567663
Short name T614
Test name
Test status
Simulation time 38489942 ps
CPU time 2.71 seconds
Started Aug 08 05:29:53 PM PDT 24
Finished Aug 08 05:29:56 PM PDT 24
Peak memory 208976 kb
Host smart-ebfc3b4e-aa0d-4d60-802b-734a855088d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524567663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.524567663
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.847048060
Short name T832
Test name
Test status
Simulation time 169755333 ps
CPU time 3.94 seconds
Started Aug 08 05:29:51 PM PDT 24
Finished Aug 08 05:29:55 PM PDT 24
Peak memory 207032 kb
Host smart-597e53cc-283c-4c8e-9661-aa3398a42734
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847048060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.847048060
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2922639879
Short name T489
Test name
Test status
Simulation time 126297450 ps
CPU time 2.66 seconds
Started Aug 08 05:30:11 PM PDT 24
Finished Aug 08 05:30:13 PM PDT 24
Peak memory 214348 kb
Host smart-d339eccc-b697-4713-b220-81e5451aae75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922639879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2922639879
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.577273593
Short name T607
Test name
Test status
Simulation time 190033927 ps
CPU time 2.71 seconds
Started Aug 08 05:29:52 PM PDT 24
Finished Aug 08 05:29:55 PM PDT 24
Peak memory 206812 kb
Host smart-b5771f1e-b8ea-47a3-b862-f8c423326501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577273593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.577273593
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1480501444
Short name T102
Test name
Test status
Simulation time 3214156866 ps
CPU time 17.55 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:25 PM PDT 24
Peak memory 217060 kb
Host smart-7820206a-6552-4d64-8f4c-350c7732fd68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480501444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1480501444
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1107652457
Short name T672
Test name
Test status
Simulation time 325784942 ps
CPU time 5.6 seconds
Started Aug 08 05:29:52 PM PDT 24
Finished Aug 08 05:29:58 PM PDT 24
Peak memory 207380 kb
Host smart-95b1cb78-9ce6-44bb-a22c-d5f4e690ebe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107652457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1107652457
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3384665376
Short name T455
Test name
Test status
Simulation time 17316440 ps
CPU time 0.93 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:09 PM PDT 24
Peak memory 206036 kb
Host smart-a96950ad-f692-44d6-97e8-3504674dda39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384665376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3384665376
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1318265915
Short name T538
Test name
Test status
Simulation time 67407414 ps
CPU time 2.99 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:12 PM PDT 24
Peak memory 218380 kb
Host smart-c5228022-3fac-439b-b27a-790a71ca906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318265915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1318265915
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1670814032
Short name T178
Test name
Test status
Simulation time 724100475 ps
CPU time 3.05 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 209672 kb
Host smart-9595ca87-3cb3-48a2-83bd-8d1a14f2d41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670814032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1670814032
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.4261234868
Short name T275
Test name
Test status
Simulation time 117085342 ps
CPU time 3.53 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 221040 kb
Host smart-1f66edc5-ceaf-4141-b409-3b948c52f990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261234868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.4261234868
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1773836820
Short name T704
Test name
Test status
Simulation time 297450229 ps
CPU time 3.73 seconds
Started Aug 08 05:30:04 PM PDT 24
Finished Aug 08 05:30:08 PM PDT 24
Peak memory 219944 kb
Host smart-2afbeff9-ff9f-4596-8091-7f6be896d067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773836820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1773836820
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3561759680
Short name T287
Test name
Test status
Simulation time 2033188728 ps
CPU time 12.99 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:19 PM PDT 24
Peak memory 208716 kb
Host smart-5a5d98f8-df1f-4086-a1fd-418f3b674631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561759680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3561759680
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.909169158
Short name T748
Test name
Test status
Simulation time 186339313 ps
CPU time 5.54 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:13 PM PDT 24
Peak memory 207884 kb
Host smart-9d80b58f-c90e-4ccb-91c7-8e5a40f6d481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909169158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.909169158
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2281458076
Short name T579
Test name
Test status
Simulation time 173580780 ps
CPU time 6.14 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:14 PM PDT 24
Peak memory 208756 kb
Host smart-ff31daf9-c6ea-4441-ba0c-9c0ef60feb1e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281458076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2281458076
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.388013565
Short name T642
Test name
Test status
Simulation time 1197485703 ps
CPU time 8.85 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:15 PM PDT 24
Peak memory 208044 kb
Host smart-8950ea8d-330d-4a53-b514-8bef750a4d7f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388013565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.388013565
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1664956622
Short name T596
Test name
Test status
Simulation time 399227479 ps
CPU time 3.97 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:09 PM PDT 24
Peak memory 208756 kb
Host smart-449d10c8-de51-423d-9253-a480ff926b2b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664956622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1664956622
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1755982339
Short name T711
Test name
Test status
Simulation time 225039821 ps
CPU time 5.28 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:11 PM PDT 24
Peak memory 214316 kb
Host smart-c3a9d052-7152-46d7-9b19-ae9eec12f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755982339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1755982339
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3611523914
Short name T571
Test name
Test status
Simulation time 53053870 ps
CPU time 2.46 seconds
Started Aug 08 05:30:04 PM PDT 24
Finished Aug 08 05:30:06 PM PDT 24
Peak memory 206724 kb
Host smart-7e53c85e-8577-4988-9abd-abe69da17245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611523914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3611523914
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2877632880
Short name T673
Test name
Test status
Simulation time 470291044 ps
CPU time 5.41 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:11 PM PDT 24
Peak memory 207540 kb
Host smart-08e9d9ee-416e-4790-947b-205ab3d6e208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877632880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2877632880
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3473197165
Short name T734
Test name
Test status
Simulation time 149046897 ps
CPU time 3.32 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:09 PM PDT 24
Peak memory 210088 kb
Host smart-3cfd7b5d-7636-45aa-94e3-7cdbeb391b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473197165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3473197165
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3132273355
Short name T483
Test name
Test status
Simulation time 13062440 ps
CPU time 0.95 seconds
Started Aug 08 05:30:04 PM PDT 24
Finished Aug 08 05:30:05 PM PDT 24
Peak memory 205920 kb
Host smart-5f9936bf-b02a-49ab-9e71-caddb219eaf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132273355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3132273355
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3023075684
Short name T757
Test name
Test status
Simulation time 326818196 ps
CPU time 2.44 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:08 PM PDT 24
Peak memory 218404 kb
Host smart-77667584-106c-409f-b387-457aa5663e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023075684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3023075684
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3877760565
Short name T830
Test name
Test status
Simulation time 60902768 ps
CPU time 1.98 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 214236 kb
Host smart-6835694c-1bca-4b2a-add4-e1c9e1d373c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877760565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3877760565
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3836455206
Short name T677
Test name
Test status
Simulation time 175177806 ps
CPU time 2.88 seconds
Started Aug 08 05:30:04 PM PDT 24
Finished Aug 08 05:30:07 PM PDT 24
Peak memory 214232 kb
Host smart-1c6fa204-da93-4d9b-a3db-02aae35b55ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836455206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3836455206
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.939767316
Short name T52
Test name
Test status
Simulation time 63551404 ps
CPU time 3.38 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:08 PM PDT 24
Peak memory 222304 kb
Host smart-eac106d6-0962-4aea-b507-2f6a59c62830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939767316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.939767316
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.982914658
Short name T45
Test name
Test status
Simulation time 129729940 ps
CPU time 4.05 seconds
Started Aug 08 05:30:04 PM PDT 24
Finished Aug 08 05:30:08 PM PDT 24
Peak memory 210656 kb
Host smart-be90ee6f-58b6-4f1b-9be7-cd854d6e7709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982914658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.982914658
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2912764235
Short name T740
Test name
Test status
Simulation time 698493180 ps
CPU time 3.35 seconds
Started Aug 08 05:30:09 PM PDT 24
Finished Aug 08 05:30:13 PM PDT 24
Peak memory 209684 kb
Host smart-8b577755-62e4-433d-950b-1c5f77a25d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912764235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2912764235
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.340312727
Short name T226
Test name
Test status
Simulation time 173241655 ps
CPU time 4.6 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 208820 kb
Host smart-ceadd30b-2e6e-40fc-b261-783d7ba9448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340312727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.340312727
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1468412387
Short name T396
Test name
Test status
Simulation time 63227915 ps
CPU time 3.26 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:09 PM PDT 24
Peak memory 208160 kb
Host smart-9ad21e2c-9b95-4fe0-9b23-54cc64459460
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468412387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1468412387
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.508660187
Short name T78
Test name
Test status
Simulation time 136002391 ps
CPU time 4.07 seconds
Started Aug 08 05:30:04 PM PDT 24
Finished Aug 08 05:30:08 PM PDT 24
Peak memory 208648 kb
Host smart-af26fc37-c568-4b58-9643-361d9e97b565
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508660187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.508660187
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2623165889
Short name T669
Test name
Test status
Simulation time 1705805206 ps
CPU time 7.38 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:15 PM PDT 24
Peak memory 207988 kb
Host smart-212dab3b-cf0c-4d74-9882-a09f717335d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623165889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2623165889
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3819169058
Short name T327
Test name
Test status
Simulation time 302888593 ps
CPU time 3.77 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:09 PM PDT 24
Peak memory 209964 kb
Host smart-c7cfc95c-e944-495f-8755-a2aeb74c3bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819169058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3819169058
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2947873793
Short name T747
Test name
Test status
Simulation time 527500400 ps
CPU time 4.87 seconds
Started Aug 08 05:30:09 PM PDT 24
Finished Aug 08 05:30:14 PM PDT 24
Peak memory 206976 kb
Host smart-88bb7ac1-11b3-4c68-839e-1ca6c26dba5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947873793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2947873793
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2719209409
Short name T122
Test name
Test status
Simulation time 448879611 ps
CPU time 9.76 seconds
Started Aug 08 05:30:04 PM PDT 24
Finished Aug 08 05:30:14 PM PDT 24
Peak memory 222492 kb
Host smart-8f3464ef-e69d-40a9-90c8-28709a6b372b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719209409 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2719209409
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3238351298
Short name T228
Test name
Test status
Simulation time 390762224 ps
CPU time 3.24 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:11 PM PDT 24
Peak memory 207832 kb
Host smart-fafd2006-c666-4a97-afa1-7c96b897ef7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238351298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3238351298
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.186598887
Short name T357
Test name
Test status
Simulation time 67106689 ps
CPU time 2.9 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 210532 kb
Host smart-685d5938-9086-4b41-b6c8-7c4922b0805c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186598887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.186598887
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.942707844
Short name T687
Test name
Test status
Simulation time 57147274 ps
CPU time 0.7 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:07 PM PDT 24
Peak memory 205952 kb
Host smart-889b6f03-071d-47ec-9159-477ddd81e21f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942707844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.942707844
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2076864267
Short name T389
Test name
Test status
Simulation time 143917953 ps
CPU time 4.11 seconds
Started Aug 08 05:30:10 PM PDT 24
Finished Aug 08 05:30:14 PM PDT 24
Peak memory 214436 kb
Host smart-76d66516-c7a1-49d1-a5a2-31b85b07bbf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076864267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2076864267
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3133341476
Short name T678
Test name
Test status
Simulation time 4576376345 ps
CPU time 27.83 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:36 PM PDT 24
Peak memory 209176 kb
Host smart-3f4b9a86-77bd-4175-a721-b2008955f0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133341476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3133341476
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.848376505
Short name T86
Test name
Test status
Simulation time 211078617 ps
CPU time 3.76 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:12 PM PDT 24
Peak memory 214412 kb
Host smart-f73c2cf5-f10a-47d8-b774-a28a24284a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848376505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.848376505
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.4250947322
Short name T231
Test name
Test status
Simulation time 55992151 ps
CPU time 3.4 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:11 PM PDT 24
Peak memory 221880 kb
Host smart-723f52a8-ad3a-42ef-92d0-4649f606a349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250947322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.4250947322
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2182731283
Short name T61
Test name
Test status
Simulation time 132877586 ps
CPU time 3.39 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:12 PM PDT 24
Peak memory 208044 kb
Host smart-d9f8deb8-cf11-42cb-ac56-135bd1e120e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182731283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2182731283
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1279884529
Short name T306
Test name
Test status
Simulation time 290071088 ps
CPU time 6.63 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:15 PM PDT 24
Peak memory 209460 kb
Host smart-be1971ce-a39b-4078-9892-0443814e00dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279884529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1279884529
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1509113897
Short name T884
Test name
Test status
Simulation time 25786749743 ps
CPU time 56.94 seconds
Started Aug 08 05:30:06 PM PDT 24
Finished Aug 08 05:31:03 PM PDT 24
Peak memory 208060 kb
Host smart-7f70c2bc-dcb4-4f53-86a0-42d13b7413c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509113897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1509113897
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.477624032
Short name T835
Test name
Test status
Simulation time 142551086 ps
CPU time 1.89 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 206956 kb
Host smart-19984565-139e-404c-82d4-c857ceffc1c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477624032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.477624032
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3982853664
Short name T569
Test name
Test status
Simulation time 346584837 ps
CPU time 2.7 seconds
Started Aug 08 05:30:09 PM PDT 24
Finished Aug 08 05:30:12 PM PDT 24
Peak memory 207008 kb
Host smart-e6c87779-63d6-40cc-b8c4-52b75e9630b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982853664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3982853664
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2708620244
Short name T134
Test name
Test status
Simulation time 83677947 ps
CPU time 3.23 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:09 PM PDT 24
Peak memory 209760 kb
Host smart-de6b4104-ae72-4842-864f-b3a9c8b98595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708620244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2708620244
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3146132024
Short name T883
Test name
Test status
Simulation time 61819473 ps
CPU time 2.28 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 206904 kb
Host smart-1d9bc3b7-0b09-4540-93b1-fd6b7363608d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146132024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3146132024
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2421442645
Short name T189
Test name
Test status
Simulation time 358663185 ps
CPU time 4.57 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:12 PM PDT 24
Peak memory 210128 kb
Host smart-c52e0de5-69ff-4f9d-9fd9-fa00e6908a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421442645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2421442645
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.751903958
Short name T667
Test name
Test status
Simulation time 2390193485 ps
CPU time 24.54 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:32 PM PDT 24
Peak memory 211160 kb
Host smart-d3fde018-ed19-4417-aacc-c9e7e68bdc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751903958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.751903958
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3077906371
Short name T434
Test name
Test status
Simulation time 48166757 ps
CPU time 0.87 seconds
Started Aug 08 05:30:17 PM PDT 24
Finished Aug 08 05:30:18 PM PDT 24
Peak memory 205988 kb
Host smart-9d19413e-2123-40f2-acb4-ca5b4d001e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077906371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3077906371
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1160909200
Short name T391
Test name
Test status
Simulation time 57048141 ps
CPU time 4.39 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 214428 kb
Host smart-deb146e2-9e0b-44e6-afa8-7692bd5afc89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1160909200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1160909200
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2643364535
Short name T68
Test name
Test status
Simulation time 79640565 ps
CPU time 2.15 seconds
Started Aug 08 05:30:06 PM PDT 24
Finished Aug 08 05:30:08 PM PDT 24
Peak memory 214436 kb
Host smart-8ee72c8b-98dc-442c-922c-e6ffcd455f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643364535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2643364535
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.306498204
Short name T24
Test name
Test status
Simulation time 474579722 ps
CPU time 5.19 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:13 PM PDT 24
Peak memory 220936 kb
Host smart-f14ea9a1-17ca-4aa8-a660-054cc2b1362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306498204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.306498204
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1214790895
Short name T55
Test name
Test status
Simulation time 230574160 ps
CPU time 6.79 seconds
Started Aug 08 05:30:11 PM PDT 24
Finished Aug 08 05:30:18 PM PDT 24
Peak memory 220848 kb
Host smart-693b470f-a9fc-4ee8-984d-d868f64d98f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214790895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1214790895
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.311493935
Short name T198
Test name
Test status
Simulation time 388591918 ps
CPU time 3.72 seconds
Started Aug 08 05:30:06 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 215892 kb
Host smart-3f2aebee-a642-493b-8325-7d3d6fbbf49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311493935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.311493935
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2127702580
Short name T461
Test name
Test status
Simulation time 308559441 ps
CPU time 10.31 seconds
Started Aug 08 05:30:08 PM PDT 24
Finished Aug 08 05:30:19 PM PDT 24
Peak memory 208824 kb
Host smart-a1398697-ac3a-4cd0-8715-8a68b16057fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127702580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2127702580
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.299299939
Short name T676
Test name
Test status
Simulation time 37451618 ps
CPU time 2.78 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:08 PM PDT 24
Peak memory 208496 kb
Host smart-00ccf5fa-4ea6-4232-9e49-0954e53fcf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299299939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.299299939
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3662980064
Short name T492
Test name
Test status
Simulation time 20460554 ps
CPU time 1.67 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:07 PM PDT 24
Peak memory 207012 kb
Host smart-5cceaa91-4e36-4a3c-b25a-f9432d13f6ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662980064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3662980064
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2520622153
Short name T490
Test name
Test status
Simulation time 49407102 ps
CPU time 2.12 seconds
Started Aug 08 05:30:05 PM PDT 24
Finished Aug 08 05:30:08 PM PDT 24
Peak memory 208896 kb
Host smart-2d29edb0-fd3a-4296-8264-d28532d1b127
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520622153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2520622153
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1892288566
Short name T737
Test name
Test status
Simulation time 1802517070 ps
CPU time 18.65 seconds
Started Aug 08 05:30:06 PM PDT 24
Finished Aug 08 05:30:25 PM PDT 24
Peak memory 209308 kb
Host smart-2c45f7e2-bc7b-40cc-b3a8-608977707865
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892288566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1892288566
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4087144625
Short name T106
Test name
Test status
Simulation time 35876831 ps
CPU time 1.59 seconds
Started Aug 08 05:30:06 PM PDT 24
Finished Aug 08 05:30:08 PM PDT 24
Peak memory 208276 kb
Host smart-eb19e431-9699-4595-bd0d-c370be9e1494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087144625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4087144625
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1043817118
Short name T833
Test name
Test status
Simulation time 132832263 ps
CPU time 3.28 seconds
Started Aug 08 05:30:06 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 207980 kb
Host smart-03f3a3d2-f788-4f35-92d2-69fa36fd69e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043817118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1043817118
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.4190080322
Short name T74
Test name
Test status
Simulation time 6064878441 ps
CPU time 30.67 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:38 PM PDT 24
Peak memory 221756 kb
Host smart-1b296c02-27fc-43e8-8e0c-b21d4af3b4ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190080322 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.4190080322
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2428235910
Short name T732
Test name
Test status
Simulation time 868865171 ps
CPU time 6.23 seconds
Started Aug 08 05:30:11 PM PDT 24
Finished Aug 08 05:30:18 PM PDT 24
Peak memory 208304 kb
Host smart-5b9a8569-8d9e-4021-8bfa-4efab915720c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428235910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2428235910
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3242178876
Short name T530
Test name
Test status
Simulation time 119090888 ps
CPU time 2.6 seconds
Started Aug 08 05:30:07 PM PDT 24
Finished Aug 08 05:30:10 PM PDT 24
Peak memory 210072 kb
Host smart-58200bb2-b01b-40f9-ac45-dcaee07e0230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242178876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3242178876
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3664625720
Short name T821
Test name
Test status
Simulation time 167548197 ps
CPU time 0.84 seconds
Started Aug 08 05:29:08 PM PDT 24
Finished Aug 08 05:29:09 PM PDT 24
Peak memory 205948 kb
Host smart-b48edad7-78d4-48cf-ac52-f812a45ba150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664625720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3664625720
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2745717276
Short name T315
Test name
Test status
Simulation time 1417971257 ps
CPU time 9.11 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:18 PM PDT 24
Peak memory 222436 kb
Host smart-dac68d6f-a093-4066-99b2-960ca51a1f2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745717276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2745717276
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1484313312
Short name T812
Test name
Test status
Simulation time 311096609 ps
CPU time 3.05 seconds
Started Aug 08 05:29:12 PM PDT 24
Finished Aug 08 05:29:15 PM PDT 24
Peak memory 207884 kb
Host smart-e32380a3-ce1c-4508-9481-2895ac8c19ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484313312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1484313312
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2024340398
Short name T437
Test name
Test status
Simulation time 63986110 ps
CPU time 2.34 seconds
Started Aug 08 05:29:11 PM PDT 24
Finished Aug 08 05:29:13 PM PDT 24
Peak memory 207680 kb
Host smart-3fa03629-10ae-4e7b-9d64-0b80fcaee723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024340398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2024340398
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1301097721
Short name T340
Test name
Test status
Simulation time 113138692 ps
CPU time 2.16 seconds
Started Aug 08 05:29:06 PM PDT 24
Finished Aug 08 05:29:09 PM PDT 24
Peak memory 214332 kb
Host smart-f1f86944-3428-4d40-b050-36a6d7d43d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301097721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1301097721
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.822011949
Short name T533
Test name
Test status
Simulation time 230424177 ps
CPU time 8.18 seconds
Started Aug 08 05:29:08 PM PDT 24
Finished Aug 08 05:29:16 PM PDT 24
Peak memory 214340 kb
Host smart-4b71e134-9977-48ef-b177-9fcc627ee0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822011949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.822011949
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.3671927680
Short name T725
Test name
Test status
Simulation time 375506162 ps
CPU time 5.6 seconds
Started Aug 08 05:29:10 PM PDT 24
Finished Aug 08 05:29:16 PM PDT 24
Peak memory 219740 kb
Host smart-9112205a-67c0-4adb-8beb-63b07dbc60ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671927680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3671927680
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1738188629
Short name T99
Test name
Test status
Simulation time 1432491543 ps
CPU time 6.53 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:15 PM PDT 24
Peak memory 237920 kb
Host smart-ffde2e10-d3a8-411d-a6d1-9cabec075c60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738188629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1738188629
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1422608575
Short name T582
Test name
Test status
Simulation time 141407926 ps
CPU time 2.55 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:29:00 PM PDT 24
Peak memory 208512 kb
Host smart-36864c0c-593c-42da-9fff-357208d61ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422608575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1422608575
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1080129644
Short name T400
Test name
Test status
Simulation time 131912777 ps
CPU time 3.06 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:12 PM PDT 24
Peak memory 206652 kb
Host smart-a2b1f8f1-d6da-4bb8-95aa-994f2a6e9564
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080129644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1080129644
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2497665595
Short name T328
Test name
Test status
Simulation time 174853377 ps
CPU time 2.55 seconds
Started Aug 08 05:29:00 PM PDT 24
Finished Aug 08 05:29:03 PM PDT 24
Peak memory 206860 kb
Host smart-aed57404-7e6a-46b3-a8b1-feb1bb70c05e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497665595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2497665595
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3294980490
Short name T580
Test name
Test status
Simulation time 191635912 ps
CPU time 4.59 seconds
Started Aug 08 05:29:13 PM PDT 24
Finished Aug 08 05:29:17 PM PDT 24
Peak memory 208968 kb
Host smart-25e748ee-de32-46d5-aceb-fbd5c57c511e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294980490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3294980490
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.289729639
Short name T720
Test name
Test status
Simulation time 465407058 ps
CPU time 2.26 seconds
Started Aug 08 05:29:12 PM PDT 24
Finished Aug 08 05:29:15 PM PDT 24
Peak memory 215452 kb
Host smart-b3a11324-c773-4d93-8a0e-ce9d16e0d05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289729639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.289729639
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1663829053
Short name T17
Test name
Test status
Simulation time 135015665 ps
CPU time 2.46 seconds
Started Aug 08 05:28:57 PM PDT 24
Finished Aug 08 05:29:00 PM PDT 24
Peak memory 208544 kb
Host smart-426025bd-c5e1-4fec-9b73-db65870ef352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663829053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1663829053
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.790447919
Short name T675
Test name
Test status
Simulation time 99428137 ps
CPU time 4.18 seconds
Started Aug 08 05:29:07 PM PDT 24
Finished Aug 08 05:29:11 PM PDT 24
Peak memory 214332 kb
Host smart-d7b8a062-487f-4d9d-9aa3-41e0dae959bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790447919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.790447919
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2816380214
Short name T168
Test name
Test status
Simulation time 720904357 ps
CPU time 1.96 seconds
Started Aug 08 05:29:11 PM PDT 24
Finished Aug 08 05:29:13 PM PDT 24
Peak memory 209740 kb
Host smart-1c95c047-860e-48fa-a150-2862ffb52d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816380214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2816380214
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2001290978
Short name T618
Test name
Test status
Simulation time 25469517 ps
CPU time 0.9 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:20 PM PDT 24
Peak memory 206008 kb
Host smart-eb46f5f8-ef32-472f-b027-1fbaaa033396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001290978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2001290978
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1402144058
Short name T29
Test name
Test status
Simulation time 137658919 ps
CPU time 2.98 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:22 PM PDT 24
Peak memory 214668 kb
Host smart-e490ea12-df17-4899-bd38-f3a29a6dc53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402144058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1402144058
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1174021936
Short name T47
Test name
Test status
Simulation time 86090159 ps
CPU time 2.45 seconds
Started Aug 08 05:30:18 PM PDT 24
Finished Aug 08 05:30:20 PM PDT 24
Peak memory 209520 kb
Host smart-932c20f1-8bfd-45ea-91d6-50f833bac209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174021936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1174021936
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2313746960
Short name T233
Test name
Test status
Simulation time 93136350 ps
CPU time 2.66 seconds
Started Aug 08 05:30:16 PM PDT 24
Finished Aug 08 05:30:19 PM PDT 24
Peak memory 206044 kb
Host smart-6c37d50a-3846-487c-83be-07b6818c7349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313746960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2313746960
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3333663868
Short name T848
Test name
Test status
Simulation time 44640781 ps
CPU time 2.23 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:23 PM PDT 24
Peak memory 208024 kb
Host smart-cb7ff198-5e28-4215-b677-1eec368e12fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333663868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3333663868
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2986681073
Short name T860
Test name
Test status
Simulation time 791902188 ps
CPU time 20.08 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:41 PM PDT 24
Peak memory 208948 kb
Host smart-63fae88a-5c80-40f7-8261-7e82f1ef63f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986681073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2986681073
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2325130736
Short name T503
Test name
Test status
Simulation time 207597405 ps
CPU time 5.78 seconds
Started Aug 08 05:30:16 PM PDT 24
Finished Aug 08 05:30:22 PM PDT 24
Peak memory 208544 kb
Host smart-e48f8546-08bc-4e4e-8e1b-9d833e77927e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325130736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2325130736
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3767888545
Short name T663
Test name
Test status
Simulation time 32547610 ps
CPU time 2.25 seconds
Started Aug 08 05:30:23 PM PDT 24
Finished Aug 08 05:30:25 PM PDT 24
Peak memory 207008 kb
Host smart-02209939-8be1-434e-b325-b5182f56266c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767888545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3767888545
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4170859088
Short name T296
Test name
Test status
Simulation time 146970198 ps
CPU time 4.56 seconds
Started Aug 08 05:30:23 PM PDT 24
Finished Aug 08 05:30:28 PM PDT 24
Peak memory 208000 kb
Host smart-23011490-ac4c-4640-b0dd-f6cde091f674
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170859088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4170859088
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1266400115
Short name T448
Test name
Test status
Simulation time 120363542 ps
CPU time 3.82 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:25 PM PDT 24
Peak memory 206840 kb
Host smart-9a6d40a6-4275-4381-b3e6-ed5274a7db89
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266400115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1266400115
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.501439362
Short name T903
Test name
Test status
Simulation time 434337338 ps
CPU time 9.11 seconds
Started Aug 08 05:30:18 PM PDT 24
Finished Aug 08 05:30:28 PM PDT 24
Peak memory 208912 kb
Host smart-ff1dac39-8701-486f-baf9-303c807f045d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501439362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.501439362
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3567937650
Short name T771
Test name
Test status
Simulation time 314538528 ps
CPU time 3.89 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:23 PM PDT 24
Peak memory 208192 kb
Host smart-e1ce4534-964e-4f19-86f7-ae5887c453c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567937650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3567937650
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.488611204
Short name T119
Test name
Test status
Simulation time 150045781 ps
CPU time 10.2 seconds
Started Aug 08 05:30:18 PM PDT 24
Finished Aug 08 05:30:28 PM PDT 24
Peak memory 222504 kb
Host smart-99615c18-f9a0-4cfc-a3f2-29e74780059b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488611204 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.488611204
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1956038292
Short name T1
Test name
Test status
Simulation time 124741754 ps
CPU time 2.63 seconds
Started Aug 08 05:30:18 PM PDT 24
Finished Aug 08 05:30:21 PM PDT 24
Peak memory 214320 kb
Host smart-bf3cb1dd-06e4-4796-a22a-fd0522c6e811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956038292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1956038292
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3084382618
Short name T813
Test name
Test status
Simulation time 136275230 ps
CPU time 1.24 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:23 PM PDT 24
Peak memory 209476 kb
Host smart-6f177053-3ab3-451d-aba1-1f24a3c7007b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084382618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3084382618
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3679627727
Short name T447
Test name
Test status
Simulation time 25951137 ps
CPU time 0.9 seconds
Started Aug 08 05:30:17 PM PDT 24
Finished Aug 08 05:30:18 PM PDT 24
Peak memory 206128 kb
Host smart-3977d008-95dd-43ba-b322-1f311041afe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679627727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3679627727
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2861711961
Short name T237
Test name
Test status
Simulation time 114035076 ps
CPU time 6.04 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:28 PM PDT 24
Peak memory 215268 kb
Host smart-b838130c-9179-4eba-a71c-deadf82556f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861711961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2861711961
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.39611093
Short name T20
Test name
Test status
Simulation time 188706153 ps
CPU time 4.55 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:24 PM PDT 24
Peak memory 209780 kb
Host smart-07b979d5-562b-401a-8f5f-ca693300b9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39611093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.39611093
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1102890246
Short name T770
Test name
Test status
Simulation time 31076829 ps
CPU time 1.54 seconds
Started Aug 08 05:30:20 PM PDT 24
Finished Aug 08 05:30:22 PM PDT 24
Peak memory 206948 kb
Host smart-cd2771ed-685a-4e8e-bada-b2d5cd12a197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102890246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1102890246
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1421732653
Short name T839
Test name
Test status
Simulation time 113045898 ps
CPU time 4.6 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:26 PM PDT 24
Peak memory 214184 kb
Host smart-66f41a35-b34b-4fd7-8bb3-dd1c1aca8326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421732653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1421732653
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1449129111
Short name T205
Test name
Test status
Simulation time 239974098 ps
CPU time 3.38 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:23 PM PDT 24
Peak memory 220136 kb
Host smart-2c1e850d-8cc1-4f92-9333-c4f7a82cc0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449129111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1449129111
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.4266056155
Short name T329
Test name
Test status
Simulation time 93731833 ps
CPU time 4.5 seconds
Started Aug 08 05:30:18 PM PDT 24
Finished Aug 08 05:30:22 PM PDT 24
Peak memory 208764 kb
Host smart-a49cae2e-5cbd-4028-86e2-b2965a5ba83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266056155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.4266056155
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2620502137
Short name T887
Test name
Test status
Simulation time 3187465631 ps
CPU time 41.28 seconds
Started Aug 08 05:30:18 PM PDT 24
Finished Aug 08 05:30:59 PM PDT 24
Peak memory 208928 kb
Host smart-e948077e-6d24-46b7-aa12-775ff7dff074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620502137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2620502137
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3948725593
Short name T101
Test name
Test status
Simulation time 841012182 ps
CPU time 8.14 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:30 PM PDT 24
Peak memory 208360 kb
Host smart-27fff56b-c3e4-45c7-a916-49e1f1032012
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948725593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3948725593
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.702312088
Short name T285
Test name
Test status
Simulation time 271602491 ps
CPU time 3.63 seconds
Started Aug 08 05:30:18 PM PDT 24
Finished Aug 08 05:30:22 PM PDT 24
Peak memory 206964 kb
Host smart-3c9c6748-e3c2-46ce-a3a9-5deabd11a74c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702312088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.702312088
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.925453716
Short name T450
Test name
Test status
Simulation time 44133597 ps
CPU time 2.53 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:24 PM PDT 24
Peak memory 206968 kb
Host smart-b7a47f6e-3125-4c4e-a42b-6f7b369589a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925453716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.925453716
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.773117650
Short name T519
Test name
Test status
Simulation time 111416930 ps
CPU time 2.68 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:22 PM PDT 24
Peak memory 215784 kb
Host smart-6158e3c2-5f2f-429c-ab8b-58363b73b0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773117650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.773117650
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3347695675
Short name T446
Test name
Test status
Simulation time 365851625 ps
CPU time 2.4 seconds
Started Aug 08 05:30:17 PM PDT 24
Finished Aug 08 05:30:19 PM PDT 24
Peak memory 208624 kb
Host smart-c622f5d7-ff5c-4874-b690-7500322c3b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347695675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3347695675
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.253250174
Short name T192
Test name
Test status
Simulation time 2052008768 ps
CPU time 44.3 seconds
Started Aug 08 05:30:20 PM PDT 24
Finished Aug 08 05:31:05 PM PDT 24
Peak memory 209292 kb
Host smart-c49ebbcc-5045-463f-ad87-2f530368286b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253250174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.253250174
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.314042086
Short name T685
Test name
Test status
Simulation time 95652161 ps
CPU time 3.27 seconds
Started Aug 08 05:30:17 PM PDT 24
Finished Aug 08 05:30:20 PM PDT 24
Peak memory 210064 kb
Host smart-f6321af1-8e61-47c5-8ea0-9776735246ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314042086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.314042086
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3571737671
Short name T611
Test name
Test status
Simulation time 17845893 ps
CPU time 0.82 seconds
Started Aug 08 05:30:23 PM PDT 24
Finished Aug 08 05:30:24 PM PDT 24
Peak memory 205996 kb
Host smart-d7993e78-a64b-4aa9-a98a-8d6dc97902d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571737671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3571737671
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1144241432
Short name T452
Test name
Test status
Simulation time 811964168 ps
CPU time 9.26 seconds
Started Aug 08 05:30:22 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 214292 kb
Host smart-d9742fd5-4a1c-4456-bc33-d3542b705df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144241432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1144241432
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3903288883
Short name T751
Test name
Test status
Simulation time 91694952 ps
CPU time 4.25 seconds
Started Aug 08 05:30:22 PM PDT 24
Finished Aug 08 05:30:27 PM PDT 24
Peak memory 214328 kb
Host smart-dd9b9dde-126c-42d8-85ce-41003a0fb523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903288883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3903288883
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.853679590
Short name T274
Test name
Test status
Simulation time 88627356 ps
CPU time 3.89 seconds
Started Aug 08 05:30:23 PM PDT 24
Finished Aug 08 05:30:27 PM PDT 24
Peak memory 222404 kb
Host smart-10f9f07a-157e-4e99-84f9-d77b19448f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853679590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.853679590
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.425323522
Short name T206
Test name
Test status
Simulation time 60360625 ps
CPU time 3.03 seconds
Started Aug 08 05:30:23 PM PDT 24
Finished Aug 08 05:30:26 PM PDT 24
Peak memory 222600 kb
Host smart-aba97cf0-4681-437d-a743-c0f53a05f547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425323522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.425323522
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2589260582
Short name T360
Test name
Test status
Simulation time 873785180 ps
CPU time 4.58 seconds
Started Aug 08 05:30:18 PM PDT 24
Finished Aug 08 05:30:23 PM PDT 24
Peak memory 207552 kb
Host smart-17d5fe32-a503-4aea-86d3-db5d97c076c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589260582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2589260582
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2228795877
Short name T293
Test name
Test status
Simulation time 8663782149 ps
CPU time 21.79 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:41 PM PDT 24
Peak memory 208964 kb
Host smart-821132e0-fc59-42ad-9e98-95034c664ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228795877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2228795877
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3526243223
Short name T610
Test name
Test status
Simulation time 248702183 ps
CPU time 5.26 seconds
Started Aug 08 05:30:20 PM PDT 24
Finished Aug 08 05:30:26 PM PDT 24
Peak memory 208096 kb
Host smart-fa3b2493-0fa8-47c3-8454-da295e0bb29c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526243223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3526243223
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.475310624
Short name T130
Test name
Test status
Simulation time 630290101 ps
CPU time 4.97 seconds
Started Aug 08 05:30:20 PM PDT 24
Finished Aug 08 05:30:25 PM PDT 24
Peak memory 208704 kb
Host smart-1aaa5346-819a-4f48-9749-4f7522e9f3e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475310624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.475310624
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3427918794
Short name T431
Test name
Test status
Simulation time 24937828 ps
CPU time 1.91 seconds
Started Aug 08 05:30:18 PM PDT 24
Finished Aug 08 05:30:20 PM PDT 24
Peak memory 208680 kb
Host smart-92218d60-7bed-4fbe-a34f-dc974d672623
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427918794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3427918794
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2421960830
Short name T840
Test name
Test status
Simulation time 266651165 ps
CPU time 3.17 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:22 PM PDT 24
Peak memory 207428 kb
Host smart-d06a0ab5-7bf8-4272-9fff-292762cae500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421960830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2421960830
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2930379274
Short name T194
Test name
Test status
Simulation time 422925158 ps
CPU time 3.08 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:25 PM PDT 24
Peak memory 208360 kb
Host smart-706484cf-9392-40ec-af80-a9237346cdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930379274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2930379274
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.4116514218
Short name T128
Test name
Test status
Simulation time 450339500 ps
CPU time 5.22 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:26 PM PDT 24
Peak memory 210280 kb
Host smart-99f2e55f-3d40-45ac-9061-dd986e1b834b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116514218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.4116514218
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1211046974
Short name T547
Test name
Test status
Simulation time 74966872 ps
CPU time 2.02 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:21 PM PDT 24
Peak memory 209720 kb
Host smart-ee20c19d-cb9e-4215-bb11-5bb828bb6392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211046974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1211046974
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.963432250
Short name T705
Test name
Test status
Simulation time 40176678 ps
CPU time 1.02 seconds
Started Aug 08 05:30:22 PM PDT 24
Finished Aug 08 05:30:24 PM PDT 24
Peak memory 206080 kb
Host smart-d4e80739-6695-4493-969b-77e291fdbcce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963432250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.963432250
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.639130512
Short name T259
Test name
Test status
Simulation time 31445173 ps
CPU time 2.33 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:21 PM PDT 24
Peak memory 214516 kb
Host smart-c0ef3d19-e38b-4280-9e4e-cb04e25ae16a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639130512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.639130512
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1850626417
Short name T32
Test name
Test status
Simulation time 247404817 ps
CPU time 1.71 seconds
Started Aug 08 05:30:16 PM PDT 24
Finished Aug 08 05:30:18 PM PDT 24
Peak memory 209324 kb
Host smart-809ecbdb-f446-45e4-b557-fa372e7d2fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850626417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1850626417
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.738319801
Short name T688
Test name
Test status
Simulation time 74540542 ps
CPU time 2.59 seconds
Started Aug 08 05:30:16 PM PDT 24
Finished Aug 08 05:30:19 PM PDT 24
Peak memory 210384 kb
Host smart-47938c4d-235f-4dd7-a54f-71fb0dfbcb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738319801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.738319801
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1128400235
Short name T219
Test name
Test status
Simulation time 568673912 ps
CPU time 3.24 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:22 PM PDT 24
Peak memory 209184 kb
Host smart-b03ca786-d9b4-4c91-b895-be310e142afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128400235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1128400235
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1504410030
Short name T622
Test name
Test status
Simulation time 44413059 ps
CPU time 2.33 seconds
Started Aug 08 05:30:15 PM PDT 24
Finished Aug 08 05:30:18 PM PDT 24
Peak memory 214408 kb
Host smart-bdecaf23-920b-491c-9a9c-864854909ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504410030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1504410030
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3724469755
Short name T862
Test name
Test status
Simulation time 167025489 ps
CPU time 3.49 seconds
Started Aug 08 05:30:22 PM PDT 24
Finished Aug 08 05:30:26 PM PDT 24
Peak memory 222408 kb
Host smart-25a74cfd-d67b-40ff-9cbf-b8dcc0e558f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724469755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3724469755
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2509693454
Short name T820
Test name
Test status
Simulation time 235995143 ps
CPU time 6.28 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:26 PM PDT 24
Peak memory 209272 kb
Host smart-c1293b12-1eb3-4c42-b3bc-6f9d8f28dc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509693454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2509693454
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3283410381
Short name T619
Test name
Test status
Simulation time 346481239 ps
CPU time 2.98 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:24 PM PDT 24
Peak memory 206876 kb
Host smart-6a230c23-2793-46bb-a953-e1eebd3aeb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283410381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3283410381
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3311713833
Short name T681
Test name
Test status
Simulation time 124566742 ps
CPU time 4.98 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:24 PM PDT 24
Peak memory 207920 kb
Host smart-0486c58c-1e5d-45f4-a238-7afe7042fe3a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311713833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3311713833
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2898495280
Short name T670
Test name
Test status
Simulation time 74363139 ps
CPU time 2.3 seconds
Started Aug 08 05:30:19 PM PDT 24
Finished Aug 08 05:30:21 PM PDT 24
Peak memory 206928 kb
Host smart-130eb68e-14ec-4cc6-9c28-7e5ec0a1aef8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898495280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2898495280
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.61474447
Short name T103
Test name
Test status
Simulation time 122802515 ps
CPU time 3.96 seconds
Started Aug 08 05:30:17 PM PDT 24
Finished Aug 08 05:30:21 PM PDT 24
Peak memory 206844 kb
Host smart-5e9e322b-3bf6-4be0-864e-81eacecd116d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61474447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.61474447
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.904638600
Short name T310
Test name
Test status
Simulation time 165018306 ps
CPU time 4.86 seconds
Started Aug 08 05:30:18 PM PDT 24
Finished Aug 08 05:30:23 PM PDT 24
Peak memory 214364 kb
Host smart-1df4ca87-0b80-4516-bf25-0acec4cac6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904638600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.904638600
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3175204481
Short name T453
Test name
Test status
Simulation time 473181617 ps
CPU time 3.04 seconds
Started Aug 08 05:30:16 PM PDT 24
Finished Aug 08 05:30:20 PM PDT 24
Peak memory 206780 kb
Host smart-d6ffff2c-93b3-4678-a8f8-fcffe2d2d8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175204481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3175204481
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2019951013
Short name T742
Test name
Test status
Simulation time 1827308905 ps
CPU time 24.88 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:47 PM PDT 24
Peak memory 218616 kb
Host smart-db0f326a-c72c-4daf-8ad8-bff89fd9aa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019951013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2019951013
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2863880591
Short name T355
Test name
Test status
Simulation time 443665135 ps
CPU time 2.83 seconds
Started Aug 08 05:30:17 PM PDT 24
Finished Aug 08 05:30:20 PM PDT 24
Peak memory 209964 kb
Host smart-c8b5a433-3f3c-4458-affd-23ffa007ea08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863880591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2863880591
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3657430112
Short name T480
Test name
Test status
Simulation time 41359003 ps
CPU time 0.83 seconds
Started Aug 08 05:30:32 PM PDT 24
Finished Aug 08 05:30:33 PM PDT 24
Peak memory 205976 kb
Host smart-01c30e1e-5037-4095-8bd7-76480aa4642f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657430112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3657430112
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.485462874
Short name T364
Test name
Test status
Simulation time 925095983 ps
CPU time 3.19 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:32 PM PDT 24
Peak memory 207684 kb
Host smart-b13d23e4-248c-44ee-a579-ca58f1b83aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485462874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.485462874
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2041552310
Short name T69
Test name
Test status
Simulation time 960692113 ps
CPU time 6.74 seconds
Started Aug 08 05:30:26 PM PDT 24
Finished Aug 08 05:30:33 PM PDT 24
Peak memory 208292 kb
Host smart-d4acf859-2206-4e65-9063-3e1797c6d706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041552310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2041552310
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1634091082
Short name T217
Test name
Test status
Simulation time 180680839 ps
CPU time 3.14 seconds
Started Aug 08 05:30:36 PM PDT 24
Finished Aug 08 05:30:40 PM PDT 24
Peak memory 220236 kb
Host smart-362fe2d3-e51a-4d08-bb67-c19627fabd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634091082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1634091082
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2113337798
Short name T674
Test name
Test status
Simulation time 170098463 ps
CPU time 3.8 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:32 PM PDT 24
Peak memory 214280 kb
Host smart-3b88894a-1324-4637-9d56-96886ced69c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113337798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2113337798
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.1725661439
Short name T240
Test name
Test status
Simulation time 288979247 ps
CPU time 4.68 seconds
Started Aug 08 05:30:32 PM PDT 24
Finished Aug 08 05:30:37 PM PDT 24
Peak memory 208344 kb
Host smart-840447c6-0f5e-4e95-a4fd-503172754221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725661439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1725661439
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2808801827
Short name T764
Test name
Test status
Simulation time 81001402 ps
CPU time 2.58 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:30:25 PM PDT 24
Peak memory 208540 kb
Host smart-d99bce95-48e9-44d2-adb3-d8fd2015eb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808801827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2808801827
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2617732498
Short name T697
Test name
Test status
Simulation time 87069712 ps
CPU time 3.79 seconds
Started Aug 08 05:30:26 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 208784 kb
Host smart-1a8aab65-ca3d-4d14-9500-ec14a02b991f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617732498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2617732498
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3854938860
Short name T427
Test name
Test status
Simulation time 207812574 ps
CPU time 2.97 seconds
Started Aug 08 05:30:17 PM PDT 24
Finished Aug 08 05:30:20 PM PDT 24
Peak memory 208592 kb
Host smart-6b553449-5c5a-4c55-acb2-1470932efc95
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854938860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3854938860
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2387611296
Short name T859
Test name
Test status
Simulation time 307228681 ps
CPU time 2.02 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:30 PM PDT 24
Peak memory 207320 kb
Host smart-a890aadf-3849-4aa2-8d05-8a4f2e81eea1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387611296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2387611296
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1984976876
Short name T869
Test name
Test status
Simulation time 54446039 ps
CPU time 2.79 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 215448 kb
Host smart-6fb8130d-b607-4b10-a7a3-7db60a3f05eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984976876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1984976876
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2451724384
Short name T468
Test name
Test status
Simulation time 5742955202 ps
CPU time 48.23 seconds
Started Aug 08 05:30:21 PM PDT 24
Finished Aug 08 05:31:10 PM PDT 24
Peak memory 208004 kb
Host smart-10a54384-f874-46d1-b1da-a9f213dfff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451724384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2451724384
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1679925955
Short name T762
Test name
Test status
Simulation time 133070748 ps
CPU time 3.93 seconds
Started Aug 08 05:30:25 PM PDT 24
Finished Aug 08 05:30:29 PM PDT 24
Peak memory 207352 kb
Host smart-3646bdf0-7f6a-44e1-b9d8-59bc2b9ac2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679925955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1679925955
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.4206291456
Short name T647
Test name
Test status
Simulation time 303998423 ps
CPU time 2.01 seconds
Started Aug 08 05:30:34 PM PDT 24
Finished Aug 08 05:30:36 PM PDT 24
Peak memory 210008 kb
Host smart-b28a9e46-2f0c-48b7-8632-8a713bd309ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206291456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.4206291456
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1507144058
Short name T534
Test name
Test status
Simulation time 83810095 ps
CPU time 0.76 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:29 PM PDT 24
Peak memory 205924 kb
Host smart-773fe168-229c-4966-9668-2752eb4025e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507144058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1507144058
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1897523966
Short name T876
Test name
Test status
Simulation time 164915949 ps
CPU time 3.01 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 209856 kb
Host smart-3cdb3d1b-17df-4020-b3fa-1a55c2dce06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897523966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1897523966
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.531552054
Short name T875
Test name
Test status
Simulation time 35745237 ps
CPU time 2.34 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 214612 kb
Host smart-9d19f287-ec08-4531-bfe5-a0ca55f54eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531552054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.531552054
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.328801811
Short name T300
Test name
Test status
Simulation time 124518337 ps
CPU time 2.2 seconds
Started Aug 08 05:30:26 PM PDT 24
Finished Aug 08 05:30:29 PM PDT 24
Peak memory 206020 kb
Host smart-11379363-887c-4af7-aa5d-f03ecf861692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328801811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.328801811
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.4187676696
Short name T551
Test name
Test status
Simulation time 71132756 ps
CPU time 2.93 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 214792 kb
Host smart-93c78873-da51-4151-aae7-4d7d1a9fdfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187676696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.4187676696
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.186324249
Short name T443
Test name
Test status
Simulation time 162206056 ps
CPU time 4.11 seconds
Started Aug 08 05:30:27 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 214320 kb
Host smart-c470ca90-1962-48a9-a0a7-e4cc5a385dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186324249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.186324249
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.803866553
Short name T541
Test name
Test status
Simulation time 110457737 ps
CPU time 3.06 seconds
Started Aug 08 05:30:27 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 206836 kb
Host smart-191dd3c4-fc82-45a0-a707-c86c826a7cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803866553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.803866553
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3580421628
Short name T439
Test name
Test status
Simulation time 3405125893 ps
CPU time 54.7 seconds
Started Aug 08 05:30:36 PM PDT 24
Finished Aug 08 05:31:31 PM PDT 24
Peak memory 208704 kb
Host smart-9fa5e2b0-4616-45f0-b7d7-5c0c2e6d578c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580421628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3580421628
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.4170185638
Short name T648
Test name
Test status
Simulation time 100367619 ps
CPU time 3.45 seconds
Started Aug 08 05:30:27 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 208504 kb
Host smart-3fe6541c-fa05-4526-9629-b8d4dd304aec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170185638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4170185638
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2718035607
Short name T878
Test name
Test status
Simulation time 1366707292 ps
CPU time 8.05 seconds
Started Aug 08 05:30:33 PM PDT 24
Finished Aug 08 05:30:41 PM PDT 24
Peak memory 208468 kb
Host smart-2b6fe0fb-1383-44d4-b01f-5bf82c8f2856
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718035607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2718035607
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1869405258
Short name T323
Test name
Test status
Simulation time 236586767 ps
CPU time 8.05 seconds
Started Aug 08 05:30:29 PM PDT 24
Finished Aug 08 05:30:37 PM PDT 24
Peak memory 218560 kb
Host smart-b2a1628d-55ff-48b8-a8bb-7b33a42de2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869405258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1869405258
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.649255503
Short name T662
Test name
Test status
Simulation time 75049650 ps
CPU time 3.32 seconds
Started Aug 08 05:30:34 PM PDT 24
Finished Aug 08 05:30:38 PM PDT 24
Peak memory 206688 kb
Host smart-3346debc-fe06-449a-beb8-8068b89bb154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649255503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.649255503
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1623913871
Short name T504
Test name
Test status
Simulation time 920645016 ps
CPU time 7.22 seconds
Started Aug 08 05:30:25 PM PDT 24
Finished Aug 08 05:30:33 PM PDT 24
Peak memory 214320 kb
Host smart-35ab3a86-4d09-4386-957f-1212b8591ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623913871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1623913871
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3680828100
Short name T5
Test name
Test status
Simulation time 201031469 ps
CPU time 1.87 seconds
Started Aug 08 05:30:26 PM PDT 24
Finished Aug 08 05:30:28 PM PDT 24
Peak memory 209984 kb
Host smart-88591193-822f-4bdc-a957-f079f1be664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680828100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3680828100
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2206382404
Short name T861
Test name
Test status
Simulation time 108642629 ps
CPU time 0.83 seconds
Started Aug 08 05:30:36 PM PDT 24
Finished Aug 08 05:30:37 PM PDT 24
Peak memory 206008 kb
Host smart-a947ddfa-c660-4584-8172-57a0ec4bd4b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206382404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2206382404
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1833071822
Short name T294
Test name
Test status
Simulation time 643612690 ps
CPU time 8.4 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:36 PM PDT 24
Peak memory 214544 kb
Host smart-afe20ce4-51c0-448a-b5a9-88eb7c6e7a5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1833071822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1833071822
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3654590844
Short name T726
Test name
Test status
Simulation time 71190817 ps
CPU time 2.16 seconds
Started Aug 08 05:30:27 PM PDT 24
Finished Aug 08 05:30:30 PM PDT 24
Peak memory 208936 kb
Host smart-fb588a40-349e-473b-ad9e-50fe0433bba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654590844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3654590844
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3893026114
Short name T34
Test name
Test status
Simulation time 19240500 ps
CPU time 1.62 seconds
Started Aug 08 05:30:29 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 207528 kb
Host smart-0207fe09-976d-4f25-b668-6576643d154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893026114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3893026114
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1249832007
Short name T84
Test name
Test status
Simulation time 196963737 ps
CPU time 3.51 seconds
Started Aug 08 05:30:36 PM PDT 24
Finished Aug 08 05:30:40 PM PDT 24
Peak memory 209832 kb
Host smart-ef1e5e74-de6b-4982-b716-744a830275d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249832007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1249832007
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1085756248
Short name T339
Test name
Test status
Simulation time 146418736 ps
CPU time 3.25 seconds
Started Aug 08 05:30:27 PM PDT 24
Finished Aug 08 05:30:30 PM PDT 24
Peak memory 222424 kb
Host smart-8bdc4ac1-7ae5-4114-9b15-f950320e47d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085756248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1085756248
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.513792697
Short name T767
Test name
Test status
Simulation time 179397691 ps
CPU time 5.09 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:33 PM PDT 24
Peak memory 214944 kb
Host smart-93dc6764-0437-4f24-955a-c007ad6c7bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513792697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.513792697
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3140599611
Short name T236
Test name
Test status
Simulation time 269890849 ps
CPU time 3.76 seconds
Started Aug 08 05:30:36 PM PDT 24
Finished Aug 08 05:30:40 PM PDT 24
Peak memory 210104 kb
Host smart-8aaad155-a923-482b-842f-ce1b9c7024b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140599611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3140599611
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.4290233544
Short name T760
Test name
Test status
Simulation time 172900692 ps
CPU time 4.62 seconds
Started Aug 08 05:30:31 PM PDT 24
Finished Aug 08 05:30:36 PM PDT 24
Peak memory 208052 kb
Host smart-34e7a704-423f-4a37-bdf8-3c2807fa773f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290233544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.4290233544
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2106458760
Short name T765
Test name
Test status
Simulation time 67723193 ps
CPU time 2.54 seconds
Started Aug 08 05:30:27 PM PDT 24
Finished Aug 08 05:30:30 PM PDT 24
Peak memory 208852 kb
Host smart-d198c64f-12c4-491d-8e32-5dc91cb6bd01
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106458760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2106458760
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1282970401
Short name T394
Test name
Test status
Simulation time 60148042 ps
CPU time 2.31 seconds
Started Aug 08 05:30:33 PM PDT 24
Finished Aug 08 05:30:35 PM PDT 24
Peak memory 207000 kb
Host smart-a6b0c15d-4089-4168-8091-ef386ca826da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282970401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1282970401
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3571464998
Short name T641
Test name
Test status
Simulation time 162951909 ps
CPU time 2.66 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:32 PM PDT 24
Peak memory 206796 kb
Host smart-4730e194-35bd-48d5-913b-fb842a89cd36
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571464998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3571464998
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.803002565
Short name T332
Test name
Test status
Simulation time 32568109 ps
CPU time 2.12 seconds
Started Aug 08 05:30:32 PM PDT 24
Finished Aug 08 05:30:34 PM PDT 24
Peak memory 209132 kb
Host smart-4d595683-1b55-4b8f-a33b-ce59583bccfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803002565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.803002565
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.4267744049
Short name T393
Test name
Test status
Simulation time 81403222 ps
CPU time 2.69 seconds
Started Aug 08 05:30:34 PM PDT 24
Finished Aug 08 05:30:37 PM PDT 24
Peak memory 206728 kb
Host smart-12d1ce3c-1ade-4113-b37b-065596fae9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267744049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.4267744049
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.705346341
Short name T804
Test name
Test status
Simulation time 1244715670 ps
CPU time 10.15 seconds
Started Aug 08 05:30:26 PM PDT 24
Finished Aug 08 05:30:37 PM PDT 24
Peak memory 215148 kb
Host smart-37b72ad6-e123-4501-a3af-56c8ccc83577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705346341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.705346341
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2311720080
Short name T546
Test name
Test status
Simulation time 283992489 ps
CPU time 7.22 seconds
Started Aug 08 05:30:27 PM PDT 24
Finished Aug 08 05:30:35 PM PDT 24
Peak memory 207916 kb
Host smart-dc5d694c-a544-4c2f-8afc-7cd85d893c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311720080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2311720080
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1015753739
Short name T40
Test name
Test status
Simulation time 476110089 ps
CPU time 3.76 seconds
Started Aug 08 05:30:33 PM PDT 24
Finished Aug 08 05:30:37 PM PDT 24
Peak memory 210040 kb
Host smart-5f197a01-97a0-476d-b607-49f18228fc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015753739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1015753739
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.502357979
Short name T852
Test name
Test status
Simulation time 18503533 ps
CPU time 0.79 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:42 PM PDT 24
Peak memory 205956 kb
Host smart-f7862af6-3e95-4a70-a6ca-f5e4a6419113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502357979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.502357979
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.399009183
Short name T630
Test name
Test status
Simulation time 990612472 ps
CPU time 7.9 seconds
Started Aug 08 05:30:39 PM PDT 24
Finished Aug 08 05:30:47 PM PDT 24
Peak memory 221552 kb
Host smart-171ef083-797d-47d0-802c-f803ea47e6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399009183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.399009183
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3309798624
Short name T280
Test name
Test status
Simulation time 80914332 ps
CPU time 3.86 seconds
Started Aug 08 05:30:31 PM PDT 24
Finished Aug 08 05:30:35 PM PDT 24
Peak memory 218344 kb
Host smart-bddbabb8-2569-4ca8-877d-ed08d1055907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309798624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3309798624
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1777732402
Short name T222
Test name
Test status
Simulation time 94382399 ps
CPU time 4.68 seconds
Started Aug 08 05:30:39 PM PDT 24
Finished Aug 08 05:30:44 PM PDT 24
Peak memory 222432 kb
Host smart-f4e98238-924d-47bb-9b24-636fa82a066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777732402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1777732402
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1235761381
Short name T488
Test name
Test status
Simulation time 291595550 ps
CPU time 3.16 seconds
Started Aug 08 05:30:27 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 214360 kb
Host smart-26a5b51b-437f-426a-b1df-e43628044915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235761381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1235761381
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.437797405
Short name T707
Test name
Test status
Simulation time 449727238 ps
CPU time 4.44 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:33 PM PDT 24
Peak memory 209036 kb
Host smart-b5e3107f-7b6f-4df4-8994-22940042b5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437797405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.437797405
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.346869126
Short name T750
Test name
Test status
Simulation time 450171590 ps
CPU time 10.14 seconds
Started Aug 08 05:30:36 PM PDT 24
Finished Aug 08 05:30:47 PM PDT 24
Peak memory 207448 kb
Host smart-969e02c0-d1bd-4dca-afd3-48201df9c37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346869126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.346869126
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.538962709
Short name T129
Test name
Test status
Simulation time 218430405 ps
CPU time 4.88 seconds
Started Aug 08 05:30:28 PM PDT 24
Finished Aug 08 05:30:34 PM PDT 24
Peak memory 208360 kb
Host smart-75597f5b-004e-472e-82a6-104e88f49cf5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538962709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.538962709
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.256036866
Short name T736
Test name
Test status
Simulation time 67770686 ps
CPU time 2.7 seconds
Started Aug 08 05:30:31 PM PDT 24
Finished Aug 08 05:30:34 PM PDT 24
Peak memory 208656 kb
Host smart-f090494f-c89a-4bf7-a4aa-295686836b9f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256036866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.256036866
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3808643325
Short name T311
Test name
Test status
Simulation time 72650744 ps
CPU time 2.7 seconds
Started Aug 08 05:30:40 PM PDT 24
Finished Aug 08 05:30:43 PM PDT 24
Peak memory 218504 kb
Host smart-e2c097b3-3bc0-4764-a90d-8ffbbc6a9a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808643325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3808643325
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1962627262
Short name T722
Test name
Test status
Simulation time 980075497 ps
CPU time 5.87 seconds
Started Aug 08 05:30:36 PM PDT 24
Finished Aug 08 05:30:42 PM PDT 24
Peak memory 208444 kb
Host smart-62c60bd6-dacd-4a32-a3ab-b5d2ecdccde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962627262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1962627262
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3807390191
Short name T341
Test name
Test status
Simulation time 8214841490 ps
CPU time 51.49 seconds
Started Aug 08 05:30:43 PM PDT 24
Finished Aug 08 05:31:34 PM PDT 24
Peak memory 221804 kb
Host smart-a49b6c18-d8c9-4888-bb06-9049f9c469c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807390191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3807390191
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.578176386
Short name T615
Test name
Test status
Simulation time 7645448838 ps
CPU time 84.93 seconds
Started Aug 08 05:30:34 PM PDT 24
Finished Aug 08 05:31:59 PM PDT 24
Peak memory 222148 kb
Host smart-d36271fe-17a3-427f-8ed1-1a0f3ab85931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578176386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.578176386
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3426865080
Short name T606
Test name
Test status
Simulation time 112461301 ps
CPU time 2.35 seconds
Started Aug 08 05:30:40 PM PDT 24
Finished Aug 08 05:30:43 PM PDT 24
Peak memory 209860 kb
Host smart-975421c6-32f9-49c5-b2ed-fee810f12738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426865080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3426865080
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1734836260
Short name T768
Test name
Test status
Simulation time 23799161 ps
CPU time 0.78 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:42 PM PDT 24
Peak memory 206008 kb
Host smart-1f32335d-cea2-4c8d-8b0e-6ee457c5594e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734836260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1734836260
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1523069848
Short name T894
Test name
Test status
Simulation time 32207744 ps
CPU time 2.55 seconds
Started Aug 08 05:30:42 PM PDT 24
Finished Aug 08 05:30:45 PM PDT 24
Peak memory 214364 kb
Host smart-b3fa8436-4420-4789-9c25-3acfa55f0982
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523069848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1523069848
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.413852012
Short name T758
Test name
Test status
Simulation time 148096486 ps
CPU time 3.36 seconds
Started Aug 08 05:30:39 PM PDT 24
Finished Aug 08 05:30:42 PM PDT 24
Peak memory 218460 kb
Host smart-cbef233b-c142-4d5e-9932-da388ff92b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413852012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.413852012
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.401925537
Short name T88
Test name
Test status
Simulation time 1605592070 ps
CPU time 7.35 seconds
Started Aug 08 05:30:40 PM PDT 24
Finished Aug 08 05:30:47 PM PDT 24
Peak memory 209516 kb
Host smart-49cc4dfe-25b2-48b0-a01b-73f83221a168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401925537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.401925537
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1495039009
Short name T273
Test name
Test status
Simulation time 384220603 ps
CPU time 3.39 seconds
Started Aug 08 05:30:39 PM PDT 24
Finished Aug 08 05:30:43 PM PDT 24
Peak memory 214272 kb
Host smart-a34dec5c-c13d-4a3a-83f6-03a154c46001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495039009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1495039009
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.4170146123
Short name T180
Test name
Test status
Simulation time 75286012 ps
CPU time 2.1 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:44 PM PDT 24
Peak memory 214216 kb
Host smart-cada8c9f-7a67-477a-a719-2e2f95e59674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170146123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.4170146123
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1732600828
Short name T227
Test name
Test status
Simulation time 658150992 ps
CPU time 7.89 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:49 PM PDT 24
Peak memory 209484 kb
Host smart-c49d2b47-d51a-4597-bc89-b5f8c8dfedcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732600828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1732600828
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3485528589
Short name T566
Test name
Test status
Simulation time 164804443 ps
CPU time 3.07 seconds
Started Aug 08 05:30:40 PM PDT 24
Finished Aug 08 05:30:44 PM PDT 24
Peak memory 208668 kb
Host smart-eaa01c75-ea93-43b2-9129-0dcb09ee53ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485528589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3485528589
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.601127797
Short name T652
Test name
Test status
Simulation time 176410572 ps
CPU time 2.48 seconds
Started Aug 08 05:30:50 PM PDT 24
Finished Aug 08 05:30:52 PM PDT 24
Peak memory 207012 kb
Host smart-e102c42f-981e-49f4-8a88-c97ec881e0a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601127797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.601127797
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3877618470
Short name T651
Test name
Test status
Simulation time 1109796874 ps
CPU time 3.09 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:45 PM PDT 24
Peak memory 208556 kb
Host smart-87ce2664-08aa-4dfe-8aec-d8bd56780d74
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877618470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3877618470
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2272542984
Short name T126
Test name
Test status
Simulation time 2022611012 ps
CPU time 23.88 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:31:05 PM PDT 24
Peak memory 208956 kb
Host smart-3d5c70e7-2964-4719-b332-75f2955bbc91
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272542984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2272542984
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4222269949
Short name T698
Test name
Test status
Simulation time 94210437 ps
CPU time 2.48 seconds
Started Aug 08 05:30:42 PM PDT 24
Finished Aug 08 05:30:44 PM PDT 24
Peak memory 209384 kb
Host smart-ffd5b9f3-98f6-4033-9e17-8d932d1e6fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222269949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4222269949
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2207918607
Short name T595
Test name
Test status
Simulation time 54997959 ps
CPU time 1.93 seconds
Started Aug 08 05:30:42 PM PDT 24
Finished Aug 08 05:30:44 PM PDT 24
Peak memory 206844 kb
Host smart-5a2991e7-e007-49ca-8c82-50d65ffc5389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207918607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2207918607
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3831983411
Short name T334
Test name
Test status
Simulation time 216439391 ps
CPU time 2.96 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:44 PM PDT 24
Peak memory 208404 kb
Host smart-2a143624-c603-4b2a-9a2e-9f4c4c3424e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831983411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3831983411
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3800899599
Short name T680
Test name
Test status
Simulation time 378600643 ps
CPU time 4.75 seconds
Started Aug 08 05:30:40 PM PDT 24
Finished Aug 08 05:30:45 PM PDT 24
Peak memory 209692 kb
Host smart-1486b2ee-4436-4e33-a592-cf2cb2ff2a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800899599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3800899599
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1114865465
Short name T729
Test name
Test status
Simulation time 130947117 ps
CPU time 2.81 seconds
Started Aug 08 05:30:43 PM PDT 24
Finished Aug 08 05:30:46 PM PDT 24
Peak memory 209956 kb
Host smart-3fad5b05-5e2e-440c-b1f4-13ba702fe719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114865465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1114865465
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.4045308709
Short name T460
Test name
Test status
Simulation time 36200327 ps
CPU time 0.8 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:42 PM PDT 24
Peak memory 205964 kb
Host smart-ddc867c3-118c-476c-b492-d29d943b6eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045308709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.4045308709
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1002142982
Short name T369
Test name
Test status
Simulation time 38423355 ps
CPU time 2.76 seconds
Started Aug 08 05:30:51 PM PDT 24
Finished Aug 08 05:30:54 PM PDT 24
Peak memory 214372 kb
Host smart-1cbf8381-f6d5-49eb-9db0-fe3afc7e6dab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002142982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1002142982
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.4116873395
Short name T28
Test name
Test status
Simulation time 190312315 ps
CPU time 2.56 seconds
Started Aug 08 05:30:40 PM PDT 24
Finished Aug 08 05:30:43 PM PDT 24
Peak memory 217420 kb
Host smart-6a8e3617-0d2e-499e-8be4-e694fe813e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116873395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.4116873395
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3035699810
Short name T899
Test name
Test status
Simulation time 153033326 ps
CPU time 4.6 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:45 PM PDT 24
Peak memory 214288 kb
Host smart-08d1cc13-7d20-434d-a551-6e344ce392f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035699810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3035699810
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.4221359255
Short name T87
Test name
Test status
Simulation time 511638439 ps
CPU time 3.15 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:45 PM PDT 24
Peak memory 214280 kb
Host smart-39f73070-de68-4442-a7e2-f5b2fd8935a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221359255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.4221359255
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.731370371
Short name T338
Test name
Test status
Simulation time 37797424 ps
CPU time 2.92 seconds
Started Aug 08 05:30:40 PM PDT 24
Finished Aug 08 05:30:43 PM PDT 24
Peak memory 214264 kb
Host smart-d759a0b2-20a4-4c92-b78c-9e54f6e9ff27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731370371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.731370371
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3863158256
Short name T616
Test name
Test status
Simulation time 581797548 ps
CPU time 4.19 seconds
Started Aug 08 05:30:51 PM PDT 24
Finished Aug 08 05:30:55 PM PDT 24
Peak memory 222528 kb
Host smart-3d7d48c4-2b58-4eac-8301-4949f5626ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863158256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3863158256
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1689816996
Short name T788
Test name
Test status
Simulation time 1201034708 ps
CPU time 4.12 seconds
Started Aug 08 05:30:40 PM PDT 24
Finished Aug 08 05:30:45 PM PDT 24
Peak memory 207560 kb
Host smart-6dd7f8af-94f2-4d90-be5a-c41231274179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689816996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1689816996
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.571179931
Short name T604
Test name
Test status
Simulation time 172570652 ps
CPU time 5.01 seconds
Started Aug 08 05:30:51 PM PDT 24
Finished Aug 08 05:30:56 PM PDT 24
Peak memory 207952 kb
Host smart-7bee2824-52b6-49fe-a4f3-e1ab78c84da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571179931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.571179931
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.4135074281
Short name T880
Test name
Test status
Simulation time 74095086 ps
CPU time 3.46 seconds
Started Aug 08 05:30:42 PM PDT 24
Finished Aug 08 05:30:45 PM PDT 24
Peak memory 209068 kb
Host smart-d87013c9-8e6c-45a4-9f94-2b3ce0d26210
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135074281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.4135074281
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1769371350
Short name T617
Test name
Test status
Simulation time 60241736 ps
CPU time 3.04 seconds
Started Aug 08 05:30:40 PM PDT 24
Finished Aug 08 05:30:43 PM PDT 24
Peak memory 208684 kb
Host smart-b8d2ca0b-c255-469f-9a46-3e4eccabafa9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769371350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1769371350
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1322646860
Short name T575
Test name
Test status
Simulation time 791687577 ps
CPU time 6.22 seconds
Started Aug 08 05:30:39 PM PDT 24
Finished Aug 08 05:30:45 PM PDT 24
Peak memory 209020 kb
Host smart-ae9cc64b-5f6f-4383-b385-960755832c33
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322646860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1322646860
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.64936837
Short name T458
Test name
Test status
Simulation time 785613224 ps
CPU time 3.41 seconds
Started Aug 08 05:30:50 PM PDT 24
Finished Aug 08 05:30:54 PM PDT 24
Peak memory 209880 kb
Host smart-057313e9-03e4-4561-8b85-89868a6cb074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64936837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.64936837
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1263164477
Short name T83
Test name
Test status
Simulation time 122613161 ps
CPU time 2.24 seconds
Started Aug 08 05:30:51 PM PDT 24
Finished Aug 08 05:30:53 PM PDT 24
Peak memory 208452 kb
Host smart-e14a9e63-15d7-4511-b5a9-22e724d6a2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263164477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1263164477
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.176955788
Short name T207
Test name
Test status
Simulation time 1955678154 ps
CPU time 28.78 seconds
Started Aug 08 05:30:42 PM PDT 24
Finished Aug 08 05:31:11 PM PDT 24
Peak memory 222460 kb
Host smart-1e387bff-1897-4cbd-9e0c-312f53d4fa6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176955788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.176955788
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2667293549
Short name T605
Test name
Test status
Simulation time 67780550 ps
CPU time 2.64 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:44 PM PDT 24
Peak memory 208280 kb
Host smart-fa8ef640-1db7-47d6-93fe-815615b4c591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667293549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2667293549
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2546349533
Short name T800
Test name
Test status
Simulation time 203594348 ps
CPU time 3.94 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:45 PM PDT 24
Peak memory 210228 kb
Host smart-91f3471a-6139-4c6c-b264-a1fafcb6e81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546349533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2546349533
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3491981590
Short name T888
Test name
Test status
Simulation time 11616803 ps
CPU time 0.87 seconds
Started Aug 08 05:29:11 PM PDT 24
Finished Aug 08 05:29:12 PM PDT 24
Peak memory 205864 kb
Host smart-d17130cb-a356-4115-91a9-4325c914cd6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491981590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3491981590
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3797507740
Short name T374
Test name
Test status
Simulation time 396740989 ps
CPU time 5.51 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:15 PM PDT 24
Peak memory 214336 kb
Host smart-f1909843-2ab2-48c3-ba86-8e4300fff26c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797507740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3797507740
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.955611510
Short name T795
Test name
Test status
Simulation time 143023082 ps
CPU time 2.23 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:11 PM PDT 24
Peak memory 208836 kb
Host smart-ec42b9da-1917-445d-be25-97fa0f6c832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955611510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.955611510
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2018324899
Short name T710
Test name
Test status
Simulation time 47010789 ps
CPU time 2.37 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:11 PM PDT 24
Peak memory 214396 kb
Host smart-afd7cbaa-a91e-48f9-b40a-89051352162a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018324899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2018324899
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2776258880
Short name T4
Test name
Test status
Simulation time 583785165 ps
CPU time 8.54 seconds
Started Aug 08 05:29:10 PM PDT 24
Finished Aug 08 05:29:18 PM PDT 24
Peak memory 209172 kb
Host smart-53281d33-56d7-4c9b-9905-334ff9e9466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776258880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2776258880
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.749904405
Short name T15
Test name
Test status
Simulation time 513748484 ps
CPU time 4.5 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:14 PM PDT 24
Peak memory 215076 kb
Host smart-fb09229c-1aa5-4756-aa60-075047acb16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749904405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.749904405
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.326842278
Short name T401
Test name
Test status
Simulation time 177210675 ps
CPU time 2.83 seconds
Started Aug 08 05:29:11 PM PDT 24
Finished Aug 08 05:29:14 PM PDT 24
Peak memory 216240 kb
Host smart-d79f3fa8-6347-4b1e-9fa2-0c003d17564c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326842278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.326842278
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.668562773
Short name T785
Test name
Test status
Simulation time 266707314 ps
CPU time 4.89 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:14 PM PDT 24
Peak memory 219188 kb
Host smart-eb055aee-a42c-4f30-a8c0-64336bd68b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668562773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.668562773
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1345932889
Short name T759
Test name
Test status
Simulation time 2899248040 ps
CPU time 21.04 seconds
Started Aug 08 05:29:10 PM PDT 24
Finished Aug 08 05:29:31 PM PDT 24
Peak memory 207984 kb
Host smart-75ee088c-1b91-430e-b813-5973d43d8932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345932889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1345932889
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1429647188
Short name T365
Test name
Test status
Simulation time 1029804869 ps
CPU time 27.53 seconds
Started Aug 08 05:29:08 PM PDT 24
Finished Aug 08 05:29:36 PM PDT 24
Peak memory 208920 kb
Host smart-783dbb3e-e8d4-46f5-b00b-8ebdef58dac8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429647188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1429647188
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1470747707
Short name T523
Test name
Test status
Simulation time 249633691 ps
CPU time 7.22 seconds
Started Aug 08 05:29:07 PM PDT 24
Finished Aug 08 05:29:14 PM PDT 24
Peak memory 207904 kb
Host smart-ffc5c1d1-ac72-49dc-a525-33a067c8c9e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470747707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1470747707
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3490524846
Short name T564
Test name
Test status
Simulation time 106257233 ps
CPU time 3.92 seconds
Started Aug 08 05:29:10 PM PDT 24
Finished Aug 08 05:29:14 PM PDT 24
Peak memory 206808 kb
Host smart-0c9e1b1f-44b5-4d44-b5f6-c2c5abb53a33
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490524846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3490524846
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2977883467
Short name T600
Test name
Test status
Simulation time 376493922 ps
CPU time 5.02 seconds
Started Aug 08 05:29:10 PM PDT 24
Finished Aug 08 05:29:15 PM PDT 24
Peak memory 214456 kb
Host smart-9fd82c98-96ca-4354-96a4-c4d38b41c513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977883467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2977883467
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2036432748
Short name T803
Test name
Test status
Simulation time 409606188 ps
CPU time 2.78 seconds
Started Aug 08 05:29:08 PM PDT 24
Finished Aug 08 05:29:11 PM PDT 24
Peak memory 208708 kb
Host smart-7972c947-5656-4b84-a792-896e8d7b8a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036432748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2036432748
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2058799398
Short name T322
Test name
Test status
Simulation time 14067431566 ps
CPU time 22.49 seconds
Started Aug 08 05:29:08 PM PDT 24
Finished Aug 08 05:29:31 PM PDT 24
Peak memory 221356 kb
Host smart-f45e0e93-ad6a-4ac9-b36b-fa9681d211ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058799398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2058799398
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1933384269
Short name T307
Test name
Test status
Simulation time 135094595 ps
CPU time 5.55 seconds
Started Aug 08 05:29:10 PM PDT 24
Finished Aug 08 05:29:16 PM PDT 24
Peak memory 214352 kb
Host smart-65c05455-c188-451f-a358-8400361c9838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933384269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1933384269
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.4003344004
Short name T635
Test name
Test status
Simulation time 79902942 ps
CPU time 1.06 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:30:54 PM PDT 24
Peak memory 206028 kb
Host smart-d61e5d6b-3315-49b7-9e94-2866b4297f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003344004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.4003344004
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1967770973
Short name T271
Test name
Test status
Simulation time 155352740 ps
CPU time 8.27 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:31:02 PM PDT 24
Peak memory 214264 kb
Host smart-2a41304a-4c8d-4975-b0e3-a30bb556df92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1967770973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1967770973
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.4156434084
Short name T263
Test name
Test status
Simulation time 4717732093 ps
CPU time 19.51 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:31:12 PM PDT 24
Peak memory 209044 kb
Host smart-a2a52a08-0441-40e1-9d08-066301e59500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156434084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.4156434084
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1190754014
Short name T695
Test name
Test status
Simulation time 49087739 ps
CPU time 3.17 seconds
Started Aug 08 05:30:55 PM PDT 24
Finished Aug 08 05:30:58 PM PDT 24
Peak memory 209868 kb
Host smart-867a9a02-81d5-462b-a8a1-94906bf01a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190754014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1190754014
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3917386481
Short name T238
Test name
Test status
Simulation time 400297493 ps
CPU time 3.29 seconds
Started Aug 08 05:31:02 PM PDT 24
Finished Aug 08 05:31:06 PM PDT 24
Peak memory 208204 kb
Host smart-e2be0bf8-a17b-4621-a157-0f977dfabd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917386481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3917386481
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3766503350
Short name T646
Test name
Test status
Simulation time 227923348 ps
CPU time 5.35 seconds
Started Aug 08 05:30:43 PM PDT 24
Finished Aug 08 05:30:48 PM PDT 24
Peak memory 209676 kb
Host smart-80104ca0-eb9d-4ee4-8b3c-b4feb4bb8d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766503350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3766503350
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1862620799
Short name T481
Test name
Test status
Simulation time 472929386 ps
CPU time 3.66 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:45 PM PDT 24
Peak memory 208440 kb
Host smart-929330b6-00ce-47eb-ab05-1d194ab2f449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862620799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1862620799
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3806290047
Short name T325
Test name
Test status
Simulation time 315584259 ps
CPU time 2.97 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:44 PM PDT 24
Peak memory 208792 kb
Host smart-905e6317-dca4-4c4e-9f92-a902c2e5547c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806290047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3806290047
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2647697648
Short name T690
Test name
Test status
Simulation time 380288571 ps
CPU time 4.72 seconds
Started Aug 08 05:30:41 PM PDT 24
Finished Aug 08 05:30:45 PM PDT 24
Peak memory 208812 kb
Host smart-497f7236-d103-4fdd-9edc-465307a5c3a3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647697648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2647697648
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3612886460
Short name T527
Test name
Test status
Simulation time 177787681 ps
CPU time 3.09 seconds
Started Aug 08 05:30:55 PM PDT 24
Finished Aug 08 05:30:58 PM PDT 24
Peak memory 209180 kb
Host smart-1097bc66-9945-4e51-b873-d0acadfdeb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612886460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3612886460
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.217623976
Short name T627
Test name
Test status
Simulation time 125916559 ps
CPU time 3.53 seconds
Started Aug 08 05:30:40 PM PDT 24
Finished Aug 08 05:30:44 PM PDT 24
Peak memory 207824 kb
Host smart-0a66add2-d76c-46a8-8e52-db981bffe900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217623976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.217623976
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3170020123
Short name T172
Test name
Test status
Simulation time 587885409 ps
CPU time 19.76 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:31:13 PM PDT 24
Peak memory 220372 kb
Host smart-6a16e86c-bd25-4de5-b7ac-992495f3c7fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170020123 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3170020123
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1440454596
Short name T345
Test name
Test status
Simulation time 261438441 ps
CPU time 5.68 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:31:00 PM PDT 24
Peak memory 207364 kb
Host smart-43bee803-dd7b-463e-8415-17170f1165c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440454596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1440454596
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3216187243
Short name T404
Test name
Test status
Simulation time 43889183 ps
CPU time 2.69 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:30:56 PM PDT 24
Peak memory 210088 kb
Host smart-c3b5b551-e501-4c63-ab70-cebb486be8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216187243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3216187243
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3295198564
Short name T781
Test name
Test status
Simulation time 43895519 ps
CPU time 0.74 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:30:55 PM PDT 24
Peak memory 205996 kb
Host smart-6041b3e4-c861-4c17-9b4f-4e5c5a90bb4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295198564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3295198564
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2572884417
Short name T526
Test name
Test status
Simulation time 316512931 ps
CPU time 3.31 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:30:56 PM PDT 24
Peak memory 207004 kb
Host smart-d9cf469f-7018-4b5a-b533-84b6e900d787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572884417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2572884417
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.4283958576
Short name T653
Test name
Test status
Simulation time 8645082872 ps
CPU time 11.87 seconds
Started Aug 08 05:30:51 PM PDT 24
Finished Aug 08 05:31:03 PM PDT 24
Peak memory 209304 kb
Host smart-cb08e092-3317-4868-b654-eb491b073ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283958576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.4283958576
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3591290571
Short name T743
Test name
Test status
Simulation time 325227390 ps
CPU time 4.71 seconds
Started Aug 08 05:30:52 PM PDT 24
Finished Aug 08 05:30:57 PM PDT 24
Peak memory 221752 kb
Host smart-accbe098-55a7-4c0a-8b2b-67299aadd400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591290571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3591290571
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.414036083
Short name T7
Test name
Test status
Simulation time 102233201 ps
CPU time 3.25 seconds
Started Aug 08 05:30:52 PM PDT 24
Finished Aug 08 05:30:56 PM PDT 24
Peak memory 214348 kb
Host smart-9f8ba8de-7208-4034-90aa-274c52027862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414036083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.414036083
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.198823129
Short name T516
Test name
Test status
Simulation time 2484110522 ps
CPU time 9.22 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:31:04 PM PDT 24
Peak memory 209400 kb
Host smart-9156e557-92f5-4078-8db2-d59fa2129ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198823129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.198823129
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4222088692
Short name T855
Test name
Test status
Simulation time 71442452 ps
CPU time 2.53 seconds
Started Aug 08 05:30:55 PM PDT 24
Finished Aug 08 05:30:58 PM PDT 24
Peak memory 208656 kb
Host smart-fc29c60b-c2c1-4338-a3af-fe9f209f14be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222088692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4222088692
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2511399130
Short name T624
Test name
Test status
Simulation time 369568079 ps
CPU time 2.34 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:30:56 PM PDT 24
Peak memory 208112 kb
Host smart-e1876221-ef5d-438a-94eb-ba8da691482d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511399130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2511399130
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1850290213
Short name T735
Test name
Test status
Simulation time 7615964024 ps
CPU time 31.61 seconds
Started Aug 08 05:30:52 PM PDT 24
Finished Aug 08 05:31:24 PM PDT 24
Peak memory 208480 kb
Host smart-f96dc7f1-78e2-415a-b2b9-280a353d67dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850290213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1850290213
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2405905711
Short name T532
Test name
Test status
Simulation time 1437772080 ps
CPU time 4.33 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:30:59 PM PDT 24
Peak memory 208952 kb
Host smart-66b59764-1361-430a-aa40-61472e7e1415
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405905711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2405905711
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1695373257
Short name T290
Test name
Test status
Simulation time 2612843720 ps
CPU time 24.49 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:31:18 PM PDT 24
Peak memory 208216 kb
Host smart-7fadd10c-ab71-4968-8a19-f83acefcfcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695373257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1695373257
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2542985637
Short name T689
Test name
Test status
Simulation time 41129266 ps
CPU time 1.89 seconds
Started Aug 08 05:30:52 PM PDT 24
Finished Aug 08 05:30:54 PM PDT 24
Peak memory 208548 kb
Host smart-0e064637-e406-473a-a54e-44e6a910ec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542985637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2542985637
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2624344036
Short name T201
Test name
Test status
Simulation time 769506880 ps
CPU time 21.12 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:31:14 PM PDT 24
Peak memory 215276 kb
Host smart-8d31753c-4093-4882-8cc1-70a145b0b104
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624344036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2624344036
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3725302644
Short name T305
Test name
Test status
Simulation time 513617216 ps
CPU time 20.78 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:31:15 PM PDT 24
Peak memory 220356 kb
Host smart-f5d865a5-06e8-456e-9ec5-d02cca679ea2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725302644 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3725302644
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.207067047
Short name T241
Test name
Test status
Simulation time 90238552 ps
CPU time 3.53 seconds
Started Aug 08 05:30:52 PM PDT 24
Finished Aug 08 05:30:56 PM PDT 24
Peak memory 214424 kb
Host smart-a9d5779a-9bde-43e7-9b84-43d62b68b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207067047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.207067047
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1591766897
Short name T477
Test name
Test status
Simulation time 15388891 ps
CPU time 0.83 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:30:55 PM PDT 24
Peak memory 206000 kb
Host smart-f8c7d7d4-6620-4203-a85e-3b460b15eb27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591766897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1591766897
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3803769206
Short name T136
Test name
Test status
Simulation time 138782615 ps
CPU time 2.49 seconds
Started Aug 08 05:31:03 PM PDT 24
Finished Aug 08 05:31:06 PM PDT 24
Peak memory 214352 kb
Host smart-a97530db-e734-494b-8f65-d8e96cb74933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803769206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3803769206
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.380556078
Short name T712
Test name
Test status
Simulation time 57651023 ps
CPU time 3.66 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:30:56 PM PDT 24
Peak memory 222576 kb
Host smart-03602e60-0bec-4d9f-9388-025c6d2d8448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380556078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.380556078
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.313069018
Short name T507
Test name
Test status
Simulation time 2050853449 ps
CPU time 6.9 seconds
Started Aug 08 05:30:58 PM PDT 24
Finished Aug 08 05:31:05 PM PDT 24
Peak memory 218508 kb
Host smart-7ebd75bd-6b48-459e-b015-7fdda4a71b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313069018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.313069018
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.146099230
Short name T854
Test name
Test status
Simulation time 320182418 ps
CPU time 2.88 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:30:56 PM PDT 24
Peak memory 214304 kb
Host smart-9341e0b7-d27f-4bfd-b8b2-c31311ad0d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146099230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.146099230
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3527967159
Short name T304
Test name
Test status
Simulation time 572710438 ps
CPU time 6.1 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:31:01 PM PDT 24
Peak memory 222448 kb
Host smart-efa52b3a-b3e1-4d81-a018-0a7cf3bc4517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527967159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3527967159
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.4243847402
Short name T863
Test name
Test status
Simulation time 339973781 ps
CPU time 3.68 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:30:57 PM PDT 24
Peak memory 208084 kb
Host smart-39eb81b9-28f7-450c-b3aa-9ac9b950f009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243847402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.4243847402
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1408624429
Short name T868
Test name
Test status
Simulation time 915166470 ps
CPU time 7.82 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:31:02 PM PDT 24
Peak memory 218220 kb
Host smart-c746af4e-20dd-4b9e-a280-10c7d3be8b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408624429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1408624429
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2013281866
Short name T444
Test name
Test status
Simulation time 48161176 ps
CPU time 2.75 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:30:56 PM PDT 24
Peak memory 206844 kb
Host smart-2398b296-d182-42f5-a06b-79a7a37523ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013281866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2013281866
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2241846111
Short name T421
Test name
Test status
Simulation time 155959058 ps
CPU time 2.91 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:30:57 PM PDT 24
Peak memory 209084 kb
Host smart-7445e0af-b224-4e26-a789-d89476ed7f1f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241846111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2241846111
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3987174185
Short name T430
Test name
Test status
Simulation time 355243085 ps
CPU time 7.41 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:31:00 PM PDT 24
Peak memory 208076 kb
Host smart-38d36bf2-ea87-4be2-8bb5-97e55cc8a84a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987174185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3987174185
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2002019590
Short name T474
Test name
Test status
Simulation time 13108743987 ps
CPU time 30.39 seconds
Started Aug 08 05:30:56 PM PDT 24
Finished Aug 08 05:31:26 PM PDT 24
Peak memory 208656 kb
Host smart-36ad913c-e549-4b69-b688-70230b3f6b44
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002019590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2002019590
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2273997356
Short name T554
Test name
Test status
Simulation time 125308844 ps
CPU time 5.11 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:30:59 PM PDT 24
Peak memory 218408 kb
Host smart-c99e96a3-a2a4-43b1-8244-8dc1e4598d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273997356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2273997356
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.706529714
Short name T593
Test name
Test status
Simulation time 99358367 ps
CPU time 2.52 seconds
Started Aug 08 05:30:52 PM PDT 24
Finished Aug 08 05:30:55 PM PDT 24
Peak memory 208464 kb
Host smart-5556c98f-5119-40d5-93a2-79ae3aefed7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706529714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.706529714
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3997226916
Short name T187
Test name
Test status
Simulation time 1453977492 ps
CPU time 27.83 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:31:22 PM PDT 24
Peak memory 222376 kb
Host smart-7f2f4a58-6799-428f-8d7a-5e089a7d78d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997226916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3997226916
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.77053216
Short name T752
Test name
Test status
Simulation time 61764856 ps
CPU time 2.19 seconds
Started Aug 08 05:30:55 PM PDT 24
Finished Aug 08 05:30:57 PM PDT 24
Peak memory 209940 kb
Host smart-604fe605-5f28-4e65-af37-de54c0afafcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77053216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.77053216
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2524270758
Short name T445
Test name
Test status
Simulation time 12896110 ps
CPU time 0.81 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:07 PM PDT 24
Peak memory 205916 kb
Host smart-206e5cb0-c648-4902-bfdf-e2f42c4433f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524270758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2524270758
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2691483820
Short name T77
Test name
Test status
Simulation time 1231755431 ps
CPU time 13.8 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:31:07 PM PDT 24
Peak memory 214304 kb
Host smart-ab9e7ce6-39d5-48b1-a7da-b9a03fb6e6e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691483820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2691483820
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3709323642
Short name T98
Test name
Test status
Simulation time 54368750 ps
CPU time 3.29 seconds
Started Aug 08 05:31:07 PM PDT 24
Finished Aug 08 05:31:11 PM PDT 24
Peak memory 214524 kb
Host smart-72d29747-d8c2-4958-ae17-ee72d254eeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709323642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3709323642
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1801780813
Short name T778
Test name
Test status
Simulation time 164929594 ps
CPU time 3.91 seconds
Started Aug 08 05:31:04 PM PDT 24
Finished Aug 08 05:31:08 PM PDT 24
Peak memory 209644 kb
Host smart-bd10a082-fbc7-4dd3-a94d-baa81c548eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801780813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1801780813
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3507837879
Short name T350
Test name
Test status
Simulation time 34269214 ps
CPU time 2.52 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 214248 kb
Host smart-4e49d5e4-407c-44fd-9b13-606e88b57467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507837879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3507837879
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.498857776
Short name T682
Test name
Test status
Simulation time 3929435883 ps
CPU time 60.64 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:32:07 PM PDT 24
Peak memory 222108 kb
Host smart-75d97caf-323f-42a8-b1b5-6271dd8f9310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498857776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.498857776
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.850081390
Short name T411
Test name
Test status
Simulation time 649573518 ps
CPU time 18.31 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:31:11 PM PDT 24
Peak memory 220088 kb
Host smart-bb2d0c5e-d2be-426b-a8c8-aee47f537b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850081390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.850081390
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1728063303
Short name T542
Test name
Test status
Simulation time 69271293 ps
CPU time 3.23 seconds
Started Aug 08 05:30:52 PM PDT 24
Finished Aug 08 05:30:55 PM PDT 24
Peak memory 207952 kb
Host smart-454cd94d-1eb7-4a9b-88c4-be898370faa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728063303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1728063303
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4283628134
Short name T655
Test name
Test status
Simulation time 81459818 ps
CPU time 3.15 seconds
Started Aug 08 05:30:54 PM PDT 24
Finished Aug 08 05:30:57 PM PDT 24
Peak memory 208640 kb
Host smart-c5210075-9005-4b94-9c0c-b749a238068a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283628134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4283628134
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2163241532
Short name T487
Test name
Test status
Simulation time 722045262 ps
CPU time 8.55 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:31:02 PM PDT 24
Peak memory 208404 kb
Host smart-277499be-f0f9-4bc3-8dc6-68fca3d7b0f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163241532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2163241532
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2388070662
Short name T857
Test name
Test status
Simulation time 379010965 ps
CPU time 3.02 seconds
Started Aug 08 05:30:53 PM PDT 24
Finished Aug 08 05:30:56 PM PDT 24
Peak memory 208772 kb
Host smart-f7655f45-4213-41df-a533-5e07640f61a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388070662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2388070662
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3265348352
Short name T104
Test name
Test status
Simulation time 1598945940 ps
CPU time 39.67 seconds
Started Aug 08 05:30:55 PM PDT 24
Finished Aug 08 05:31:34 PM PDT 24
Peak memory 208580 kb
Host smart-e6f4bcb3-e123-4c85-a265-b4cb1848d21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265348352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3265348352
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2109671718
Short name T361
Test name
Test status
Simulation time 1371844459 ps
CPU time 10.33 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:16 PM PDT 24
Peak memory 219692 kb
Host smart-10088acf-60d6-4118-868f-d5dd991bccfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109671718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2109671718
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3238357358
Short name T877
Test name
Test status
Simulation time 272966695 ps
CPU time 7.86 seconds
Started Aug 08 05:31:04 PM PDT 24
Finished Aug 08 05:31:12 PM PDT 24
Peak memory 214324 kb
Host smart-ddeb1b61-283a-4990-999b-cdc46f0f2532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238357358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3238357358
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3195140310
Short name T497
Test name
Test status
Simulation time 12174014 ps
CPU time 0.84 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:06 PM PDT 24
Peak memory 205884 kb
Host smart-32400e63-1aee-47e8-bce8-bd10dfad02c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195140310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3195140310
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1043697566
Short name T377
Test name
Test status
Simulation time 53889885 ps
CPU time 3.78 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:11 PM PDT 24
Peak memory 214304 kb
Host smart-4d8f66f8-87ad-4cc8-8713-c43318836ab8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043697566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1043697566
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3605231579
Short name T814
Test name
Test status
Simulation time 112818210 ps
CPU time 2.74 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:08 PM PDT 24
Peak memory 209916 kb
Host smart-f61d79f0-3b29-4fd5-bf75-f04a19502d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605231579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3605231579
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1758751159
Short name T838
Test name
Test status
Simulation time 4399139794 ps
CPU time 27.86 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:35 PM PDT 24
Peak memory 218380 kb
Host smart-3c01288f-3510-45a7-a463-9ec4eaad3c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758751159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1758751159
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2804532241
Short name T900
Test name
Test status
Simulation time 115884116 ps
CPU time 2.14 seconds
Started Aug 08 05:31:07 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 214268 kb
Host smart-b991ffce-5568-4817-a407-6f1aa470bc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804532241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2804532241
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1288630667
Short name T245
Test name
Test status
Simulation time 268841835 ps
CPU time 1.91 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 214316 kb
Host smart-63662080-3c56-4d5e-888c-7e7e08eb7e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288630667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1288630667
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2030720966
Short name T870
Test name
Test status
Simulation time 287462899 ps
CPU time 2.95 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:10 PM PDT 24
Peak memory 215644 kb
Host smart-5e4f7341-6aab-46fd-ae91-4a689fd72966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030720966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2030720966
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3928165359
Short name T639
Test name
Test status
Simulation time 4717723219 ps
CPU time 30.29 seconds
Started Aug 08 05:31:04 PM PDT 24
Finished Aug 08 05:31:35 PM PDT 24
Peak memory 217832 kb
Host smart-44fcd28c-2cc8-4363-b363-26e6e8018b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928165359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3928165359
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.28506238
Short name T182
Test name
Test status
Simulation time 76360368 ps
CPU time 3.76 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 208656 kb
Host smart-ef7a745c-97cf-474d-aa75-dc53952dce9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28506238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.28506238
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2180191359
Short name T776
Test name
Test status
Simulation time 172301972 ps
CPU time 1.8 seconds
Started Aug 08 05:31:03 PM PDT 24
Finished Aug 08 05:31:05 PM PDT 24
Peak memory 206828 kb
Host smart-7bdc8165-f3a3-4289-81d4-8f3548992e6b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180191359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2180191359
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2617950059
Short name T291
Test name
Test status
Simulation time 147718679 ps
CPU time 4.5 seconds
Started Aug 08 05:31:03 PM PDT 24
Finished Aug 08 05:31:07 PM PDT 24
Peak memory 208140 kb
Host smart-ed29c8bb-be48-49f4-98c5-f03d4e2fa5a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617950059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2617950059
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3303696016
Short name T464
Test name
Test status
Simulation time 1857555906 ps
CPU time 20.4 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:27 PM PDT 24
Peak memory 208304 kb
Host smart-1aff16b5-7a77-47a1-bccd-24c938be3e26
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303696016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3303696016
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3740091628
Short name T592
Test name
Test status
Simulation time 57032462 ps
CPU time 2.72 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:08 PM PDT 24
Peak memory 217976 kb
Host smart-42c4794c-b9d5-4f65-af55-89daf4f1f055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740091628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3740091628
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2231809743
Short name T683
Test name
Test status
Simulation time 515185787 ps
CPU time 3.53 seconds
Started Aug 08 05:31:03 PM PDT 24
Finished Aug 08 05:31:07 PM PDT 24
Peak memory 208336 kb
Host smart-19b87e4d-28a9-464c-b341-0e9e34d9d06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231809743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2231809743
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3585763507
Short name T563
Test name
Test status
Simulation time 433023208 ps
CPU time 20.54 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:27 PM PDT 24
Peak memory 222572 kb
Host smart-1fe3752e-831e-44f7-91a4-60446c3bf1b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585763507 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3585763507
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3341281664
Short name T745
Test name
Test status
Simulation time 607161978 ps
CPU time 4.3 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 209260 kb
Host smart-7573d531-6563-4cb2-acaf-f4bad772c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341281664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3341281664
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.335120042
Short name T535
Test name
Test status
Simulation time 64471514 ps
CPU time 2.71 seconds
Started Aug 08 05:31:04 PM PDT 24
Finished Aug 08 05:31:07 PM PDT 24
Peak memory 209788 kb
Host smart-3ae1295a-fb3b-48b5-9aec-6618fc012fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335120042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.335120042
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.664483506
Short name T713
Test name
Test status
Simulation time 164314887 ps
CPU time 0.83 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:06 PM PDT 24
Peak memory 206004 kb
Host smart-925bdb60-e3c8-44bb-8e0d-63d9daf6b80b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664483506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.664483506
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3361273851
Short name T738
Test name
Test status
Simulation time 62224398 ps
CPU time 2.9 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 218276 kb
Host smart-567fdb3c-9fee-4286-99e8-4224597a40b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361273851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3361273851
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1101509721
Short name T321
Test name
Test status
Simulation time 246141782 ps
CPU time 2.75 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 214312 kb
Host smart-eeee8696-bc57-40e4-a289-d448cfd0ec5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101509721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1101509721
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.744855666
Short name T51
Test name
Test status
Simulation time 40529593 ps
CPU time 2.03 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:07 PM PDT 24
Peak memory 214720 kb
Host smart-abd08e8b-1599-43bb-a4c4-dcd1fee8084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744855666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.744855666
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3609504550
Short name T794
Test name
Test status
Simulation time 253556227 ps
CPU time 2.53 seconds
Started Aug 08 05:31:07 PM PDT 24
Finished Aug 08 05:31:10 PM PDT 24
Peak memory 207996 kb
Host smart-1491faa4-9d1f-4630-aa05-31251ace497d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609504550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3609504550
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2649711064
Short name T465
Test name
Test status
Simulation time 325916902 ps
CPU time 3.11 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 206812 kb
Host smart-ee08851f-bbee-46ef-b5ef-298fc95344a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649711064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2649711064
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4209855765
Short name T428
Test name
Test status
Simulation time 451537956 ps
CPU time 3.53 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:10 PM PDT 24
Peak memory 208212 kb
Host smart-2e20bca5-aae1-4c05-aafa-965fd1a6850c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209855765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4209855765
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2767639899
Short name T558
Test name
Test status
Simulation time 142348314 ps
CPU time 2.96 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:10 PM PDT 24
Peak memory 208784 kb
Host smart-2473f508-f46e-47be-bb2b-d5a6c784a2ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767639899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2767639899
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2903350076
Short name T815
Test name
Test status
Simulation time 124625290 ps
CPU time 4.52 seconds
Started Aug 08 05:31:04 PM PDT 24
Finished Aug 08 05:31:08 PM PDT 24
Peak memory 208292 kb
Host smart-506aaeee-f9d5-4400-8503-abe2b07ba859
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903350076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2903350076
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.181485760
Short name T485
Test name
Test status
Simulation time 30574526 ps
CPU time 2.04 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:08 PM PDT 24
Peak memory 207276 kb
Host smart-ca44e450-6a75-46fc-a9eb-da94a53da85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181485760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.181485760
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.759712742
Short name T699
Test name
Test status
Simulation time 778579135 ps
CPU time 4.21 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 207856 kb
Host smart-fe6f4f33-73e1-4659-a38d-d1e6c321a0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759712742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.759712742
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2097559399
Short name T269
Test name
Test status
Simulation time 4258850687 ps
CPU time 11.56 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:16 PM PDT 24
Peak memory 214412 kb
Host smart-0bbc5a6a-81b9-4ae8-8852-e7c48ba2279d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097559399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2097559399
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3320049340
Short name T586
Test name
Test status
Simulation time 93647349 ps
CPU time 3.13 seconds
Started Aug 08 05:31:07 PM PDT 24
Finished Aug 08 05:31:10 PM PDT 24
Peak memory 206972 kb
Host smart-8aba719a-0ba8-45f1-8016-411506b508ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320049340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3320049340
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2693746116
Short name T41
Test name
Test status
Simulation time 146994916 ps
CPU time 1.89 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:08 PM PDT 24
Peak memory 209824 kb
Host smart-4bc47c89-23cc-439f-bcb6-d5a27fedb28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693746116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2693746116
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2160045329
Short name T97
Test name
Test status
Simulation time 43258642 ps
CPU time 0.79 seconds
Started Aug 08 05:31:11 PM PDT 24
Finished Aug 08 05:31:12 PM PDT 24
Peak memory 205488 kb
Host smart-7c690849-1bbd-423d-a589-5c771cafe144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160045329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2160045329
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1443864785
Short name T224
Test name
Test status
Simulation time 986457115 ps
CPU time 52.33 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:58 PM PDT 24
Peak memory 214648 kb
Host smart-f23c1001-bb52-4c36-8d00-0c547564b3c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1443864785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1443864785
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2531783131
Short name T65
Test name
Test status
Simulation time 159541327 ps
CPU time 3.11 seconds
Started Aug 08 05:31:12 PM PDT 24
Finished Aug 08 05:31:15 PM PDT 24
Peak memory 220260 kb
Host smart-3232763b-f07f-40ee-b4ff-a7420e2e911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531783131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2531783131
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.349416341
Short name T272
Test name
Test status
Simulation time 119833261 ps
CPU time 2.82 seconds
Started Aug 08 05:31:07 PM PDT 24
Finished Aug 08 05:31:10 PM PDT 24
Peak memory 208132 kb
Host smart-7d9a4408-3ad2-4583-be89-96e7dd2019c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349416341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.349416341
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2383092164
Short name T409
Test name
Test status
Simulation time 17911660612 ps
CPU time 75.89 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:32:22 PM PDT 24
Peak memory 214400 kb
Host smart-154d97b7-4470-4606-a62b-270de6d01af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383092164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2383092164
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3286455517
Short name T679
Test name
Test status
Simulation time 677155528 ps
CPU time 3.8 seconds
Started Aug 08 05:31:12 PM PDT 24
Finished Aug 08 05:31:16 PM PDT 24
Peak memory 214280 kb
Host smart-a29621c7-5270-4fe6-b3e0-ee3f7e3fdb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286455517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3286455517
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2978775701
Short name T210
Test name
Test status
Simulation time 2477964206 ps
CPU time 21.43 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:27 PM PDT 24
Peak memory 209492 kb
Host smart-af90113a-018f-45e2-bd11-a45472899ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978775701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2978775701
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1999915478
Short name T505
Test name
Test status
Simulation time 47582596 ps
CPU time 3.04 seconds
Started Aug 08 05:31:04 PM PDT 24
Finished Aug 08 05:31:07 PM PDT 24
Peak memory 207380 kb
Host smart-c618d96d-785b-482a-829d-be3f58c6382f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999915478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1999915478
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.309361802
Short name T403
Test name
Test status
Simulation time 282961161 ps
CPU time 2.96 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:08 PM PDT 24
Peak memory 207372 kb
Host smart-c359334b-30e4-44ce-8bdd-b14e625dec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309361802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.309361802
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.161628109
Short name T718
Test name
Test status
Simulation time 222270695 ps
CPU time 3.03 seconds
Started Aug 08 05:31:12 PM PDT 24
Finished Aug 08 05:31:15 PM PDT 24
Peak memory 207608 kb
Host smart-8d1a1711-24ad-4134-a62c-043e6d80cc15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161628109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.161628109
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1846040981
Short name T470
Test name
Test status
Simulation time 241299691 ps
CPU time 2.8 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 208612 kb
Host smart-56d16702-92c3-4b10-8b6b-8a1e2a76d60e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846040981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1846040981
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2631610994
Short name T197
Test name
Test status
Simulation time 335640224 ps
CPU time 3.61 seconds
Started Aug 08 05:31:04 PM PDT 24
Finished Aug 08 05:31:08 PM PDT 24
Peak memory 206988 kb
Host smart-552c6866-59cf-4f83-a928-99116433d821
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631610994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2631610994
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1274975227
Short name T359
Test name
Test status
Simulation time 1009130239 ps
CPU time 4.67 seconds
Started Aug 08 05:31:08 PM PDT 24
Finished Aug 08 05:31:12 PM PDT 24
Peak memory 218588 kb
Host smart-ddc5ec90-affb-48ea-8f5f-810e3b36b4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274975227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1274975227
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.10661023
Short name T817
Test name
Test status
Simulation time 3353263835 ps
CPU time 7.34 seconds
Started Aug 08 05:31:08 PM PDT 24
Finished Aug 08 05:31:15 PM PDT 24
Peak memory 206812 kb
Host smart-5c3061c9-779c-4f42-a07c-b48702a59fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10661023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.10661023
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3072438819
Short name T199
Test name
Test status
Simulation time 696564366 ps
CPU time 8.28 seconds
Started Aug 08 05:31:07 PM PDT 24
Finished Aug 08 05:31:15 PM PDT 24
Peak memory 222448 kb
Host smart-52052169-ba6f-4c02-afa2-08824f6da47a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072438819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3072438819
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.547419416
Short name T657
Test name
Test status
Simulation time 359693910 ps
CPU time 6.37 seconds
Started Aug 08 05:31:12 PM PDT 24
Finished Aug 08 05:31:19 PM PDT 24
Peak memory 208924 kb
Host smart-e7fb8957-82d3-4ffc-a554-9973b32c7026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547419416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.547419416
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.57717178
Short name T131
Test name
Test status
Simulation time 546018726 ps
CPU time 3.77 seconds
Started Aug 08 05:31:10 PM PDT 24
Finished Aug 08 05:31:14 PM PDT 24
Peak memory 210048 kb
Host smart-e7b2dafa-7650-45f1-b7c2-6f8bf1a0b295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57717178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.57717178
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3824930857
Short name T834
Test name
Test status
Simulation time 35741261 ps
CPU time 0.74 seconds
Started Aug 08 05:31:20 PM PDT 24
Finished Aug 08 05:31:21 PM PDT 24
Peak memory 206000 kb
Host smart-be1feed1-4060-4c6b-9012-34ed0c29a70d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824930857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3824930857
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3913318118
Short name T376
Test name
Test status
Simulation time 57301154 ps
CPU time 3.96 seconds
Started Aug 08 05:31:12 PM PDT 24
Finished Aug 08 05:31:16 PM PDT 24
Peak memory 214256 kb
Host smart-e356430a-2c80-4375-b618-c8ec7b5301db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913318118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3913318118
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3943097505
Short name T31
Test name
Test status
Simulation time 420437126 ps
CPU time 3.27 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:21 PM PDT 24
Peak memory 214164 kb
Host smart-b31ffa1a-84c7-4afc-8bde-258a2d7eebfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943097505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3943097505
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1594224812
Short name T449
Test name
Test status
Simulation time 63357002 ps
CPU time 1.86 seconds
Started Aug 08 05:31:08 PM PDT 24
Finished Aug 08 05:31:10 PM PDT 24
Peak memory 207488 kb
Host smart-7f7f84b6-e390-4505-a108-af3977ba79c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594224812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1594224812
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1387013914
Short name T220
Test name
Test status
Simulation time 305051040 ps
CPU time 5.37 seconds
Started Aug 08 05:31:19 PM PDT 24
Finished Aug 08 05:31:25 PM PDT 24
Peak memory 209452 kb
Host smart-8c4b17b5-4b52-4dd4-8d61-fa33a142b008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387013914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1387013914
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1974565750
Short name T36
Test name
Test status
Simulation time 478219754 ps
CPU time 6.5 seconds
Started Aug 08 05:31:18 PM PDT 24
Finished Aug 08 05:31:25 PM PDT 24
Peak memory 222456 kb
Host smart-50400d30-4d67-4333-b2df-349121fd27f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974565750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1974565750
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.451305999
Short name T589
Test name
Test status
Simulation time 481545889 ps
CPU time 7.33 seconds
Started Aug 08 05:31:08 PM PDT 24
Finished Aug 08 05:31:16 PM PDT 24
Peak memory 209976 kb
Host smart-59f8e151-0513-42fe-ac1f-85e2cc6f5bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451305999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.451305999
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.923929270
Short name T288
Test name
Test status
Simulation time 22075085567 ps
CPU time 78.99 seconds
Started Aug 08 05:31:08 PM PDT 24
Finished Aug 08 05:32:27 PM PDT 24
Peak memory 209868 kb
Host smart-3d68679e-a25f-4f3f-887f-06c13aab462f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923929270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.923929270
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.784383416
Short name T631
Test name
Test status
Simulation time 64392252 ps
CPU time 2.41 seconds
Started Aug 08 05:31:07 PM PDT 24
Finished Aug 08 05:31:10 PM PDT 24
Peak memory 206960 kb
Host smart-a2d1ffbd-983f-4080-96d2-380489ee212d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784383416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.784383416
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2569453044
Short name T469
Test name
Test status
Simulation time 97978709 ps
CPU time 2.73 seconds
Started Aug 08 05:31:05 PM PDT 24
Finished Aug 08 05:31:08 PM PDT 24
Peak memory 206820 kb
Host smart-82f4c5d0-2fec-44ff-8e58-8e0edc2eb9b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569453044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2569453044
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1248492053
Short name T824
Test name
Test status
Simulation time 32922673 ps
CPU time 2.24 seconds
Started Aug 08 05:31:10 PM PDT 24
Finished Aug 08 05:31:12 PM PDT 24
Peak memory 206724 kb
Host smart-40d2cc90-be25-482a-b7b8-e944d65969a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248492053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1248492053
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2260866273
Short name T495
Test name
Test status
Simulation time 58198634 ps
CPU time 2.51 seconds
Started Aug 08 05:31:06 PM PDT 24
Finished Aug 08 05:31:09 PM PDT 24
Peak memory 207432 kb
Host smart-8492098a-184b-4389-a3ff-001d8006c50d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260866273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2260866273
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2454469802
Short name T512
Test name
Test status
Simulation time 242142407 ps
CPU time 2.06 seconds
Started Aug 08 05:31:20 PM PDT 24
Finished Aug 08 05:31:22 PM PDT 24
Peak memory 207636 kb
Host smart-67f7fea1-a432-4488-ba39-8f4d0f3aee11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454469802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2454469802
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2830412450
Short name T638
Test name
Test status
Simulation time 53380981 ps
CPU time 2.56 seconds
Started Aug 08 05:31:11 PM PDT 24
Finished Aug 08 05:31:14 PM PDT 24
Peak memory 206732 kb
Host smart-429364a1-906e-4889-8829-92b7641a3956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830412450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2830412450
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2923795911
Short name T53
Test name
Test status
Simulation time 2111438328 ps
CPU time 20.01 seconds
Started Aug 08 05:31:15 PM PDT 24
Finished Aug 08 05:31:35 PM PDT 24
Peak memory 215128 kb
Host smart-8618b85a-261c-4a08-a6e7-8e0cebe17374
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923795911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2923795911
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1401189512
Short name T175
Test name
Test status
Simulation time 191378338 ps
CPU time 4.61 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:22 PM PDT 24
Peak memory 217512 kb
Host smart-c702c785-3213-46f5-8c33-a25c02359390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401189512 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1401189512
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.601916192
Short name T179
Test name
Test status
Simulation time 128411336 ps
CPU time 5.48 seconds
Started Aug 08 05:31:20 PM PDT 24
Finished Aug 08 05:31:26 PM PDT 24
Peak memory 210316 kb
Host smart-1033dd89-e1df-47f3-a10b-a5e3accfd782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601916192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.601916192
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2821686319
Short name T789
Test name
Test status
Simulation time 1224603425 ps
CPU time 10.32 seconds
Started Aug 08 05:31:18 PM PDT 24
Finished Aug 08 05:31:28 PM PDT 24
Peak memory 210368 kb
Host smart-d77dc444-9cb3-448e-9c9f-d453154ca13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821686319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2821686319
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.260511518
Short name T559
Test name
Test status
Simulation time 40987139 ps
CPU time 0.96 seconds
Started Aug 08 05:31:20 PM PDT 24
Finished Aug 08 05:31:21 PM PDT 24
Peak memory 206112 kb
Host smart-33adce37-c2f1-44cb-a61b-b4823db2cc2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260511518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.260511518
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2716139928
Short name T378
Test name
Test status
Simulation time 154828703 ps
CPU time 3.46 seconds
Started Aug 08 05:31:15 PM PDT 24
Finished Aug 08 05:31:18 PM PDT 24
Peak memory 214228 kb
Host smart-997c4d94-3e18-47f7-995d-10547b551c4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716139928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2716139928
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1996292524
Short name T467
Test name
Test status
Simulation time 253309889 ps
CPU time 3.19 seconds
Started Aug 08 05:31:20 PM PDT 24
Finished Aug 08 05:31:23 PM PDT 24
Peak memory 207500 kb
Host smart-b50c9c8e-dab7-4c57-9a41-5baa120c6ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996292524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1996292524
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.4077845460
Short name T48
Test name
Test status
Simulation time 73511279 ps
CPU time 2.56 seconds
Started Aug 08 05:31:16 PM PDT 24
Finished Aug 08 05:31:19 PM PDT 24
Peak memory 214352 kb
Host smart-2667adac-5976-4b78-b7c6-80fad5a39dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077845460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.4077845460
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.149652409
Short name T904
Test name
Test status
Simulation time 635346473 ps
CPU time 4.95 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:22 PM PDT 24
Peak memory 218588 kb
Host smart-c29a6cbc-a23c-41fe-ab7d-76c4764fb22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149652409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.149652409
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3742862380
Short name T744
Test name
Test status
Simulation time 306330711 ps
CPU time 4.12 seconds
Started Aug 08 05:31:16 PM PDT 24
Finished Aug 08 05:31:21 PM PDT 24
Peak memory 208396 kb
Host smart-5f58178b-e6d5-4380-878e-f91362fca0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742862380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3742862380
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.447695097
Short name T475
Test name
Test status
Simulation time 169163324 ps
CPU time 2.46 seconds
Started Aug 08 05:31:13 PM PDT 24
Finished Aug 08 05:31:16 PM PDT 24
Peak memory 207296 kb
Host smart-0d6aca7a-3853-4cd0-9765-209a1f93d40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447695097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.447695097
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2082840759
Short name T650
Test name
Test status
Simulation time 201702800 ps
CPU time 2.96 seconds
Started Aug 08 05:31:15 PM PDT 24
Finished Aug 08 05:31:18 PM PDT 24
Peak memory 208748 kb
Host smart-dfba5ee9-e69a-489b-a59b-3f0da1e7d5eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082840759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2082840759
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1462881279
Short name T133
Test name
Test status
Simulation time 286724163 ps
CPU time 7.22 seconds
Started Aug 08 05:31:19 PM PDT 24
Finished Aug 08 05:31:27 PM PDT 24
Peak memory 208192 kb
Host smart-f550b931-b1a0-4887-8989-cfa64aa5eaa0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462881279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1462881279
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2914526847
Short name T423
Test name
Test status
Simulation time 696279384 ps
CPU time 5.41 seconds
Started Aug 08 05:31:16 PM PDT 24
Finished Aug 08 05:31:22 PM PDT 24
Peak memory 207912 kb
Host smart-32b5c8e3-5a93-4a26-8fd1-cec8139d78bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914526847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2914526847
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.215553412
Short name T476
Test name
Test status
Simulation time 736623511 ps
CPU time 2.84 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:19 PM PDT 24
Peak memory 208940 kb
Host smart-9928177c-547f-44ed-ada4-00a113a6e221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215553412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.215553412
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.4099441932
Short name T459
Test name
Test status
Simulation time 139860159 ps
CPU time 2.33 seconds
Started Aug 08 05:31:15 PM PDT 24
Finished Aug 08 05:31:17 PM PDT 24
Peak memory 206824 kb
Host smart-03c51e5d-4eba-4373-a14e-0313cbcf1379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099441932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.4099441932
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.918399635
Short name T342
Test name
Test status
Simulation time 255029391 ps
CPU time 10.05 seconds
Started Aug 08 05:31:18 PM PDT 24
Finished Aug 08 05:31:28 PM PDT 24
Peak memory 216320 kb
Host smart-f4de2b53-000f-4b16-968f-9a8f5afeddab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918399635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.918399635
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1490168091
Short name T258
Test name
Test status
Simulation time 505733184 ps
CPU time 6.17 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:23 PM PDT 24
Peak memory 206948 kb
Host smart-9ef86998-1d06-444a-a074-31584c22e232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490168091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1490168091
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1393110709
Short name T368
Test name
Test status
Simulation time 38257913 ps
CPU time 1.28 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:18 PM PDT 24
Peak memory 210316 kb
Host smart-39cd6be5-35c1-4e7f-a742-f8a9c46d76b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393110709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1393110709
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2087625631
Short name T96
Test name
Test status
Simulation time 33895860 ps
CPU time 0.72 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:18 PM PDT 24
Peak memory 205952 kb
Host smart-9922e6a4-8444-46d0-83b9-da3345dd503c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087625631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2087625631
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2783533036
Short name T387
Test name
Test status
Simulation time 80939097 ps
CPU time 2.07 seconds
Started Aug 08 05:31:16 PM PDT 24
Finished Aug 08 05:31:19 PM PDT 24
Peak memory 214296 kb
Host smart-ba109ba0-5e92-41a5-a382-32dc9e508736
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2783533036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2783533036
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2603253872
Short name T27
Test name
Test status
Simulation time 196646012 ps
CPU time 4.11 seconds
Started Aug 08 05:31:20 PM PDT 24
Finished Aug 08 05:31:24 PM PDT 24
Peak memory 219456 kb
Host smart-6d2bc73f-523f-41d8-aa56-781e43760f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603253872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2603253872
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3302851101
Short name T66
Test name
Test status
Simulation time 94223192 ps
CPU time 2.97 seconds
Started Aug 08 05:31:21 PM PDT 24
Finished Aug 08 05:31:24 PM PDT 24
Peak memory 209896 kb
Host smart-abab0572-60cb-4f89-bcd5-60541c6b799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302851101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3302851101
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1611108874
Short name T337
Test name
Test status
Simulation time 116638822 ps
CPU time 3.48 seconds
Started Aug 08 05:31:18 PM PDT 24
Finished Aug 08 05:31:22 PM PDT 24
Peak memory 222492 kb
Host smart-f8b5966e-13e0-49d3-9b20-33b16d1f3fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611108874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1611108874
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.939442400
Short name T882
Test name
Test status
Simulation time 119824624 ps
CPU time 2.42 seconds
Started Aug 08 05:31:18 PM PDT 24
Finished Aug 08 05:31:21 PM PDT 24
Peak memory 214292 kb
Host smart-6b472ced-dee9-4856-9a6f-3396171ee0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939442400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.939442400
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_random.3770338551
Short name T659
Test name
Test status
Simulation time 266372934 ps
CPU time 3.74 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:21 PM PDT 24
Peak memory 209068 kb
Host smart-42a27665-22e7-4ea9-87cb-fd923af1e175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770338551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3770338551
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3511063416
Short name T723
Test name
Test status
Simulation time 468683073 ps
CPU time 3.12 seconds
Started Aug 08 05:31:16 PM PDT 24
Finished Aug 08 05:31:19 PM PDT 24
Peak memory 207508 kb
Host smart-5b4ad195-d936-412c-98a9-1f1e1db35c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511063416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3511063416
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1642034869
Short name T484
Test name
Test status
Simulation time 32262967 ps
CPU time 2.32 seconds
Started Aug 08 05:31:21 PM PDT 24
Finished Aug 08 05:31:23 PM PDT 24
Peak memory 207408 kb
Host smart-b54d88d3-de30-49b6-a386-d6b1071e9f6d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642034869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1642034869
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2982911163
Short name T741
Test name
Test status
Simulation time 131387733 ps
CPU time 2.87 seconds
Started Aug 08 05:31:16 PM PDT 24
Finished Aug 08 05:31:19 PM PDT 24
Peak memory 206996 kb
Host smart-801f777f-c288-4e68-b6fb-4b7d6c31b523
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982911163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2982911163
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2698878499
Short name T536
Test name
Test status
Simulation time 22427150 ps
CPU time 1.77 seconds
Started Aug 08 05:31:18 PM PDT 24
Finished Aug 08 05:31:19 PM PDT 24
Peak memory 206800 kb
Host smart-c8b6fa6a-6be5-48cf-8fe3-9fefada96020
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698878499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2698878499
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2134693585
Short name T416
Test name
Test status
Simulation time 137659958 ps
CPU time 3.25 seconds
Started Aug 08 05:31:16 PM PDT 24
Finished Aug 08 05:31:20 PM PDT 24
Peak memory 207868 kb
Host smart-34cb40d8-c575-4176-bf28-9440bf7d6141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134693585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2134693585
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3467053186
Short name T643
Test name
Test status
Simulation time 108838149 ps
CPU time 2.54 seconds
Started Aug 08 05:31:15 PM PDT 24
Finished Aug 08 05:31:18 PM PDT 24
Peak memory 208284 kb
Host smart-647fc5e6-b6a5-49ac-8dbf-2958d8219575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467053186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3467053186
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.445364815
Short name T209
Test name
Test status
Simulation time 5311994272 ps
CPU time 47.94 seconds
Started Aug 08 05:31:20 PM PDT 24
Finished Aug 08 05:32:08 PM PDT 24
Peak memory 222552 kb
Host smart-4773ec91-3b27-411b-8031-a02513dd2485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445364815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.445364815
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3282274841
Short name T108
Test name
Test status
Simulation time 1417828983 ps
CPU time 27.26 seconds
Started Aug 08 05:31:15 PM PDT 24
Finished Aug 08 05:31:42 PM PDT 24
Peak memory 223404 kb
Host smart-e9b4c0ab-3510-43ac-96cf-5e6ba46222c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282274841 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3282274841
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1814674228
Short name T584
Test name
Test status
Simulation time 51276948 ps
CPU time 3.51 seconds
Started Aug 08 05:31:14 PM PDT 24
Finished Aug 08 05:31:18 PM PDT 24
Peak memory 207908 kb
Host smart-4a111d07-f1c2-4a52-b1d1-d7d58ba50f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814674228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1814674228
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3737598573
Short name T353
Test name
Test status
Simulation time 97911159 ps
CPU time 3.15 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:20 PM PDT 24
Peak memory 210452 kb
Host smart-b8aaafd5-c971-424a-9b4b-9d8e83ba93d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737598573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3737598573
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.407989212
Short name T486
Test name
Test status
Simulation time 29455993 ps
CPU time 0.7 seconds
Started Aug 08 05:29:11 PM PDT 24
Finished Aug 08 05:29:12 PM PDT 24
Peak memory 205872 kb
Host smart-88c1e7d2-2c77-4877-8cac-cb166853a4db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407989212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.407989212
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3999848637
Short name T471
Test name
Test status
Simulation time 544179897 ps
CPU time 12.62 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:22 PM PDT 24
Peak memory 222720 kb
Host smart-bced3d5b-7edb-4526-8352-50a19d3c240b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999848637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3999848637
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2747804441
Short name T262
Test name
Test status
Simulation time 96085469 ps
CPU time 3.09 seconds
Started Aug 08 05:29:10 PM PDT 24
Finished Aug 08 05:29:13 PM PDT 24
Peak memory 214300 kb
Host smart-82f11d14-b9ce-4d61-bf19-9ae0eb3e20fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747804441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2747804441
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3098065436
Short name T264
Test name
Test status
Simulation time 74302579 ps
CPU time 3.01 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:12 PM PDT 24
Peak memory 214180 kb
Host smart-b383c716-d04a-4a15-b3dc-4559bc7b1839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098065436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3098065436
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2577970026
Short name T585
Test name
Test status
Simulation time 363772896 ps
CPU time 2.95 seconds
Started Aug 08 05:29:10 PM PDT 24
Finished Aug 08 05:29:13 PM PDT 24
Peak memory 220044 kb
Host smart-3e1989c2-fa47-40ba-9eb9-a748eb4549f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577970026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2577970026
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3064546933
Short name T724
Test name
Test status
Simulation time 335186646 ps
CPU time 5.82 seconds
Started Aug 08 05:29:12 PM PDT 24
Finished Aug 08 05:29:18 PM PDT 24
Peak memory 218500 kb
Host smart-ccacd09f-9856-4a59-ab66-6eda83c30f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064546933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3064546933
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.414859680
Short name T397
Test name
Test status
Simulation time 225960295 ps
CPU time 6.63 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:16 PM PDT 24
Peak memory 208392 kb
Host smart-a6a275b4-beaf-4701-a7d4-c89995e0cac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414859680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.414859680
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2180983236
Short name T811
Test name
Test status
Simulation time 296592238 ps
CPU time 2.95 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:13 PM PDT 24
Peak memory 207880 kb
Host smart-8017365b-f0d2-451e-90e8-9299f00453e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180983236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2180983236
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2454806974
Short name T694
Test name
Test status
Simulation time 73189448 ps
CPU time 1.85 seconds
Started Aug 08 05:29:13 PM PDT 24
Finished Aug 08 05:29:15 PM PDT 24
Peak memory 207028 kb
Host smart-4de2a076-7ea0-4ae1-8058-0276a67bcba1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454806974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2454806974
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3559311189
Short name T658
Test name
Test status
Simulation time 139581434 ps
CPU time 3.38 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:12 PM PDT 24
Peak memory 208612 kb
Host smart-567f4df9-92fc-4451-a287-d378f7453660
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559311189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3559311189
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1455766529
Short name T127
Test name
Test status
Simulation time 99296506 ps
CPU time 2.66 seconds
Started Aug 08 05:29:11 PM PDT 24
Finished Aug 08 05:29:14 PM PDT 24
Peak memory 209868 kb
Host smart-4b94f151-2674-4f26-894e-ae8b024eb001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455766529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1455766529
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1228726
Short name T441
Test name
Test status
Simulation time 379950965 ps
CPU time 10.38 seconds
Started Aug 08 05:29:12 PM PDT 24
Finished Aug 08 05:29:23 PM PDT 24
Peak memory 208244 kb
Host smart-a97000c5-3d13-424e-ab34-afcd8fb24695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1228726
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.4267490661
Short name T363
Test name
Test status
Simulation time 848402155 ps
CPU time 7.14 seconds
Started Aug 08 05:29:14 PM PDT 24
Finished Aug 08 05:29:21 PM PDT 24
Peak memory 215180 kb
Host smart-1c4f9d44-4f31-4502-ae0b-1f436510adb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267490661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.4267490661
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2587630535
Short name T756
Test name
Test status
Simulation time 762669823 ps
CPU time 23.88 seconds
Started Aug 08 05:29:09 PM PDT 24
Finished Aug 08 05:29:33 PM PDT 24
Peak memory 220908 kb
Host smart-53bc65fc-a36e-4976-acdd-e996726903f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587630535 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2587630535
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.223671758
Short name T784
Test name
Test status
Simulation time 237048795 ps
CPU time 4.86 seconds
Started Aug 08 05:29:10 PM PDT 24
Finished Aug 08 05:29:15 PM PDT 24
Peak memory 207396 kb
Host smart-548d6198-a852-49e9-b0a4-c0a41a1ef376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223671758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.223671758
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2672582296
Short name T59
Test name
Test status
Simulation time 352826305 ps
CPU time 3.54 seconds
Started Aug 08 05:29:14 PM PDT 24
Finished Aug 08 05:29:18 PM PDT 24
Peak memory 210340 kb
Host smart-d49f0efe-4d20-415a-85dd-8d0d9a684bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672582296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2672582296
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3778207367
Short name T500
Test name
Test status
Simulation time 162117540 ps
CPU time 0.93 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:31:25 PM PDT 24
Peak memory 205980 kb
Host smart-ee5e476b-54f0-476d-8096-52f1a0c7f1e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778207367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3778207367
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.4202032068
Short name T384
Test name
Test status
Simulation time 108034462 ps
CPU time 2.48 seconds
Started Aug 08 05:31:18 PM PDT 24
Finished Aug 08 05:31:20 PM PDT 24
Peak memory 214356 kb
Host smart-b2bb9151-7a13-4f06-9f6c-58f328d228be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202032068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.4202032068
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1352668480
Short name T844
Test name
Test status
Simulation time 65738223 ps
CPU time 2.22 seconds
Started Aug 08 05:31:22 PM PDT 24
Finished Aug 08 05:31:24 PM PDT 24
Peak memory 208520 kb
Host smart-b099a5d9-0476-4259-a3cd-89a16e09d0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352668480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1352668480
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.23400059
Short name T843
Test name
Test status
Simulation time 147135814 ps
CPU time 3.33 seconds
Started Aug 08 05:31:18 PM PDT 24
Finished Aug 08 05:31:22 PM PDT 24
Peak memory 209776 kb
Host smart-5b546861-d7a8-4465-b2f2-7af766b33617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23400059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.23400059
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1846435853
Short name T691
Test name
Test status
Simulation time 96830467 ps
CPU time 2.06 seconds
Started Aug 08 05:31:22 PM PDT 24
Finished Aug 08 05:31:24 PM PDT 24
Peak memory 214548 kb
Host smart-8fe77b2b-7f38-4e7c-bb68-36896dbe8295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846435853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1846435853
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2393558005
Short name T319
Test name
Test status
Simulation time 812332864 ps
CPU time 4.13 seconds
Started Aug 08 05:31:19 PM PDT 24
Finished Aug 08 05:31:23 PM PDT 24
Peak memory 222268 kb
Host smart-27e294da-1f6c-4b68-a76f-074cb9269999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393558005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2393558005
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2189367548
Short name T49
Test name
Test status
Simulation time 181839719 ps
CPU time 6.8 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:24 PM PDT 24
Peak memory 206064 kb
Host smart-d52ac23a-5acd-4345-b560-2696b0fb7b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189367548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2189367548
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.503862687
Short name T727
Test name
Test status
Simulation time 121928992 ps
CPU time 5.4 seconds
Started Aug 08 05:31:19 PM PDT 24
Finished Aug 08 05:31:24 PM PDT 24
Peak memory 218304 kb
Host smart-f41c465a-7e38-4184-84d4-bb01631759f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503862687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.503862687
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.4239766528
Short name T573
Test name
Test status
Simulation time 672095188 ps
CPU time 19.2 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:36 PM PDT 24
Peak memory 207824 kb
Host smart-bcc59093-66a1-42b6-a4de-59285fb37e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239766528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.4239766528
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2509250896
Short name T324
Test name
Test status
Simulation time 40377885 ps
CPU time 2.69 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:20 PM PDT 24
Peak memory 208976 kb
Host smart-f3496175-520f-41de-91c4-fae8054b329d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509250896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2509250896
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3986004291
Short name T572
Test name
Test status
Simulation time 255398446 ps
CPU time 3.77 seconds
Started Aug 08 05:31:14 PM PDT 24
Finished Aug 08 05:31:18 PM PDT 24
Peak memory 208824 kb
Host smart-f43fe90c-4a24-470a-bb7d-f89536f1a371
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986004291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3986004291
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1880290662
Short name T755
Test name
Test status
Simulation time 73063198 ps
CPU time 2.55 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:19 PM PDT 24
Peak memory 206844 kb
Host smart-9262f316-3cbf-4f9f-ab1e-a50fe22aed5d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880290662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1880290662
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3475080248
Short name T424
Test name
Test status
Simulation time 94391903 ps
CPU time 3.51 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:31:28 PM PDT 24
Peak memory 210296 kb
Host smart-0a4f452d-cd16-4c53-ab50-b45154826f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475080248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3475080248
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1670847418
Short name T721
Test name
Test status
Simulation time 186139192 ps
CPU time 6.06 seconds
Started Aug 08 05:31:19 PM PDT 24
Finished Aug 08 05:31:25 PM PDT 24
Peak memory 208620 kb
Host smart-6a9e1707-b733-428c-9e72-2afd81b466a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670847418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1670847418
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3560904560
Short name T508
Test name
Test status
Simulation time 129792898 ps
CPU time 3.47 seconds
Started Aug 08 05:31:20 PM PDT 24
Finished Aug 08 05:31:24 PM PDT 24
Peak memory 209328 kb
Host smart-f7b055ae-1348-4fb8-9cae-5578e1c97f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560904560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3560904560
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3498695083
Short name T874
Test name
Test status
Simulation time 227823753 ps
CPU time 2.61 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:20 PM PDT 24
Peak memory 210152 kb
Host smart-28b023de-f9b9-4891-a00d-f2505141d826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498695083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3498695083
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2101430112
Short name T717
Test name
Test status
Simulation time 10998324 ps
CPU time 0.77 seconds
Started Aug 08 05:31:27 PM PDT 24
Finished Aug 08 05:31:28 PM PDT 24
Peak memory 205968 kb
Host smart-78b729df-4f3f-4abe-8a4d-bf3c2cb3c89b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101430112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2101430112
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.4093832720
Short name T700
Test name
Test status
Simulation time 205267915 ps
CPU time 2.16 seconds
Started Aug 08 05:31:21 PM PDT 24
Finished Aug 08 05:31:23 PM PDT 24
Peak memory 207276 kb
Host smart-db33f787-886b-46ff-94b5-26f7cc74b836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093832720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.4093832720
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1119132031
Short name T802
Test name
Test status
Simulation time 1108182381 ps
CPU time 2.01 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:19 PM PDT 24
Peak memory 206136 kb
Host smart-ddb352b6-c2e5-4625-90dc-1ac4a94641b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119132031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1119132031
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3817025866
Short name T902
Test name
Test status
Simulation time 122133110 ps
CPU time 5.04 seconds
Started Aug 08 05:31:23 PM PDT 24
Finished Aug 08 05:31:28 PM PDT 24
Peak memory 208228 kb
Host smart-834f9b96-f1c1-4839-b0e7-57fbd0041569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817025866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3817025866
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.975425702
Short name T809
Test name
Test status
Simulation time 89092271 ps
CPU time 3.11 seconds
Started Aug 08 05:31:23 PM PDT 24
Finished Aug 08 05:31:27 PM PDT 24
Peak memory 208652 kb
Host smart-d66a4307-9aa2-437b-b93f-bad2d8c5b944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975425702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.975425702
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3427420868
Short name T433
Test name
Test status
Simulation time 619214512 ps
CPU time 3.34 seconds
Started Aug 08 05:31:22 PM PDT 24
Finished Aug 08 05:31:25 PM PDT 24
Peak memory 206992 kb
Host smart-3e582415-8540-472d-b6de-50fbc207d65d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427420868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3427420868
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.458646771
Short name T613
Test name
Test status
Simulation time 350176915 ps
CPU time 3.89 seconds
Started Aug 08 05:31:22 PM PDT 24
Finished Aug 08 05:31:26 PM PDT 24
Peak memory 208656 kb
Host smart-25c58fe3-a58b-40e9-bd63-a9f3dd4c0dcb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458646771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.458646771
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.411041903
Short name T295
Test name
Test status
Simulation time 67963091 ps
CPU time 2.38 seconds
Started Aug 08 05:31:21 PM PDT 24
Finished Aug 08 05:31:23 PM PDT 24
Peak memory 206916 kb
Host smart-805435f6-dd94-4522-9d28-582f42021c42
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411041903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.411041903
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1180753029
Short name T362
Test name
Test status
Simulation time 96519376 ps
CPU time 2.08 seconds
Started Aug 08 05:31:17 PM PDT 24
Finished Aug 08 05:31:19 PM PDT 24
Peak memory 214292 kb
Host smart-bd4592a0-1fb2-4739-a628-2e1b2496141e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180753029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1180753029
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2420004534
Short name T522
Test name
Test status
Simulation time 512605602 ps
CPU time 11.47 seconds
Started Aug 08 05:31:21 PM PDT 24
Finished Aug 08 05:31:33 PM PDT 24
Peak memory 207872 kb
Host smart-113de88b-dbac-4a3b-aad5-f95b6e7dcd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420004534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2420004534
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2638305828
Short name T412
Test name
Test status
Simulation time 1347104847 ps
CPU time 11.49 seconds
Started Aug 08 05:31:21 PM PDT 24
Finished Aug 08 05:31:33 PM PDT 24
Peak memory 218224 kb
Host smart-79becb77-adad-436d-baff-12737fff8ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638305828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2638305828
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1071793604
Short name T818
Test name
Test status
Simulation time 35613044 ps
CPU time 1.69 seconds
Started Aug 08 05:31:18 PM PDT 24
Finished Aug 08 05:31:20 PM PDT 24
Peak memory 209960 kb
Host smart-cb8f6cbd-a763-4518-bba3-1bc913efad82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071793604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1071793604
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3114449633
Short name T410
Test name
Test status
Simulation time 53791829 ps
CPU time 0.97 seconds
Started Aug 08 05:31:25 PM PDT 24
Finished Aug 08 05:31:26 PM PDT 24
Peak memory 206132 kb
Host smart-530d7c67-e11d-4dff-b255-02f2d34f27b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114449633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3114449633
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.612968166
Short name T787
Test name
Test status
Simulation time 87484285 ps
CPU time 3.54 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:31:28 PM PDT 24
Peak memory 215596 kb
Host smart-8d62b851-7051-44fa-a4d0-b57c89acabaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612968166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.612968166
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3221500391
Short name T749
Test name
Test status
Simulation time 600789475 ps
CPU time 4.87 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:31:29 PM PDT 24
Peak memory 209268 kb
Host smart-5b0e77ef-ce15-45fa-a83c-4f10c93f69ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221500391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3221500391
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3376881153
Short name T626
Test name
Test status
Simulation time 79493966 ps
CPU time 3.72 seconds
Started Aug 08 05:31:23 PM PDT 24
Finished Aug 08 05:31:27 PM PDT 24
Peak memory 218408 kb
Host smart-8059ffa8-f2e5-437d-800f-4a49aff5df4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376881153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3376881153
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1513031494
Short name T769
Test name
Test status
Simulation time 274113566 ps
CPU time 3.17 seconds
Started Aug 08 05:31:27 PM PDT 24
Finished Aug 08 05:31:30 PM PDT 24
Peak memory 214308 kb
Host smart-18b91564-9936-455e-be1e-af569537782f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513031494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1513031494
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2251986274
Short name T702
Test name
Test status
Simulation time 32348063 ps
CPU time 2.36 seconds
Started Aug 08 05:31:27 PM PDT 24
Finished Aug 08 05:31:30 PM PDT 24
Peak memory 214340 kb
Host smart-9ded16db-d95e-4a87-9e48-53e2bede892d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251986274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2251986274
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.903077017
Short name T213
Test name
Test status
Simulation time 91279492 ps
CPU time 4.48 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:31:29 PM PDT 24
Peak memory 220760 kb
Host smart-6d5731fa-3428-4d87-9cec-a80402f0c830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903077017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.903077017
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1998575074
Short name T105
Test name
Test status
Simulation time 129086213 ps
CPU time 5.13 seconds
Started Aug 08 05:31:36 PM PDT 24
Finished Aug 08 05:31:41 PM PDT 24
Peak memory 208992 kb
Host smart-e5b503df-a48e-4d01-b4ce-8168aeb6ec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998575074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1998575074
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2747923056
Short name T594
Test name
Test status
Simulation time 257565167 ps
CPU time 3.82 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:31:28 PM PDT 24
Peak memory 206976 kb
Host smart-eb1a164a-4526-4caf-acdd-7207091c3255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747923056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2747923056
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1192359530
Short name T754
Test name
Test status
Simulation time 51334036 ps
CPU time 2.49 seconds
Started Aug 08 05:31:27 PM PDT 24
Finished Aug 08 05:31:30 PM PDT 24
Peak memory 208656 kb
Host smart-9270ca40-90e6-4217-86af-d02b47986d5f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192359530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1192359530
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.694212777
Short name T308
Test name
Test status
Simulation time 54323003 ps
CPU time 2.92 seconds
Started Aug 08 05:31:37 PM PDT 24
Finished Aug 08 05:31:40 PM PDT 24
Peak memory 206956 kb
Host smart-f1657533-2644-47b1-8e76-4848ac6397b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694212777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.694212777
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3992161280
Short name T196
Test name
Test status
Simulation time 43552508 ps
CPU time 2.47 seconds
Started Aug 08 05:31:25 PM PDT 24
Finished Aug 08 05:31:28 PM PDT 24
Peak memory 207124 kb
Host smart-a9f76fe7-2071-4c4d-b513-e6cde0438809
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992161280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3992161280
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.709002742
Short name T772
Test name
Test status
Simulation time 1553746536 ps
CPU time 11.03 seconds
Started Aug 08 05:31:23 PM PDT 24
Finished Aug 08 05:31:35 PM PDT 24
Peak memory 214452 kb
Host smart-24dd8254-07fb-40a5-9fd3-c0cc2e21fd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709002742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.709002742
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4055896354
Short name T867
Test name
Test status
Simulation time 232537765 ps
CPU time 4.8 seconds
Started Aug 08 05:31:25 PM PDT 24
Finished Aug 08 05:31:30 PM PDT 24
Peak memory 206968 kb
Host smart-ff9b3aa3-98fb-4b79-8213-9f7bfaa2a67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055896354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4055896354
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.822426831
Short name T831
Test name
Test status
Simulation time 151476623 ps
CPU time 4.08 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:31:28 PM PDT 24
Peak memory 218436 kb
Host smart-b08f4ee9-581f-40e2-8ae9-e63a858ad8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822426831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.822426831
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1953877041
Short name T169
Test name
Test status
Simulation time 86168416 ps
CPU time 3.05 seconds
Started Aug 08 05:31:25 PM PDT 24
Finished Aug 08 05:31:28 PM PDT 24
Peak memory 209828 kb
Host smart-aee94115-23f7-4478-8561-c39f3c169c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953877041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1953877041
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.275888392
Short name T601
Test name
Test status
Simulation time 61663274 ps
CPU time 0.79 seconds
Started Aug 08 05:31:25 PM PDT 24
Finished Aug 08 05:31:26 PM PDT 24
Peak memory 205980 kb
Host smart-53d23650-8d2f-433f-86d6-95995e8b644b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275888392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.275888392
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3037373488
Short name T383
Test name
Test status
Simulation time 59395715 ps
CPU time 2.25 seconds
Started Aug 08 05:31:36 PM PDT 24
Finished Aug 08 05:31:38 PM PDT 24
Peak memory 214444 kb
Host smart-3ab190bd-ebd9-4fe0-ba5f-f8df1f24d162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037373488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3037373488
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.923755374
Short name T39
Test name
Test status
Simulation time 74694455 ps
CPU time 3.17 seconds
Started Aug 08 05:31:27 PM PDT 24
Finished Aug 08 05:31:31 PM PDT 24
Peak memory 218368 kb
Host smart-96f25933-5c8c-4da2-bd2c-4d9a3de49f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923755374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.923755374
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1716420673
Short name T746
Test name
Test status
Simulation time 576040232 ps
CPU time 3.15 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:31:27 PM PDT 24
Peak memory 218240 kb
Host smart-b1f02c6f-63a7-4cc1-98f3-c3d1931001e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716420673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1716420673
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3323201693
Short name T782
Test name
Test status
Simulation time 168193050 ps
CPU time 6.37 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:31:30 PM PDT 24
Peak memory 220144 kb
Host smart-d1f235c4-f46d-4774-a739-eb79c6c48b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323201693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3323201693
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.545178989
Short name T317
Test name
Test status
Simulation time 98835642 ps
CPU time 4.67 seconds
Started Aug 08 05:31:25 PM PDT 24
Finished Aug 08 05:31:29 PM PDT 24
Peak memory 222376 kb
Host smart-45131d75-3a97-495b-8ada-a85a3b37a9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545178989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.545178989
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.4049963262
Short name T816
Test name
Test status
Simulation time 285616873 ps
CPU time 4.51 seconds
Started Aug 08 05:31:26 PM PDT 24
Finished Aug 08 05:31:31 PM PDT 24
Peak memory 215452 kb
Host smart-b18e0b66-ed04-4a9b-9704-231e1d3b6390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049963262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.4049963262
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1462637292
Short name T419
Test name
Test status
Simulation time 222365242 ps
CPU time 2.99 seconds
Started Aug 08 05:31:31 PM PDT 24
Finished Aug 08 05:31:34 PM PDT 24
Peak memory 207704 kb
Host smart-15abdcd9-9e46-44a2-9c8f-c5d2b144cf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462637292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1462637292
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1313472337
Short name T520
Test name
Test status
Simulation time 541588508 ps
CPU time 3.13 seconds
Started Aug 08 05:31:25 PM PDT 24
Finished Aug 08 05:31:28 PM PDT 24
Peak memory 207748 kb
Host smart-fdac2af7-cb09-4bfb-a1c6-8c3f62092a1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313472337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1313472337
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.818570653
Short name T2
Test name
Test status
Simulation time 258711522 ps
CPU time 1.69 seconds
Started Aug 08 05:31:23 PM PDT 24
Finished Aug 08 05:31:25 PM PDT 24
Peak memory 206924 kb
Host smart-b5a9e059-126e-4ebe-9afd-444dc7e7a24f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818570653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.818570653
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2743565323
Short name T414
Test name
Test status
Simulation time 1526906515 ps
CPU time 9.94 seconds
Started Aug 08 05:31:27 PM PDT 24
Finished Aug 08 05:31:37 PM PDT 24
Peak memory 208704 kb
Host smart-46885b38-57dc-45dd-8123-16fb66c87729
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743565323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2743565323
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3719877781
Short name T366
Test name
Test status
Simulation time 31417874 ps
CPU time 2.39 seconds
Started Aug 08 05:31:25 PM PDT 24
Finished Aug 08 05:31:27 PM PDT 24
Peak memory 216084 kb
Host smart-8c8687e8-c87c-4895-b37c-31528d249033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719877781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3719877781
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1139042187
Short name T399
Test name
Test status
Simulation time 797582422 ps
CPU time 4.63 seconds
Started Aug 08 05:31:26 PM PDT 24
Finished Aug 08 05:31:30 PM PDT 24
Peak memory 208276 kb
Host smart-a2e2f0d9-6af6-4ebc-9614-5e7aa54bc3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139042187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1139042187
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2771927877
Short name T204
Test name
Test status
Simulation time 2547179761 ps
CPU time 13.61 seconds
Started Aug 08 05:31:27 PM PDT 24
Finished Aug 08 05:31:41 PM PDT 24
Peak memory 222436 kb
Host smart-7734daaa-86e7-4b5f-989d-394efc5d2814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771927877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2771927877
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3840006053
Short name T798
Test name
Test status
Simulation time 299417603 ps
CPU time 10.47 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:31:35 PM PDT 24
Peak memory 208868 kb
Host smart-07d424a2-2cc3-449f-b98f-7ce81718cd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840006053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3840006053
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.4232702744
Short name T544
Test name
Test status
Simulation time 179113714 ps
CPU time 2.51 seconds
Started Aug 08 05:31:29 PM PDT 24
Finished Aug 08 05:31:32 PM PDT 24
Peak memory 211000 kb
Host smart-794c93d1-fe70-451a-9252-af592c51c544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232702744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.4232702744
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3753632905
Short name T570
Test name
Test status
Simulation time 12527244 ps
CPU time 0.87 seconds
Started Aug 08 05:31:28 PM PDT 24
Finished Aug 08 05:31:29 PM PDT 24
Peak memory 206000 kb
Host smart-b8e05c5e-e94c-400d-bf08-99f85e830a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753632905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3753632905
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.99903477
Short name T82
Test name
Test status
Simulation time 59305595 ps
CPU time 4 seconds
Started Aug 08 05:31:38 PM PDT 24
Finished Aug 08 05:31:42 PM PDT 24
Peak memory 215316 kb
Host smart-0356c09e-c8cd-4687-9534-686d374da7d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99903477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.99903477
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2991373637
Short name T528
Test name
Test status
Simulation time 194472844 ps
CPU time 4.93 seconds
Started Aug 08 05:31:38 PM PDT 24
Finished Aug 08 05:31:43 PM PDT 24
Peak memory 214380 kb
Host smart-2d7a60a8-d727-4fdb-9da0-ce7492067d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991373637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2991373637
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3851488454
Short name T254
Test name
Test status
Simulation time 267027709 ps
CPU time 5.31 seconds
Started Aug 08 05:31:24 PM PDT 24
Finished Aug 08 05:31:29 PM PDT 24
Peak memory 210020 kb
Host smart-9647953e-4843-4d77-a14c-e0ae3488bafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851488454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3851488454
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1578539825
Short name T318
Test name
Test status
Simulation time 133817477 ps
CPU time 4.29 seconds
Started Aug 08 05:31:32 PM PDT 24
Finished Aug 08 05:31:36 PM PDT 24
Peak memory 214372 kb
Host smart-37d9c542-1e81-416c-8863-268eef4c403c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578539825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1578539825
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1809028446
Short name T898
Test name
Test status
Simulation time 448280360 ps
CPU time 5.03 seconds
Started Aug 08 05:31:28 PM PDT 24
Finished Aug 08 05:31:34 PM PDT 24
Peak memory 210304 kb
Host smart-1c590020-5508-47ca-bb3d-c9110ac00626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809028446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1809028446
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3954960703
Short name T545
Test name
Test status
Simulation time 1134319515 ps
CPU time 9.53 seconds
Started Aug 08 05:31:36 PM PDT 24
Finished Aug 08 05:31:46 PM PDT 24
Peak memory 214368 kb
Host smart-db0b3401-8d4d-4a8f-8330-5e2fc028a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954960703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3954960703
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2827704639
Short name T885
Test name
Test status
Simulation time 335108692 ps
CPU time 2.69 seconds
Started Aug 08 05:31:23 PM PDT 24
Finished Aug 08 05:31:26 PM PDT 24
Peak memory 207020 kb
Host smart-daa65290-19c0-47c5-91d9-736e80df463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827704639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2827704639
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2184049878
Short name T242
Test name
Test status
Simulation time 870848255 ps
CPU time 22.95 seconds
Started Aug 08 05:31:28 PM PDT 24
Finished Aug 08 05:31:51 PM PDT 24
Peak memory 208904 kb
Host smart-fa5d6f61-993d-47e7-9ac5-f04e32495935
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184049878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2184049878
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1108025696
Short name T634
Test name
Test status
Simulation time 1580063220 ps
CPU time 39.48 seconds
Started Aug 08 05:31:28 PM PDT 24
Finished Aug 08 05:32:07 PM PDT 24
Peak memory 208612 kb
Host smart-57d108cb-6640-466c-9f57-738e7958af46
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108025696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1108025696
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.605783650
Short name T645
Test name
Test status
Simulation time 205889980 ps
CPU time 2.76 seconds
Started Aug 08 05:31:37 PM PDT 24
Finished Aug 08 05:31:40 PM PDT 24
Peak memory 206968 kb
Host smart-190daa5c-db67-4594-8328-a9e0091e391d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605783650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.605783650
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3584672775
Short name T893
Test name
Test status
Simulation time 118816948 ps
CPU time 2.62 seconds
Started Aug 08 05:31:26 PM PDT 24
Finished Aug 08 05:31:29 PM PDT 24
Peak memory 208884 kb
Host smart-13868f3b-772e-4a11-a3d2-d6d946620af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584672775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3584672775
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3012157351
Short name T706
Test name
Test status
Simulation time 55369599 ps
CPU time 2.44 seconds
Started Aug 08 05:31:26 PM PDT 24
Finished Aug 08 05:31:29 PM PDT 24
Peak memory 206940 kb
Host smart-a6c2b57d-f76f-4bc6-a98f-2bed635e8651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012157351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3012157351
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2654761518
Short name T279
Test name
Test status
Simulation time 1444042410 ps
CPU time 29.37 seconds
Started Aug 08 05:31:25 PM PDT 24
Finished Aug 08 05:31:54 PM PDT 24
Peak memory 216148 kb
Host smart-3cffc1ea-e51e-4e3a-b38d-33f37e206d95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654761518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2654761518
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.875617708
Short name T173
Test name
Test status
Simulation time 151787259 ps
CPU time 5.06 seconds
Started Aug 08 05:31:37 PM PDT 24
Finished Aug 08 05:31:42 PM PDT 24
Peak memory 222608 kb
Host smart-a41392dc-257c-47b7-8f48-b99bbdcec072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875617708 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.875617708
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1618087322
Short name T889
Test name
Test status
Simulation time 11488427675 ps
CPU time 28.06 seconds
Started Aug 08 05:31:31 PM PDT 24
Finished Aug 08 05:31:59 PM PDT 24
Peak memory 209752 kb
Host smart-3e34a793-4ff2-4069-9c3b-16f79f5a0395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618087322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1618087322
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1738166662
Short name T358
Test name
Test status
Simulation time 42986207 ps
CPU time 1.72 seconds
Started Aug 08 05:31:27 PM PDT 24
Finished Aug 08 05:31:29 PM PDT 24
Peak memory 209556 kb
Host smart-9f55bff3-d83f-4eaf-ab78-014c6bdb0128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738166662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1738166662
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1664922104
Short name T413
Test name
Test status
Simulation time 24006906 ps
CPU time 0.9 seconds
Started Aug 08 05:31:35 PM PDT 24
Finished Aug 08 05:31:36 PM PDT 24
Peak memory 205984 kb
Host smart-26584fe3-8afd-43e6-a492-8ee3cdfd290c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664922104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1664922104
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1193882493
Short name T135
Test name
Test status
Simulation time 72491576 ps
CPU time 3.01 seconds
Started Aug 08 05:31:36 PM PDT 24
Finished Aug 08 05:31:40 PM PDT 24
Peak memory 214956 kb
Host smart-115b1973-4a89-4cb4-85d5-94fdeb916c9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1193882493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1193882493
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4037543848
Short name T550
Test name
Test status
Simulation time 434676852 ps
CPU time 2.15 seconds
Started Aug 08 05:31:32 PM PDT 24
Finished Aug 08 05:31:35 PM PDT 24
Peak memory 214328 kb
Host smart-c99cf102-11fc-4bba-b976-abee561de485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037543848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4037543848
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1756884796
Short name T335
Test name
Test status
Simulation time 91926283 ps
CPU time 2.88 seconds
Started Aug 08 05:31:33 PM PDT 24
Finished Aug 08 05:31:36 PM PDT 24
Peak memory 214264 kb
Host smart-3c35bd25-be1a-43f1-bc27-9f44d0845b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756884796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1756884796
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1200639468
Short name T92
Test name
Test status
Simulation time 161245542 ps
CPU time 5.32 seconds
Started Aug 08 05:31:35 PM PDT 24
Finished Aug 08 05:31:41 PM PDT 24
Peak memory 209452 kb
Host smart-2a09aa05-22e4-4581-8cf0-4c075724abf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200639468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1200639468
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1501614325
Short name T320
Test name
Test status
Simulation time 164161203 ps
CPU time 2.17 seconds
Started Aug 08 05:31:48 PM PDT 24
Finished Aug 08 05:31:50 PM PDT 24
Peak memory 214164 kb
Host smart-ee56b8af-d6ef-4e30-b78f-fa2662252a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501614325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1501614325
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2866098478
Short name T203
Test name
Test status
Simulation time 36139391 ps
CPU time 2.28 seconds
Started Aug 08 05:31:37 PM PDT 24
Finished Aug 08 05:31:39 PM PDT 24
Peak memory 210076 kb
Host smart-67b807f7-c822-422e-a67b-0e21fbd33b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866098478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2866098478
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2058478989
Short name T243
Test name
Test status
Simulation time 122484784 ps
CPU time 5.61 seconds
Started Aug 08 05:31:33 PM PDT 24
Finished Aug 08 05:31:39 PM PDT 24
Peak memory 208928 kb
Host smart-51b04685-af28-4218-bfc4-7b0fcd8ce766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058478989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2058478989
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.994854082
Short name T881
Test name
Test status
Simulation time 1538110364 ps
CPU time 6.31 seconds
Started Aug 08 05:31:27 PM PDT 24
Finished Aug 08 05:31:34 PM PDT 24
Peak memory 206952 kb
Host smart-543838d4-5a7a-4514-a22f-b96de3c22c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994854082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.994854082
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1509583497
Short name T856
Test name
Test status
Simulation time 128524547 ps
CPU time 2.41 seconds
Started Aug 08 05:31:26 PM PDT 24
Finished Aug 08 05:31:29 PM PDT 24
Peak memory 207108 kb
Host smart-e7b93b86-8e87-489a-bd04-df80c2dd9ec3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509583497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1509583497
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3310472262
Short name T668
Test name
Test status
Simulation time 128088979 ps
CPU time 2.95 seconds
Started Aug 08 05:31:26 PM PDT 24
Finished Aug 08 05:31:29 PM PDT 24
Peak memory 206928 kb
Host smart-16c282d6-5c4a-4a9f-b76e-c97e87faf3c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310472262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3310472262
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2657551179
Short name T478
Test name
Test status
Simulation time 211617772 ps
CPU time 2.89 seconds
Started Aug 08 05:31:36 PM PDT 24
Finished Aug 08 05:31:39 PM PDT 24
Peak memory 207196 kb
Host smart-02694adc-a931-4e50-b437-d550aef29101
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657551179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2657551179
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2064432127
Short name T660
Test name
Test status
Simulation time 46830681 ps
CPU time 2.25 seconds
Started Aug 08 05:31:33 PM PDT 24
Finished Aug 08 05:31:36 PM PDT 24
Peak memory 207472 kb
Host smart-ed8d55e7-88ad-4811-bb00-7fa22930dc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064432127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2064432127
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3471732082
Short name T620
Test name
Test status
Simulation time 1556310089 ps
CPU time 36.63 seconds
Started Aug 08 05:31:27 PM PDT 24
Finished Aug 08 05:32:04 PM PDT 24
Peak memory 208704 kb
Host smart-18cb6721-2c8b-4035-97a9-32cbe12ba490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471732082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3471732082
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.120341069
Short name T864
Test name
Test status
Simulation time 3374366697 ps
CPU time 72.08 seconds
Started Aug 08 05:31:33 PM PDT 24
Finished Aug 08 05:32:46 PM PDT 24
Peak memory 216612 kb
Host smart-6ec431a5-f72a-4080-8dda-0a59bfcf3cb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120341069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.120341069
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1885292375
Short name T866
Test name
Test status
Simulation time 467705824 ps
CPU time 17.23 seconds
Started Aug 08 05:31:34 PM PDT 24
Finished Aug 08 05:31:52 PM PDT 24
Peak memory 221388 kb
Host smart-81e9b0fe-af97-42ea-b8ab-2732ac124c61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885292375 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1885292375
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3735871802
Short name T837
Test name
Test status
Simulation time 971997224 ps
CPU time 7.62 seconds
Started Aug 08 05:31:36 PM PDT 24
Finished Aug 08 05:31:44 PM PDT 24
Peak memory 218588 kb
Host smart-42fba297-d156-4e11-b96f-027b4d50e5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735871802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3735871802
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2300449422
Short name T352
Test name
Test status
Simulation time 32660232 ps
CPU time 1.97 seconds
Started Aug 08 05:31:34 PM PDT 24
Finished Aug 08 05:31:37 PM PDT 24
Peak memory 210204 kb
Host smart-8e37a60e-6831-4d83-82c3-63255164f80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300449422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2300449422
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.277662451
Short name T440
Test name
Test status
Simulation time 53498330 ps
CPU time 0.76 seconds
Started Aug 08 05:31:35 PM PDT 24
Finished Aug 08 05:31:35 PM PDT 24
Peak memory 205864 kb
Host smart-37a84028-bf3f-40cf-a33c-ee33dbdf46a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277662451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.277662451
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.301024479
Short name T842
Test name
Test status
Simulation time 136148094 ps
CPU time 2.54 seconds
Started Aug 08 05:31:33 PM PDT 24
Finished Aug 08 05:31:35 PM PDT 24
Peak memory 215784 kb
Host smart-8b9852a1-189e-4231-9e21-61c3b94e79ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301024479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.301024479
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.643243732
Short name T567
Test name
Test status
Simulation time 55956162 ps
CPU time 2.07 seconds
Started Aug 08 05:31:36 PM PDT 24
Finished Aug 08 05:31:38 PM PDT 24
Peak memory 214312 kb
Host smart-149e7b9b-3966-4b84-9503-1c191d8475e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643243732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.643243732
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1392169347
Short name T266
Test name
Test status
Simulation time 329076221 ps
CPU time 2.66 seconds
Started Aug 08 05:31:35 PM PDT 24
Finished Aug 08 05:31:38 PM PDT 24
Peak memory 214284 kb
Host smart-0421f1f1-2862-452f-876a-43a855b1f6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392169347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1392169347
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.4186920334
Short name T496
Test name
Test status
Simulation time 103416326 ps
CPU time 3.37 seconds
Started Aug 08 05:31:36 PM PDT 24
Finished Aug 08 05:31:40 PM PDT 24
Peak memory 214348 kb
Host smart-be8cd5ba-7864-48a6-beac-7ab42ddeb774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186920334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.4186920334
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.560297578
Short name T435
Test name
Test status
Simulation time 100488604 ps
CPU time 4.63 seconds
Started Aug 08 05:31:35 PM PDT 24
Finished Aug 08 05:31:39 PM PDT 24
Peak memory 210164 kb
Host smart-12a6772c-b5c0-4af2-a46b-d7b379ffeba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560297578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.560297578
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1055067662
Short name T644
Test name
Test status
Simulation time 41461651 ps
CPU time 2.78 seconds
Started Aug 08 05:31:34 PM PDT 24
Finished Aug 08 05:31:37 PM PDT 24
Peak memory 207328 kb
Host smart-25449ef5-ebb2-4b21-8fb0-eb2e60af5134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055067662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1055067662
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2976551163
Short name T578
Test name
Test status
Simulation time 239828171 ps
CPU time 2.8 seconds
Started Aug 08 05:31:34 PM PDT 24
Finished Aug 08 05:31:37 PM PDT 24
Peak memory 206932 kb
Host smart-d993551c-da1b-483f-a05d-4a3e74bff2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976551163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2976551163
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.425488156
Short name T422
Test name
Test status
Simulation time 357931717 ps
CPU time 2.54 seconds
Started Aug 08 05:31:35 PM PDT 24
Finished Aug 08 05:31:37 PM PDT 24
Peak memory 208892 kb
Host smart-a252d560-dcfa-45cc-b194-eb106010fbd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425488156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.425488156
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.56650517
Short name T250
Test name
Test status
Simulation time 76910886 ps
CPU time 3.35 seconds
Started Aug 08 05:31:34 PM PDT 24
Finished Aug 08 05:31:38 PM PDT 24
Peak memory 208828 kb
Host smart-8243ca2a-56f4-44f0-a4b8-a146103583e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56650517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.56650517
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.4208479120
Short name T731
Test name
Test status
Simulation time 313945345 ps
CPU time 3.1 seconds
Started Aug 08 05:31:35 PM PDT 24
Finished Aug 08 05:31:38 PM PDT 24
Peak memory 207036 kb
Host smart-7ddbf721-ff8b-4068-987f-9f3a0b963be8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208479120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.4208479120
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3237287503
Short name T790
Test name
Test status
Simulation time 83981885 ps
CPU time 3.11 seconds
Started Aug 08 05:31:36 PM PDT 24
Finished Aug 08 05:31:39 PM PDT 24
Peak memory 208028 kb
Host smart-551e3d5e-ca58-4690-bffa-baa92cd42d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237287503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3237287503
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.74347074
Short name T609
Test name
Test status
Simulation time 84286718 ps
CPU time 2.81 seconds
Started Aug 08 05:31:36 PM PDT 24
Finished Aug 08 05:31:39 PM PDT 24
Peak memory 208580 kb
Host smart-42727123-a5c9-408b-b64b-cecc87c48665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74347074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.74347074
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.4187485390
Short name T174
Test name
Test status
Simulation time 1067490289 ps
CPU time 19.14 seconds
Started Aug 08 05:31:39 PM PDT 24
Finished Aug 08 05:31:58 PM PDT 24
Peak memory 222744 kb
Host smart-bd37743d-37f8-43d3-98af-bf39782b91b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187485390 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.4187485390
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1617115202
Short name T79
Test name
Test status
Simulation time 923885710 ps
CPU time 8.08 seconds
Started Aug 08 05:31:35 PM PDT 24
Finished Aug 08 05:31:43 PM PDT 24
Peak memory 218364 kb
Host smart-c1ae46ba-ce29-4687-97bd-07bf5dba8382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617115202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1617115202
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2212268181
Short name T498
Test name
Test status
Simulation time 130303983 ps
CPU time 2.3 seconds
Started Aug 08 05:31:32 PM PDT 24
Finished Aug 08 05:31:35 PM PDT 24
Peak memory 210348 kb
Host smart-1aec77c3-a9c1-4ce6-8d78-656c7f37c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212268181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2212268181
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.668371829
Short name T661
Test name
Test status
Simulation time 14337048 ps
CPU time 0.95 seconds
Started Aug 08 05:31:46 PM PDT 24
Finished Aug 08 05:31:47 PM PDT 24
Peak memory 206104 kb
Host smart-0879a494-16bc-41ca-b47e-ba90dfd35bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668371829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.668371829
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2868757611
Short name T19
Test name
Test status
Simulation time 157297852 ps
CPU time 3.36 seconds
Started Aug 08 05:31:45 PM PDT 24
Finished Aug 08 05:31:48 PM PDT 24
Peak memory 214260 kb
Host smart-2a6e0412-549e-4f42-9e2a-2a6bd4c98185
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868757611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2868757611
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2932157223
Short name T841
Test name
Test status
Simulation time 92144777 ps
CPU time 2.73 seconds
Started Aug 08 05:31:47 PM PDT 24
Finished Aug 08 05:31:50 PM PDT 24
Peak memory 208812 kb
Host smart-0d6b22e9-7943-4684-9a52-c1f358778088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932157223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2932157223
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.296834143
Short name T72
Test name
Test status
Simulation time 280432817 ps
CPU time 3.18 seconds
Started Aug 08 05:31:46 PM PDT 24
Finished Aug 08 05:31:49 PM PDT 24
Peak memory 218196 kb
Host smart-8c48aeb9-2620-46f5-ab99-5b9d2b940467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296834143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.296834143
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.288942245
Short name T336
Test name
Test status
Simulation time 74763650 ps
CPU time 1.93 seconds
Started Aug 08 05:31:48 PM PDT 24
Finished Aug 08 05:31:50 PM PDT 24
Peak memory 214388 kb
Host smart-3e5ff63b-f19e-4ec9-bd37-757689cb7429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288942245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.288942245
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.981315047
Short name T905
Test name
Test status
Simulation time 173497763 ps
CPU time 3.17 seconds
Started Aug 08 05:31:46 PM PDT 24
Finished Aug 08 05:31:49 PM PDT 24
Peak memory 222436 kb
Host smart-f4793c02-6cfb-4aac-9358-b47600a0321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981315047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.981315047
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.309777646
Short name T426
Test name
Test status
Simulation time 90491532 ps
CPU time 2.52 seconds
Started Aug 08 05:31:45 PM PDT 24
Finished Aug 08 05:31:47 PM PDT 24
Peak memory 209436 kb
Host smart-e54ae614-c251-45c1-8f86-5d4f948255b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309777646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.309777646
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1835862556
Short name T491
Test name
Test status
Simulation time 195504337 ps
CPU time 5.46 seconds
Started Aug 08 05:31:47 PM PDT 24
Finished Aug 08 05:31:52 PM PDT 24
Peak memory 209196 kb
Host smart-65ab4ee7-3a35-4f3d-bebf-fbf2ad5bdbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835862556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1835862556
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.799253252
Short name T739
Test name
Test status
Simulation time 188952326 ps
CPU time 2.86 seconds
Started Aug 08 05:31:40 PM PDT 24
Finished Aug 08 05:31:43 PM PDT 24
Peak memory 207136 kb
Host smart-d6f5f4cd-433a-4d80-bc1e-576d98ce8ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799253252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.799253252
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1048158325
Short name T671
Test name
Test status
Simulation time 232136188 ps
CPU time 3.31 seconds
Started Aug 08 05:31:40 PM PDT 24
Finished Aug 08 05:31:43 PM PDT 24
Peak memory 207100 kb
Host smart-8c071fdf-6d9b-460b-a129-491e5d58b97b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048158325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1048158325
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2546956982
Short name T451
Test name
Test status
Simulation time 136215301 ps
CPU time 3.47 seconds
Started Aug 08 05:31:36 PM PDT 24
Finished Aug 08 05:31:39 PM PDT 24
Peak memory 206992 kb
Host smart-1f763fd3-e7b3-41bc-9568-8796f24172d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546956982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2546956982
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2929945207
Short name T195
Test name
Test status
Simulation time 517977696 ps
CPU time 3.29 seconds
Started Aug 08 05:31:35 PM PDT 24
Finished Aug 08 05:31:38 PM PDT 24
Peak memory 206908 kb
Host smart-4069b58e-68d0-4418-9a8f-29a5aa12a38d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929945207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2929945207
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2325154272
Short name T537
Test name
Test status
Simulation time 175993562 ps
CPU time 2.66 seconds
Started Aug 08 05:31:46 PM PDT 24
Finished Aug 08 05:31:49 PM PDT 24
Peak memory 209996 kb
Host smart-ba65c059-d9a5-4aa5-a778-5e96d7dce572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325154272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2325154272
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1463270757
Short name T193
Test name
Test status
Simulation time 5527850227 ps
CPU time 26.08 seconds
Started Aug 08 05:31:35 PM PDT 24
Finished Aug 08 05:32:01 PM PDT 24
Peak memory 208444 kb
Host smart-292b60b4-43d3-4aef-b557-ad9bc9e4b56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463270757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1463270757
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2549283286
Short name T312
Test name
Test status
Simulation time 621064039 ps
CPU time 24.9 seconds
Started Aug 08 05:31:44 PM PDT 24
Finished Aug 08 05:32:09 PM PDT 24
Peak memory 217052 kb
Host smart-e522f0e7-a09e-4f18-aa94-85b0652d2ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549283286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2549283286
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3579119134
Short name T314
Test name
Test status
Simulation time 158893313 ps
CPU time 2.95 seconds
Started Aug 08 05:31:46 PM PDT 24
Finished Aug 08 05:31:49 PM PDT 24
Peak memory 207448 kb
Host smart-fbde003e-383c-49d8-9f6e-f89fd9119869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579119134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3579119134
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2047172939
Short name T132
Test name
Test status
Simulation time 222063625 ps
CPU time 2.45 seconds
Started Aug 08 05:31:47 PM PDT 24
Finished Aug 08 05:31:50 PM PDT 24
Peak memory 209908 kb
Host smart-22f863f1-4b1e-412b-b08c-2e5ec5174b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047172939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2047172939
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.630146170
Short name T561
Test name
Test status
Simulation time 52666494 ps
CPU time 0.78 seconds
Started Aug 08 05:31:47 PM PDT 24
Finished Aug 08 05:31:47 PM PDT 24
Peak memory 205952 kb
Host smart-0bd09b6a-6c07-4292-9a54-6881c0787703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630146170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.630146170
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2863191167
Short name T33
Test name
Test status
Simulation time 167022369 ps
CPU time 2.22 seconds
Started Aug 08 05:31:45 PM PDT 24
Finished Aug 08 05:31:47 PM PDT 24
Peak memory 214568 kb
Host smart-18020ccf-e668-44a4-ac73-5534368756cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863191167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2863191167
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4166322725
Short name T891
Test name
Test status
Simulation time 434142628 ps
CPU time 9.32 seconds
Started Aug 08 05:31:46 PM PDT 24
Finished Aug 08 05:31:56 PM PDT 24
Peak memory 209172 kb
Host smart-dc2c3d0f-96b2-497a-9144-b6ac0ab76af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166322725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4166322725
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.4225106663
Short name T89
Test name
Test status
Simulation time 33168152 ps
CPU time 2.6 seconds
Started Aug 08 05:31:48 PM PDT 24
Finished Aug 08 05:31:51 PM PDT 24
Peak memory 214312 kb
Host smart-4f403606-b5ac-4087-b152-1c65d1fa5bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225106663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.4225106663
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.578339426
Short name T819
Test name
Test status
Simulation time 34820607 ps
CPU time 1.93 seconds
Started Aug 08 05:31:44 PM PDT 24
Finished Aug 08 05:31:46 PM PDT 24
Peak memory 214316 kb
Host smart-abb1fa48-9301-42d7-bc8b-85c7d7623e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578339426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.578339426
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2441182292
Short name T791
Test name
Test status
Simulation time 364031816 ps
CPU time 3.16 seconds
Started Aug 08 05:31:46 PM PDT 24
Finished Aug 08 05:31:49 PM PDT 24
Peak memory 220224 kb
Host smart-3735f1da-d1e2-4ba6-aa26-5127850ea061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441182292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2441182292
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2848572211
Short name T253
Test name
Test status
Simulation time 93308049 ps
CPU time 4.22 seconds
Started Aug 08 05:31:44 PM PDT 24
Finished Aug 08 05:31:49 PM PDT 24
Peak memory 209944 kb
Host smart-34777dbf-328b-420d-bf2a-e5ed79d7d5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848572211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2848572211
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.557040005
Short name T346
Test name
Test status
Simulation time 40980050 ps
CPU time 2.31 seconds
Started Aug 08 05:31:47 PM PDT 24
Finished Aug 08 05:31:49 PM PDT 24
Peak memory 207320 kb
Host smart-32895c8f-da32-4569-b7bb-4358cf8f7b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557040005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.557040005
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2616758377
Short name T703
Test name
Test status
Simulation time 90894041 ps
CPU time 2.61 seconds
Started Aug 08 05:31:47 PM PDT 24
Finished Aug 08 05:31:49 PM PDT 24
Peak memory 207892 kb
Host smart-4b8d237d-fc5d-4e07-a3a2-f86977df5121
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616758377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2616758377
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2719156909
Short name T270
Test name
Test status
Simulation time 303904211 ps
CPU time 6.53 seconds
Started Aug 08 05:31:44 PM PDT 24
Finished Aug 08 05:31:51 PM PDT 24
Peak memory 208416 kb
Host smart-98995c84-c2bb-4c9e-b5db-38ef51f79ea1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719156909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2719156909
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2190600024
Short name T255
Test name
Test status
Simulation time 816980825 ps
CPU time 9.21 seconds
Started Aug 08 05:31:46 PM PDT 24
Finished Aug 08 05:31:56 PM PDT 24
Peak memory 208356 kb
Host smart-08e60db1-bac5-4381-a9b3-c26dc08f9fd2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190600024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2190600024
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3244732572
Short name T565
Test name
Test status
Simulation time 44816511 ps
CPU time 2.65 seconds
Started Aug 08 05:31:47 PM PDT 24
Finished Aug 08 05:31:50 PM PDT 24
Peak memory 207876 kb
Host smart-f8790701-aa82-45c9-8b40-a5d8ef760e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244732572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3244732572
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2443939792
Short name T515
Test name
Test status
Simulation time 38371835 ps
CPU time 1.81 seconds
Started Aug 08 05:31:45 PM PDT 24
Finished Aug 08 05:31:47 PM PDT 24
Peak memory 206792 kb
Host smart-1220909c-c253-4239-8c69-99a51ea261e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443939792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2443939792
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3607579317
Short name T215
Test name
Test status
Simulation time 6239110884 ps
CPU time 64.83 seconds
Started Aug 08 05:31:48 PM PDT 24
Finished Aug 08 05:32:53 PM PDT 24
Peak memory 216292 kb
Host smart-ae61222b-765e-4911-bf39-777b8b64af6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607579317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3607579317
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.785770480
Short name T26
Test name
Test status
Simulation time 64263509 ps
CPU time 3.34 seconds
Started Aug 08 05:31:46 PM PDT 24
Finished Aug 08 05:31:49 PM PDT 24
Peak memory 207560 kb
Host smart-a1555062-67ee-4717-a33c-170d8c978dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785770480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.785770480
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.86722147
Short name T656
Test name
Test status
Simulation time 46303361 ps
CPU time 2.04 seconds
Started Aug 08 05:31:45 PM PDT 24
Finished Aug 08 05:31:47 PM PDT 24
Peak memory 209720 kb
Host smart-e8409d3a-f8ff-4538-9b2f-71e5878c1be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86722147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.86722147
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4053907800
Short name T436
Test name
Test status
Simulation time 52876083 ps
CPU time 0.77 seconds
Started Aug 08 05:31:58 PM PDT 24
Finished Aug 08 05:31:59 PM PDT 24
Peak memory 205952 kb
Host smart-4fc8b2e3-20a3-451f-9bd9-b2e9f72917ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053907800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4053907800
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1921205993
Short name T858
Test name
Test status
Simulation time 108873638 ps
CPU time 2.44 seconds
Started Aug 08 05:31:47 PM PDT 24
Finished Aug 08 05:31:50 PM PDT 24
Peak memory 209724 kb
Host smart-68397197-eca7-40a7-b785-32dbdd8d7c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921205993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1921205993
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1198229832
Short name T696
Test name
Test status
Simulation time 166906398 ps
CPU time 3.09 seconds
Started Aug 08 05:32:05 PM PDT 24
Finished Aug 08 05:32:08 PM PDT 24
Peak memory 222484 kb
Host smart-082bca21-5050-44a6-a968-037e5f8e765b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198229832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1198229832
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2182980100
Short name T302
Test name
Test status
Simulation time 91970325 ps
CPU time 3.89 seconds
Started Aug 08 05:32:02 PM PDT 24
Finished Aug 08 05:32:06 PM PDT 24
Peak memory 222408 kb
Host smart-c23f6de0-477e-473f-bcef-2c1104a6cff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182980100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2182980100
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3600604096
Short name T846
Test name
Test status
Simulation time 282285679 ps
CPU time 3.84 seconds
Started Aug 08 05:32:04 PM PDT 24
Finished Aug 08 05:32:08 PM PDT 24
Peak memory 209468 kb
Host smart-51c6a5e1-8b3b-4eeb-873a-44b1f03318a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600604096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3600604096
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.361535167
Short name T636
Test name
Test status
Simulation time 230752675 ps
CPU time 5.58 seconds
Started Aug 08 05:31:49 PM PDT 24
Finished Aug 08 05:31:55 PM PDT 24
Peak memory 214344 kb
Host smart-4df77bbe-5c81-4d21-a309-a205fce9b6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361535167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.361535167
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2095536600
Short name T733
Test name
Test status
Simulation time 33829581 ps
CPU time 2.48 seconds
Started Aug 08 05:31:48 PM PDT 24
Finished Aug 08 05:31:51 PM PDT 24
Peak memory 207020 kb
Host smart-b950dcd8-bc92-4885-a359-7759a4013c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095536600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2095536600
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1393574622
Short name T825
Test name
Test status
Simulation time 109089790 ps
CPU time 3.21 seconds
Started Aug 08 05:31:50 PM PDT 24
Finished Aug 08 05:31:53 PM PDT 24
Peak memory 208548 kb
Host smart-dc491640-4418-4795-b268-186b2ebe3ee1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393574622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1393574622
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.71094062
Short name T309
Test name
Test status
Simulation time 142426488 ps
CPU time 3.47 seconds
Started Aug 08 05:31:47 PM PDT 24
Finished Aug 08 05:31:50 PM PDT 24
Peak memory 208848 kb
Host smart-afa4cf3a-0938-4598-ae88-05af107049e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71094062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.71094062
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1008189135
Short name T479
Test name
Test status
Simulation time 63637865 ps
CPU time 3.17 seconds
Started Aug 08 05:31:47 PM PDT 24
Finished Aug 08 05:31:50 PM PDT 24
Peak memory 209052 kb
Host smart-71411555-e04a-4de9-8aed-e959749ef8d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008189135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1008189135
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.54115755
Short name T587
Test name
Test status
Simulation time 140771669 ps
CPU time 2.43 seconds
Started Aug 08 05:32:04 PM PDT 24
Finished Aug 08 05:32:07 PM PDT 24
Peak memory 215596 kb
Host smart-229f878c-0ef2-4450-9791-881f565301e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54115755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.54115755
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.617231312
Short name T716
Test name
Test status
Simulation time 29811813 ps
CPU time 2.06 seconds
Started Aug 08 05:31:44 PM PDT 24
Finished Aug 08 05:31:46 PM PDT 24
Peak memory 206848 kb
Host smart-85dae53c-467e-4d0f-bc19-ed7fd6281c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617231312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.617231312
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1312194917
Short name T774
Test name
Test status
Simulation time 423297436 ps
CPU time 6.49 seconds
Started Aug 08 05:32:04 PM PDT 24
Finished Aug 08 05:32:11 PM PDT 24
Peak memory 219244 kb
Host smart-84979628-6cbb-43a8-9aab-0263f41d2edc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312194917 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1312194917
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3375699560
Short name T494
Test name
Test status
Simulation time 318090227 ps
CPU time 2.78 seconds
Started Aug 08 05:31:58 PM PDT 24
Finished Aug 08 05:32:01 PM PDT 24
Peak memory 207536 kb
Host smart-a6713858-3cb6-4b1d-9ae4-1f65d0b42b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375699560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3375699560
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2060754540
Short name T354
Test name
Test status
Simulation time 548515172 ps
CPU time 3.45 seconds
Started Aug 08 05:32:05 PM PDT 24
Finished Aug 08 05:32:08 PM PDT 24
Peak memory 210528 kb
Host smart-32eaf798-50aa-42a0-91b7-aad1f5a797da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060754540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2060754540
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.393872672
Short name T608
Test name
Test status
Simulation time 11703842 ps
CPU time 0.89 seconds
Started Aug 08 05:29:26 PM PDT 24
Finished Aug 08 05:29:27 PM PDT 24
Peak memory 205984 kb
Host smart-580a865f-9f33-42eb-9019-91da8681f10c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393872672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.393872672
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3737351263
Short name T380
Test name
Test status
Simulation time 300409546 ps
CPU time 2.78 seconds
Started Aug 08 05:29:21 PM PDT 24
Finished Aug 08 05:29:24 PM PDT 24
Peak memory 214380 kb
Host smart-f69a4385-f1ae-4302-9a0c-658513548e60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737351263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3737351263
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2197766877
Short name T21
Test name
Test status
Simulation time 101135213 ps
CPU time 1.79 seconds
Started Aug 08 05:29:22 PM PDT 24
Finished Aug 08 05:29:24 PM PDT 24
Peak memory 208788 kb
Host smart-fc6a0db7-e617-4dde-9f86-df0e91b54c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197766877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2197766877
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1846431452
Short name T780
Test name
Test status
Simulation time 3536527481 ps
CPU time 15.43 seconds
Started Aug 08 05:29:24 PM PDT 24
Finished Aug 08 05:29:40 PM PDT 24
Peak memory 208660 kb
Host smart-644c8cdd-634f-43df-811c-2d2ea3fb5368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846431452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1846431452
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3088248940
Short name T415
Test name
Test status
Simulation time 423536022 ps
CPU time 6.35 seconds
Started Aug 08 05:29:22 PM PDT 24
Finished Aug 08 05:29:29 PM PDT 24
Peak memory 208936 kb
Host smart-b4757535-6856-44ca-b484-fea5876dd7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088248940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3088248940
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2200127109
Short name T851
Test name
Test status
Simulation time 223320749 ps
CPU time 4.07 seconds
Started Aug 08 05:29:24 PM PDT 24
Finished Aug 08 05:29:29 PM PDT 24
Peak memory 214300 kb
Host smart-6d477a37-181e-4825-bda5-080077c8f0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200127109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2200127109
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.705433829
Short name T456
Test name
Test status
Simulation time 56157576 ps
CPU time 2.47 seconds
Started Aug 08 05:29:20 PM PDT 24
Finished Aug 08 05:29:23 PM PDT 24
Peak memory 209756 kb
Host smart-7dc49491-450f-44a0-928d-d9786a3c2968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705433829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.705433829
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1326342950
Short name T501
Test name
Test status
Simulation time 99564822 ps
CPU time 4.43 seconds
Started Aug 08 05:29:18 PM PDT 24
Finished Aug 08 05:29:23 PM PDT 24
Peak memory 214336 kb
Host smart-48e6d500-6d08-4528-a1f1-bde399609701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326342950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1326342950
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.947181133
Short name T418
Test name
Test status
Simulation time 143555324 ps
CPU time 4.27 seconds
Started Aug 08 05:29:14 PM PDT 24
Finished Aug 08 05:29:18 PM PDT 24
Peak memory 206900 kb
Host smart-17891e71-2f8f-47f1-bc6a-ee6c6bb9937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947181133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.947181133
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.595875024
Short name T349
Test name
Test status
Simulation time 36032277 ps
CPU time 2.26 seconds
Started Aug 08 05:29:24 PM PDT 24
Finished Aug 08 05:29:26 PM PDT 24
Peak memory 207328 kb
Host smart-27e96633-b9d8-4b87-a794-6672a8001bbe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595875024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.595875024
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3740872004
Short name T517
Test name
Test status
Simulation time 688261576 ps
CPU time 4.7 seconds
Started Aug 08 05:29:13 PM PDT 24
Finished Aug 08 05:29:17 PM PDT 24
Peak memory 207936 kb
Host smart-b048852d-4b2b-45d2-91aa-2632fe14d2d3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740872004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3740872004
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.304699318
Short name T525
Test name
Test status
Simulation time 599921573 ps
CPU time 2.25 seconds
Started Aug 08 05:29:23 PM PDT 24
Finished Aug 08 05:29:25 PM PDT 24
Peak memory 206796 kb
Host smart-47e9a478-a0d9-4e07-8ea1-cb167d63e73b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304699318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.304699318
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2001283111
Short name T283
Test name
Test status
Simulation time 1611626736 ps
CPU time 15.18 seconds
Started Aug 08 05:29:21 PM PDT 24
Finished Aug 08 05:29:37 PM PDT 24
Peak memory 214288 kb
Host smart-7e1b031b-ffab-4434-b413-ef3369e92374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001283111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2001283111
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.522286197
Short name T442
Test name
Test status
Simulation time 112652460 ps
CPU time 2.81 seconds
Started Aug 08 05:29:08 PM PDT 24
Finished Aug 08 05:29:11 PM PDT 24
Peak memory 208616 kb
Host smart-a0af083b-df95-4063-ac38-aea01ec620b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522286197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.522286197
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2792758250
Short name T348
Test name
Test status
Simulation time 196814026 ps
CPU time 4.72 seconds
Started Aug 08 05:29:20 PM PDT 24
Finished Aug 08 05:29:25 PM PDT 24
Peak memory 208188 kb
Host smart-6207b57d-1f67-4b0e-95bd-611dc3731a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792758250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2792758250
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2550450472
Short name T356
Test name
Test status
Simulation time 39706738 ps
CPU time 2.26 seconds
Started Aug 08 05:29:19 PM PDT 24
Finished Aug 08 05:29:22 PM PDT 24
Peak memory 210428 kb
Host smart-53d85ef9-339b-4997-8a37-52be645bc691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550450472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2550450472
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2339179371
Short name T665
Test name
Test status
Simulation time 53815289 ps
CPU time 0.69 seconds
Started Aug 08 05:29:22 PM PDT 24
Finished Aug 08 05:29:22 PM PDT 24
Peak memory 205892 kb
Host smart-ae16ce7c-3655-4eb8-b25b-bfd8366ebee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339179371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2339179371
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.4097882235
Short name T390
Test name
Test status
Simulation time 347865006 ps
CPU time 5.71 seconds
Started Aug 08 05:29:22 PM PDT 24
Finished Aug 08 05:29:28 PM PDT 24
Peak memory 214240 kb
Host smart-6d8ff6de-a8c8-4717-aa49-14b1ce7fb693
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4097882235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.4097882235
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2480290286
Short name T766
Test name
Test status
Simulation time 520158987 ps
CPU time 2.37 seconds
Started Aug 08 05:29:26 PM PDT 24
Finished Aug 08 05:29:28 PM PDT 24
Peak memory 207940 kb
Host smart-5d97fa2c-6f72-4431-a360-7e858ec14956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480290286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2480290286
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.925012150
Short name T805
Test name
Test status
Simulation time 92836906 ps
CPU time 3.01 seconds
Started Aug 08 05:29:20 PM PDT 24
Finished Aug 08 05:29:24 PM PDT 24
Peak memory 214232 kb
Host smart-f65c31a0-0830-437a-8d32-453ef2416430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925012150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.925012150
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1211856086
Short name T303
Test name
Test status
Simulation time 223620363 ps
CPU time 2.4 seconds
Started Aug 08 05:29:20 PM PDT 24
Finished Aug 08 05:29:22 PM PDT 24
Peak memory 222544 kb
Host smart-8a4b506d-fe55-4d91-ae95-a6507aa9aba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211856086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1211856086
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.78758428
Short name T232
Test name
Test status
Simulation time 231033924 ps
CPU time 3.27 seconds
Started Aug 08 05:29:21 PM PDT 24
Finished Aug 08 05:29:25 PM PDT 24
Peak memory 214212 kb
Host smart-e369db3b-2485-4e59-a566-77a47b3c89b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78758428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.78758428
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2618941299
Short name T407
Test name
Test status
Simulation time 143990828 ps
CPU time 2.09 seconds
Started Aug 08 05:29:23 PM PDT 24
Finished Aug 08 05:29:25 PM PDT 24
Peak memory 214356 kb
Host smart-bbae6818-a08e-437d-955f-c3d3df7d45f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618941299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2618941299
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3688516914
Short name T783
Test name
Test status
Simulation time 4319601088 ps
CPU time 53.05 seconds
Started Aug 08 05:29:21 PM PDT 24
Finished Aug 08 05:30:14 PM PDT 24
Peak memory 208336 kb
Host smart-12cf2527-41c0-4505-8f56-2e061ae2a2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688516914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3688516914
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.492256667
Short name T715
Test name
Test status
Simulation time 109952865 ps
CPU time 3.67 seconds
Started Aug 08 05:29:22 PM PDT 24
Finished Aug 08 05:29:26 PM PDT 24
Peak memory 208588 kb
Host smart-50a84361-c4a3-4294-8e2a-3f0bb80517ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492256667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.492256667
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3699778672
Short name T190
Test name
Test status
Simulation time 204878217 ps
CPU time 4.9 seconds
Started Aug 08 05:29:22 PM PDT 24
Finished Aug 08 05:29:27 PM PDT 24
Peak memory 208708 kb
Host smart-a9e05c29-7590-4063-9a52-cbb44e0ded9c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699778672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3699778672
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.135698980
Short name T438
Test name
Test status
Simulation time 32815847 ps
CPU time 2.45 seconds
Started Aug 08 05:29:24 PM PDT 24
Finished Aug 08 05:29:27 PM PDT 24
Peak memory 207604 kb
Host smart-988f4914-d8a7-43f7-b6b3-24be3203d16d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135698980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.135698980
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.21233304
Short name T230
Test name
Test status
Simulation time 787552328 ps
CPU time 10.91 seconds
Started Aug 08 05:29:23 PM PDT 24
Finished Aug 08 05:29:34 PM PDT 24
Peak memory 208516 kb
Host smart-cf29124e-6d50-4871-9c0a-fc2c951c62fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21233304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.21233304
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2075097310
Short name T633
Test name
Test status
Simulation time 299151218 ps
CPU time 2.42 seconds
Started Aug 08 05:29:21 PM PDT 24
Finished Aug 08 05:29:24 PM PDT 24
Peak memory 209060 kb
Host smart-e8e2dca6-b6e0-46ea-beb8-95a8db57ffb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075097310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2075097310
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3222979784
Short name T125
Test name
Test status
Simulation time 46138267 ps
CPU time 2.43 seconds
Started Aug 08 05:29:19 PM PDT 24
Finished Aug 08 05:29:22 PM PDT 24
Peak memory 208756 kb
Host smart-b784a03b-1f53-473a-95ab-0003d0724d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222979784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3222979784
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.4176741930
Short name T797
Test name
Test status
Simulation time 589600720 ps
CPU time 16.36 seconds
Started Aug 08 05:29:24 PM PDT 24
Finished Aug 08 05:29:41 PM PDT 24
Peak memory 216568 kb
Host smart-16f2e014-d2d0-4690-81de-c49ba1ebad17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176741930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.4176741930
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1588833727
Short name T598
Test name
Test status
Simulation time 81956127 ps
CPU time 3.62 seconds
Started Aug 08 05:29:19 PM PDT 24
Finished Aug 08 05:29:23 PM PDT 24
Peak memory 207712 kb
Host smart-b4a7a1af-3a0c-4f7e-8d60-96a80cb23238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588833727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1588833727
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.644119188
Short name T640
Test name
Test status
Simulation time 105480871 ps
CPU time 3.5 seconds
Started Aug 08 05:29:19 PM PDT 24
Finished Aug 08 05:29:23 PM PDT 24
Peak memory 209844 kb
Host smart-81d10ebc-02e4-4885-b29f-9987c0cf7c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644119188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.644119188
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3036796967
Short name T429
Test name
Test status
Simulation time 15997388 ps
CPU time 0.98 seconds
Started Aug 08 05:29:21 PM PDT 24
Finished Aug 08 05:29:22 PM PDT 24
Peak memory 206140 kb
Host smart-36df9ea2-0c05-4567-a635-0bae95b493e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036796967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3036796967
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2932392558
Short name T330
Test name
Test status
Simulation time 183248150 ps
CPU time 3.84 seconds
Started Aug 08 05:29:21 PM PDT 24
Finished Aug 08 05:29:25 PM PDT 24
Peak memory 214432 kb
Host smart-7d77bb91-eebe-419a-bf45-ae198f3b79d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2932392558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2932392558
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.795688001
Short name T552
Test name
Test status
Simulation time 71403801 ps
CPU time 2.43 seconds
Started Aug 08 05:29:23 PM PDT 24
Finished Aug 08 05:29:26 PM PDT 24
Peak memory 216860 kb
Host smart-d83a1a84-b091-4e82-96cc-9878ea5d1d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795688001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.795688001
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1486985354
Short name T763
Test name
Test status
Simulation time 216756802 ps
CPU time 3.01 seconds
Started Aug 08 05:29:21 PM PDT 24
Finished Aug 08 05:29:24 PM PDT 24
Peak memory 207632 kb
Host smart-5227bbbe-99d5-4add-aff7-f05a6f3fcead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486985354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1486985354
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.4113745609
Short name T684
Test name
Test status
Simulation time 118906531 ps
CPU time 2.03 seconds
Started Aug 08 05:29:22 PM PDT 24
Finished Aug 08 05:29:25 PM PDT 24
Peak memory 214284 kb
Host smart-c57bd84f-000c-4e84-96c1-92c3bf8a770c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113745609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.4113745609
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3681887767
Short name T221
Test name
Test status
Simulation time 143724802 ps
CPU time 6.5 seconds
Started Aug 08 05:29:23 PM PDT 24
Finished Aug 08 05:29:30 PM PDT 24
Peak memory 214296 kb
Host smart-75d88a64-2c98-4cf9-a38e-c627f785f35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681887767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3681887767
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2789464630
Short name T628
Test name
Test status
Simulation time 35712356 ps
CPU time 2.79 seconds
Started Aug 08 05:29:17 PM PDT 24
Finished Aug 08 05:29:20 PM PDT 24
Peak memory 214408 kb
Host smart-29aa6306-e523-477d-8ca5-447d1b8715e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789464630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2789464630
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.4012717494
Short name T597
Test name
Test status
Simulation time 57222795 ps
CPU time 2.45 seconds
Started Aug 08 05:29:20 PM PDT 24
Finished Aug 08 05:29:23 PM PDT 24
Peak memory 208288 kb
Host smart-83f9f4f0-e258-42f8-a20d-2db20cce12f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012717494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.4012717494
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2120577473
Short name T555
Test name
Test status
Simulation time 70736980 ps
CPU time 3.45 seconds
Started Aug 08 05:29:24 PM PDT 24
Finished Aug 08 05:29:27 PM PDT 24
Peak memory 208292 kb
Host smart-ada9e7fa-e561-4f39-9f7a-d27a2995a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120577473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2120577473
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3168583934
Short name T829
Test name
Test status
Simulation time 58021587 ps
CPU time 2.8 seconds
Started Aug 08 05:29:24 PM PDT 24
Finished Aug 08 05:29:27 PM PDT 24
Peak memory 207988 kb
Host smart-fefcb551-670a-4c19-827f-d4ed0270fc48
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168583934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3168583934
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2419217640
Short name T777
Test name
Test status
Simulation time 1192869390 ps
CPU time 10.42 seconds
Started Aug 08 05:29:21 PM PDT 24
Finished Aug 08 05:29:32 PM PDT 24
Peak memory 208156 kb
Host smart-be795c20-744f-492d-82cf-1cf42bfd384c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419217640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2419217640
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1435500864
Short name T398
Test name
Test status
Simulation time 1049108975 ps
CPU time 24.3 seconds
Started Aug 08 05:29:20 PM PDT 24
Finished Aug 08 05:29:45 PM PDT 24
Peak memory 208404 kb
Host smart-7d87dfcb-e7eb-4df7-a0cd-f0be6511b185
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435500864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1435500864
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1110095995
Short name T892
Test name
Test status
Simulation time 266935856 ps
CPU time 3.33 seconds
Started Aug 08 05:29:22 PM PDT 24
Finished Aug 08 05:29:25 PM PDT 24
Peak memory 209880 kb
Host smart-1f485de4-ffaa-4b2d-9f03-d8acdaa77a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110095995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1110095995
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1692753559
Short name T3
Test name
Test status
Simulation time 154923839 ps
CPU time 2.19 seconds
Started Aug 08 05:29:21 PM PDT 24
Finished Aug 08 05:29:23 PM PDT 24
Peak memory 206748 kb
Host smart-9fbafa98-ff51-4fee-b1ef-823aabdd0167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692753559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1692753559
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2586290238
Short name T793
Test name
Test status
Simulation time 89556170 ps
CPU time 4.28 seconds
Started Aug 08 05:29:24 PM PDT 24
Finished Aug 08 05:29:29 PM PDT 24
Peak memory 210108 kb
Host smart-f3e6b5c7-0cf9-4b88-baf4-e359c55fa0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586290238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2586290238
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.592019842
Short name T581
Test name
Test status
Simulation time 534229418 ps
CPU time 4.01 seconds
Started Aug 08 05:29:24 PM PDT 24
Finished Aug 08 05:29:28 PM PDT 24
Peak memory 210272 kb
Host smart-61fd18a9-d5da-419f-bd25-906f7b56c013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592019842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.592019842
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3546012094
Short name T823
Test name
Test status
Simulation time 76125642 ps
CPU time 0.82 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:29:42 PM PDT 24
Peak memory 206000 kb
Host smart-3be498f7-361f-42d2-aa68-30067261a6b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546012094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3546012094
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.4291468182
Short name T375
Test name
Test status
Simulation time 598277831 ps
CPU time 8.32 seconds
Started Aug 08 05:29:26 PM PDT 24
Finished Aug 08 05:29:34 PM PDT 24
Peak memory 214724 kb
Host smart-cc12343e-57a2-4347-b2f6-b5cd0d8cdb0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4291468182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.4291468182
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2204437311
Short name T37
Test name
Test status
Simulation time 225243547 ps
CPU time 4.91 seconds
Started Aug 08 05:29:32 PM PDT 24
Finished Aug 08 05:29:37 PM PDT 24
Peak memory 209780 kb
Host smart-479ea1f2-f61c-42c1-9574-648953a76194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204437311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2204437311
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2861202112
Short name T654
Test name
Test status
Simulation time 34482765 ps
CPU time 1.45 seconds
Started Aug 08 05:29:30 PM PDT 24
Finished Aug 08 05:29:32 PM PDT 24
Peak memory 207044 kb
Host smart-d8801023-b28e-4cb3-a7aa-03dd05926cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861202112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2861202112
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3023375735
Short name T94
Test name
Test status
Simulation time 253306360 ps
CPU time 3.33 seconds
Started Aug 08 05:29:34 PM PDT 24
Finished Aug 08 05:29:38 PM PDT 24
Peak memory 209760 kb
Host smart-ac2b60e6-ca5e-4fc2-9a23-6cee5bab9c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023375735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3023375735
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2651479869
Short name T466
Test name
Test status
Simulation time 30615824 ps
CPU time 1.85 seconds
Started Aug 08 05:29:29 PM PDT 24
Finished Aug 08 05:29:31 PM PDT 24
Peak memory 214284 kb
Host smart-c8265eb5-e836-43a3-9d44-452a99c54eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651479869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2651479869
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1773894179
Short name T808
Test name
Test status
Simulation time 1091465059 ps
CPU time 5.52 seconds
Started Aug 08 05:29:31 PM PDT 24
Finished Aug 08 05:29:36 PM PDT 24
Peak memory 222444 kb
Host smart-cdbcdeb5-9563-4313-823e-4cf806fbbf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773894179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1773894179
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2501850558
Short name T432
Test name
Test status
Simulation time 540166715 ps
CPU time 5.98 seconds
Started Aug 08 05:29:26 PM PDT 24
Finished Aug 08 05:29:32 PM PDT 24
Peak memory 210156 kb
Host smart-9fe12904-182e-4b43-ac01-88b143a04934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501850558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2501850558
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2854418865
Short name T728
Test name
Test status
Simulation time 412945321 ps
CPU time 4.78 seconds
Started Aug 08 05:29:26 PM PDT 24
Finished Aug 08 05:29:31 PM PDT 24
Peak memory 207332 kb
Host smart-a0164f8e-3ab8-4065-b569-d98e6ab2aebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854418865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2854418865
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2250207883
Short name T408
Test name
Test status
Simulation time 69973804 ps
CPU time 2.62 seconds
Started Aug 08 05:29:26 PM PDT 24
Finished Aug 08 05:29:29 PM PDT 24
Peak memory 208804 kb
Host smart-bae5759d-9ea8-4a30-a735-d8477c5b3f3e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250207883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2250207883
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1750834012
Short name T277
Test name
Test status
Simulation time 106811058 ps
CPU time 4.91 seconds
Started Aug 08 05:29:26 PM PDT 24
Finished Aug 08 05:29:31 PM PDT 24
Peak memory 209104 kb
Host smart-1d210114-be04-46fa-83df-3e0b525cbdb6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750834012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1750834012
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3672460210
Short name T896
Test name
Test status
Simulation time 172983893 ps
CPU time 6.33 seconds
Started Aug 08 05:29:18 PM PDT 24
Finished Aug 08 05:29:25 PM PDT 24
Peak memory 208988 kb
Host smart-80027025-33c1-4f14-ad63-4ae7f79b4fd7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672460210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3672460210
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1524694660
Short name T686
Test name
Test status
Simulation time 134077924 ps
CPU time 3.46 seconds
Started Aug 08 05:29:40 PM PDT 24
Finished Aug 08 05:29:44 PM PDT 24
Peak memory 214416 kb
Host smart-9d04c8ae-8340-47fa-bb41-e32b79bed4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524694660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1524694660
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1523308080
Short name T901
Test name
Test status
Simulation time 509057921 ps
CPU time 4.99 seconds
Started Aug 08 05:29:24 PM PDT 24
Finished Aug 08 05:29:29 PM PDT 24
Peak memory 206772 kb
Host smart-c7435a9b-6131-49c8-9931-b3d8425657e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523308080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1523308080
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1120950646
Short name T42
Test name
Test status
Simulation time 597242280 ps
CPU time 9.34 seconds
Started Aug 08 05:29:33 PM PDT 24
Finished Aug 08 05:29:42 PM PDT 24
Peak memory 222592 kb
Host smart-ee9b8b47-95bd-4635-a4e9-326030b0c852
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120950646 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1120950646
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2671879857
Short name T845
Test name
Test status
Simulation time 276110043 ps
CPU time 3.75 seconds
Started Aug 08 05:29:29 PM PDT 24
Finished Aug 08 05:29:33 PM PDT 24
Peak memory 218484 kb
Host smart-cb5871e8-3044-4293-bc3b-2408a51f91aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671879857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2671879857
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.134073172
Short name T629
Test name
Test status
Simulation time 119457025 ps
CPU time 2.05 seconds
Started Aug 08 05:29:29 PM PDT 24
Finished Aug 08 05:29:31 PM PDT 24
Peak memory 210300 kb
Host smart-c066bb7f-d559-44ee-ac1d-de6e4916ce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134073172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.134073172
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2026009366
Short name T865
Test name
Test status
Simulation time 12779077 ps
CPU time 0.77 seconds
Started Aug 08 05:29:29 PM PDT 24
Finished Aug 08 05:29:30 PM PDT 24
Peak memory 205940 kb
Host smart-a8b079ee-fb96-4fcc-887d-b8163d63d964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026009366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2026009366
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.59996629
Short name T235
Test name
Test status
Simulation time 84125400 ps
CPU time 4.55 seconds
Started Aug 08 05:29:34 PM PDT 24
Finished Aug 08 05:29:39 PM PDT 24
Peak memory 214360 kb
Host smart-2bcca62c-9076-488d-b53b-06071a50603a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59996629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.59996629
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.404153026
Short name T402
Test name
Test status
Simulation time 807326843 ps
CPU time 8.59 seconds
Started Aug 08 05:29:34 PM PDT 24
Finished Aug 08 05:29:42 PM PDT 24
Peak memory 220644 kb
Host smart-f180766f-f07b-4330-b94e-8cddcc0d4248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404153026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.404153026
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2825201143
Short name T786
Test name
Test status
Simulation time 57867082 ps
CPU time 2.18 seconds
Started Aug 08 05:29:33 PM PDT 24
Finished Aug 08 05:29:36 PM PDT 24
Peak memory 208416 kb
Host smart-c0f437b8-e46e-47ee-b586-5e51c28eefa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825201143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2825201143
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2198343078
Short name T265
Test name
Test status
Simulation time 108381111 ps
CPU time 2.07 seconds
Started Aug 08 05:29:35 PM PDT 24
Finished Aug 08 05:29:37 PM PDT 24
Peak memory 214516 kb
Host smart-c40089d0-4af3-4b56-8348-ecf67cfa48f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198343078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2198343078
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2518394502
Short name T850
Test name
Test status
Simulation time 40534537 ps
CPU time 2.16 seconds
Started Aug 08 05:29:31 PM PDT 24
Finished Aug 08 05:29:33 PM PDT 24
Peak memory 219808 kb
Host smart-8183998b-5a3d-4d81-bf45-4fa71c497463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518394502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2518394502
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.847925658
Short name T229
Test name
Test status
Simulation time 101525461 ps
CPU time 4.58 seconds
Started Aug 08 05:29:32 PM PDT 24
Finished Aug 08 05:29:36 PM PDT 24
Peak memory 209528 kb
Host smart-584bb8f0-725e-4228-969e-64c5605f70ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847925658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.847925658
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3105354371
Short name T249
Test name
Test status
Simulation time 121863068 ps
CPU time 4.23 seconds
Started Aug 08 05:29:30 PM PDT 24
Finished Aug 08 05:29:34 PM PDT 24
Peak memory 208600 kb
Host smart-a80a8ce1-de8b-47a5-bd6e-4f0ff0d0bb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105354371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3105354371
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.4130507051
Short name T425
Test name
Test status
Simulation time 245916740 ps
CPU time 3.54 seconds
Started Aug 08 05:29:41 PM PDT 24
Finished Aug 08 05:29:45 PM PDT 24
Peak memory 208892 kb
Host smart-8f2241d9-5573-4764-a8a5-a82e3eac853b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130507051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.4130507051
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2030437507
Short name T482
Test name
Test status
Simulation time 5895500988 ps
CPU time 38.14 seconds
Started Aug 08 05:29:34 PM PDT 24
Finished Aug 08 05:30:12 PM PDT 24
Peak memory 208456 kb
Host smart-67456f11-8401-4b73-96df-b192440e902c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030437507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2030437507
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3838681100
Short name T454
Test name
Test status
Simulation time 256792862 ps
CPU time 4.14 seconds
Started Aug 08 05:29:31 PM PDT 24
Finished Aug 08 05:29:35 PM PDT 24
Peak memory 208116 kb
Host smart-96216ed2-adda-4c45-b4df-2c732f8db64e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838681100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3838681100
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3411255531
Short name T509
Test name
Test status
Simulation time 152107022 ps
CPU time 2.08 seconds
Started Aug 08 05:29:30 PM PDT 24
Finished Aug 08 05:29:33 PM PDT 24
Peak memory 215648 kb
Host smart-820bd4f2-4d64-4a2a-8bc3-ccc730ec3383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411255531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3411255531
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.738619799
Short name T529
Test name
Test status
Simulation time 708568995 ps
CPU time 5.11 seconds
Started Aug 08 05:29:29 PM PDT 24
Finished Aug 08 05:29:35 PM PDT 24
Peak memory 208868 kb
Host smart-5e3db997-c6ca-4e15-a08b-d7e14a6c0c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738619799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.738619799
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.4034801698
Short name T775
Test name
Test status
Simulation time 544592431 ps
CPU time 16.56 seconds
Started Aug 08 05:29:34 PM PDT 24
Finished Aug 08 05:29:51 PM PDT 24
Peak memory 215444 kb
Host smart-b8d441f2-3ad0-4691-a2a7-e637a4d723de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034801698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.4034801698
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.672514686
Short name T873
Test name
Test status
Simulation time 1167405212 ps
CPU time 22.73 seconds
Started Aug 08 05:29:34 PM PDT 24
Finished Aug 08 05:29:57 PM PDT 24
Peak memory 218276 kb
Host smart-0289042a-7b09-4af4-9559-51468b6edc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672514686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.672514686
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1472924782
Short name T171
Test name
Test status
Simulation time 278312284 ps
CPU time 2.98 seconds
Started Aug 08 05:29:43 PM PDT 24
Finished Aug 08 05:29:46 PM PDT 24
Peak memory 210084 kb
Host smart-73615d0c-512a-408e-be52-0b7db7f517a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472924782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1472924782
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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