Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	17	32	65.31

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	16	19	54.29	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	42	1			T14	1		T45	2		T46	3
auto[OpGenId]	14	1			T60	1		T6	1		T205	1
auto[OpGenSwOut]	21	1			T46	1		T192	1		T56	1
auto[OpGenHwOut]	23	1			T20	1		T40	1		T4	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1791	1			T2	3		T44	1		T26	1
auto[StInit]	98	1			T2	1		T14	1		T44	1
auto[StCreatorRootKey]	71	1			T2	2		T44	1		T54	1
auto[StOwnerIntKey]	43	1			T13	1		T35	1		T45	1
auto[StOwnerKey]	43	1			T38	1		T45	1		T61	1
auto[StDisabled]	551	1			T2	4		T13	4		T44	14
auto[StInvalid]	50	1			T86	1		T62	1		T102	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3643

1

T1

1

T2

11

T3

1

auto[1]

100

1

T14

1

T20

1

T45

2

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1781	1			T2	3		T44	1		T26	1
auto[StReset]	auto[1]	10	1			T45	1		T108	1		T49	1
auto[StInit]	auto[0]	54	1			T2	1		T44	1		T39	1
auto[StInit]	auto[1]	44	1			T14	1		T46	2		T192	1
auto[StCreatorRootKey]	auto[0]	52	1			T2	2		T44	1		T54	1
auto[StCreatorRootKey]	auto[1]	19	1			T46	2		T56	1		T108	1
auto[StOwnerIntKey]	auto[0]	33	1			T13	1		T35	1		T59	1
auto[StOwnerIntKey]	auto[1]	10	1			T45	1		T60	1		T108	1
auto[StOwnerKey]	auto[0]	37	1			T38	1		T45	1		T61	1
auto[StOwnerKey]	auto[1]	6	1			T4	1		T206	1		T207	1
auto[StDisabled]	auto[0]	540	1			T2	4		T13	4		T44	14
auto[StDisabled]	auto[1]	11	1			T20	1		T68	1		T47	1
auto[StInvalid]	auto[0]	50	1			T86	1		T62	1		T102	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	16	19	54.29	16

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	10	1			T45	1		T108	1		T49	1
auto[StInit]	auto[OpAdvance]	17	1			T14	1		T46	1		T208	1
auto[StInit]	auto[OpGenId]	7	1			T6	1		T209	1		T41	1
auto[StInit]	auto[OpGenSwOut]	10	1			T46	1		T192	1		T210	1
auto[StInit]	auto[OpGenHwOut]	10	1			T40	1		T5	1		T6	2
auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T46	2		T173	1		T145	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T211	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T56	1		T212	1		T213	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	5	1			T108	1		T214	1		T215	1
auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T45	1		T216	1		T217	1
auto[StOwnerIntKey]	auto[OpGenId]	3	1			T60	1		T218	1		T219	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T108	1		T220	1		-	-
auto[StOwnerKey]	auto[OpGenId]	1	1			T221	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T206	1		T207	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	3	1			T4	1		T171	1		T222	1
auto[StDisabled]	auto[OpAdvance]	2	1			T47	1		T223	1		-	-
auto[StDisabled]	auto[OpGenId]	2	1			T205	1		T224	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T68	1		T225	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	5	1			T20	1		T226	1		T224	2