Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11916

1

T1

7

T2

27

T3

8

auto[Attestation]

8544

1

T1

9

T2

24

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2973	1			T1	4		T2	9		T3	2
auto[Aes]	3710	1			T1	1		T2	5		T3	2
auto[Kmac]	3627	1			T1	3		T2	7		T3	3
auto[Otbn]	3627	1			T1	4		T2	9		T3	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8424	1			T1	8		T2	37		T3	8
auto[OpGenId]	6523	1			T1	4		T2	21		T3	3
auto[OpGenSwOut]	6599	1			T1	7		T2	25		T3	5
auto[OpGenHwOut]	7338	1			T1	5		T2	5		T3	3
auto[OpDisable]	156	1			T44	4		T48	1		T45	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11536

1

T1

10

T2

41

T3

6

auto[OpDoneFail]

17504

1

T1

14

T2

47

T3

13

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6866	1			T1	1		T2	12		T3	2
auto[StInit]	4179	1			T1	1		T2	20		T3	6
auto[StCreatorRootKey]	3407	1			T1	1		T2	12		T3	2
auto[StOwnerIntKey]	3067	1			T1	5		T2	8		T3	1
auto[StOwnerKey]	2652	1			T1	3		T2	8		T3	1
auto[StDisabled]	8869	1			T1	13		T2	28		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	372	1			T34	1		T44	3		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	111	1			T2	1		T3	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	84	1			T2	1		T87	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	98	1			T1	1		T35	1		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	71	1			T44	1		T126	1		T45	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	242	1			T1	1		T13	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	327	1			T3	1		T44	2		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	112	1			T16	1		T18	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	107	1			T122	1		T193	1		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	88	1			T18	1		T44	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	78	1			T2	1		T193	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	251	1			T2	1		T13	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	334	1			T2	1		T34	3		T44	8
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	105	1			T3	1		T13	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	78	1			T18	1		T44	2		T122	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T13	1		T19	1		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	58	1			T44	1		T196	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	226	1			T2	1		T13	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	373	1			T2	2		T34	2		T44	5
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	133	1			T2	1		T13	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T18	1		T44	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T44	1		T195	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	83	1			T1	1		T88	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	258	1			T2	3		T16	1		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	85	1			T44	5		T45	3		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T2	1		T34	1		T23	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	84	1			T2	1		T44	1		T122	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	77	1			T44	1		T124	1		T193	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T2	1		T38	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	264	1			T1	1		T2	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	103	1			T44	4		T45	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	131	1			T3	1		T123	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	92	1			T34	1		T44	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	76	1			T124	1		T67	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	63	1			T44	1		T198	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	261	1			T2	1		T13	1		T44	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	97	1			T44	4		T45	3		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	105	1			T2	2		T13	1		T44	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	108	1			T44	2		T23	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	98	1			T1	1		T2	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	73	1			T2	1		T44	1		T45	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	243	1			T2	1		T3	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	103	1			T44	2		T46	1		T186	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	111	1			T44	1		T123	1		T23	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	74	1			T2	1		T13	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	81	1			T13	1		T44	3		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	45	1			T124	1		T199	1		T45	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	246	1			T1	2		T2	2		T88	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	279	1			T19	1		T34	1		T44	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	89	1			T2	1		T18	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T2	1		T123	1		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T44	1		T23	1		T125	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T13	1		T88	1		T44	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	197	1			T3	1		T16	1		T44	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	475	1			T2	1		T19	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	142	1			T15	1		T18	1		T44	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	110	1			T13	2		T15	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	106	1			T19	1		T34	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	91	1			T15	1		T139	1		T44	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	305	1			T2	1		T15	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	457	1			T44	5		T37	1		T125	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	117	1			T3	1		T13	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T139	1		T44	1		T123	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T13	2		T34	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	91	1			T1	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	341	1			T13	1		T16	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	406	1			T19	1		T44	5		T126	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	132	1			T19	1		T44	1		T123	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T3	1		T139	1		T44	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	92	1			T18	1		T19	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	90	1			T13	2		T139	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	324	1			T13	2		T44	2		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T44	4		T45	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	110	1			T2	1		T123	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	74	1			T45	1		T46	1		T52	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	62	1			T45	3		T46	1		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T88	1		T44	2		T123	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	194	1			T1	1		T13	1		T44	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	66	1			T44	2		T45	1		T186	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	114	1			T19	1		T44	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	117	1			T88	1		T44	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	108	1			T15	1		T34	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	78	1			T196	1		T83	1		T202	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	309	1			T1	1		T13	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	64	1			T44	2		T45	2		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	138	1			T18	1		T44	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	113	1			T13	1		T19	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	119	1			T19	1		T87	2		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	98	1			T203	1		T204	1		T46	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	297	1			T1	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	71	1			T44	2		T186	2		T68	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	121	1			T16	1		T44	4		T123	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	102	1			T19	1		T185	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	114	1			T34	1		T44	1		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	99	1			T13	1		T139	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	304	1			T1	1		T16	1		T87	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	237	1			T2	1		T87	1		T44	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	741	1			T1	2		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	250	1			T2	1		T44	1		T122	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	713	1			T2	1		T3	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	193	1			T13	1		T18	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	682	1			T2	2		T3	1		T13	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	228	1			T1	1		T88	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	784	1			T2	6		T13	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	190	1			T2	2		T44	2		T122	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	471	1			T1	1		T2	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	212	1			T34	1		T44	2		T124	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	514	1			T2	1		T3	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	258	1			T1	1		T2	2		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	466	1			T2	3		T3	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	185	1			T2	1		T13	2		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	475	1			T1	2		T2	2		T88	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	187	1			T2	1		T13	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	586	1			T2	1		T3	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	291	1			T13	2		T15	2		T19	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	938	1			T2	2		T15	4		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	268	1			T1	1		T13	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	931	1			T3	1		T13	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	262	1			T3	1		T13	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	882	1			T13	2		T19	2		T44	9
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	174	1			T88	1		T44	2		T123	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	387	1			T1	1		T2	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	288	1			T15	1		T34	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	504	1			T1	1		T13	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	306	1			T13	1		T19	2		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	523	1			T1	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	299	1			T13	1		T19	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	512	1			T1	1		T16	2		T87	1