Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35463

1

T1

29

T2

104

T3

23

auto[1]

277

1

T16

6

T122

8

T140

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	35475	1			T1	29		T2	104		T3	23
auto[134217728:268435455]	6	1			T122	2		T140	2		T256	1
auto[268435456:402653183]	6	1			T130	1		T239	1		T398	1
auto[402653184:536870911]	11	1			T239	1		T383	2		T266	1
auto[536870912:671088639]	9	1			T179	1		T264	1		T106	1
auto[671088640:805306367]	11	1			T256	1		T239	2		T266	1
auto[805306368:939524095]	9	1			T383	2		T291	1		T266	1
auto[939524096:1073741823]	9	1			T256	1		T315	1		T350	1
auto[1073741824:1207959551]	5	1			T383	1		T291	1		T398	1
auto[1207959552:1342177279]	8	1			T227	1		T129	1		T179	1
auto[1342177280:1476395007]	6	1			T122	1		T227	2		T375	1
auto[1476395008:1610612735]	8	1			T227	2		T375	1		T266	1
auto[1610612736:1744830463]	6	1			T140	2		T130	1		T256	1
auto[1744830464:1879048191]	4	1			T130	1		T315	1		T257	1
auto[1879048192:2013265919]	13	1			T16	1		T128	1		T129	1
auto[2013265920:2147483647]	5	1			T227	1		T384	1		T387	1
auto[2147483648:2281701375]	12	1			T16	1		T227	1		T256	1
auto[2281701376:2415919103]	13	1			T129	1		T179	1		T264	1
auto[2415919104:2550136831]	8	1			T375	2		T106	2		T324	1
auto[2550136832:2684354559]	6	1			T122	1		T140	1		T128	1
auto[2684354560:2818572287]	6	1			T227	1		T386	1		T387	2
auto[2818572288:2952790015]	5	1			T122	1		T140	1		T256	1
auto[2952790016:3087007743]	15	1			T16	1		T130	2		T256	1
auto[3087007744:3221225471]	11	1			T129	1		T239	1		T291	1
auto[3221225472:3355443199]	11	1			T256	1		T266	1		T315	2
auto[3355443200:3489660927]	7	1			T375	1		T239	1		T315	1
auto[3489660928:3623878655]	8	1			T16	1		T140	2		T227	1
auto[3623878656:3758096383]	12	1			T227	1		T129	1		T130	1
auto[3758096384:3892314111]	8	1			T16	1		T140	1		T239	1
auto[3892314112:4026531839]	9	1			T130	1		T291	1		T266	2
auto[4026531840:4160749567]	10	1			T122	1		T256	1		T264	2
auto[4160749568:4294967295]	8	1			T16	1		T140	1		T375	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	35463	1			T1	29		T2	104		T3	23
auto[0:134217727]	auto[1]	12	1			T122	2		T129	1		T256	1
auto[134217728:268435455]	auto[1]	6	1			T122	2		T140	2		T256	1
auto[268435456:402653183]	auto[1]	6	1			T130	1		T239	1		T398	1
auto[402653184:536870911]	auto[1]	11	1			T239	1		T383	2		T266	1
auto[536870912:671088639]	auto[1]	9	1			T179	1		T264	1		T106	1
auto[671088640:805306367]	auto[1]	11	1			T256	1		T239	2		T266	1
auto[805306368:939524095]	auto[1]	9	1			T383	2		T291	1		T266	1
auto[939524096:1073741823]	auto[1]	9	1			T256	1		T315	1		T350	1
auto[1073741824:1207959551]	auto[1]	5	1			T383	1		T291	1		T398	1
auto[1207959552:1342177279]	auto[1]	8	1			T227	1		T129	1		T179	1
auto[1342177280:1476395007]	auto[1]	6	1			T122	1		T227	2		T375	1
auto[1476395008:1610612735]	auto[1]	8	1			T227	2		T375	1		T266	1
auto[1610612736:1744830463]	auto[1]	6	1			T140	2		T130	1		T256	1
auto[1744830464:1879048191]	auto[1]	4	1			T130	1		T315	1		T257	1
auto[1879048192:2013265919]	auto[1]	13	1			T16	1		T128	1		T129	1
auto[2013265920:2147483647]	auto[1]	5	1			T227	1		T384	1		T387	1
auto[2147483648:2281701375]	auto[1]	12	1			T16	1		T227	1		T256	1
auto[2281701376:2415919103]	auto[1]	13	1			T129	1		T179	1		T264	1
auto[2415919104:2550136831]	auto[1]	8	1			T375	2		T106	2		T324	1
auto[2550136832:2684354559]	auto[1]	6	1			T122	1		T140	1		T128	1
auto[2684354560:2818572287]	auto[1]	6	1			T227	1		T386	1		T387	2
auto[2818572288:2952790015]	auto[1]	5	1			T122	1		T140	1		T256	1
auto[2952790016:3087007743]	auto[1]	15	1			T16	1		T130	2		T256	1
auto[3087007744:3221225471]	auto[1]	11	1			T129	1		T239	1		T291	1
auto[3221225472:3355443199]	auto[1]	11	1			T256	1		T266	1		T315	2
auto[3355443200:3489660927]	auto[1]	7	1			T375	1		T239	1		T315	1
auto[3489660928:3623878655]	auto[1]	8	1			T16	1		T140	2		T227	1
auto[3623878656:3758096383]	auto[1]	12	1			T227	1		T129	1		T130	1
auto[3758096384:3892314111]	auto[1]	8	1			T16	1		T140	1		T239	1
auto[3892314112:4026531839]	auto[1]	9	1			T130	1		T291	1		T266	2
auto[4026531840:4160749567]	auto[1]	10	1			T122	1		T256	1		T264	2
auto[4160749568:4294967295]	auto[1]	8	1			T16	1		T140	1		T375	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1653

1

T1

1

T13

1

T16

1

auto[1]

1863

1

T1

2

T2

3

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T19	1		T44	4		T45	1
auto[134217728:268435455]	103	1			T18	1		T44	2		T24	1
auto[268435456:402653183]	106	1			T44	1		T48	1		T46	1
auto[402653184:536870911]	115	1			T44	3		T195	1		T45	1
auto[536870912:671088639]	118	1			T87	1		T44	2		T122	1
auto[671088640:805306367]	109	1			T87	1		T124	1		T126	1
auto[805306368:939524095]	104	1			T13	1		T44	4		T36	2
auto[939524096:1073741823]	116	1			T1	1		T44	1		T195	1
auto[1073741824:1207959551]	110	1			T37	1		T24	1		T196	1
auto[1207959552:1342177279]	111	1			T3	1		T87	1		T44	1
auto[1342177280:1476395007]	104	1			T44	2		T67	1		T95	1
auto[1476395008:1610612735]	122	1			T139	2		T44	2		T123	1
auto[1610612736:1744830463]	111	1			T44	1		T123	1		T48	1
auto[1744830464:1879048191]	121	1			T19	1		T122	1		T36	1
auto[1879048192:2013265919]	109	1			T16	2		T44	2		T36	1
auto[2013265920:2147483647]	113	1			T34	1		T24	1		T45	2
auto[2147483648:2281701375]	93	1			T13	1		T195	1		T45	2
auto[2281701376:2415919103]	116	1			T44	1		T122	1		T125	1
auto[2415919104:2550136831]	102	1			T2	1		T44	2		T126	1
auto[2550136832:2684354559]	97	1			T44	1		T37	1		T23	1
auto[2684354560:2818572287]	112	1			T13	1		T88	1		T44	2
auto[2818572288:2952790015]	110	1			T13	1		T34	1		T88	1
auto[2952790016:3087007743]	121	1			T1	1		T13	1		T44	2
auto[3087007744:3221225471]	106	1			T13	1		T16	1		T139	1
auto[3221225472:3355443199]	113	1			T2	2		T19	1		T67	1
auto[3355443200:3489660927]	93	1			T44	1		T199	1		T45	1
auto[3489660928:3623878655]	113	1			T44	2		T45	2		T46	3
auto[3623878656:3758096383]	109	1			T44	3		T122	1		T36	1
auto[3758096384:3892314111]	113	1			T3	1		T16	1		T87	1
auto[3892314112:4026531839]	95	1			T1	1		T16	1		T20	1
auto[4026531840:4160749567]	123	1			T44	1		T199	2		T95	1
auto[4160749568:4294967295]	126	1			T3	1		T18	1		T44	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	41	1			T19	1		T44	2		T56	1
auto[0:134217727]	auto[1]	61	1			T44	2		T45	1		T46	2
auto[134217728:268435455]	auto[0]	55	1			T18	1		T44	1		T24	1
auto[134217728:268435455]	auto[1]	48	1			T44	1		T140	1		T186	1
auto[268435456:402653183]	auto[0]	44	1			T48	1		T185	1		T69	2
auto[268435456:402653183]	auto[1]	62	1			T44	1		T46	1		T64	1
auto[402653184:536870911]	auto[0]	60	1			T44	2		T195	1		T46	1
auto[402653184:536870911]	auto[1]	55	1			T44	1		T45	1		T46	1
auto[536870912:671088639]	auto[0]	58	1			T87	1		T44	1		T122	1
auto[536870912:671088639]	auto[1]	60	1			T44	1		T45	1		T46	2
auto[671088640:805306367]	auto[0]	51	1			T126	1		T61	1		T46	1
auto[671088640:805306367]	auto[1]	58	1			T87	1		T124	1		T45	1
auto[805306368:939524095]	auto[0]	55	1			T44	4		T36	1		T46	1
auto[805306368:939524095]	auto[1]	49	1			T13	1		T36	1		T46	3
auto[939524096:1073741823]	auto[0]	59	1			T44	1		T45	2		T46	1
auto[939524096:1073741823]	auto[1]	57	1			T1	1		T195	1		T194	1
auto[1073741824:1207959551]	auto[0]	59	1			T37	1		T199	1		T45	1
auto[1073741824:1207959551]	auto[1]	51	1			T24	1		T196	1		T46	1
auto[1207959552:1342177279]	auto[0]	46	1			T44	1		T195	1		T199	1
auto[1207959552:1342177279]	auto[1]	65	1			T3	1		T87	1		T196	1
auto[1342177280:1476395007]	auto[0]	51	1			T44	1		T67	1		T46	2
auto[1342177280:1476395007]	auto[1]	53	1			T44	1		T95	1		T46	1
auto[1476395008:1610612735]	auto[0]	56	1			T139	1		T44	2		T195	1
auto[1476395008:1610612735]	auto[1]	66	1			T139	1		T123	1		T45	2
auto[1610612736:1744830463]	auto[0]	45	1			T44	1		T48	1		T45	1
auto[1610612736:1744830463]	auto[1]	66	1			T123	1		T46	4		T185	1
auto[1744830464:1879048191]	auto[0]	57	1			T36	1		T86	1		T127	2
auto[1744830464:1879048191]	auto[1]	64	1			T19	1		T122	1		T53	1
auto[1879048192:2013265919]	auto[0]	48	1			T16	1		T36	1		T95	1
auto[1879048192:2013265919]	auto[1]	61	1			T16	1		T44	2		T46	1
auto[2013265920:2147483647]	auto[0]	49	1			T24	1		T45	1		T46	2
auto[2013265920:2147483647]	auto[1]	64	1			T34	1		T45	1		T25	2
auto[2147483648:2281701375]	auto[0]	38	1			T13	1		T195	1		T45	1
auto[2147483648:2281701375]	auto[1]	55	1			T45	1		T46	1		T140	1
auto[2281701376:2415919103]	auto[0]	46	1			T44	1		T125	1		T86	1
auto[2281701376:2415919103]	auto[1]	70	1			T122	1		T126	1		T48	1
auto[2415919104:2550136831]	auto[0]	50	1			T44	1		T126	1		T67	1
auto[2415919104:2550136831]	auto[1]	52	1			T2	1		T44	1		T45	1
auto[2550136832:2684354559]	auto[0]	47	1			T44	1		T37	1		T45	1
auto[2550136832:2684354559]	auto[1]	50	1			T23	1		T126	1		T195	1
auto[2684354560:2818572287]	auto[0]	62	1			T88	1		T44	1		T67	1
auto[2684354560:2818572287]	auto[1]	50	1			T13	1		T44	1		T124	1
auto[2818572288:2952790015]	auto[0]	55	1			T44	1		T45	1		T86	1
auto[2818572288:2952790015]	auto[1]	55	1			T13	1		T34	1		T88	1
auto[2952790016:3087007743]	auto[0]	47	1			T1	1		T44	1		T46	1
auto[2952790016:3087007743]	auto[1]	74	1			T13	1		T44	1		T62	1
auto[3087007744:3221225471]	auto[0]	53	1			T139	1		T44	1		T196	1
auto[3087007744:3221225471]	auto[1]	53	1			T13	1		T16	1		T44	1
auto[3221225472:3355443199]	auto[0]	49	1			T67	1		T45	1		T53	1
auto[3221225472:3355443199]	auto[1]	64	1			T2	2		T19	1		T45	5
auto[3355443200:3489660927]	auto[0]	41	1			T44	1		T199	1		T45	1
auto[3355443200:3489660927]	auto[1]	52	1			T185	1		T227	1		T129	1
auto[3489660928:3623878655]	auto[0]	60	1			T44	1		T45	1		T46	3
auto[3489660928:3623878655]	auto[1]	53	1			T44	1		T45	1		T316	2
auto[3623878656:3758096383]	auto[0]	51	1			T44	1		T36	1		T127	1
auto[3623878656:3758096383]	auto[1]	58	1			T44	2		T122	1		T45	2
auto[3758096384:3892314111]	auto[0]	47	1			T46	1		T51	1		T192	1
auto[3758096384:3892314111]	auto[1]	66	1			T3	1		T16	1		T87	1
auto[3892314112:4026531839]	auto[0]	45	1			T45	1		T25	1		T275	1
auto[3892314112:4026531839]	auto[1]	50	1			T1	1		T16	1		T20	1
auto[4026531840:4160749567]	auto[0]	67	1			T44	1		T46	1		T80	1
auto[4026531840:4160749567]	auto[1]	56	1			T199	2		T95	1		T64	1
auto[4160749568:4294967295]	auto[0]	61	1			T60	1		T65	1		T119	2
auto[4160749568:4294967295]	auto[1]	65	1			T3	1		T18	1		T44	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1633

1

T1

1

T13

2

T16

1

auto[1]

1882

1

T1

2

T2

3

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T16	1		T44	3		T122	1
auto[134217728:268435455]	111	1			T87	1		T195	1		T20	1
auto[268435456:402653183]	81	1			T44	2		T45	1		T46	1
auto[402653184:536870911]	111	1			T16	1		T23	1		T46	2
auto[536870912:671088639]	148	1			T139	1		T44	1		T195	1
auto[671088640:805306367]	104	1			T18	1		T24	1		T196	1
auto[805306368:939524095]	111	1			T13	1		T44	3		T122	2
auto[939524096:1073741823]	123	1			T44	3		T24	1		T45	2
auto[1073741824:1207959551]	108	1			T2	1		T44	2		T45	1
auto[1207959552:1342177279]	115	1			T1	1		T13	1		T139	1
auto[1342177280:1476395007]	108	1			T44	1		T123	1		T23	1
auto[1476395008:1610612735]	98	1			T34	1		T44	2		T126	1
auto[1610612736:1744830463]	118	1			T3	1		T13	1		T87	1
auto[1744830464:1879048191]	110	1			T16	1		T44	1		T37	1
auto[1879048192:2013265919]	114	1			T1	1		T44	1		T36	1
auto[2013265920:2147483647]	96	1			T195	1		T95	1		T46	1
auto[2147483648:2281701375]	96	1			T13	2		T87	1		T44	2
auto[2281701376:2415919103]	104	1			T44	3		T199	1		T45	1
auto[2415919104:2550136831]	120	1			T3	1		T44	3		T45	3
auto[2550136832:2684354559]	108	1			T19	1		T126	1		T67	1
auto[2684354560:2818572287]	113	1			T34	1		T44	1		T124	1
auto[2818572288:2952790015]	105	1			T88	1		T195	1		T67	1
auto[2952790016:3087007743]	112	1			T44	2		T36	1		T24	1
auto[3087007744:3221225471]	109	1			T88	1		T61	1		T46	1
auto[3221225472:3355443199]	123	1			T3	1		T19	1		T44	2
auto[3355443200:3489660927]	94	1			T2	1		T44	3		T45	1
auto[3489660928:3623878655]	102	1			T2	1		T44	1		T36	1
auto[3623878656:3758096383]	102	1			T16	1		T139	1		T44	2
auto[3758096384:3892314111]	125	1			T87	1		T45	2		T46	1
auto[3892314112:4026531839]	97	1			T1	1		T13	1		T19	1
auto[4026531840:4160749567]	122	1			T44	1		T122	1		T126	1
auto[4160749568:4294967295]	113	1			T16	1		T18	1		T34	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	61	1			T44	1		T122	1		T67	1
auto[0:134217727]	auto[1]	53	1			T16	1		T44	2		T37	1
auto[134217728:268435455]	auto[0]	53	1			T45	1		T185	1		T230	1
auto[134217728:268435455]	auto[1]	58	1			T87	1		T195	1		T20	1
auto[268435456:402653183]	auto[0]	34	1			T44	1		T51	1		T192	1
auto[268435456:402653183]	auto[1]	47	1			T44	1		T45	1		T46	1
auto[402653184:536870911]	auto[0]	44	1			T23	1		T46	1		T140	1
auto[402653184:536870911]	auto[1]	67	1			T16	1		T46	1		T62	1
auto[536870912:671088639]	auto[0]	61	1			T139	1		T44	1		T45	1
auto[536870912:671088639]	auto[1]	87	1			T195	1		T20	1		T95	1
auto[671088640:805306367]	auto[0]	55	1			T18	1		T24	1		T199	1
auto[671088640:805306367]	auto[1]	49	1			T196	1		T62	1		T237	1
auto[805306368:939524095]	auto[0]	53	1			T44	2		T122	1		T46	2
auto[805306368:939524095]	auto[1]	58	1			T13	1		T44	1		T122	1
auto[939524096:1073741823]	auto[0]	57	1			T44	2		T45	1		T46	1
auto[939524096:1073741823]	auto[1]	66	1			T44	1		T24	1		T45	1
auto[1073741824:1207959551]	auto[0]	45	1			T44	1		T45	1		T46	1
auto[1073741824:1207959551]	auto[1]	63	1			T2	1		T44	1		T46	2
auto[1207959552:1342177279]	auto[0]	53	1			T1	1		T44	1		T37	1
auto[1207959552:1342177279]	auto[1]	62	1			T13	1		T139	1		T123	1
auto[1342177280:1476395007]	auto[0]	55	1			T44	1		T24	1		T196	1
auto[1342177280:1476395007]	auto[1]	53	1			T123	1		T23	1		T196	1
auto[1476395008:1610612735]	auto[0]	40	1			T44	2		T126	1		T45	1
auto[1476395008:1610612735]	auto[1]	58	1			T34	1		T194	1		T95	1
auto[1610612736:1744830463]	auto[0]	46	1			T44	1		T36	1		T45	1
auto[1610612736:1744830463]	auto[1]	72	1			T3	1		T13	1		T87	1
auto[1744830464:1879048191]	auto[0]	53	1			T16	1		T37	1		T59	1
auto[1744830464:1879048191]	auto[1]	57	1			T44	1		T23	1		T45	1
auto[1879048192:2013265919]	auto[0]	48	1			T36	1		T45	3		T46	2
auto[1879048192:2013265919]	auto[1]	66	1			T1	1		T44	1		T196	1
auto[2013265920:2147483647]	auto[0]	46	1			T56	1		T60	1		T275	1
auto[2013265920:2147483647]	auto[1]	50	1			T195	1		T95	1		T46	1
auto[2147483648:2281701375]	auto[0]	41	1			T13	2		T87	1		T44	1
auto[2147483648:2281701375]	auto[1]	55	1			T44	1		T124	1		T199	1
auto[2281701376:2415919103]	auto[0]	51	1			T44	1		T199	1		T61	1
auto[2281701376:2415919103]	auto[1]	53	1			T44	2		T45	1		T401	1
auto[2415919104:2550136831]	auto[0]	58	1			T44	2		T45	2		T46	1
auto[2415919104:2550136831]	auto[1]	62	1			T3	1		T44	1		T45	1
auto[2550136832:2684354559]	auto[0]	58	1			T126	1		T67	1		T46	1
auto[2550136832:2684354559]	auto[1]	50	1			T19	1		T45	1		T62	1
auto[2684354560:2818572287]	auto[0]	51	1			T195	1		T80	1		T64	1
auto[2684354560:2818572287]	auto[1]	62	1			T34	1		T44	1		T124	1
auto[2818572288:2952790015]	auto[0]	40	1			T195	1		T46	1		T127	1
auto[2818572288:2952790015]	auto[1]	65	1			T88	1		T67	1		T95	1
auto[2952790016:3087007743]	auto[0]	57	1			T44	1		T36	1		T45	1
auto[2952790016:3087007743]	auto[1]	55	1			T44	1		T24	1		T118	1
auto[3087007744:3221225471]	auto[0]	48	1			T88	1		T46	1		T242	1
auto[3087007744:3221225471]	auto[1]	61	1			T61	1		T64	1		T275	1
auto[3221225472:3355443199]	auto[0]	61	1			T44	1		T36	1		T48	1
auto[3221225472:3355443199]	auto[1]	62	1			T3	1		T19	1		T44	1
auto[3355443200:3489660927]	auto[0]	39	1			T44	2		T45	1		T51	1
auto[3355443200:3489660927]	auto[1]	55	1			T2	1		T44	1		T64	2
auto[3489660928:3623878655]	auto[0]	45	1			T44	1		T36	1		T126	1
auto[3489660928:3623878655]	auto[1]	57	1			T2	1		T199	1		T45	3
auto[3623878656:3758096383]	auto[0]	49	1			T44	2		T25	1		T127	1
auto[3623878656:3758096383]	auto[1]	53	1			T16	1		T139	1		T67	1
auto[3758096384:3892314111]	auto[0]	63	1			T45	1		T86	1		T118	1
auto[3758096384:3892314111]	auto[1]	62	1			T87	1		T45	1		T46	1
auto[3892314112:4026531839]	auto[0]	54	1			T44	2		T67	1		T199	1
auto[3892314112:4026531839]	auto[1]	43	1			T1	1		T13	1		T19	1
auto[4026531840:4160749567]	auto[0]	65	1			T195	1		T45	1		T46	1
auto[4026531840:4160749567]	auto[1]	57	1			T44	1		T122	1		T126	1
auto[4160749568:4294967295]	auto[0]	49	1			T18	1		T34	1		T44	1
auto[4160749568:4294967295]	auto[1]	64	1			T16	1		T44	1		T48	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1651

1

T1

1

T3

1

T13

2

auto[1]

1864

1

T1

2

T2

3

T3

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T44	1		T45	1		T140	1
auto[134217728:268435455]	101	1			T18	1		T87	1		T44	1
auto[268435456:402653183]	110	1			T122	1		T48	1		T45	1
auto[402653184:536870911]	105	1			T13	3		T87	2		T44	2
auto[536870912:671088639]	106	1			T16	1		T44	1		T123	1
auto[671088640:805306367]	117	1			T44	1		T36	1		T123	1
auto[805306368:939524095]	100	1			T16	1		T44	2		T67	1
auto[939524096:1073741823]	113	1			T87	1		T88	1		T44	3
auto[1073741824:1207959551]	115	1			T44	2		T126	1		T24	1
auto[1207959552:1342177279]	107	1			T139	1		T199	1		T25	1
auto[1342177280:1476395007]	129	1			T44	2		T122	1		T36	1
auto[1476395008:1610612735]	117	1			T2	1		T48	1		T45	1
auto[1610612736:1744830463]	125	1			T13	1		T19	1		T34	2
auto[1744830464:1879048191]	117	1			T1	1		T139	1		T122	1
auto[1879048192:2013265919]	109	1			T3	1		T44	2		T124	1
auto[2013265920:2147483647]	105	1			T44	2		T122	1		T45	1
auto[2147483648:2281701375]	126	1			T18	1		T44	2		T124	1
auto[2281701376:2415919103]	101	1			T16	1		T19	1		T44	3
auto[2415919104:2550136831]	100	1			T139	1		T44	1		T126	1
auto[2550136832:2684354559]	118	1			T2	1		T44	1		T126	1
auto[2684354560:2818572287]	100	1			T1	1		T124	1		T37	1
auto[2818572288:2952790015]	107	1			T13	1		T16	1		T44	1
auto[2952790016:3087007743]	116	1			T1	1		T34	1		T44	3
auto[3087007744:3221225471]	110	1			T3	1		T125	1		T45	2
auto[3221225472:3355443199]	103	1			T19	1		T88	1		T44	1
auto[3355443200:3489660927]	111	1			T13	1		T44	3		T122	1
auto[3489660928:3623878655]	109	1			T44	2		T195	2		T80	1
auto[3623878656:3758096383]	79	1			T44	2		T23	1		T48	1
auto[3758096384:3892314111]	115	1			T48	1		T95	1		T45	7
auto[3892314112:4026531839]	106	1			T2	1		T3	1		T44	2
auto[4026531840:4160749567]	117	1			T16	1		T44	3		T20	1
auto[4160749568:4294967295]	117	1			T44	2		T24	1		T20	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T44	1		T45	1		T59	1
auto[0:134217727]	auto[1]	50	1			T140	1		T59	1		T129	1
auto[134217728:268435455]	auto[0]	47	1			T18	1		T44	1		T86	1
auto[134217728:268435455]	auto[1]	54	1			T87	1		T67	1		T95	1
auto[268435456:402653183]	auto[0]	62	1			T122	1		T48	1		T45	1
auto[268435456:402653183]	auto[1]	48	1			T46	1		T52	1		T186	1
auto[402653184:536870911]	auto[0]	48	1			T44	1		T36	1		T45	1
auto[402653184:536870911]	auto[1]	57	1			T13	3		T87	2		T44	1
auto[536870912:671088639]	auto[0]	43	1			T44	1		T195	1		T67	1
auto[536870912:671088639]	auto[1]	63	1			T16	1		T123	1		T24	1
auto[671088640:805306367]	auto[0]	49	1			T36	1		T46	2		T118	1
auto[671088640:805306367]	auto[1]	68	1			T44	1		T123	1		T37	1
auto[805306368:939524095]	auto[0]	44	1			T16	1		T44	1		T67	1
auto[805306368:939524095]	auto[1]	56	1			T44	1		T46	1		T185	1
auto[939524096:1073741823]	auto[0]	53	1			T87	1		T44	1		T199	1
auto[939524096:1073741823]	auto[1]	60	1			T88	1		T44	2		T23	1
auto[1073741824:1207959551]	auto[0]	59	1			T126	1		T24	1		T199	1
auto[1073741824:1207959551]	auto[1]	56	1			T44	2		T46	1		T186	1
auto[1207959552:1342177279]	auto[0]	54	1			T25	1		T140	1		T237	1
auto[1207959552:1342177279]	auto[1]	53	1			T139	1		T199	1		T192	1
auto[1342177280:1476395007]	auto[0]	59	1			T44	2		T122	1		T36	1
auto[1342177280:1476395007]	auto[1]	70	1			T196	1		T45	2		T46	1
auto[1476395008:1610612735]	auto[0]	53	1			T45	1		T61	1		T46	3
auto[1476395008:1610612735]	auto[1]	64	1			T2	1		T48	1		T60	1
auto[1610612736:1744830463]	auto[0]	60	1			T13	1		T44	1		T37	1
auto[1610612736:1744830463]	auto[1]	65	1			T19	1		T34	2		T195	1
auto[1744830464:1879048191]	auto[0]	40	1			T139	1		T36	1		T45	1
auto[1744830464:1879048191]	auto[1]	77	1			T1	1		T122	1		T80	2
auto[1879048192:2013265919]	auto[0]	44	1			T44	1		T199	1		T45	2
auto[1879048192:2013265919]	auto[1]	65	1			T3	1		T44	1		T124	1
auto[2013265920:2147483647]	auto[0]	56	1			T44	2		T45	1		T46	1
auto[2013265920:2147483647]	auto[1]	49	1			T122	1		T227	1		T273	1
auto[2147483648:2281701375]	auto[0]	56	1			T18	1		T44	1		T86	1
auto[2147483648:2281701375]	auto[1]	70	1			T44	1		T124	1		T45	1
auto[2281701376:2415919103]	auto[0]	52	1			T126	1		T67	2		T46	1
auto[2281701376:2415919103]	auto[1]	49	1			T16	1		T19	1		T44	3
auto[2415919104:2550136831]	auto[0]	51	1			T139	1		T192	1		T60	1
auto[2415919104:2550136831]	auto[1]	49	1			T44	1		T126	1		T46	2
auto[2550136832:2684354559]	auto[0]	46	1			T44	1		T126	1		T46	1
auto[2550136832:2684354559]	auto[1]	72	1			T2	1		T118	1		T128	1
auto[2684354560:2818572287]	auto[0]	42	1			T37	1		T86	1		T65	1
auto[2684354560:2818572287]	auto[1]	58	1			T1	1		T124	1		T194	1
auto[2818572288:2952790015]	auto[0]	59	1			T13	1		T46	1		T86	1
auto[2818572288:2952790015]	auto[1]	48	1			T16	1		T44	1		T46	2
auto[2952790016:3087007743]	auto[0]	66	1			T1	1		T34	1		T44	2
auto[2952790016:3087007743]	auto[1]	50	1			T44	1		T123	1		T23	1
auto[3087007744:3221225471]	auto[0]	49	1			T3	1		T125	1		T45	1
auto[3087007744:3221225471]	auto[1]	61	1			T45	1		T46	2		T401	1
auto[3221225472:3355443199]	auto[0]	45	1			T88	1		T44	1		T51	1
auto[3221225472:3355443199]	auto[1]	58	1			T19	1		T36	1		T126	1
auto[3355443200:3489660927]	auto[0]	50	1			T44	1		T196	1		T46	1
auto[3355443200:3489660927]	auto[1]	61	1			T13	1		T44	2		T122	1
auto[3489660928:3623878655]	auto[0]	62	1			T44	2		T195	1		T80	1
auto[3489660928:3623878655]	auto[1]	47	1			T195	1		T62	1		T69	1
auto[3623878656:3758096383]	auto[0]	32	1			T44	1		T23	1		T48	1
auto[3623878656:3758096383]	auto[1]	47	1			T44	1		T46	2		T60	1
auto[3758096384:3892314111]	auto[0]	55	1			T95	1		T45	4		T46	1
auto[3758096384:3892314111]	auto[1]	60	1			T48	1		T45	3		T46	2
auto[3892314112:4026531839]	auto[0]	43	1			T44	2		T24	1		T45	2
auto[3892314112:4026531839]	auto[1]	63	1			T2	1		T3	1		T195	1
auto[4026531840:4160749567]	auto[0]	60	1			T44	1		T45	1		T46	1
auto[4026531840:4160749567]	auto[1]	57	1			T16	1		T44	2		T20	1
auto[4160749568:4294967295]	auto[0]	58	1			T44	2		T24	1		T46	1
auto[4160749568:4294967295]	auto[1]	59	1			T20	1		T61	1		T46	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1649

1

T13

1

T16

1

T18

1

auto[1]

1866

1

T1

3

T2

3

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T44	1		T195	1		T45	4
auto[134217728:268435455]	113	1			T16	2		T87	1		T88	1
auto[268435456:402653183]	111	1			T139	1		T122	1		T46	1
auto[402653184:536870911]	100	1			T44	1		T123	1		T48	1
auto[536870912:671088639]	112	1			T44	2		T37	1		T196	1
auto[671088640:805306367]	108	1			T13	1		T19	1		T44	1
auto[805306368:939524095]	114	1			T2	1		T44	2		T122	1
auto[939524096:1073741823]	116	1			T44	2		T36	1		T20	2
auto[1073741824:1207959551]	108	1			T13	1		T87	1		T44	2
auto[1207959552:1342177279]	115	1			T44	1		T36	1		T123	1
auto[1342177280:1476395007]	117	1			T2	1		T19	1		T34	1
auto[1476395008:1610612735]	112	1			T3	1		T126	1		T195	1
auto[1610612736:1744830463]	109	1			T1	1		T139	2		T195	1
auto[1744830464:1879048191]	103	1			T13	1		T18	1		T44	1
auto[1879048192:2013265919]	106	1			T18	1		T44	1		T23	2
auto[2013265920:2147483647]	96	1			T44	1		T124	1		T37	1
auto[2147483648:2281701375]	98	1			T16	1		T87	1		T48	1
auto[2281701376:2415919103]	115	1			T44	4		T36	1		T67	1
auto[2415919104:2550136831]	124	1			T3	1		T44	1		T23	1
auto[2550136832:2684354559]	113	1			T44	1		T36	1		T126	1
auto[2684354560:2818572287]	93	1			T34	1		T44	3		T126	1
auto[2818572288:2952790015]	123	1			T44	4		T67	1		T199	1
auto[2952790016:3087007743]	105	1			T1	1		T122	1		T20	1
auto[3087007744:3221225471]	117	1			T19	1		T44	2		T67	1
auto[3221225472:3355443199]	112	1			T2	1		T44	2		T45	1
auto[3355443200:3489660927]	136	1			T3	1		T13	2		T16	1
auto[3489660928:3623878655]	122	1			T44	5		T125	1		T196	1
auto[3623878656:3758096383]	103	1			T88	1		T44	2		T45	4
auto[3758096384:3892314111]	104	1			T13	1		T44	2		T45	3
auto[3892314112:4026531839]	100	1			T1	1		T44	1		T122	1
auto[4026531840:4160749567]	110	1			T16	1		T196	1		T45	1
auto[4160749568:4294967295]	100	1			T34	1		T44	1		T124	1