Unified Coverage Report :: Group Instance : sealing_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1661

1

T1

1

T13

2

T16

1

auto[1]

1855

1

T1

2

T2

3

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T44	1		T48	1		T45	5
auto[134217728:268435455]	98	1			T44	1		T122	1		T124	1
auto[268435456:402653183]	106	1			T34	1		T44	2		T48	1
auto[402653184:536870911]	116	1			T13	1		T194	1		T199	1
auto[536870912:671088639]	102	1			T13	1		T16	1		T87	1
auto[671088640:805306367]	124	1			T44	1		T126	1		T24	2
auto[805306368:939524095]	112	1			T2	1		T18	1		T139	1
auto[939524096:1073741823]	92	1			T44	2		T67	1		T199	1
auto[1073741824:1207959551]	112	1			T44	1		T126	1		T196	1
auto[1207959552:1342177279]	114	1			T1	1		T87	1		T44	2
auto[1342177280:1476395007]	103	1			T34	1		T44	2		T45	2
auto[1476395008:1610612735]	124	1			T2	1		T87	1		T44	1
auto[1610612736:1744830463]	106	1			T87	1		T44	1		T23	1
auto[1744830464:1879048191]	110	1			T1	1		T44	2		T48	1
auto[1879048192:2013265919]	102	1			T13	1		T44	1		T37	1
auto[2013265920:2147483647]	106	1			T3	1		T19	1		T44	3
auto[2147483648:2281701375]	115	1			T44	1		T23	2		T24	1
auto[2281701376:2415919103]	102	1			T2	1		T44	3		T195	1
auto[2415919104:2550136831]	124	1			T34	1		T44	2		T195	1
auto[2550136832:2684354559]	118	1			T19	1		T44	3		T122	1
auto[2684354560:2818572287]	119	1			T3	1		T37	1		T67	1
auto[2818572288:2952790015]	107	1			T1	1		T13	1		T44	1
auto[2952790016:3087007743]	90	1			T16	1		T88	1		T44	3
auto[3087007744:3221225471]	128	1			T44	2		T195	1		T95	1
auto[3221225472:3355443199]	122	1			T3	1		T36	2		T67	1
auto[3355443200:3489660927]	121	1			T13	1		T44	1		T45	2
auto[3489660928:3623878655]	108	1			T18	1		T139	1		T44	3
auto[3623878656:3758096383]	109	1			T13	1		T16	1		T19	1
auto[3758096384:3892314111]	113	1			T16	2		T88	1		T122	1
auto[3892314112:4026531839]	103	1			T123	1		T20	1		T199	1
auto[4026531840:4160749567]	99	1			T44	1		T126	1		T45	2
auto[4160749568:4294967295]	113	1			T139	1		T44	2		T124	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T44	1		T45	2		T46	1
auto[0:134217727]	auto[1]	50	1			T48	1		T45	3		T46	2
auto[134217728:268435455]	auto[0]	45	1			T122	1		T37	1		T51	1
auto[134217728:268435455]	auto[1]	53	1			T44	1		T124	1		T46	1
auto[268435456:402653183]	auto[0]	51	1			T44	2		T48	1		T199	1
auto[268435456:402653183]	auto[1]	55	1			T34	1		T45	1		T46	4
auto[402653184:536870911]	auto[0]	62	1			T199	1		T45	3		T25	1
auto[402653184:536870911]	auto[1]	54	1			T13	1		T194	1		T46	1
auto[536870912:671088639]	auto[0]	50	1			T196	1		T199	1		T45	1
auto[536870912:671088639]	auto[1]	52	1			T13	1		T16	1		T87	1
auto[671088640:805306367]	auto[0]	51	1			T126	1		T24	1		T195	1
auto[671088640:805306367]	auto[1]	73	1			T44	1		T24	1		T195	1
auto[805306368:939524095]	auto[0]	58	1			T44	2		T61	1		T46	1
auto[805306368:939524095]	auto[1]	54	1			T2	1		T18	1		T139	1
auto[939524096:1073741823]	auto[0]	44	1			T44	2		T67	1		T401	1
auto[939524096:1073741823]	auto[1]	48	1			T199	1		T53	1		T46	1
auto[1073741824:1207959551]	auto[0]	48	1			T192	1		T273	1		T128	1
auto[1073741824:1207959551]	auto[1]	64	1			T44	1		T126	1		T196	1
auto[1207959552:1342177279]	auto[0]	57	1			T44	2		T36	1		T67	1
auto[1207959552:1342177279]	auto[1]	57	1			T1	1		T87	1		T123	1
auto[1342177280:1476395007]	auto[0]	46	1			T44	1		T59	1		T186	1
auto[1342177280:1476395007]	auto[1]	57	1			T34	1		T44	1		T45	2
auto[1476395008:1610612735]	auto[0]	57	1			T44	1		T36	1		T45	2
auto[1476395008:1610612735]	auto[1]	67	1			T2	1		T87	1		T20	1
auto[1610612736:1744830463]	auto[0]	58	1			T87	1		T23	1		T45	1
auto[1610612736:1744830463]	auto[1]	48	1			T44	1		T196	1		T256	1
auto[1744830464:1879048191]	auto[0]	49	1			T44	1		T45	2		T186	1
auto[1744830464:1879048191]	auto[1]	61	1			T1	1		T44	1		T48	1
auto[1879048192:2013265919]	auto[0]	42	1			T44	1		T140	1		T186	2
auto[1879048192:2013265919]	auto[1]	60	1			T13	1		T37	1		T24	1
auto[2013265920:2147483647]	auto[0]	44	1			T44	2		T196	1		T53	1
auto[2013265920:2147483647]	auto[1]	62	1			T3	1		T19	1		T44	1
auto[2147483648:2281701375]	auto[0]	53	1			T24	1		T46	1		T68	1
auto[2147483648:2281701375]	auto[1]	62	1			T44	1		T23	2		T195	1
auto[2281701376:2415919103]	auto[0]	37	1			T195	1		T48	1		T86	1
auto[2281701376:2415919103]	auto[1]	65	1			T2	1		T44	3		T45	1
auto[2415919104:2550136831]	auto[0]	57	1			T44	2		T195	1		T45	2
auto[2415919104:2550136831]	auto[1]	67	1			T34	1		T45	1		T46	1
auto[2550136832:2684354559]	auto[0]	56	1			T44	2		T36	1		T48	1
auto[2550136832:2684354559]	auto[1]	62	1			T19	1		T44	1		T122	1
auto[2684354560:2818572287]	auto[0]	55	1			T37	1		T45	1		T86	1
auto[2684354560:2818572287]	auto[1]	64	1			T3	1		T67	1		T46	2
auto[2818572288:2952790015]	auto[0]	65	1			T1	1		T13	1		T44	1
auto[2818572288:2952790015]	auto[1]	42	1			T199	1		T45	1		T61	1
auto[2952790016:3087007743]	auto[0]	49	1			T16	1		T44	2		T86	1
auto[2952790016:3087007743]	auto[1]	41	1			T88	1		T44	1		T46	4
auto[3087007744:3221225471]	auto[0]	58	1			T44	1		T46	2		T64	1
auto[3087007744:3221225471]	auto[1]	70	1			T44	1		T195	1		T95	1
auto[3221225472:3355443199]	auto[0]	51	1			T36	2		T67	1		T46	1
auto[3221225472:3355443199]	auto[1]	71	1			T3	1		T46	1		T52	1
auto[3355443200:3489660927]	auto[0]	63	1			T13	1		T44	1		T45	1
auto[3355443200:3489660927]	auto[1]	58	1			T45	1		T80	1		T62	1
auto[3489660928:3623878655]	auto[0]	59	1			T18	1		T139	1		T122	1
auto[3489660928:3623878655]	auto[1]	49	1			T44	3		T124	1		T126	1
auto[3623878656:3758096383]	auto[0]	53	1			T44	1		T45	1		T127	1
auto[3623878656:3758096383]	auto[1]	56	1			T13	1		T16	1		T19	1
auto[3758096384:3892314111]	auto[0]	54	1			T88	1		T126	1		T45	1
auto[3758096384:3892314111]	auto[1]	59	1			T16	2		T122	1		T64	1
auto[3892314112:4026531839]	auto[0]	52	1			T46	1		T118	1		T59	1
auto[3892314112:4026531839]	auto[1]	51	1			T123	1		T20	1		T199	1
auto[4026531840:4160749567]	auto[0]	45	1			T44	1		T126	1		T45	1
auto[4026531840:4160749567]	auto[1]	54	1			T45	1		T118	1		T197	1
auto[4160749568:4294967295]	auto[0]	44	1			T139	1		T45	1		T46	2
auto[4160749568:4294967295]	auto[1]	69	1			T44	2		T124	1		T46	1