Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7295

1

T1

9

T2

11

T3

6

auto[1]

249

1

T16

4

T122

2

T140

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3087	1			T1	3		T2	3		T3	3
auto[134217728:268435455]	157	1			T13	1		T16	1		T87	1
auto[268435456:402653183]	162	1			T1	1		T13	1		T16	1
auto[402653184:536870911]	187	1			T2	1		T13	1		T88	1
auto[536870912:671088639]	164	1			T18	1		T87	1		T44	2
auto[671088640:805306367]	176	1			T3	1		T19	1		T44	3
auto[805306368:939524095]	148	1			T2	1		T16	1		T87	1
auto[939524096:1073741823]	141	1			T13	1		T44	1		T37	1
auto[1073741824:1207959551]	137	1			T16	1		T34	1		T44	2
auto[1207959552:1342177279]	134	1			T1	1		T2	1		T44	1
auto[1342177280:1476395007]	161	1			T3	2		T16	1		T18	1
auto[1476395008:1610612735]	133	1			T16	1		T44	1		T23	1
auto[1610612736:1744830463]	139	1			T122	1		T37	1		T199	2
auto[1744830464:1879048191]	127	1			T139	1		T123	1		T124	1
auto[1879048192:2013265919]	133	1			T19	1		T44	1		T123	1
auto[2013265920:2147483647]	139	1			T44	3		T36	1		T123	1
auto[2147483648:2281701375]	141	1			T2	1		T34	1		T139	1
auto[2281701376:2415919103]	148	1			T16	1		T44	1		T122	1
auto[2415919104:2550136831]	124	1			T1	1		T18	1		T44	3
auto[2550136832:2684354559]	123	1			T1	1		T87	1		T44	3
auto[2684354560:2818572287]	124	1			T18	2		T87	1		T44	1
auto[2818572288:2952790015]	128	1			T13	1		T44	1		T36	2
auto[2952790016:3087007743]	131	1			T2	1		T87	1		T44	1
auto[3087007744:3221225471]	138	1			T13	1		T16	1		T19	1
auto[3221225472:3355443199]	151	1			T44	1		T37	1		T24	1
auto[3355443200:3489660927]	146	1			T44	2		T123	1		T195	2
auto[3489660928:3623878655]	146	1			T2	1		T16	1		T23	1
auto[3623878656:3758096383]	135	1			T2	2		T87	1		T44	1
auto[3758096384:3892314111]	150	1			T19	1		T87	1		T44	2
auto[3892314112:4026531839]	128	1			T1	1		T44	2		T126	1
auto[4026531840:4160749567]	167	1			T18	1		T139	1		T44	7
auto[4160749568:4294967295]	139	1			T1	1		T87	2		T34	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	3083	1			T1	3		T2	3		T3	3
auto[0:134217727]	auto[1]	4	1			T315	2		T403	1		T404	1
auto[134217728:268435455]	auto[0]	151	1			T13	1		T16	1		T87	1
auto[134217728:268435455]	auto[1]	6	1			T130	1		T256	1		T291	2
auto[268435456:402653183]	auto[0]	153	1			T1	1		T13	1		T18	1
auto[268435456:402653183]	auto[1]	9	1			T16	1		T140	1		T256	1
auto[402653184:536870911]	auto[0]	177	1			T2	1		T13	1		T88	1
auto[402653184:536870911]	auto[1]	10	1			T140	1		T130	1		T264	1
auto[536870912:671088639]	auto[0]	151	1			T18	1		T87	1		T44	2
auto[536870912:671088639]	auto[1]	13	1			T140	1		T227	1		T128	1
auto[671088640:805306367]	auto[0]	165	1			T3	1		T19	1		T44	3
auto[671088640:805306367]	auto[1]	11	1			T227	1		T256	1		T383	1
auto[805306368:939524095]	auto[0]	140	1			T2	1		T16	1		T87	1
auto[805306368:939524095]	auto[1]	8	1			T140	1		T129	2		T239	1
auto[939524096:1073741823]	auto[0]	135	1			T13	1		T44	1		T37	1
auto[939524096:1073741823]	auto[1]	6	1			T129	1		T264	1		T350	1
auto[1073741824:1207959551]	auto[0]	128	1			T16	1		T34	1		T44	2
auto[1073741824:1207959551]	auto[1]	9	1			T106	1		T398	1		T405	1
auto[1207959552:1342177279]	auto[0]	130	1			T1	1		T2	1		T44	1
auto[1207959552:1342177279]	auto[1]	4	1			T264	1		T406	1		T407	1
auto[1342177280:1476395007]	auto[0]	153	1			T3	2		T16	1		T18	1
auto[1342177280:1476395007]	auto[1]	8	1			T130	1		T256	1		T266	1
auto[1476395008:1610612735]	auto[0]	124	1			T44	1		T23	1		T20	1
auto[1476395008:1610612735]	auto[1]	9	1			T16	1		T375	1		T291	1
auto[1610612736:1744830463]	auto[0]	132	1			T122	1		T37	1		T199	2
auto[1610612736:1744830463]	auto[1]	7	1			T140	1		T264	1		T385	1
auto[1744830464:1879048191]	auto[0]	121	1			T139	1		T123	1		T124	1
auto[1744830464:1879048191]	auto[1]	6	1			T256	2		T383	1		T266	1
auto[1879048192:2013265919]	auto[0]	126	1			T19	1		T44	1		T123	1
auto[1879048192:2013265919]	auto[1]	7	1			T140	2		T255	1		T263	1
auto[2013265920:2147483647]	auto[0]	135	1			T44	3		T36	1		T123	1
auto[2013265920:2147483647]	auto[1]	4	1			T239	1		T266	1		T398	1
auto[2147483648:2281701375]	auto[0]	132	1			T2	1		T34	1		T139	1
auto[2147483648:2281701375]	auto[1]	9	1			T129	2		T375	1		T291	1
auto[2281701376:2415919103]	auto[0]	139	1			T44	1		T122	1		T194	1
auto[2281701376:2415919103]	auto[1]	9	1			T16	1		T238	1		T398	1
auto[2415919104:2550136831]	auto[0]	121	1			T1	1		T18	1		T44	3
auto[2415919104:2550136831]	auto[1]	3	1			T140	1		T408	1		T407	1
auto[2550136832:2684354559]	auto[0]	118	1			T1	1		T87	1		T44	3
auto[2550136832:2684354559]	auto[1]	5	1			T409	1		T404	2		T410	2
auto[2684354560:2818572287]	auto[0]	116	1			T18	2		T87	1		T44	1
auto[2684354560:2818572287]	auto[1]	8	1			T129	1		T130	1		T375	1
auto[2818572288:2952790015]	auto[0]	119	1			T13	1		T44	1		T36	2
auto[2818572288:2952790015]	auto[1]	9	1			T266	1		T315	1		T398	1
auto[2952790016:3087007743]	auto[0]	124	1			T2	1		T87	1		T44	1
auto[2952790016:3087007743]	auto[1]	7	1			T129	1		T238	1		T239	1
auto[3087007744:3221225471]	auto[0]	133	1			T13	1		T16	1		T19	1
auto[3087007744:3221225471]	auto[1]	5	1			T122	1		T129	1		T130	1
auto[3221225472:3355443199]	auto[0]	135	1			T44	1		T37	1		T24	1
auto[3221225472:3355443199]	auto[1]	16	1			T227	1		T264	1		T238	2
auto[3355443200:3489660927]	auto[0]	139	1			T44	2		T123	1		T195	2
auto[3355443200:3489660927]	auto[1]	7	1			T227	1		T264	1		T266	1
auto[3489660928:3623878655]	auto[0]	133	1			T2	1		T23	1		T195	1
auto[3489660928:3623878655]	auto[1]	13	1			T16	1		T256	1		T291	1
auto[3623878656:3758096383]	auto[0]	131	1			T2	2		T87	1		T44	1
auto[3623878656:3758096383]	auto[1]	4	1			T239	1		T383	1		T406	1
auto[3758096384:3892314111]	auto[0]	142	1			T19	1		T87	1		T44	2
auto[3758096384:3892314111]	auto[1]	8	1			T122	1		T130	2		T315	2
auto[3892314112:4026531839]	auto[0]	118	1			T1	1		T44	2		T126	1
auto[3892314112:4026531839]	auto[1]	10	1			T179	1		T244	2		T106	1
auto[4026531840:4160749567]	auto[0]	160	1			T18	1		T139	1		T44	7
auto[4026531840:4160749567]	auto[1]	7	1			T140	1		T256	2		T264	1
auto[4160749568:4294967295]	auto[0]	131	1			T1	1		T87	2		T34	1
auto[4160749568:4294967295]	auto[1]	8	1			T130	1		T106	1		T257	1