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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.04 98.07 98.33 100.00 99.02 98.41 91.22


Total test records in report: 1096
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T1008 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3892568645 Aug 09 05:40:27 PM PDT 24 Aug 09 05:40:29 PM PDT 24 24093449 ps
T1009 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2933151591 Aug 09 05:40:35 PM PDT 24 Aug 09 05:40:37 PM PDT 24 97364845 ps
T1010 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2011761427 Aug 09 05:40:16 PM PDT 24 Aug 09 05:40:26 PM PDT 24 553715526 ps
T1011 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1824484810 Aug 09 05:40:27 PM PDT 24 Aug 09 05:40:29 PM PDT 24 54268561 ps
T1012 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4191637556 Aug 09 05:40:21 PM PDT 24 Aug 09 05:40:23 PM PDT 24 67185113 ps
T1013 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1949977017 Aug 09 05:40:11 PM PDT 24 Aug 09 05:40:12 PM PDT 24 17556626 ps
T1014 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3098808447 Aug 09 05:40:10 PM PDT 24 Aug 09 05:40:12 PM PDT 24 71059100 ps
T1015 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2951480981 Aug 09 05:40:26 PM PDT 24 Aug 09 05:40:30 PM PDT 24 175853812 ps
T1016 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2782428571 Aug 09 05:40:10 PM PDT 24 Aug 09 05:40:12 PM PDT 24 313475012 ps
T1017 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2590244599 Aug 09 05:40:08 PM PDT 24 Aug 09 05:40:09 PM PDT 24 37222829 ps
T1018 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.843221144 Aug 09 05:40:44 PM PDT 24 Aug 09 05:40:47 PM PDT 24 135366122 ps
T1019 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3461301653 Aug 09 05:40:36 PM PDT 24 Aug 09 05:40:39 PM PDT 24 37894237 ps
T1020 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1905434792 Aug 09 05:40:12 PM PDT 24 Aug 09 05:40:14 PM PDT 24 25668699 ps
T1021 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2143727386 Aug 09 05:40:11 PM PDT 24 Aug 09 05:40:13 PM PDT 24 27264890 ps
T1022 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.738892783 Aug 09 05:40:21 PM PDT 24 Aug 09 05:40:22 PM PDT 24 44616856 ps
T158 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3543710543 Aug 09 05:40:13 PM PDT 24 Aug 09 05:40:18 PM PDT 24 102652218 ps
T1023 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3515358817 Aug 09 05:40:35 PM PDT 24 Aug 09 05:40:36 PM PDT 24 11028839 ps
T1024 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1889981350 Aug 09 05:40:27 PM PDT 24 Aug 09 05:40:29 PM PDT 24 28005420 ps
T1025 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2924498439 Aug 09 05:40:21 PM PDT 24 Aug 09 05:40:23 PM PDT 24 26349649 ps
T1026 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3182566575 Aug 09 05:40:20 PM PDT 24 Aug 09 05:40:23 PM PDT 24 165564409 ps
T1027 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.486799818 Aug 09 05:40:12 PM PDT 24 Aug 09 05:40:24 PM PDT 24 3835584268 ps
T1028 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3665358716 Aug 09 05:40:13 PM PDT 24 Aug 09 05:40:15 PM PDT 24 365096839 ps
T1029 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.71505517 Aug 09 05:40:42 PM PDT 24 Aug 09 05:40:42 PM PDT 24 36489935 ps
T1030 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2700080985 Aug 09 05:40:43 PM PDT 24 Aug 09 05:40:44 PM PDT 24 39652895 ps
T1031 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2145897505 Aug 09 05:40:46 PM PDT 24 Aug 09 05:40:48 PM PDT 24 83660523 ps
T1032 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1524608452 Aug 09 05:40:22 PM PDT 24 Aug 09 05:40:26 PM PDT 24 109652016 ps
T1033 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2471006537 Aug 09 05:40:20 PM PDT 24 Aug 09 05:40:25 PM PDT 24 2186384579 ps
T1034 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1138265109 Aug 09 05:40:51 PM PDT 24 Aug 09 05:40:52 PM PDT 24 26206074 ps
T1035 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2540947662 Aug 09 05:40:53 PM PDT 24 Aug 09 05:40:54 PM PDT 24 19564809 ps
T1036 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.123421315 Aug 09 05:40:50 PM PDT 24 Aug 09 05:40:51 PM PDT 24 11540101 ps
T1037 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1332638315 Aug 09 05:40:35 PM PDT 24 Aug 09 05:40:37 PM PDT 24 144563172 ps
T160 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2651521693 Aug 09 05:40:29 PM PDT 24 Aug 09 05:40:34 PM PDT 24 332550785 ps
T1038 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.943257756 Aug 09 05:40:13 PM PDT 24 Aug 09 05:40:14 PM PDT 24 287923846 ps
T1039 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1335204678 Aug 09 05:40:28 PM PDT 24 Aug 09 05:40:42 PM PDT 24 5443766585 ps
T1040 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1152825148 Aug 09 05:40:24 PM PDT 24 Aug 09 05:40:26 PM PDT 24 50997939 ps
T1041 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3652754735 Aug 09 05:40:28 PM PDT 24 Aug 09 05:40:30 PM PDT 24 43649835 ps
T1042 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3627163169 Aug 09 05:40:50 PM PDT 24 Aug 09 05:40:51 PM PDT 24 35252762 ps
T1043 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.57908502 Aug 09 05:40:32 PM PDT 24 Aug 09 05:40:33 PM PDT 24 11765619 ps
T1044 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3678712851 Aug 09 05:40:36 PM PDT 24 Aug 09 05:40:43 PM PDT 24 287132944 ps
T1045 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2095900545 Aug 09 05:40:26 PM PDT 24 Aug 09 05:40:28 PM PDT 24 21523053 ps
T1046 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2283604355 Aug 09 05:40:11 PM PDT 24 Aug 09 05:40:13 PM PDT 24 110184330 ps
T1047 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3792346949 Aug 09 05:40:27 PM PDT 24 Aug 09 05:40:35 PM PDT 24 573310175 ps
T1048 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3091446857 Aug 09 05:40:47 PM PDT 24 Aug 09 05:40:49 PM PDT 24 40533844 ps
T1049 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2124832160 Aug 09 05:40:51 PM PDT 24 Aug 09 05:40:52 PM PDT 24 46171990 ps
T1050 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.884831560 Aug 09 05:40:44 PM PDT 24 Aug 09 05:40:46 PM PDT 24 44794631 ps
T1051 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.692486587 Aug 09 05:40:53 PM PDT 24 Aug 09 05:40:54 PM PDT 24 49609102 ps
T1052 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.70550663 Aug 09 05:40:23 PM PDT 24 Aug 09 05:40:26 PM PDT 24 104319335 ps
T1053 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.409884594 Aug 09 05:40:24 PM PDT 24 Aug 09 05:40:26 PM PDT 24 186863356 ps
T1054 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.105058211 Aug 09 05:40:16 PM PDT 24 Aug 09 05:40:18 PM PDT 24 164502884 ps
T1055 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3248033956 Aug 09 05:40:21 PM PDT 24 Aug 09 05:40:25 PM PDT 24 392388388 ps
T1056 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2104142575 Aug 09 05:40:13 PM PDT 24 Aug 09 05:40:24 PM PDT 24 1970455567 ps
T1057 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.77373855 Aug 09 05:40:32 PM PDT 24 Aug 09 05:40:45 PM PDT 24 1284057148 ps
T1058 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.599230585 Aug 09 05:40:13 PM PDT 24 Aug 09 05:40:26 PM PDT 24 363180225 ps
T1059 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3871969075 Aug 09 05:40:50 PM PDT 24 Aug 09 05:40:52 PM PDT 24 217194706 ps
T155 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2687974296 Aug 09 05:40:13 PM PDT 24 Aug 09 05:40:17 PM PDT 24 103111959 ps
T1060 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.439254577 Aug 09 05:40:21 PM PDT 24 Aug 09 05:40:22 PM PDT 24 16941840 ps
T166 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.409706532 Aug 09 05:40:36 PM PDT 24 Aug 09 05:40:43 PM PDT 24 218111125 ps
T1061 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.355497564 Aug 09 05:40:32 PM PDT 24 Aug 09 05:40:33 PM PDT 24 20170133 ps
T1062 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2153952620 Aug 09 05:40:43 PM PDT 24 Aug 09 05:40:47 PM PDT 24 271343041 ps
T1063 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3102932719 Aug 09 05:40:14 PM PDT 24 Aug 09 05:40:18 PM PDT 24 119967434 ps
T1064 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.603075405 Aug 09 05:40:22 PM PDT 24 Aug 09 05:40:24 PM PDT 24 92747628 ps
T1065 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.781310337 Aug 09 05:40:54 PM PDT 24 Aug 09 05:40:55 PM PDT 24 41488486 ps
T1066 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2084738386 Aug 09 05:40:24 PM PDT 24 Aug 09 05:40:28 PM PDT 24 672403400 ps
T1067 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.22163974 Aug 09 05:40:07 PM PDT 24 Aug 09 05:40:17 PM PDT 24 412763421 ps
T1068 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2617485846 Aug 09 05:40:22 PM PDT 24 Aug 09 05:40:23 PM PDT 24 22847810 ps
T1069 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.48128609 Aug 09 05:40:37 PM PDT 24 Aug 09 05:40:38 PM PDT 24 23357634 ps
T1070 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.211290673 Aug 09 05:40:14 PM PDT 24 Aug 09 05:40:17 PM PDT 24 105322337 ps
T1071 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.159873871 Aug 09 05:40:53 PM PDT 24 Aug 09 05:40:54 PM PDT 24 7405453 ps
T1072 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.682299361 Aug 09 05:40:51 PM PDT 24 Aug 09 05:40:52 PM PDT 24 13416507 ps
T1073 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.72878233 Aug 09 05:40:32 PM PDT 24 Aug 09 05:40:35 PM PDT 24 43673066 ps
T1074 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1351947536 Aug 09 05:40:47 PM PDT 24 Aug 09 05:40:48 PM PDT 24 14636909 ps
T1075 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.805139710 Aug 09 05:40:36 PM PDT 24 Aug 09 05:40:39 PM PDT 24 277802361 ps
T1076 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2866858333 Aug 09 05:40:08 PM PDT 24 Aug 09 05:40:10 PM PDT 24 98738139 ps
T168 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1853168907 Aug 09 05:40:35 PM PDT 24 Aug 09 05:40:39 PM PDT 24 182705957 ps
T1077 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.331463310 Aug 09 05:40:54 PM PDT 24 Aug 09 05:40:54 PM PDT 24 94600075 ps
T1078 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.154977583 Aug 09 05:40:45 PM PDT 24 Aug 09 05:40:46 PM PDT 24 220831121 ps
T1079 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2930782189 Aug 09 05:40:52 PM PDT 24 Aug 09 05:40:52 PM PDT 24 50314066 ps
T1080 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2351798240 Aug 09 05:40:39 PM PDT 24 Aug 09 05:40:41 PM PDT 24 1543592349 ps
T1081 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3213476150 Aug 09 05:40:28 PM PDT 24 Aug 09 05:40:34 PM PDT 24 621696609 ps
T1082 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3392902222 Aug 09 05:40:53 PM PDT 24 Aug 09 05:40:54 PM PDT 24 10706142 ps
T161 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.89503104 Aug 09 05:40:23 PM PDT 24 Aug 09 05:40:33 PM PDT 24 481657031 ps
T167 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1960381047 Aug 09 05:40:19 PM PDT 24 Aug 09 05:40:24 PM PDT 24 1258416117 ps
T1083 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1266985443 Aug 09 05:40:39 PM PDT 24 Aug 09 05:40:41 PM PDT 24 55360746 ps
T1084 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2360008295 Aug 09 05:40:28 PM PDT 24 Aug 09 05:40:29 PM PDT 24 32151771 ps
T1085 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.822859353 Aug 09 05:40:52 PM PDT 24 Aug 09 05:40:53 PM PDT 24 14839538 ps
T1086 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1156795398 Aug 09 05:40:12 PM PDT 24 Aug 09 05:40:14 PM PDT 24 32185047 ps
T1087 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1371092198 Aug 09 05:40:07 PM PDT 24 Aug 09 05:40:17 PM PDT 24 557392883 ps
T1088 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2355942926 Aug 09 05:40:27 PM PDT 24 Aug 09 05:40:28 PM PDT 24 11767817 ps
T1089 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2760415926 Aug 09 05:40:23 PM PDT 24 Aug 09 05:40:28 PM PDT 24 305229521 ps
T1090 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2799082479 Aug 09 05:40:32 PM PDT 24 Aug 09 05:40:37 PM PDT 24 203892606 ps
T1091 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1942821529 Aug 09 05:40:32 PM PDT 24 Aug 09 05:40:33 PM PDT 24 22831051 ps
T1092 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.21167332 Aug 09 05:40:13 PM PDT 24 Aug 09 05:40:18 PM PDT 24 139593010 ps
T1093 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3080211573 Aug 09 05:40:52 PM PDT 24 Aug 09 05:40:53 PM PDT 24 13609935 ps
T1094 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3603672171 Aug 09 05:40:28 PM PDT 24 Aug 09 05:40:32 PM PDT 24 439194447 ps
T1095 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1538139467 Aug 09 05:40:52 PM PDT 24 Aug 09 05:40:53 PM PDT 24 46621468 ps
T1096 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3331604850 Aug 09 05:40:45 PM PDT 24 Aug 09 05:40:54 PM PDT 24 182623140 ps

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2351589617
Short name T2
Test name
Test status
Simulation time 390508043 ps
CPU time 14.62 seconds
Started Aug 09 05:23:20 PM PDT 24
Finished Aug 09 05:23:34 PM PDT 24
Peak memory 220196 kb
Host smart-541e4959-6500-450e-8559-e9ca49d97584
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351589617 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2351589617
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3205954671
Short name T44
Test name
Test status
Simulation time 7677807730 ps
CPU time 96.56 seconds
Started Aug 09 05:22:57 PM PDT 24
Finished Aug 09 05:24:33 PM PDT 24
Peak memory 222568 kb
Host smart-8b2ca821-c371-4bdc-9c71-79ed1f98b574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205954671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3205954671
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2922388407
Short name T45
Test name
Test status
Simulation time 2648335560 ps
CPU time 48.21 seconds
Started Aug 09 05:23:08 PM PDT 24
Finished Aug 09 05:23:56 PM PDT 24
Peak memory 222612 kb
Host smart-f76e8c27-36c0-4dc9-8049-af98ecb5d668
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922388407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2922388407
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2942774117
Short name T11
Test name
Test status
Simulation time 496865840 ps
CPU time 10.46 seconds
Started Aug 09 05:20:59 PM PDT 24
Finished Aug 09 05:21:09 PM PDT 24
Peak memory 233732 kb
Host smart-c9841027-55db-494e-9cdb-4931d8a40179
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942774117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2942774117
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2870762228
Short name T68
Test name
Test status
Simulation time 2281627520 ps
CPU time 23.1 seconds
Started Aug 09 05:22:18 PM PDT 24
Finished Aug 09 05:22:42 PM PDT 24
Peak memory 222612 kb
Host smart-5e1fbcc4-bff3-48ea-84fa-52b8bf3d646e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870762228 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2870762228
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.962820825
Short name T6
Test name
Test status
Simulation time 53693788811 ps
CPU time 289.91 seconds
Started Aug 09 05:21:45 PM PDT 24
Finished Aug 09 05:26:35 PM PDT 24
Peak memory 218360 kb
Host smart-107f9770-4a40-4a41-8b60-a720efd85d6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962820825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.962820825
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.276104201
Short name T16
Test name
Test status
Simulation time 194162918 ps
CPU time 10.95 seconds
Started Aug 09 05:21:49 PM PDT 24
Finished Aug 09 05:22:00 PM PDT 24
Peak memory 214416 kb
Host smart-aac2e219-64c2-45e8-a74e-976552f53190
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=276104201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.276104201
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1201078818
Short name T46
Test name
Test status
Simulation time 1490369197 ps
CPU time 44.54 seconds
Started Aug 09 05:21:57 PM PDT 24
Finished Aug 09 05:22:42 PM PDT 24
Peak memory 217136 kb
Host smart-2f6eed88-7797-48cd-b3f5-c23a16c37307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201078818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1201078818
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1285371768
Short name T7
Test name
Test status
Simulation time 101947435 ps
CPU time 1.76 seconds
Started Aug 09 05:22:12 PM PDT 24
Finished Aug 09 05:22:14 PM PDT 24
Peak memory 216676 kb
Host smart-ec9f7544-deea-4f3f-b553-c64cd6f809b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285371768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1285371768
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1879655136
Short name T112
Test name
Test status
Simulation time 135117882 ps
CPU time 3.49 seconds
Started Aug 09 05:40:35 PM PDT 24
Finished Aug 09 05:40:39 PM PDT 24
Peak memory 214500 kb
Host smart-100b0779-8585-4156-b1e9-81175fdee1d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879655136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1879655136
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3292414922
Short name T266
Test name
Test status
Simulation time 330386793 ps
CPU time 9.29 seconds
Started Aug 09 05:22:39 PM PDT 24
Finished Aug 09 05:22:48 PM PDT 24
Peak memory 214724 kb
Host smart-79cc8f37-112a-46da-a7bc-866ceb37d10e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292414922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3292414922
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2769174319
Short name T35
Test name
Test status
Simulation time 134204459 ps
CPU time 3.51 seconds
Started Aug 09 05:21:49 PM PDT 24
Finished Aug 09 05:21:53 PM PDT 24
Peak memory 209900 kb
Host smart-f22ae419-c613-48db-8c15-75285f7b2d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769174319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2769174319
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.64737048
Short name T404
Test name
Test status
Simulation time 1069233849 ps
CPU time 25.99 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:23:21 PM PDT 24
Peak memory 215320 kb
Host smart-600079e1-e697-461d-bc28-13ea22801ac6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64737048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.64737048
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.60099044
Short name T92
Test name
Test status
Simulation time 34673520 ps
CPU time 2.38 seconds
Started Aug 09 05:20:43 PM PDT 24
Finished Aug 09 05:20:45 PM PDT 24
Peak memory 219652 kb
Host smart-ba83f052-6bec-496f-b08b-9e6399fd0534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60099044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.60099044
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1973076761
Short name T111
Test name
Test status
Simulation time 321771279 ps
CPU time 2.35 seconds
Started Aug 09 05:40:37 PM PDT 24
Finished Aug 09 05:40:40 PM PDT 24
Peak memory 214656 kb
Host smart-ce071fc1-d75b-4027-b453-16943498f144
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973076761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1973076761
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.100549726
Short name T140
Test name
Test status
Simulation time 5833387117 ps
CPU time 74.55 seconds
Started Aug 09 05:21:00 PM PDT 24
Finished Aug 09 05:22:14 PM PDT 24
Peak memory 215828 kb
Host smart-2af48305-4af6-49cb-9868-6b5b72e870d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100549726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.100549726
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1782271904
Short name T375
Test name
Test status
Simulation time 416885618 ps
CPU time 10.67 seconds
Started Aug 09 05:22:18 PM PDT 24
Finished Aug 09 05:22:29 PM PDT 24
Peak memory 215140 kb
Host smart-5b0f71c8-aaab-499d-a248-f2163ac30592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1782271904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1782271904
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1244486344
Short name T36
Test name
Test status
Simulation time 104766290 ps
CPU time 2.08 seconds
Started Aug 09 05:21:15 PM PDT 24
Finished Aug 09 05:21:17 PM PDT 24
Peak memory 214220 kb
Host smart-7b83ff38-38a9-4f46-b492-f1935ea3d8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244486344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1244486344
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3306933294
Short name T186
Test name
Test status
Simulation time 617207713 ps
CPU time 22.47 seconds
Started Aug 09 05:20:50 PM PDT 24
Finished Aug 09 05:21:13 PM PDT 24
Peak memory 220228 kb
Host smart-c7c7b56b-8557-40d3-a1f1-b99d5c2e47f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306933294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3306933294
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.601499565
Short name T227
Test name
Test status
Simulation time 291812368 ps
CPU time 12.67 seconds
Started Aug 09 05:21:54 PM PDT 24
Finished Aug 09 05:22:07 PM PDT 24
Peak memory 214724 kb
Host smart-c392285f-87cf-4512-816d-2499e9904afa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601499565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.601499565
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1466228710
Short name T21
Test name
Test status
Simulation time 66422629 ps
CPU time 2.63 seconds
Started Aug 09 05:22:13 PM PDT 24
Finished Aug 09 05:22:15 PM PDT 24
Peak memory 208764 kb
Host smart-585ac028-15db-42f5-886c-8062e55cd886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466228710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1466228710
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1513460501
Short name T315
Test name
Test status
Simulation time 854751527 ps
CPU time 22.67 seconds
Started Aug 09 05:23:34 PM PDT 24
Finished Aug 09 05:23:56 PM PDT 24
Peak memory 214876 kb
Host smart-f404a229-7ef2-44f2-9fd5-bd87433f9a94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513460501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1513460501
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1135727197
Short name T40
Test name
Test status
Simulation time 992514703 ps
CPU time 5.79 seconds
Started Aug 09 05:22:41 PM PDT 24
Finished Aug 09 05:22:46 PM PDT 24
Peak memory 220168 kb
Host smart-bbebaf9c-5b76-4175-bf67-9e9157aca034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135727197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1135727197
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1023145208
Short name T119
Test name
Test status
Simulation time 8903299122 ps
CPU time 22.43 seconds
Started Aug 09 05:21:53 PM PDT 24
Finished Aug 09 05:22:16 PM PDT 24
Peak memory 222984 kb
Host smart-273192dc-cd76-40ff-935d-dab480f01a39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023145208 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1023145208
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1231533651
Short name T143
Test name
Test status
Simulation time 177937659 ps
CPU time 4.35 seconds
Started Aug 09 05:21:09 PM PDT 24
Finished Aug 09 05:21:14 PM PDT 24
Peak memory 217724 kb
Host smart-3ba81efc-a8bc-4fbf-9e19-10e28c82449c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231533651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1231533651
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1791943485
Short name T222
Test name
Test status
Simulation time 1542367454 ps
CPU time 7.58 seconds
Started Aug 09 05:21:25 PM PDT 24
Finished Aug 09 05:21:32 PM PDT 24
Peak memory 209028 kb
Host smart-1c0cbf18-68e1-4ac3-a940-ea38a3f7b0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791943485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1791943485
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.286577017
Short name T383
Test name
Test status
Simulation time 242753273 ps
CPU time 13.73 seconds
Started Aug 09 05:23:06 PM PDT 24
Finished Aug 09 05:23:20 PM PDT 24
Peak memory 214188 kb
Host smart-0ace4d42-d19c-4585-98f1-4f221c068333
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286577017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.286577017
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2768055144
Short name T97
Test name
Test status
Simulation time 1262391637 ps
CPU time 8.03 seconds
Started Aug 09 05:20:59 PM PDT 24
Finished Aug 09 05:21:07 PM PDT 24
Peak memory 214236 kb
Host smart-9b447e75-0018-4ee3-bce8-116c931b0207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768055144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2768055144
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.380719540
Short name T4
Test name
Test status
Simulation time 5160791786 ps
CPU time 37.4 seconds
Started Aug 09 05:22:03 PM PDT 24
Finished Aug 09 05:22:41 PM PDT 24
Peak memory 217188 kb
Host smart-9fb3b068-d56d-4af4-ab40-7712fc67c527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380719540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.380719540
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1051844786
Short name T406
Test name
Test status
Simulation time 4720443702 ps
CPU time 71.91 seconds
Started Aug 09 05:22:04 PM PDT 24
Finished Aug 09 05:23:16 PM PDT 24
Peak memory 214480 kb
Host smart-509a8927-970e-432b-9a14-c6a9bf1e95dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051844786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1051844786
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3755334851
Short name T289
Test name
Test status
Simulation time 10542652698 ps
CPU time 51.75 seconds
Started Aug 09 05:23:25 PM PDT 24
Finished Aug 09 05:24:17 PM PDT 24
Peak memory 215772 kb
Host smart-723db2a4-3819-4b47-afe3-8d1e76517653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755334851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3755334851
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.4209496422
Short name T150
Test name
Test status
Simulation time 1771290146 ps
CPU time 6.72 seconds
Started Aug 09 05:40:53 PM PDT 24
Finished Aug 09 05:40:59 PM PDT 24
Peak memory 214164 kb
Host smart-5e1a5ad0-ca48-4923-beb1-7d1de948c7f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209496422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.4209496422
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3810283698
Short name T85
Test name
Test status
Simulation time 53144502 ps
CPU time 0.84 seconds
Started Aug 09 05:21:35 PM PDT 24
Finished Aug 09 05:21:36 PM PDT 24
Peak memory 205848 kb
Host smart-8bc52c41-6ece-44c1-9173-b8b659fb2cde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810283698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3810283698
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2018157051
Short name T18
Test name
Test status
Simulation time 847520437 ps
CPU time 5.93 seconds
Started Aug 09 05:22:49 PM PDT 24
Finished Aug 09 05:22:55 PM PDT 24
Peak memory 209884 kb
Host smart-9864b79a-97c2-4e48-b6bd-df1ad4e8ebc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018157051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2018157051
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2576592048
Short name T86
Test name
Test status
Simulation time 276534276 ps
CPU time 3.71 seconds
Started Aug 09 05:21:29 PM PDT 24
Finished Aug 09 05:21:33 PM PDT 24
Peak memory 211108 kb
Host smart-af8eb181-a6e9-48e4-a62b-6d32fa7f711f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576592048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2576592048
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2390779676
Short name T256
Test name
Test status
Simulation time 4231167260 ps
CPU time 62.69 seconds
Started Aug 09 05:23:07 PM PDT 24
Finished Aug 09 05:24:10 PM PDT 24
Peak memory 215828 kb
Host smart-182ffaa3-3b82-4035-a957-5f3707145a78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2390779676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2390779676
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.544905139
Short name T325
Test name
Test status
Simulation time 516378333 ps
CPU time 20.36 seconds
Started Aug 09 05:23:25 PM PDT 24
Finished Aug 09 05:23:46 PM PDT 24
Peak memory 220652 kb
Host smart-67083fa0-8f2d-4ae4-8cac-6029fb0913e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544905139 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.544905139
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2245838784
Short name T159
Test name
Test status
Simulation time 1986721510 ps
CPU time 7.29 seconds
Started Aug 09 05:40:12 PM PDT 24
Finished Aug 09 05:40:19 PM PDT 24
Peak memory 214232 kb
Host smart-70a0816e-6762-4e5d-a659-9fd4d95138f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245838784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2245838784
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.4136337434
Short name T179
Test name
Test status
Simulation time 188221435 ps
CPU time 4.22 seconds
Started Aug 09 05:23:31 PM PDT 24
Finished Aug 09 05:23:36 PM PDT 24
Peak memory 215196 kb
Host smart-77ee7161-dd6e-4794-a169-b359aaba7bbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4136337434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.4136337434
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.409706532
Short name T166
Test name
Test status
Simulation time 218111125 ps
CPU time 6.79 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:43 PM PDT 24
Peak memory 214420 kb
Host smart-04a8ec70-062c-4b40-9d6e-8da375da82d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409706532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.409706532
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1000130853
Short name T244
Test name
Test status
Simulation time 151265680 ps
CPU time 3.05 seconds
Started Aug 09 05:22:04 PM PDT 24
Finished Aug 09 05:22:07 PM PDT 24
Peak memory 215248 kb
Host smart-aab7828d-527a-45cb-ad5e-b69d00da0fa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1000130853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1000130853
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2205801092
Short name T234
Test name
Test status
Simulation time 72813783 ps
CPU time 3.74 seconds
Started Aug 09 05:23:09 PM PDT 24
Finished Aug 09 05:23:13 PM PDT 24
Peak memory 214256 kb
Host smart-69eded87-5471-46e5-97ac-1af96a379095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205801092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2205801092
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.194321536
Short name T249
Test name
Test status
Simulation time 148903200 ps
CPU time 3.73 seconds
Started Aug 09 05:21:40 PM PDT 24
Finished Aug 09 05:21:43 PM PDT 24
Peak memory 214332 kb
Host smart-145db7e5-e17b-4a6e-82f7-853f25fb7ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194321536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.194321536
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1436607319
Short name T279
Test name
Test status
Simulation time 61348399 ps
CPU time 1.66 seconds
Started Aug 09 05:21:09 PM PDT 24
Finished Aug 09 05:21:11 PM PDT 24
Peak memory 214228 kb
Host smart-291eeafb-38f2-4d2a-a381-0e643700c3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436607319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1436607319
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.442907938
Short name T328
Test name
Test status
Simulation time 4458507517 ps
CPU time 60.64 seconds
Started Aug 09 05:21:15 PM PDT 24
Finished Aug 09 05:22:16 PM PDT 24
Peak memory 221428 kb
Host smart-827327bb-d36d-4300-90fc-3670896f2c41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442907938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.442907938
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1912955139
Short name T141
Test name
Test status
Simulation time 164847268 ps
CPU time 4.39 seconds
Started Aug 09 05:21:56 PM PDT 24
Finished Aug 09 05:22:01 PM PDT 24
Peak memory 218324 kb
Host smart-54a54559-b35a-4f1d-bb90-e42d59ab207c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912955139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1912955139
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2095751385
Short name T407
Test name
Test status
Simulation time 6071138778 ps
CPU time 75.27 seconds
Started Aug 09 05:21:58 PM PDT 24
Finished Aug 09 05:23:13 PM PDT 24
Peak memory 216360 kb
Host smart-67474bd4-22e5-4691-86e4-c2c2cb50fe2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095751385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2095751385
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.943883280
Short name T259
Test name
Test status
Simulation time 2112821289 ps
CPU time 40.76 seconds
Started Aug 09 05:23:22 PM PDT 24
Finished Aug 09 05:24:03 PM PDT 24
Peak memory 222316 kb
Host smart-a67a7f03-8c2c-4e15-a41a-1b4c26de497f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943883280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.943883280
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2159144954
Short name T225
Test name
Test status
Simulation time 932149368 ps
CPU time 37.05 seconds
Started Aug 09 05:23:39 PM PDT 24
Finished Aug 09 05:24:16 PM PDT 24
Peak memory 216524 kb
Host smart-85600207-e010-42d6-a441-da04db1a148c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159144954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2159144954
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1158843380
Short name T163
Test name
Test status
Simulation time 253074420 ps
CPU time 5.16 seconds
Started Aug 09 05:40:44 PM PDT 24
Finished Aug 09 05:40:49 PM PDT 24
Peak memory 215496 kb
Host smart-c200ad86-2072-4c1e-aa01-0231605c0a7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158843380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1158843380
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.89503104
Short name T161
Test name
Test status
Simulation time 481657031 ps
CPU time 9.36 seconds
Started Aug 09 05:40:23 PM PDT 24
Finished Aug 09 05:40:33 PM PDT 24
Peak memory 214188 kb
Host smart-5f429f6d-1055-460a-92c6-6d84f524009d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89503104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.89503104
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2651521693
Short name T160
Test name
Test status
Simulation time 332550785 ps
CPU time 5.08 seconds
Started Aug 09 05:40:29 PM PDT 24
Finished Aug 09 05:40:34 PM PDT 24
Peak memory 206088 kb
Host smart-ea87297a-4fcb-4ab6-820f-9c47e53f1157
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651521693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2651521693
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2389615584
Short name T71
Test name
Test status
Simulation time 3039761296 ps
CPU time 83.49 seconds
Started Aug 09 05:22:18 PM PDT 24
Finished Aug 09 05:23:42 PM PDT 24
Peak memory 222480 kb
Host smart-a3f542df-f9ba-4c21-a93c-a3767b666ab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389615584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2389615584
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1920035869
Short name T236
Test name
Test status
Simulation time 31837044 ps
CPU time 1.87 seconds
Started Aug 09 05:22:36 PM PDT 24
Finished Aug 09 05:22:38 PM PDT 24
Peak memory 214184 kb
Host smart-c72d7bed-4be5-4749-82d2-fdae7ea6efcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920035869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1920035869
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2065272183
Short name T309
Test name
Test status
Simulation time 691045943 ps
CPU time 18.49 seconds
Started Aug 09 05:23:16 PM PDT 24
Finished Aug 09 05:23:34 PM PDT 24
Peak memory 216388 kb
Host smart-91220823-8aa0-4e1d-824f-4d22def2203c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065272183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2065272183
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3180848620
Short name T321
Test name
Test status
Simulation time 23117986 ps
CPU time 1.66 seconds
Started Aug 09 05:23:25 PM PDT 24
Finished Aug 09 05:23:27 PM PDT 24
Peak memory 214336 kb
Host smart-25b74087-26d4-493e-a03f-e2a34bbf9c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180848620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3180848620
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.587779786
Short name T213
Test name
Test status
Simulation time 168043334 ps
CPU time 4.27 seconds
Started Aug 09 05:20:54 PM PDT 24
Finished Aug 09 05:20:59 PM PDT 24
Peak memory 221324 kb
Host smart-6c602bf3-d7d2-4d24-842b-18d156e6e546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587779786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.587779786
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2820122095
Short name T142
Test name
Test status
Simulation time 39781110 ps
CPU time 2.7 seconds
Started Aug 09 05:23:32 PM PDT 24
Finished Aug 09 05:23:34 PM PDT 24
Peak memory 217920 kb
Host smart-2bdf8c7d-2cd5-4882-a3dd-5f69f2436286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820122095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2820122095
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3160835508
Short name T146
Test name
Test status
Simulation time 179602469 ps
CPU time 5.31 seconds
Started Aug 09 05:22:29 PM PDT 24
Finished Aug 09 05:22:34 PM PDT 24
Peak memory 218240 kb
Host smart-3f3ac8d8-f56c-4f92-908d-33ff51a0ecee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160835508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3160835508
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3920116428
Short name T144
Test name
Test status
Simulation time 132164449 ps
CPU time 2.74 seconds
Started Aug 09 05:22:47 PM PDT 24
Finished Aug 09 05:22:50 PM PDT 24
Peak memory 217076 kb
Host smart-c64dad42-e68f-4429-a922-e959c754d026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920116428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3920116428
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3704069070
Short name T528
Test name
Test status
Simulation time 99666800 ps
CPU time 2.72 seconds
Started Aug 09 05:20:44 PM PDT 24
Finished Aug 09 05:20:47 PM PDT 24
Peak memory 207124 kb
Host smart-c8bda992-8c08-4fa4-9452-66caac999111
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704069070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3704069070
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2022338964
Short name T272
Test name
Test status
Simulation time 233916655 ps
CPU time 5.49 seconds
Started Aug 09 05:20:50 PM PDT 24
Finished Aug 09 05:20:56 PM PDT 24
Peak memory 214296 kb
Host smart-c8c27dc1-e5f2-4d84-b73b-17c3ac86aad0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2022338964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2022338964
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2217032730
Short name T129
Test name
Test status
Simulation time 221554793 ps
CPU time 4.03 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:40 PM PDT 24
Peak memory 214328 kb
Host smart-21c2d127-4ce9-4ffc-9792-b42445aa03dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2217032730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2217032730
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1569403068
Short name T525
Test name
Test status
Simulation time 796273406 ps
CPU time 3.68 seconds
Started Aug 09 05:21:44 PM PDT 24
Finished Aug 09 05:21:47 PM PDT 24
Peak memory 210252 kb
Host smart-0a57d7d4-dd6f-4c33-9428-4dbb2e93296c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569403068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1569403068
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3403123628
Short name T174
Test name
Test status
Simulation time 2675345765 ps
CPU time 26.36 seconds
Started Aug 09 05:22:04 PM PDT 24
Finished Aug 09 05:22:30 PM PDT 24
Peak memory 221040 kb
Host smart-f52f94f9-ea40-4d32-98cc-5c21a871008b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403123628 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3403123628
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.784009085
Short name T297
Test name
Test status
Simulation time 308966975 ps
CPU time 3.82 seconds
Started Aug 09 05:22:09 PM PDT 24
Finished Aug 09 05:22:13 PM PDT 24
Peak memory 222436 kb
Host smart-191fd3df-65e0-4052-bdf3-57af182d483e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784009085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.784009085
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.960645642
Short name T108
Test name
Test status
Simulation time 4611420498 ps
CPU time 37.64 seconds
Started Aug 09 05:20:58 PM PDT 24
Finished Aug 09 05:21:36 PM PDT 24
Peak memory 215440 kb
Host smart-38357630-3fe5-43b2-9087-a9fbc7effe35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960645642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.960645642
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3433887310
Short name T237
Test name
Test status
Simulation time 122959348 ps
CPU time 5.73 seconds
Started Aug 09 05:22:45 PM PDT 24
Finished Aug 09 05:22:51 PM PDT 24
Peak memory 218496 kb
Host smart-db593be3-2a28-467f-965e-7a69aa132301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433887310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3433887310
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3684165768
Short name T346
Test name
Test status
Simulation time 278846587 ps
CPU time 4.2 seconds
Started Aug 09 05:22:51 PM PDT 24
Finished Aug 09 05:22:55 PM PDT 24
Peak memory 214364 kb
Host smart-f44c5e68-1abb-4738-8a11-ebee27860f2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3684165768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3684165768
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1278382247
Short name T121
Test name
Test status
Simulation time 157999594 ps
CPU time 7.89 seconds
Started Aug 09 05:22:51 PM PDT 24
Finished Aug 09 05:22:59 PM PDT 24
Peak memory 222584 kb
Host smart-caa82ed2-7d89-4bd9-bb36-33aca27e10b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278382247 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1278382247
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_random.1986210528
Short name T195
Test name
Test status
Simulation time 394119831 ps
CPU time 4.97 seconds
Started Aug 09 05:23:08 PM PDT 24
Finished Aug 09 05:23:13 PM PDT 24
Peak memory 214316 kb
Host smart-51bb1301-fd1c-41ed-a0cf-6b6d0a11c3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986210528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1986210528
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1072980747
Short name T255
Test name
Test status
Simulation time 38057431 ps
CPU time 2.68 seconds
Started Aug 09 05:21:12 PM PDT 24
Finished Aug 09 05:21:15 PM PDT 24
Peak memory 215168 kb
Host smart-50ee21c9-2654-42eb-a339-e43cab184467
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072980747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1072980747
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2631173107
Short name T285
Test name
Test status
Simulation time 450133805 ps
CPU time 2.75 seconds
Started Aug 09 05:23:41 PM PDT 24
Finished Aug 09 05:23:44 PM PDT 24
Peak memory 214188 kb
Host smart-b90739c4-f08d-43a1-a6e8-e7c6ea95d38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631173107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2631173107
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1186856653
Short name T151
Test name
Test status
Simulation time 282275420 ps
CPU time 10.25 seconds
Started Aug 09 05:40:31 PM PDT 24
Finished Aug 09 05:40:41 PM PDT 24
Peak memory 214404 kb
Host smart-5991f649-3a96-4ebe-b338-c3841e6760ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186856653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1186856653
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3070679344
Short name T157
Test name
Test status
Simulation time 255640179 ps
CPU time 7.06 seconds
Started Aug 09 05:40:46 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 214156 kb
Host smart-dc375f8e-bf34-4c21-b571-2ef0521411d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070679344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3070679344
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2687974296
Short name T155
Test name
Test status
Simulation time 103111959 ps
CPU time 4.68 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:17 PM PDT 24
Peak memory 206140 kb
Host smart-0a079c24-e244-4023-a82d-da182da8ceb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687974296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2687974296
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1143362404
Short name T154
Test name
Test status
Simulation time 180730637 ps
CPU time 5.56 seconds
Started Aug 09 05:40:26 PM PDT 24
Finished Aug 09 05:40:32 PM PDT 24
Peak memory 214304 kb
Host smart-d30a6313-8597-4c19-a79c-1a1b8615c11d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143362404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1143362404
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1718873380
Short name T31
Test name
Test status
Simulation time 70155477 ps
CPU time 2.96 seconds
Started Aug 09 05:22:58 PM PDT 24
Finished Aug 09 05:23:01 PM PDT 24
Peak memory 210424 kb
Host smart-730c7070-d71e-466c-9e98-47e9c6428ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718873380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1718873380
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3995230393
Short name T147
Test name
Test status
Simulation time 69554995 ps
CPU time 2.13 seconds
Started Aug 09 05:23:32 PM PDT 24
Finished Aug 09 05:23:34 PM PDT 24
Peak memory 215408 kb
Host smart-1701e711-cef3-46d9-b6a7-dbb0ada16928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995230393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3995230393
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3486927814
Short name T53
Test name
Test status
Simulation time 360936169 ps
CPU time 4.87 seconds
Started Aug 09 05:21:53 PM PDT 24
Finished Aug 09 05:21:58 PM PDT 24
Peak memory 217708 kb
Host smart-7a022888-4bb7-4ec4-9f84-f4c0103f7549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486927814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3486927814
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.4022040602
Short name T218
Test name
Test status
Simulation time 898416861 ps
CPU time 5.27 seconds
Started Aug 09 05:20:43 PM PDT 24
Finished Aug 09 05:20:48 PM PDT 24
Peak memory 214224 kb
Host smart-23259563-fcdd-4f47-b7eb-221d5f1013e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022040602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.4022040602
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1775926019
Short name T905
Test name
Test status
Simulation time 47548388 ps
CPU time 2.18 seconds
Started Aug 09 05:20:43 PM PDT 24
Finished Aug 09 05:20:45 PM PDT 24
Peak memory 209648 kb
Host smart-6390d18f-b3a7-43d2-89e9-319e3634ac2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775926019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1775926019
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2141866742
Short name T25
Test name
Test status
Simulation time 640574178 ps
CPU time 6.66 seconds
Started Aug 09 05:20:52 PM PDT 24
Finished Aug 09 05:20:58 PM PDT 24
Peak memory 214268 kb
Host smart-bb202ea8-4415-4a08-a85c-dd6956c2c87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141866742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2141866742
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2887237954
Short name T78
Test name
Test status
Simulation time 14685091163 ps
CPU time 24.54 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:22:00 PM PDT 24
Peak memory 222628 kb
Host smart-245a89d9-ac8f-4aaf-96e6-077b533926bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887237954 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2887237954
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3602736792
Short name T248
Test name
Test status
Simulation time 80436035 ps
CPU time 2.1 seconds
Started Aug 09 05:22:05 PM PDT 24
Finished Aug 09 05:22:07 PM PDT 24
Peak memory 220252 kb
Host smart-ae977788-9a01-4d8f-9282-d7b35b8cc08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602736792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3602736792
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.902894691
Short name T38
Test name
Test status
Simulation time 55587895 ps
CPU time 1.92 seconds
Started Aug 09 05:22:03 PM PDT 24
Finished Aug 09 05:22:05 PM PDT 24
Peak memory 209932 kb
Host smart-324b9007-ee7f-41da-870a-4eb68a85c3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902894691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.902894691
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3049920196
Short name T47
Test name
Test status
Simulation time 371148220 ps
CPU time 14.33 seconds
Started Aug 09 05:22:11 PM PDT 24
Finished Aug 09 05:22:25 PM PDT 24
Peak memory 222256 kb
Host smart-92e2b1f9-403e-40ab-9b7b-593855a7e48b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049920196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3049920196
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1769874334
Short name T224
Test name
Test status
Simulation time 6182202858 ps
CPU time 39.65 seconds
Started Aug 09 05:22:25 PM PDT 24
Finished Aug 09 05:23:05 PM PDT 24
Peak memory 215284 kb
Host smart-38d95425-3018-4c2b-b241-4281d5a58080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769874334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1769874334
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1746064090
Short name T318
Test name
Test status
Simulation time 4332244246 ps
CPU time 44.51 seconds
Started Aug 09 05:22:33 PM PDT 24
Finished Aug 09 05:23:18 PM PDT 24
Peak memory 216788 kb
Host smart-c198335e-5e31-4d19-b700-00f18ae89e22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746064090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1746064090
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2580571348
Short name T221
Test name
Test status
Simulation time 608485736 ps
CPU time 9.45 seconds
Started Aug 09 05:22:32 PM PDT 24
Finished Aug 09 05:22:42 PM PDT 24
Peak memory 222516 kb
Host smart-9ed48081-d7be-4158-ae31-3c67d46bafc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580571348 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2580571348
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.359307873
Short name T206
Test name
Test status
Simulation time 130256257 ps
CPU time 6.3 seconds
Started Aug 09 05:22:35 PM PDT 24
Finished Aug 09 05:22:42 PM PDT 24
Peak memory 218772 kb
Host smart-59c87426-38b1-4746-aa55-4011f0404294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359307873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.359307873
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1584991392
Short name T802
Test name
Test status
Simulation time 3687963830 ps
CPU time 51.55 seconds
Started Aug 09 05:22:42 PM PDT 24
Finished Aug 09 05:23:33 PM PDT 24
Peak memory 222244 kb
Host smart-1cd648c9-2890-422d-865b-0683169c2ca8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584991392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1584991392
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.4026335994
Short name T264
Test name
Test status
Simulation time 9043644947 ps
CPU time 121.09 seconds
Started Aug 09 05:22:52 PM PDT 24
Finished Aug 09 05:24:53 PM PDT 24
Peak memory 218484 kb
Host smart-04a6342c-4400-40dd-901b-e6e0a6adbe13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026335994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.4026335994
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.526725530
Short name T96
Test name
Test status
Simulation time 96423385 ps
CPU time 3.37 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:22:59 PM PDT 24
Peak memory 214244 kb
Host smart-1a455fc2-f75e-4c4b-adfc-739fa6519790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526725530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.526725530
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.494238290
Short name T378
Test name
Test status
Simulation time 909791804 ps
CPU time 7.54 seconds
Started Aug 09 05:23:04 PM PDT 24
Finished Aug 09 05:23:12 PM PDT 24
Peak memory 214252 kb
Host smart-aa9e115e-358b-4a67-add2-8261548afb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494238290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.494238290
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.4048727713
Short name T211
Test name
Test status
Simulation time 3658929658 ps
CPU time 22.97 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:26 PM PDT 24
Peak memory 214292 kb
Host smart-7731eb55-7422-4cd5-8a0c-7b814b87c2a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048727713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.4048727713
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.941660604
Short name T364
Test name
Test status
Simulation time 1431114901 ps
CPU time 11.64 seconds
Started Aug 09 05:23:10 PM PDT 24
Finished Aug 09 05:23:22 PM PDT 24
Peak memory 207744 kb
Host smart-910f9e98-2863-4a7e-a9b4-5b98973b560f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941660604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.941660604
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2383155935
Short name T371
Test name
Test status
Simulation time 102613515 ps
CPU time 4.63 seconds
Started Aug 09 05:23:16 PM PDT 24
Finished Aug 09 05:23:21 PM PDT 24
Peak memory 220680 kb
Host smart-12928420-e3be-4c80-918e-96e3fb1b7c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383155935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2383155935
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2597276789
Short name T314
Test name
Test status
Simulation time 534213394 ps
CPU time 10.84 seconds
Started Aug 09 05:21:22 PM PDT 24
Finished Aug 09 05:21:33 PM PDT 24
Peak memory 209636 kb
Host smart-b03c6334-da22-4def-98ce-aea7ac640c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597276789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2597276789
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.872418752
Short name T145
Test name
Test status
Simulation time 107704924 ps
CPU time 3.89 seconds
Started Aug 09 05:23:10 PM PDT 24
Finished Aug 09 05:23:14 PM PDT 24
Peak memory 222500 kb
Host smart-08fea0e6-f18a-4b4f-bb02-ce618bbc9edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872418752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.872418752
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.22163974
Short name T1067
Test name
Test status
Simulation time 412763421 ps
CPU time 9.48 seconds
Started Aug 09 05:40:07 PM PDT 24
Finished Aug 09 05:40:17 PM PDT 24
Peak memory 206064 kb
Host smart-3fef6320-5990-48b3-9e9d-3b1e2abb6a11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22163974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.22163974
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3473701434
Short name T991
Test name
Test status
Simulation time 2557492440 ps
CPU time 8.59 seconds
Started Aug 09 05:40:08 PM PDT 24
Finished Aug 09 05:40:16 PM PDT 24
Peak memory 206240 kb
Host smart-e01b8bf6-2914-4d80-a491-2c8d59a0f7aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473701434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
473701434
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1116903651
Short name T993
Test name
Test status
Simulation time 67433162 ps
CPU time 1.16 seconds
Started Aug 09 05:40:10 PM PDT 24
Finished Aug 09 05:40:11 PM PDT 24
Peak memory 206080 kb
Host smart-d18b0837-9d00-44b4-bb66-9ef8ce149579
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116903651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
116903651
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2143727386
Short name T1021
Test name
Test status
Simulation time 27264890 ps
CPU time 1.46 seconds
Started Aug 09 05:40:11 PM PDT 24
Finished Aug 09 05:40:13 PM PDT 24
Peak memory 206064 kb
Host smart-2ac0ff83-f353-4f54-a6ca-52dd53f8c94e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143727386 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2143727386
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.550826601
Short name T977
Test name
Test status
Simulation time 30457983 ps
CPU time 0.86 seconds
Started Aug 09 05:40:07 PM PDT 24
Finished Aug 09 05:40:09 PM PDT 24
Peak memory 205908 kb
Host smart-25b35191-00eb-4c1b-bf71-a2b18509fcbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550826601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.550826601
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2590244599
Short name T1017
Test name
Test status
Simulation time 37222829 ps
CPU time 0.72 seconds
Started Aug 09 05:40:08 PM PDT 24
Finished Aug 09 05:40:09 PM PDT 24
Peak memory 205832 kb
Host smart-4e2c7956-4434-4135-b5a1-f3d7de488b37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590244599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2590244599
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3098808447
Short name T1014
Test name
Test status
Simulation time 71059100 ps
CPU time 2.09 seconds
Started Aug 09 05:40:10 PM PDT 24
Finished Aug 09 05:40:12 PM PDT 24
Peak memory 206152 kb
Host smart-ae6574ce-c6a2-444b-9761-3abd17774413
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098808447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3098808447
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2866858333
Short name T1076
Test name
Test status
Simulation time 98738139 ps
CPU time 1.53 seconds
Started Aug 09 05:40:08 PM PDT 24
Finished Aug 09 05:40:10 PM PDT 24
Peak memory 214712 kb
Host smart-b0a5a1db-811e-411e-8284-ad8c28743f6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866858333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2866858333
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3924926446
Short name T947
Test name
Test status
Simulation time 171796394 ps
CPU time 4.44 seconds
Started Aug 09 05:40:07 PM PDT 24
Finished Aug 09 05:40:12 PM PDT 24
Peak memory 214680 kb
Host smart-4a47aa4d-8fcf-4858-9dde-af3f8e9c83cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924926446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3924926446
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2782428571
Short name T1016
Test name
Test status
Simulation time 313475012 ps
CPU time 1.99 seconds
Started Aug 09 05:40:10 PM PDT 24
Finished Aug 09 05:40:12 PM PDT 24
Peak memory 214316 kb
Host smart-ad810e72-5802-43e4-a86c-18e60994bda4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782428571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2782428571
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2177201509
Short name T149
Test name
Test status
Simulation time 402962136 ps
CPU time 5.69 seconds
Started Aug 09 05:40:09 PM PDT 24
Finished Aug 09 05:40:15 PM PDT 24
Peak memory 215452 kb
Host smart-888059bb-d594-4fe2-bd3a-d0a6433374d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177201509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2177201509
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1652906554
Short name T133
Test name
Test status
Simulation time 257633598 ps
CPU time 9.12 seconds
Started Aug 09 05:40:12 PM PDT 24
Finished Aug 09 05:40:21 PM PDT 24
Peak memory 206188 kb
Host smart-8057956a-7cc4-4377-b7fe-c6752216c657
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652906554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
652906554
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.318547174
Short name T972
Test name
Test status
Simulation time 1292551885 ps
CPU time 30.25 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:44 PM PDT 24
Peak memory 206220 kb
Host smart-16e617ac-8900-45c4-8847-754223459e53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318547174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.318547174
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2560568366
Short name T928
Test name
Test status
Simulation time 32941050 ps
CPU time 0.98 seconds
Started Aug 09 05:40:11 PM PDT 24
Finished Aug 09 05:40:12 PM PDT 24
Peak memory 205848 kb
Host smart-9e1dd4b9-6b22-4d0a-9588-e9be57b2ef20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560568366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
560568366
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1190205355
Short name T960
Test name
Test status
Simulation time 175089806 ps
CPU time 1.54 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:15 PM PDT 24
Peak memory 214336 kb
Host smart-e5a05252-ba3b-4f69-8ce1-e35e5e51801d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190205355 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1190205355
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1905434792
Short name T1020
Test name
Test status
Simulation time 25668699 ps
CPU time 0.98 seconds
Started Aug 09 05:40:12 PM PDT 24
Finished Aug 09 05:40:14 PM PDT 24
Peak memory 206152 kb
Host smart-94deeb69-f40c-40e3-abf7-9567374dc21b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905434792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1905434792
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3269260038
Short name T926
Test name
Test status
Simulation time 20203387 ps
CPU time 0.71 seconds
Started Aug 09 05:40:07 PM PDT 24
Finished Aug 09 05:40:08 PM PDT 24
Peak memory 205808 kb
Host smart-6ac88ad3-1a31-4115-9d80-24781cdb00e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269260038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3269260038
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2283604355
Short name T1046
Test name
Test status
Simulation time 110184330 ps
CPU time 1.95 seconds
Started Aug 09 05:40:11 PM PDT 24
Finished Aug 09 05:40:13 PM PDT 24
Peak memory 206024 kb
Host smart-7d698355-5e3d-4d64-9bee-9c51f11d088c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283604355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2283604355
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1130239791
Short name T943
Test name
Test status
Simulation time 35601231 ps
CPU time 1.39 seconds
Started Aug 09 05:40:07 PM PDT 24
Finished Aug 09 05:40:09 PM PDT 24
Peak memory 214652 kb
Host smart-3a2f4518-a34d-4b5c-a41d-2f275a083889
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130239791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1130239791
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.521869451
Short name T982
Test name
Test status
Simulation time 285503451 ps
CPU time 7.84 seconds
Started Aug 09 05:40:07 PM PDT 24
Finished Aug 09 05:40:15 PM PDT 24
Peak memory 221120 kb
Host smart-4017fe13-1cb4-4c22-b222-0b44d34abd06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521869451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.521869451
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2755202147
Short name T935
Test name
Test status
Simulation time 306867106 ps
CPU time 3.08 seconds
Started Aug 09 05:40:08 PM PDT 24
Finished Aug 09 05:40:11 PM PDT 24
Peak memory 214348 kb
Host smart-f06d967e-6cab-43cf-bda9-e9eeb8986c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755202147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2755202147
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1371092198
Short name T1087
Test name
Test status
Simulation time 557392883 ps
CPU time 10.02 seconds
Started Aug 09 05:40:07 PM PDT 24
Finished Aug 09 05:40:17 PM PDT 24
Peak memory 214292 kb
Host smart-73c69fee-bb6e-454e-88be-9be7090dcf34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371092198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1371092198
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1889981350
Short name T1024
Test name
Test status
Simulation time 28005420 ps
CPU time 1.22 seconds
Started Aug 09 05:40:27 PM PDT 24
Finished Aug 09 05:40:29 PM PDT 24
Peak memory 214284 kb
Host smart-017050ae-f84d-4f08-a911-4e70b4a3ee8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889981350 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1889981350
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2095900545
Short name T1045
Test name
Test status
Simulation time 21523053 ps
CPU time 0.95 seconds
Started Aug 09 05:40:26 PM PDT 24
Finished Aug 09 05:40:28 PM PDT 24
Peak memory 205944 kb
Host smart-59e51d5a-688b-4956-a7dd-8c35b61ff05e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095900545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2095900545
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1942821529
Short name T1091
Test name
Test status
Simulation time 22831051 ps
CPU time 0.71 seconds
Started Aug 09 05:40:32 PM PDT 24
Finished Aug 09 05:40:33 PM PDT 24
Peak memory 205832 kb
Host smart-81863303-7031-4d7b-81c2-644342a79611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942821529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1942821529
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1927109557
Short name T1000
Test name
Test status
Simulation time 778164734 ps
CPU time 2.81 seconds
Started Aug 09 05:40:29 PM PDT 24
Finished Aug 09 05:40:32 PM PDT 24
Peak memory 214316 kb
Host smart-43de8259-ba57-4f6b-924e-71ad26156f55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927109557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1927109557
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1062287129
Short name T116
Test name
Test status
Simulation time 491466130 ps
CPU time 2.04 seconds
Started Aug 09 05:40:29 PM PDT 24
Finished Aug 09 05:40:31 PM PDT 24
Peak memory 214724 kb
Host smart-23372ce8-1710-42f5-b4c5-c7a5fd935d66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062287129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1062287129
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3792346949
Short name T1047
Test name
Test status
Simulation time 573310175 ps
CPU time 8.17 seconds
Started Aug 09 05:40:27 PM PDT 24
Finished Aug 09 05:40:35 PM PDT 24
Peak memory 220784 kb
Host smart-ca6baced-e281-4de0-8b95-1258327f146e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792346949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3792346949
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.72878233
Short name T1073
Test name
Test status
Simulation time 43673066 ps
CPU time 2.79 seconds
Started Aug 09 05:40:32 PM PDT 24
Finished Aug 09 05:40:35 PM PDT 24
Peak memory 214336 kb
Host smart-d85cd01b-b4c4-409a-b2d3-9de71fe4682c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72878233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.72878233
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3933511349
Short name T1001
Test name
Test status
Simulation time 35426760 ps
CPU time 1.91 seconds
Started Aug 09 05:40:29 PM PDT 24
Finished Aug 09 05:40:31 PM PDT 24
Peak memory 214324 kb
Host smart-bf297c18-088e-4252-b4d8-266562eeb579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933511349 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3933511349
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2360008295
Short name T1084
Test name
Test status
Simulation time 32151771 ps
CPU time 0.92 seconds
Started Aug 09 05:40:28 PM PDT 24
Finished Aug 09 05:40:29 PM PDT 24
Peak memory 205812 kb
Host smart-d1e60682-5fcd-43fb-9a31-8bb9abdb1600
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360008295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2360008295
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2355942926
Short name T1088
Test name
Test status
Simulation time 11767817 ps
CPU time 0.8 seconds
Started Aug 09 05:40:27 PM PDT 24
Finished Aug 09 05:40:28 PM PDT 24
Peak memory 205908 kb
Host smart-f7b6f44d-df00-4882-90e8-356f266e0647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355942926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2355942926
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3892568645
Short name T1008
Test name
Test status
Simulation time 24093449 ps
CPU time 1.51 seconds
Started Aug 09 05:40:27 PM PDT 24
Finished Aug 09 05:40:29 PM PDT 24
Peak memory 206072 kb
Host smart-412999db-433d-4ddb-9944-7471a1e28d59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892568645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3892568645
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2951480981
Short name T1015
Test name
Test status
Simulation time 175853812 ps
CPU time 4 seconds
Started Aug 09 05:40:26 PM PDT 24
Finished Aug 09 05:40:30 PM PDT 24
Peak memory 214604 kb
Host smart-19142e2f-56c9-46a1-87be-c8bafb3c709c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951480981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2951480981
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.77373855
Short name T1057
Test name
Test status
Simulation time 1284057148 ps
CPU time 12.68 seconds
Started Aug 09 05:40:32 PM PDT 24
Finished Aug 09 05:40:45 PM PDT 24
Peak memory 214564 kb
Host smart-8fed4cb5-0eb8-4cd1-a631-88bb1584398b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77373855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.k
eymgr_shadow_reg_errors_with_csr_rw.77373855
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3286489186
Short name T979
Test name
Test status
Simulation time 1310238704 ps
CPU time 3.37 seconds
Started Aug 09 05:40:29 PM PDT 24
Finished Aug 09 05:40:32 PM PDT 24
Peak memory 214408 kb
Host smart-b87a9213-b158-4879-91c0-044274909b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286489186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3286489186
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3603672171
Short name T1094
Test name
Test status
Simulation time 439194447 ps
CPU time 4.62 seconds
Started Aug 09 05:40:28 PM PDT 24
Finished Aug 09 05:40:32 PM PDT 24
Peak memory 214352 kb
Host smart-15275565-2669-46b3-803f-620714ef7dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603672171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3603672171
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1966177658
Short name T152
Test name
Test status
Simulation time 166196060 ps
CPU time 1.92 seconds
Started Aug 09 05:40:37 PM PDT 24
Finished Aug 09 05:40:39 PM PDT 24
Peak memory 214316 kb
Host smart-5aa6b165-685d-46c4-ac33-57fec59a423c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966177658 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1966177658
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3034068243
Short name T965
Test name
Test status
Simulation time 54523221 ps
CPU time 1.17 seconds
Started Aug 09 05:40:38 PM PDT 24
Finished Aug 09 05:40:39 PM PDT 24
Peak memory 206036 kb
Host smart-d042653b-fe70-4940-bfe0-9f59a3364ed0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034068243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3034068243
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3940302621
Short name T994
Test name
Test status
Simulation time 10892125 ps
CPU time 0.72 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:37 PM PDT 24
Peak memory 205836 kb
Host smart-1b960560-a932-416c-99d7-57bfa781b8df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940302621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3940302621
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2979807122
Short name T136
Test name
Test status
Simulation time 221920370 ps
CPU time 2.21 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:38 PM PDT 24
Peak memory 206156 kb
Host smart-55796719-cd1c-41d0-b690-e530ebcbeea2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979807122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2979807122
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.457815494
Short name T978
Test name
Test status
Simulation time 162071047 ps
CPU time 4.39 seconds
Started Aug 09 05:40:29 PM PDT 24
Finished Aug 09 05:40:34 PM PDT 24
Peak memory 214584 kb
Host smart-ea4f3255-db04-4687-bcdd-48d48c26fbd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457815494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.457815494
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2328667396
Short name T970
Test name
Test status
Simulation time 306509468 ps
CPU time 3.33 seconds
Started Aug 09 05:40:29 PM PDT 24
Finished Aug 09 05:40:33 PM PDT 24
Peak memory 214580 kb
Host smart-4575c908-1ff7-48fe-8613-e60e0f78a451
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328667396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2328667396
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3858403519
Short name T995
Test name
Test status
Simulation time 291543236 ps
CPU time 3.19 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:39 PM PDT 24
Peak memory 214364 kb
Host smart-1da0b745-2035-4d92-83ec-261ace436e96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858403519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3858403519
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2351421974
Short name T984
Test name
Test status
Simulation time 65595058 ps
CPU time 3.27 seconds
Started Aug 09 05:40:35 PM PDT 24
Finished Aug 09 05:40:39 PM PDT 24
Peak memory 214256 kb
Host smart-3e75fa04-6f64-4052-ab85-47705f9af6bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351421974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2351421974
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.590631510
Short name T985
Test name
Test status
Simulation time 55738357 ps
CPU time 1.34 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:37 PM PDT 24
Peak memory 214356 kb
Host smart-872b244d-f0b8-4a32-9ba1-9ca3b878deed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590631510 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.590631510
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1332638315
Short name T1037
Test name
Test status
Simulation time 144563172 ps
CPU time 1.24 seconds
Started Aug 09 05:40:35 PM PDT 24
Finished Aug 09 05:40:37 PM PDT 24
Peak memory 206096 kb
Host smart-c560c0bc-a25c-41f2-9e53-273555f744df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332638315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1332638315
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1299963780
Short name T971
Test name
Test status
Simulation time 23782344 ps
CPU time 0.84 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:37 PM PDT 24
Peak memory 205884 kb
Host smart-bb341b17-0731-49d4-a463-01be07cbe492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299963780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1299963780
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.544443400
Short name T951
Test name
Test status
Simulation time 56235220 ps
CPU time 2.12 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:38 PM PDT 24
Peak memory 206024 kb
Host smart-587787b2-c26f-4d06-a872-cfc6f5a5e321
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544443400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.544443400
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3678712851
Short name T1044
Test name
Test status
Simulation time 287132944 ps
CPU time 6.49 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:43 PM PDT 24
Peak memory 214692 kb
Host smart-b4306792-868e-4f6c-93d6-e2298b9674d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678712851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3678712851
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1344469362
Short name T1002
Test name
Test status
Simulation time 52309364 ps
CPU time 2.04 seconds
Started Aug 09 05:40:33 PM PDT 24
Finished Aug 09 05:40:35 PM PDT 24
Peak memory 214512 kb
Host smart-9d24f343-11b6-4a10-91d9-34b2b4565093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344469362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1344469362
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1853168907
Short name T168
Test name
Test status
Simulation time 182705957 ps
CPU time 4.35 seconds
Started Aug 09 05:40:35 PM PDT 24
Finished Aug 09 05:40:39 PM PDT 24
Peak memory 214356 kb
Host smart-d6df0418-51d2-413f-a97d-88f004b0e104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853168907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1853168907
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1266985443
Short name T1083
Test name
Test status
Simulation time 55360746 ps
CPU time 2.34 seconds
Started Aug 09 05:40:39 PM PDT 24
Finished Aug 09 05:40:41 PM PDT 24
Peak memory 214328 kb
Host smart-ed99f3e8-869b-44bf-ab7e-74c7b6c9952f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266985443 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1266985443
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.48128609
Short name T1069
Test name
Test status
Simulation time 23357634 ps
CPU time 0.92 seconds
Started Aug 09 05:40:37 PM PDT 24
Finished Aug 09 05:40:38 PM PDT 24
Peak memory 205924 kb
Host smart-d2d4f49c-3c51-471c-910d-cc6a0b9783a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48128609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.48128609
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2666962218
Short name T967
Test name
Test status
Simulation time 32326259 ps
CPU time 0.76 seconds
Started Aug 09 05:40:38 PM PDT 24
Finished Aug 09 05:40:39 PM PDT 24
Peak memory 205780 kb
Host smart-c5324f33-d1a3-4b35-9f80-2cd4baf2a6af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666962218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2666962218
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3461301653
Short name T1019
Test name
Test status
Simulation time 37894237 ps
CPU time 2.44 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:39 PM PDT 24
Peak memory 206152 kb
Host smart-be789246-ea61-40e5-83b0-f23b39f7ea77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461301653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3461301653
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.301555705
Short name T117
Test name
Test status
Simulation time 305389101 ps
CPU time 2.17 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:38 PM PDT 24
Peak memory 214620 kb
Host smart-b4d6b56f-d7a0-427f-b1ae-52841bbca54d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301555705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.301555705
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3340535641
Short name T980
Test name
Test status
Simulation time 691681092 ps
CPU time 6.24 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:42 PM PDT 24
Peak memory 214648 kb
Host smart-81634c23-fe19-42ed-b713-89b872323710
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340535641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3340535641
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2351798240
Short name T1080
Test name
Test status
Simulation time 1543592349 ps
CPU time 2.32 seconds
Started Aug 09 05:40:39 PM PDT 24
Finished Aug 09 05:40:41 PM PDT 24
Peak memory 214288 kb
Host smart-b85bb207-cafe-4b40-a115-784248d9b9bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351798240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2351798240
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1875434026
Short name T148
Test name
Test status
Simulation time 151261004 ps
CPU time 4.13 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:41 PM PDT 24
Peak memory 214304 kb
Host smart-39beec7a-e80e-4808-a7d7-afad72bd3077
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875434026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1875434026
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2933151591
Short name T1009
Test name
Test status
Simulation time 97364845 ps
CPU time 1.04 seconds
Started Aug 09 05:40:35 PM PDT 24
Finished Aug 09 05:40:37 PM PDT 24
Peak memory 205992 kb
Host smart-68a7e4bb-a898-4706-afc1-47338dd9ce3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933151591 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2933151591
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2531589316
Short name T949
Test name
Test status
Simulation time 26758894 ps
CPU time 0.98 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:37 PM PDT 24
Peak memory 205924 kb
Host smart-d62a91e4-8093-4204-aaa0-1e4eb73870d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531589316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2531589316
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3515358817
Short name T1023
Test name
Test status
Simulation time 11028839 ps
CPU time 0.76 seconds
Started Aug 09 05:40:35 PM PDT 24
Finished Aug 09 05:40:36 PM PDT 24
Peak memory 205884 kb
Host smart-62079fee-2426-453d-914e-4df5976cc33f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515358817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3515358817
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1780545767
Short name T132
Test name
Test status
Simulation time 49534550 ps
CPU time 1.37 seconds
Started Aug 09 05:40:35 PM PDT 24
Finished Aug 09 05:40:37 PM PDT 24
Peak memory 206120 kb
Host smart-a8b97bea-a4c0-457e-96d3-67e793eb8325
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780545767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1780545767
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.805139710
Short name T1075
Test name
Test status
Simulation time 277802361 ps
CPU time 2.71 seconds
Started Aug 09 05:40:36 PM PDT 24
Finished Aug 09 05:40:39 PM PDT 24
Peak memory 214612 kb
Host smart-cc806489-f5e9-4b53-96fb-576d832c1889
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805139710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.805139710
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3920439520
Short name T961
Test name
Test status
Simulation time 86247717 ps
CPU time 2.6 seconds
Started Aug 09 05:40:37 PM PDT 24
Finished Aug 09 05:40:40 PM PDT 24
Peak memory 215412 kb
Host smart-fba8f6a0-6b8c-4e38-a80f-3f3fcf40a9f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920439520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3920439520
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.399161783
Short name T933
Test name
Test status
Simulation time 29001695 ps
CPU time 1.59 seconds
Started Aug 09 05:40:46 PM PDT 24
Finished Aug 09 05:40:48 PM PDT 24
Peak memory 214380 kb
Host smart-90542ffd-d863-4384-b282-fb81370907cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399161783 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.399161783
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3056648964
Short name T131
Test name
Test status
Simulation time 14813636 ps
CPU time 0.84 seconds
Started Aug 09 05:40:48 PM PDT 24
Finished Aug 09 05:40:49 PM PDT 24
Peak memory 205876 kb
Host smart-9cf3c57f-0e09-4960-89f5-6992310b44c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056648964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3056648964
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.71505517
Short name T1029
Test name
Test status
Simulation time 36489935 ps
CPU time 0.78 seconds
Started Aug 09 05:40:42 PM PDT 24
Finished Aug 09 05:40:42 PM PDT 24
Peak memory 205872 kb
Host smart-1f8e6d14-b483-4b9b-b384-ce0675c26d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71505517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.71505517
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2558119173
Short name T953
Test name
Test status
Simulation time 32158499 ps
CPU time 1.89 seconds
Started Aug 09 05:40:44 PM PDT 24
Finished Aug 09 05:40:46 PM PDT 24
Peak memory 206108 kb
Host smart-034f87bb-bb6f-4cf8-857b-19c5aa47f127
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558119173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2558119173
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1641576948
Short name T114
Test name
Test status
Simulation time 285574039 ps
CPU time 2.93 seconds
Started Aug 09 05:40:48 PM PDT 24
Finished Aug 09 05:40:51 PM PDT 24
Peak memory 214544 kb
Host smart-fcd7252a-4236-41cf-8b45-152100092048
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641576948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1641576948
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3331604850
Short name T1096
Test name
Test status
Simulation time 182623140 ps
CPU time 8.93 seconds
Started Aug 09 05:40:45 PM PDT 24
Finished Aug 09 05:40:54 PM PDT 24
Peak memory 214536 kb
Host smart-bb78d7a1-4716-4bbb-b184-db39f6d2b73f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331604850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3331604850
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.843221144
Short name T1018
Test name
Test status
Simulation time 135366122 ps
CPU time 3.06 seconds
Started Aug 09 05:40:44 PM PDT 24
Finished Aug 09 05:40:47 PM PDT 24
Peak memory 217472 kb
Host smart-1d11f46a-d661-4788-8e24-d30b459716a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843221144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.843221144
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.884831560
Short name T1050
Test name
Test status
Simulation time 44794631 ps
CPU time 2.08 seconds
Started Aug 09 05:40:44 PM PDT 24
Finished Aug 09 05:40:46 PM PDT 24
Peak memory 222564 kb
Host smart-8cc8aa64-9967-4cdb-b7e8-edb4d0b8e181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884831560 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.884831560
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.154977583
Short name T1078
Test name
Test status
Simulation time 220831121 ps
CPU time 1.44 seconds
Started Aug 09 05:40:45 PM PDT 24
Finished Aug 09 05:40:46 PM PDT 24
Peak memory 206092 kb
Host smart-0cf518db-311c-44aa-a2f9-720cc1710077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154977583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.154977583
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1351947536
Short name T1074
Test name
Test status
Simulation time 14636909 ps
CPU time 0.84 seconds
Started Aug 09 05:40:47 PM PDT 24
Finished Aug 09 05:40:48 PM PDT 24
Peak memory 205860 kb
Host smart-fb0745cb-aa0e-4c3c-9b20-d92c5823cefe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351947536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1351947536
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2700080985
Short name T1030
Test name
Test status
Simulation time 39652895 ps
CPU time 1.46 seconds
Started Aug 09 05:40:43 PM PDT 24
Finished Aug 09 05:40:44 PM PDT 24
Peak memory 206056 kb
Host smart-6072e8ac-51dc-4c41-b307-a329d1f5738e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700080985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2700080985
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3091446857
Short name T1048
Test name
Test status
Simulation time 40533844 ps
CPU time 1.69 seconds
Started Aug 09 05:40:47 PM PDT 24
Finished Aug 09 05:40:49 PM PDT 24
Peak memory 214684 kb
Host smart-dd4c5eeb-7388-49dd-86ca-8146d9091f65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091446857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3091446857
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2153952620
Short name T1062
Test name
Test status
Simulation time 271343041 ps
CPU time 4.21 seconds
Started Aug 09 05:40:43 PM PDT 24
Finished Aug 09 05:40:47 PM PDT 24
Peak memory 214504 kb
Host smart-fd1fa15a-b0c3-46b3-af92-3e0b8bb9e335
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153952620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2153952620
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2609480852
Short name T925
Test name
Test status
Simulation time 40323585 ps
CPU time 2.94 seconds
Started Aug 09 05:40:44 PM PDT 24
Finished Aug 09 05:40:47 PM PDT 24
Peak memory 214340 kb
Host smart-c95a5438-3241-44f3-848c-c495c3c556cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609480852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2609480852
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1729498522
Short name T165
Test name
Test status
Simulation time 80840586 ps
CPU time 3.66 seconds
Started Aug 09 05:40:42 PM PDT 24
Finished Aug 09 05:40:46 PM PDT 24
Peak memory 214256 kb
Host smart-2d129534-69ec-42f2-bec6-7fe450a79774
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729498522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1729498522
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2145897505
Short name T1031
Test name
Test status
Simulation time 83660523 ps
CPU time 1.99 seconds
Started Aug 09 05:40:46 PM PDT 24
Finished Aug 09 05:40:48 PM PDT 24
Peak memory 214360 kb
Host smart-d1f9b45f-8ca9-4b3b-994c-f7d350cc67fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145897505 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2145897505
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1609931347
Short name T997
Test name
Test status
Simulation time 73668275 ps
CPU time 0.97 seconds
Started Aug 09 05:40:43 PM PDT 24
Finished Aug 09 05:40:44 PM PDT 24
Peak memory 205872 kb
Host smart-bdd8da89-b7ef-484f-b00e-fbb1af9ea8d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609931347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1609931347
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.4274180118
Short name T959
Test name
Test status
Simulation time 15921521 ps
CPU time 0.94 seconds
Started Aug 09 05:40:45 PM PDT 24
Finished Aug 09 05:40:46 PM PDT 24
Peak memory 205988 kb
Host smart-d7988ba4-2dfd-41cc-b655-d42e3d7cf03e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274180118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4274180118
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2638907092
Short name T990
Test name
Test status
Simulation time 515913579 ps
CPU time 1.73 seconds
Started Aug 09 05:40:44 PM PDT 24
Finished Aug 09 05:40:46 PM PDT 24
Peak memory 206020 kb
Host smart-2d1cc445-98f3-4cd1-8432-083988a59c60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638907092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2638907092
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3172232823
Short name T999
Test name
Test status
Simulation time 254811530 ps
CPU time 2.54 seconds
Started Aug 09 05:40:46 PM PDT 24
Finished Aug 09 05:40:49 PM PDT 24
Peak memory 214704 kb
Host smart-8334d3aa-8d3a-46ef-9568-d9af9ebf6ab0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172232823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3172232823
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3861483310
Short name T138
Test name
Test status
Simulation time 187612926 ps
CPU time 4.74 seconds
Started Aug 09 05:40:44 PM PDT 24
Finished Aug 09 05:40:49 PM PDT 24
Peak memory 214580 kb
Host smart-a180e70f-0d10-4744-8e36-2596882d7c1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861483310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3861483310
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2888321753
Short name T954
Test name
Test status
Simulation time 94684999 ps
CPU time 2.81 seconds
Started Aug 09 05:40:45 PM PDT 24
Finished Aug 09 05:40:48 PM PDT 24
Peak memory 216820 kb
Host smart-f3ae5c42-6516-41bd-9aff-3b77e025740a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888321753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2888321753
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1925318043
Short name T934
Test name
Test status
Simulation time 15382844 ps
CPU time 1.25 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 214364 kb
Host smart-1fe04ee8-82fb-49f0-9ead-615f444de571
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925318043 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1925318043
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2164554479
Short name T134
Test name
Test status
Simulation time 12830768 ps
CPU time 1.18 seconds
Started Aug 09 05:40:54 PM PDT 24
Finished Aug 09 05:40:55 PM PDT 24
Peak memory 206048 kb
Host smart-883c328a-68db-4974-8f12-95a53c83206e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164554479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2164554479
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2652426401
Short name T1003
Test name
Test status
Simulation time 13331832 ps
CPU time 0.74 seconds
Started Aug 09 05:40:54 PM PDT 24
Finished Aug 09 05:40:55 PM PDT 24
Peak memory 205876 kb
Host smart-d5d260d7-7274-4681-adb6-449da8b33e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652426401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2652426401
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3871969075
Short name T1059
Test name
Test status
Simulation time 217194706 ps
CPU time 2.01 seconds
Started Aug 09 05:40:50 PM PDT 24
Finished Aug 09 05:40:52 PM PDT 24
Peak memory 206028 kb
Host smart-9e185d2f-a45c-4015-bf87-1aeba62d8aff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871969075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3871969075
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1422446754
Short name T942
Test name
Test status
Simulation time 315197935 ps
CPU time 2.34 seconds
Started Aug 09 05:40:54 PM PDT 24
Finished Aug 09 05:40:56 PM PDT 24
Peak memory 214768 kb
Host smart-636ebd35-a3c7-4660-876f-7f12aa78b3fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422446754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1422446754
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2795425860
Short name T975
Test name
Test status
Simulation time 1271856784 ps
CPU time 13.9 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:41:06 PM PDT 24
Peak memory 214764 kb
Host smart-9364165e-69b0-4e60-b72b-b4b74a9efa88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795425860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2795425860
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1399765780
Short name T927
Test name
Test status
Simulation time 226844131 ps
CPU time 1.59 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:40:54 PM PDT 24
Peak memory 216368 kb
Host smart-bd64ddc1-6af4-462f-b0ed-9c35e237e98f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399765780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1399765780
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.599230585
Short name T1058
Test name
Test status
Simulation time 363180225 ps
CPU time 13.46 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:26 PM PDT 24
Peak memory 206036 kb
Host smart-faf0f63b-e518-437e-bcfa-79ce6369797b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599230585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.599230585
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.799892458
Short name T962
Test name
Test status
Simulation time 643004447 ps
CPU time 14.16 seconds
Started Aug 09 05:40:14 PM PDT 24
Finished Aug 09 05:40:29 PM PDT 24
Peak memory 206100 kb
Host smart-945a78c7-2e9f-42e5-a19f-057347bb781d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799892458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.799892458
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.105058211
Short name T1054
Test name
Test status
Simulation time 164502884 ps
CPU time 1.2 seconds
Started Aug 09 05:40:16 PM PDT 24
Finished Aug 09 05:40:18 PM PDT 24
Peak memory 206072 kb
Host smart-49f3a59c-52ff-4910-a835-7bc131ee6752
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105058211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.105058211
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1426130193
Short name T998
Test name
Test status
Simulation time 231369195 ps
CPU time 1.68 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:15 PM PDT 24
Peak memory 214436 kb
Host smart-f2ebcb98-f1cc-4215-98ff-097d70b5c8cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426130193 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1426130193
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1156795398
Short name T1086
Test name
Test status
Simulation time 32185047 ps
CPU time 1.2 seconds
Started Aug 09 05:40:12 PM PDT 24
Finished Aug 09 05:40:14 PM PDT 24
Peak memory 206012 kb
Host smart-9b866e12-cc43-4498-9951-6e28f5ffa241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156795398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1156795398
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.19849541
Short name T964
Test name
Test status
Simulation time 12009366 ps
CPU time 0.86 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:14 PM PDT 24
Peak memory 205888 kb
Host smart-87dd21aa-d6d6-4cf7-b8cb-bf2421cc2eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19849541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.19849541
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1077015339
Short name T955
Test name
Test status
Simulation time 20798665 ps
CPU time 1.58 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:15 PM PDT 24
Peak memory 206188 kb
Host smart-be744979-0ce9-46b3-a360-546db96703ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077015339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1077015339
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2324903695
Short name T992
Test name
Test status
Simulation time 676858589 ps
CPU time 4.89 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:18 PM PDT 24
Peak memory 214680 kb
Host smart-ac0e2bf1-5b7a-4c55-bbbc-b4f6a2b1c8cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324903695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2324903695
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2011761427
Short name T1010
Test name
Test status
Simulation time 553715526 ps
CPU time 9.87 seconds
Started Aug 09 05:40:16 PM PDT 24
Finished Aug 09 05:40:26 PM PDT 24
Peak memory 214432 kb
Host smart-aeaf173f-a00d-4edf-b4e1-cb1a55e24d92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011761427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2011761427
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1949977017
Short name T1013
Test name
Test status
Simulation time 17556626 ps
CPU time 1.31 seconds
Started Aug 09 05:40:11 PM PDT 24
Finished Aug 09 05:40:12 PM PDT 24
Peak memory 214460 kb
Host smart-c8f31085-48df-4195-a380-b8924a148140
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949977017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1949977017
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3543710543
Short name T158
Test name
Test status
Simulation time 102652218 ps
CPU time 5.28 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:18 PM PDT 24
Peak memory 206808 kb
Host smart-0472975f-d007-4c9b-98e3-db3d0fe46c9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543710543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3543710543
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1665594678
Short name T938
Test name
Test status
Simulation time 10210032 ps
CPU time 0.74 seconds
Started Aug 09 05:40:53 PM PDT 24
Finished Aug 09 05:40:54 PM PDT 24
Peak memory 205936 kb
Host smart-2c7dd998-87d9-4704-8f7d-b578d340b422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665594678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1665594678
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.782768331
Short name T1006
Test name
Test status
Simulation time 162245610 ps
CPU time 0.75 seconds
Started Aug 09 05:40:51 PM PDT 24
Finished Aug 09 05:40:52 PM PDT 24
Peak memory 205784 kb
Host smart-747a0906-6921-4483-8b0c-be10f0abc37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782768331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.782768331
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2540947662
Short name T1035
Test name
Test status
Simulation time 19564809 ps
CPU time 0.82 seconds
Started Aug 09 05:40:53 PM PDT 24
Finished Aug 09 05:40:54 PM PDT 24
Peak memory 205732 kb
Host smart-7f4f232b-93e4-46b5-951c-f7d606f8e0be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540947662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2540947662
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2260466958
Short name T1004
Test name
Test status
Simulation time 29991594 ps
CPU time 0.8 seconds
Started Aug 09 05:40:50 PM PDT 24
Finished Aug 09 05:40:51 PM PDT 24
Peak memory 205920 kb
Host smart-5574ca8a-1096-4463-8fd5-cfd83bece2ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260466958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2260466958
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.331463310
Short name T1077
Test name
Test status
Simulation time 94600075 ps
CPU time 0.73 seconds
Started Aug 09 05:40:54 PM PDT 24
Finished Aug 09 05:40:54 PM PDT 24
Peak memory 205928 kb
Host smart-e3caa0ef-cb7e-41bd-9204-13d0ba2b0ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331463310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.331463310
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.722442466
Short name T1007
Test name
Test status
Simulation time 16958663 ps
CPU time 0.7 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 205832 kb
Host smart-fa01d5c4-72c3-449a-9819-8d155a43cf97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722442466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.722442466
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.822859353
Short name T1085
Test name
Test status
Simulation time 14839538 ps
CPU time 0.83 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 205860 kb
Host smart-a8efe651-0c99-4165-ba16-e70e64033bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822859353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.822859353
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.159873871
Short name T1071
Test name
Test status
Simulation time 7405453 ps
CPU time 0.74 seconds
Started Aug 09 05:40:53 PM PDT 24
Finished Aug 09 05:40:54 PM PDT 24
Peak memory 205812 kb
Host smart-e273da04-932c-4414-9a92-8388fbc89e79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159873871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.159873871
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.781310337
Short name T1065
Test name
Test status
Simulation time 41488486 ps
CPU time 0.84 seconds
Started Aug 09 05:40:54 PM PDT 24
Finished Aug 09 05:40:55 PM PDT 24
Peak memory 205876 kb
Host smart-43d2dc44-499e-4d06-a570-9936b9896b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781310337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.781310337
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3627163169
Short name T1042
Test name
Test status
Simulation time 35252762 ps
CPU time 0.81 seconds
Started Aug 09 05:40:50 PM PDT 24
Finished Aug 09 05:40:51 PM PDT 24
Peak memory 205816 kb
Host smart-b23c5362-ce6d-47ca-8104-c0bf7259a9e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627163169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3627163169
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2104142575
Short name T1056
Test name
Test status
Simulation time 1970455567 ps
CPU time 10.58 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:24 PM PDT 24
Peak memory 206208 kb
Host smart-0f7d3c56-7ea1-4aa3-9f9b-bab56abd24f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104142575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
104142575
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2934879996
Short name T966
Test name
Test status
Simulation time 1742395327 ps
CPU time 9.27 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:23 PM PDT 24
Peak memory 206084 kb
Host smart-c70d80e5-cae2-4a53-a1ce-8a3967dacf2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934879996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
934879996
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4072028471
Short name T973
Test name
Test status
Simulation time 113753931 ps
CPU time 1.37 seconds
Started Aug 09 05:40:15 PM PDT 24
Finished Aug 09 05:40:16 PM PDT 24
Peak memory 206056 kb
Host smart-363b50b4-eea7-4d64-be72-272a1351e5e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072028471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
072028471
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.585725710
Short name T932
Test name
Test status
Simulation time 32223431 ps
CPU time 1.32 seconds
Started Aug 09 05:40:16 PM PDT 24
Finished Aug 09 05:40:18 PM PDT 24
Peak memory 206084 kb
Host smart-0d621c6a-5a90-47f3-b35b-068c2ea0b3cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585725710 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.585725710
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3336981877
Short name T137
Test name
Test status
Simulation time 46177423 ps
CPU time 1.01 seconds
Started Aug 09 05:40:12 PM PDT 24
Finished Aug 09 05:40:13 PM PDT 24
Peak memory 206132 kb
Host smart-d7f09d25-949d-4ec0-89d8-1258a57b5a1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336981877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3336981877
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3828789259
Short name T969
Test name
Test status
Simulation time 34122444 ps
CPU time 0.78 seconds
Started Aug 09 05:40:12 PM PDT 24
Finished Aug 09 05:40:13 PM PDT 24
Peak memory 205812 kb
Host smart-e0a3d5aa-dad4-4de2-9daf-2454830bfec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828789259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3828789259
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3665358716
Short name T1028
Test name
Test status
Simulation time 365096839 ps
CPU time 2.57 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:15 PM PDT 24
Peak memory 206208 kb
Host smart-efcdc601-7cab-4a6f-8837-399711a8e220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665358716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3665358716
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2921535194
Short name T989
Test name
Test status
Simulation time 157328879 ps
CPU time 2.04 seconds
Started Aug 09 05:40:15 PM PDT 24
Finished Aug 09 05:40:17 PM PDT 24
Peak memory 214656 kb
Host smart-559a6872-a2f9-45fb-b37e-0b5c32c2b203
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921535194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2921535194
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.486799818
Short name T1027
Test name
Test status
Simulation time 3835584268 ps
CPU time 12.03 seconds
Started Aug 09 05:40:12 PM PDT 24
Finished Aug 09 05:40:24 PM PDT 24
Peak memory 221388 kb
Host smart-1be449a0-f7b8-4411-9525-26f58ceab8cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486799818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.486799818
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3102932719
Short name T1063
Test name
Test status
Simulation time 119967434 ps
CPU time 3.24 seconds
Started Aug 09 05:40:14 PM PDT 24
Finished Aug 09 05:40:18 PM PDT 24
Peak memory 213768 kb
Host smart-f50e5c10-85c6-4ae5-a3f5-61b08fdfdbae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102932719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3102932719
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.123421315
Short name T1036
Test name
Test status
Simulation time 11540101 ps
CPU time 0.87 seconds
Started Aug 09 05:40:50 PM PDT 24
Finished Aug 09 05:40:51 PM PDT 24
Peak memory 205848 kb
Host smart-cc25983f-a2da-43b8-9b23-78d5fd51f28c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123421315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.123421315
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3415358051
Short name T929
Test name
Test status
Simulation time 13687287 ps
CPU time 0.88 seconds
Started Aug 09 05:40:53 PM PDT 24
Finished Aug 09 05:40:54 PM PDT 24
Peak memory 205968 kb
Host smart-9c4613a8-2782-49b0-b704-115977b00da8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415358051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3415358051
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3525535859
Short name T944
Test name
Test status
Simulation time 33731041 ps
CPU time 0.76 seconds
Started Aug 09 05:40:51 PM PDT 24
Finished Aug 09 05:40:52 PM PDT 24
Peak memory 205856 kb
Host smart-b94f9a0a-6f88-456b-ac6a-05244849228a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525535859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3525535859
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1865926220
Short name T976
Test name
Test status
Simulation time 33294032 ps
CPU time 0.75 seconds
Started Aug 09 05:40:51 PM PDT 24
Finished Aug 09 05:40:52 PM PDT 24
Peak memory 205908 kb
Host smart-01a10a05-7cce-449d-a075-4fb362f2312a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865926220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1865926220
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2124832160
Short name T1049
Test name
Test status
Simulation time 46171990 ps
CPU time 0.7 seconds
Started Aug 09 05:40:51 PM PDT 24
Finished Aug 09 05:40:52 PM PDT 24
Peak memory 205812 kb
Host smart-75204e19-2a4a-45a8-a1da-544045310153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124832160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2124832160
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.550610577
Short name T988
Test name
Test status
Simulation time 38157459 ps
CPU time 0.81 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 205892 kb
Host smart-e67e35cf-7213-47fb-b27b-940b249bc82e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550610577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.550610577
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.476720495
Short name T974
Test name
Test status
Simulation time 31237928 ps
CPU time 0.68 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 205932 kb
Host smart-b8fefca5-aae4-4ac8-a397-eb4426bccf83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476720495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.476720495
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1192155514
Short name T941
Test name
Test status
Simulation time 62700375 ps
CPU time 0.71 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 205824 kb
Host smart-55ec4bef-b2dc-4a04-bbd3-40de6e9ce492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192155514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1192155514
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3080211573
Short name T1093
Test name
Test status
Simulation time 13609935 ps
CPU time 0.72 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 205736 kb
Host smart-9c7cf928-ab3a-4b4b-be1c-cd40c35e6b93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080211573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3080211573
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1293325887
Short name T981
Test name
Test status
Simulation time 12318936 ps
CPU time 0.7 seconds
Started Aug 09 05:40:51 PM PDT 24
Finished Aug 09 05:40:52 PM PDT 24
Peak memory 205788 kb
Host smart-08d0938e-98c8-4696-85c9-274518ef423b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293325887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1293325887
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2236767257
Short name T987
Test name
Test status
Simulation time 939944626 ps
CPU time 3.89 seconds
Started Aug 09 05:40:22 PM PDT 24
Finished Aug 09 05:40:26 PM PDT 24
Peak memory 206032 kb
Host smart-b7878c3e-cecc-4a9e-a67e-2a5477e3eeff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236767257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
236767257
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2263646579
Short name T946
Test name
Test status
Simulation time 5145184851 ps
CPU time 32.25 seconds
Started Aug 09 05:40:24 PM PDT 24
Finished Aug 09 05:40:57 PM PDT 24
Peak memory 206176 kb
Host smart-d370a508-dd00-415a-89d0-98f778d7bb2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263646579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
263646579
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.943257756
Short name T1038
Test name
Test status
Simulation time 287923846 ps
CPU time 1.19 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:14 PM PDT 24
Peak memory 206028 kb
Host smart-0ebca0d3-4f2e-431e-b060-5d1bcc35a891
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943257756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.943257756
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4191637556
Short name T1012
Test name
Test status
Simulation time 67185113 ps
CPU time 1.45 seconds
Started Aug 09 05:40:21 PM PDT 24
Finished Aug 09 05:40:23 PM PDT 24
Peak memory 214528 kb
Host smart-60a68b47-485f-4e0b-b724-f519f7f4b4cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191637556 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.4191637556
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2617485846
Short name T1068
Test name
Test status
Simulation time 22847810 ps
CPU time 1.29 seconds
Started Aug 09 05:40:22 PM PDT 24
Finished Aug 09 05:40:23 PM PDT 24
Peak memory 206104 kb
Host smart-65000d4a-70d6-4911-8ead-18592ecad11f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617485846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2617485846
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2439292516
Short name T952
Test name
Test status
Simulation time 16747918 ps
CPU time 0.89 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:14 PM PDT 24
Peak memory 205988 kb
Host smart-235765c7-8288-420c-9b05-3511dba463c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439292516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2439292516
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.495989780
Short name T983
Test name
Test status
Simulation time 336803308 ps
CPU time 2.5 seconds
Started Aug 09 05:40:22 PM PDT 24
Finished Aug 09 05:40:25 PM PDT 24
Peak memory 206256 kb
Host smart-7407e8dc-3795-4db0-86c2-bfdd0804fe91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495989780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.495989780
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2284665863
Short name T113
Test name
Test status
Simulation time 221172437 ps
CPU time 2.53 seconds
Started Aug 09 05:40:14 PM PDT 24
Finished Aug 09 05:40:17 PM PDT 24
Peak memory 214540 kb
Host smart-e310011e-1ca9-4147-9f0f-37618a284a39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284665863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2284665863
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.21167332
Short name T1092
Test name
Test status
Simulation time 139593010 ps
CPU time 4.3 seconds
Started Aug 09 05:40:13 PM PDT 24
Finished Aug 09 05:40:18 PM PDT 24
Peak memory 214604 kb
Host smart-68d3e0ed-f8e4-4cd0-bfd3-2f43bed382b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21167332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.ke
ymgr_shadow_reg_errors_with_csr_rw.21167332
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.211290673
Short name T1070
Test name
Test status
Simulation time 105322337 ps
CPU time 2.69 seconds
Started Aug 09 05:40:14 PM PDT 24
Finished Aug 09 05:40:17 PM PDT 24
Peak memory 215772 kb
Host smart-c738745e-a400-4271-98ea-0191fb6541a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211290673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.211290673
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.682299361
Short name T1072
Test name
Test status
Simulation time 13416507 ps
CPU time 0.68 seconds
Started Aug 09 05:40:51 PM PDT 24
Finished Aug 09 05:40:52 PM PDT 24
Peak memory 205828 kb
Host smart-1df26212-9d24-429a-909c-9926a673b580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682299361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.682299361
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3392902222
Short name T1082
Test name
Test status
Simulation time 10706142 ps
CPU time 0.81 seconds
Started Aug 09 05:40:53 PM PDT 24
Finished Aug 09 05:40:54 PM PDT 24
Peak memory 205860 kb
Host smart-0120db8e-4375-429a-a198-084790fc4369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392902222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3392902222
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2597681593
Short name T936
Test name
Test status
Simulation time 17833561 ps
CPU time 0.8 seconds
Started Aug 09 05:40:50 PM PDT 24
Finished Aug 09 05:40:51 PM PDT 24
Peak memory 205936 kb
Host smart-a8849392-d853-40b5-85cd-13b23166b2c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597681593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2597681593
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4239585814
Short name T931
Test name
Test status
Simulation time 60094484 ps
CPU time 0.77 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 205948 kb
Host smart-137adf55-37c0-4279-821a-0ab5bc4bc6d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239585814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4239585814
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2930782189
Short name T1079
Test name
Test status
Simulation time 50314066 ps
CPU time 0.78 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:40:52 PM PDT 24
Peak memory 205864 kb
Host smart-d7f8ff29-fafe-41f1-9a9a-1ea068dde449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930782189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2930782189
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2796511390
Short name T996
Test name
Test status
Simulation time 20288847 ps
CPU time 0.73 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 205908 kb
Host smart-8404e838-a6c7-465c-8ec3-411d5660adc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796511390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2796511390
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1939158768
Short name T945
Test name
Test status
Simulation time 34140019 ps
CPU time 0.86 seconds
Started Aug 09 05:40:51 PM PDT 24
Finished Aug 09 05:40:52 PM PDT 24
Peak memory 205892 kb
Host smart-051a8ba0-ad3f-4a38-adb0-be85cce17e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939158768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1939158768
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1538139467
Short name T1095
Test name
Test status
Simulation time 46621468 ps
CPU time 0.71 seconds
Started Aug 09 05:40:52 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 205760 kb
Host smart-04aed9f9-7b78-4576-bc1d-d8296057969a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538139467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1538139467
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.692486587
Short name T1051
Test name
Test status
Simulation time 49609102 ps
CPU time 0.76 seconds
Started Aug 09 05:40:53 PM PDT 24
Finished Aug 09 05:40:54 PM PDT 24
Peak memory 205776 kb
Host smart-860d8605-920f-4197-b5d2-2abe28d8de2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692486587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.692486587
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1138265109
Short name T1034
Test name
Test status
Simulation time 26206074 ps
CPU time 0.71 seconds
Started Aug 09 05:40:51 PM PDT 24
Finished Aug 09 05:40:52 PM PDT 24
Peak memory 205936 kb
Host smart-d3ad190e-737f-4e6a-9622-922056cae7e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138265109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1138265109
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.871491315
Short name T958
Test name
Test status
Simulation time 76363866 ps
CPU time 1.43 seconds
Started Aug 09 05:40:22 PM PDT 24
Finished Aug 09 05:40:24 PM PDT 24
Peak memory 217876 kb
Host smart-098c5e97-d066-4cd8-91da-0fc49c454d99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871491315 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.871491315
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.603075405
Short name T1064
Test name
Test status
Simulation time 92747628 ps
CPU time 1.47 seconds
Started Aug 09 05:40:22 PM PDT 24
Finished Aug 09 05:40:24 PM PDT 24
Peak memory 206028 kb
Host smart-220fb7f8-56f3-4a75-af7f-800e28b881ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603075405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.603075405
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.439254577
Short name T1060
Test name
Test status
Simulation time 16941840 ps
CPU time 0.81 seconds
Started Aug 09 05:40:21 PM PDT 24
Finished Aug 09 05:40:22 PM PDT 24
Peak memory 205852 kb
Host smart-501235e5-8e2c-4f3f-b336-41f9bca76a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439254577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.439254577
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3248033956
Short name T1055
Test name
Test status
Simulation time 392388388 ps
CPU time 3.72 seconds
Started Aug 09 05:40:21 PM PDT 24
Finished Aug 09 05:40:25 PM PDT 24
Peak memory 214304 kb
Host smart-2f73c640-3765-46b6-a6ad-10607d7563f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248033956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3248033956
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2084738386
Short name T1066
Test name
Test status
Simulation time 672403400 ps
CPU time 3.4 seconds
Started Aug 09 05:40:24 PM PDT 24
Finished Aug 09 05:40:28 PM PDT 24
Peak memory 214608 kb
Host smart-4004c560-c587-482b-8a22-2186e962606a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084738386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2084738386
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2471006537
Short name T1033
Test name
Test status
Simulation time 2186384579 ps
CPU time 4.97 seconds
Started Aug 09 05:40:20 PM PDT 24
Finished Aug 09 05:40:25 PM PDT 24
Peak memory 214732 kb
Host smart-1cb1790e-b2fc-4e62-8e09-a9b3a53a8d9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471006537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2471006537
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1524608452
Short name T1032
Test name
Test status
Simulation time 109652016 ps
CPU time 3.94 seconds
Started Aug 09 05:40:22 PM PDT 24
Finished Aug 09 05:40:26 PM PDT 24
Peak memory 222464 kb
Host smart-3e5ee137-f7e7-4cb4-aa92-417cc183a462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524608452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1524608452
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1960381047
Short name T167
Test name
Test status
Simulation time 1258416117 ps
CPU time 4.43 seconds
Started Aug 09 05:40:19 PM PDT 24
Finished Aug 09 05:40:24 PM PDT 24
Peak memory 214296 kb
Host smart-52c638aa-4a74-45ca-a331-f3fe3e34d790
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960381047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1960381047
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1152825148
Short name T1040
Test name
Test status
Simulation time 50997939 ps
CPU time 1.81 seconds
Started Aug 09 05:40:24 PM PDT 24
Finished Aug 09 05:40:26 PM PDT 24
Peak memory 214372 kb
Host smart-ffc7007a-b783-43ff-a9e8-5c64d941a888
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152825148 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1152825148
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2320846795
Short name T968
Test name
Test status
Simulation time 332947414 ps
CPU time 1.16 seconds
Started Aug 09 05:40:23 PM PDT 24
Finished Aug 09 05:40:24 PM PDT 24
Peak memory 206048 kb
Host smart-1c7756d4-f402-4e00-9cc2-c223713b91c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320846795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2320846795
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2462801643
Short name T950
Test name
Test status
Simulation time 23044310 ps
CPU time 0.73 seconds
Started Aug 09 05:40:18 PM PDT 24
Finished Aug 09 05:40:19 PM PDT 24
Peak memory 205768 kb
Host smart-cf9d31c3-e01f-4914-a8c6-94f9cac961b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462801643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2462801643
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3734977329
Short name T957
Test name
Test status
Simulation time 1394191498 ps
CPU time 2.84 seconds
Started Aug 09 05:40:23 PM PDT 24
Finished Aug 09 05:40:26 PM PDT 24
Peak memory 206140 kb
Host smart-f6e67ac4-a0c1-40f1-83a2-a28ae55ec49d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734977329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3734977329
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.409884594
Short name T1053
Test name
Test status
Simulation time 186863356 ps
CPU time 1.59 seconds
Started Aug 09 05:40:24 PM PDT 24
Finished Aug 09 05:40:26 PM PDT 24
Peak memory 214612 kb
Host smart-dfca1127-a71a-47d9-bbf7-4abe92e01c2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409884594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.409884594
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.254485742
Short name T1005
Test name
Test status
Simulation time 3021799749 ps
CPU time 15.07 seconds
Started Aug 09 05:40:23 PM PDT 24
Finished Aug 09 05:40:39 PM PDT 24
Peak memory 214556 kb
Host smart-03bfddf6-a71d-48d2-a975-6c991d154f5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254485742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.254485742
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1562627561
Short name T939
Test name
Test status
Simulation time 217962268 ps
CPU time 2.89 seconds
Started Aug 09 05:40:21 PM PDT 24
Finished Aug 09 05:40:24 PM PDT 24
Peak memory 215412 kb
Host smart-fd975667-ba2d-47c4-8bf7-f3f784a5b68a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562627561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1562627561
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.70550663
Short name T1052
Test name
Test status
Simulation time 104319335 ps
CPU time 3.54 seconds
Started Aug 09 05:40:23 PM PDT 24
Finished Aug 09 05:40:26 PM PDT 24
Peak memory 214312 kb
Host smart-a3f68aa9-9938-44bf-a27b-5d1188ef037a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70550663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.70550663
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3313173609
Short name T930
Test name
Test status
Simulation time 244608143 ps
CPU time 2.3 seconds
Started Aug 09 05:40:21 PM PDT 24
Finished Aug 09 05:40:24 PM PDT 24
Peak memory 220092 kb
Host smart-ff42a47d-011a-4b45-9d76-e6657c9d9a43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313173609 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3313173609
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2686298849
Short name T963
Test name
Test status
Simulation time 52516536 ps
CPU time 1.52 seconds
Started Aug 09 05:40:23 PM PDT 24
Finished Aug 09 05:40:25 PM PDT 24
Peak memory 206024 kb
Host smart-b1d2bf80-44cc-488f-a3d0-1e1d51fdd48d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686298849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2686298849
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.738892783
Short name T1022
Test name
Test status
Simulation time 44616856 ps
CPU time 0.73 seconds
Started Aug 09 05:40:21 PM PDT 24
Finished Aug 09 05:40:22 PM PDT 24
Peak memory 205844 kb
Host smart-3fc0c097-d04a-41b9-9fff-ff7eced4c408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738892783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.738892783
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2150811372
Short name T135
Test name
Test status
Simulation time 126578626 ps
CPU time 1.41 seconds
Started Aug 09 05:40:21 PM PDT 24
Finished Aug 09 05:40:23 PM PDT 24
Peak memory 206060 kb
Host smart-12157422-c5b3-4147-bd08-766136df19f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150811372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2150811372
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2760415926
Short name T1089
Test name
Test status
Simulation time 305229521 ps
CPU time 5.02 seconds
Started Aug 09 05:40:23 PM PDT 24
Finished Aug 09 05:40:28 PM PDT 24
Peak memory 219000 kb
Host smart-5d7f940b-5691-4ba2-9a1a-deeb22d09f8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760415926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2760415926
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.40413574
Short name T115
Test name
Test status
Simulation time 309841021 ps
CPU time 4.86 seconds
Started Aug 09 05:40:21 PM PDT 24
Finished Aug 09 05:40:26 PM PDT 24
Peak memory 214596 kb
Host smart-b866cf3c-e97f-40a7-8195-c1fc0fa3bbf7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40413574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.ke
ymgr_shadow_reg_errors_with_csr_rw.40413574
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2924498439
Short name T1025
Test name
Test status
Simulation time 26349649 ps
CPU time 2.09 seconds
Started Aug 09 05:40:21 PM PDT 24
Finished Aug 09 05:40:23 PM PDT 24
Peak memory 214392 kb
Host smart-b2161f81-5f97-49b5-9cba-5ffc4db2e547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924498439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2924498439
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1824484810
Short name T1011
Test name
Test status
Simulation time 54268561 ps
CPU time 1.18 seconds
Started Aug 09 05:40:27 PM PDT 24
Finished Aug 09 05:40:29 PM PDT 24
Peak memory 206048 kb
Host smart-479e6d73-93c9-48d9-b44f-ed81b7a51a93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824484810 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1824484810
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3612751755
Short name T382
Test name
Test status
Simulation time 57141762 ps
CPU time 1.12 seconds
Started Aug 09 05:40:26 PM PDT 24
Finished Aug 09 05:40:28 PM PDT 24
Peak memory 206088 kb
Host smart-3bd78083-e9cb-4156-9f37-e318308bb8c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612751755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3612751755
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.57908502
Short name T1043
Test name
Test status
Simulation time 11765619 ps
CPU time 0.81 seconds
Started Aug 09 05:40:32 PM PDT 24
Finished Aug 09 05:40:33 PM PDT 24
Peak memory 205936 kb
Host smart-b9163182-03d7-434d-84ed-8a0cb3801e6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57908502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.57908502
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3652754735
Short name T1041
Test name
Test status
Simulation time 43649835 ps
CPU time 1.6 seconds
Started Aug 09 05:40:28 PM PDT 24
Finished Aug 09 05:40:30 PM PDT 24
Peak memory 206112 kb
Host smart-7704a347-0489-4b65-91da-908b522c0dbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652754735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3652754735
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3182566575
Short name T1026
Test name
Test status
Simulation time 165564409 ps
CPU time 3.1 seconds
Started Aug 09 05:40:20 PM PDT 24
Finished Aug 09 05:40:23 PM PDT 24
Peak memory 214680 kb
Host smart-93576261-5f56-4407-bc05-7e02ccd84dcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182566575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3182566575
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2799082479
Short name T1090
Test name
Test status
Simulation time 203892606 ps
CPU time 4.99 seconds
Started Aug 09 05:40:32 PM PDT 24
Finished Aug 09 05:40:37 PM PDT 24
Peak memory 214708 kb
Host smart-6189541d-ec75-4564-825a-6f19ea4f9079
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799082479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2799082479
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3784626375
Short name T956
Test name
Test status
Simulation time 222289005 ps
CPU time 2.81 seconds
Started Aug 09 05:40:28 PM PDT 24
Finished Aug 09 05:40:31 PM PDT 24
Peak memory 214356 kb
Host smart-9f77bc2e-2d46-4371-81a2-1082cc4d6de8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784626375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3784626375
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3416376596
Short name T986
Test name
Test status
Simulation time 13747152 ps
CPU time 1.05 seconds
Started Aug 09 05:40:27 PM PDT 24
Finished Aug 09 05:40:29 PM PDT 24
Peak memory 205984 kb
Host smart-388a73fa-a03f-4798-97b4-299f24178382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416376596 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3416376596
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.355497564
Short name T1061
Test name
Test status
Simulation time 20170133 ps
CPU time 1.31 seconds
Started Aug 09 05:40:32 PM PDT 24
Finished Aug 09 05:40:33 PM PDT 24
Peak memory 206172 kb
Host smart-4227a5c3-a6d3-47f5-a84e-035f874d52ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355497564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.355497564
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1698722922
Short name T937
Test name
Test status
Simulation time 25170967 ps
CPU time 0.79 seconds
Started Aug 09 05:40:28 PM PDT 24
Finished Aug 09 05:40:29 PM PDT 24
Peak memory 205888 kb
Host smart-1109f704-31b7-4074-87f4-7286c1a4b60f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698722922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1698722922
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1434666307
Short name T948
Test name
Test status
Simulation time 22342454 ps
CPU time 1.57 seconds
Started Aug 09 05:40:27 PM PDT 24
Finished Aug 09 05:40:29 PM PDT 24
Peak memory 206168 kb
Host smart-c51672c8-4b91-4689-a51f-23323bef3b7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434666307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1434666307
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.360817202
Short name T940
Test name
Test status
Simulation time 260404651 ps
CPU time 3.6 seconds
Started Aug 09 05:40:26 PM PDT 24
Finished Aug 09 05:40:30 PM PDT 24
Peak memory 214688 kb
Host smart-0102e74e-cbc8-4639-9c96-5b09e768b462
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360817202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.360817202
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1335204678
Short name T1039
Test name
Test status
Simulation time 5443766585 ps
CPU time 13.94 seconds
Started Aug 09 05:40:28 PM PDT 24
Finished Aug 09 05:40:42 PM PDT 24
Peak memory 214688 kb
Host smart-c8276088-a661-4337-a074-768ed8b70d0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335204678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1335204678
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3213476150
Short name T1081
Test name
Test status
Simulation time 621696609 ps
CPU time 5.61 seconds
Started Aug 09 05:40:28 PM PDT 24
Finished Aug 09 05:40:34 PM PDT 24
Peak memory 214240 kb
Host smart-34642a96-2af1-4bfc-8ced-306ea04e5aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213476150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3213476150
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2615828715
Short name T100
Test name
Test status
Simulation time 22273947 ps
CPU time 0.8 seconds
Started Aug 09 05:20:43 PM PDT 24
Finished Aug 09 05:20:44 PM PDT 24
Peak memory 205844 kb
Host smart-67cd144a-293e-4533-bf62-98ba3fd6aaf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615828715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2615828715
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1168042874
Short name T408
Test name
Test status
Simulation time 2447794826 ps
CPU time 61.04 seconds
Started Aug 09 05:20:44 PM PDT 24
Finished Aug 09 05:21:46 PM PDT 24
Peak memory 214304 kb
Host smart-78ffb353-356c-4255-9533-d188f04d072b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168042874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1168042874
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.545773440
Short name T817
Test name
Test status
Simulation time 483593123 ps
CPU time 3.69 seconds
Started Aug 09 05:20:43 PM PDT 24
Finished Aug 09 05:20:47 PM PDT 24
Peak memory 222292 kb
Host smart-3132752b-eef7-463d-a17f-1d2ecc11ede0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545773440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.545773440
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.325051205
Short name T5
Test name
Test status
Simulation time 88045915 ps
CPU time 2.44 seconds
Started Aug 09 05:20:43 PM PDT 24
Finished Aug 09 05:20:45 PM PDT 24
Peak memory 219760 kb
Host smart-68c9fa29-a7f3-4f97-9923-c114719de698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325051205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.325051205
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2794859694
Short name T795
Test name
Test status
Simulation time 95151392 ps
CPU time 4.29 seconds
Started Aug 09 05:20:38 PM PDT 24
Finished Aug 09 05:20:42 PM PDT 24
Peak memory 208872 kb
Host smart-7f847266-6289-4230-b265-7087a1f9b8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794859694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2794859694
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1569706698
Short name T10
Test name
Test status
Simulation time 1249983330 ps
CPU time 24.59 seconds
Started Aug 09 05:20:42 PM PDT 24
Finished Aug 09 05:21:07 PM PDT 24
Peak memory 238132 kb
Host smart-11186537-edab-4d70-a18c-88ffbb60b2e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569706698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1569706698
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2530116821
Short name T862
Test name
Test status
Simulation time 87983263 ps
CPU time 3.47 seconds
Started Aug 09 05:20:39 PM PDT 24
Finished Aug 09 05:20:42 PM PDT 24
Peak memory 208488 kb
Host smart-6e29fc87-5916-4762-be04-bd84595626d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530116821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2530116821
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2592873873
Short name T852
Test name
Test status
Simulation time 129613911 ps
CPU time 3.42 seconds
Started Aug 09 05:20:38 PM PDT 24
Finished Aug 09 05:20:42 PM PDT 24
Peak memory 206820 kb
Host smart-6636934d-a0c2-4991-aedf-1a07cfa36569
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592873873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2592873873
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2088522568
Short name T807
Test name
Test status
Simulation time 373355640 ps
CPU time 6.19 seconds
Started Aug 09 05:20:38 PM PDT 24
Finished Aug 09 05:20:44 PM PDT 24
Peak memory 208024 kb
Host smart-6560b957-438e-467f-9f54-d23d048372f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088522568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2088522568
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3718678739
Short name T530
Test name
Test status
Simulation time 1652126859 ps
CPU time 11.23 seconds
Started Aug 09 05:20:45 PM PDT 24
Finished Aug 09 05:20:56 PM PDT 24
Peak memory 208692 kb
Host smart-e6dd0805-e98a-4e3a-99fe-fbced4b6747f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718678739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3718678739
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.4083359045
Short name T473
Test name
Test status
Simulation time 133411007 ps
CPU time 2.73 seconds
Started Aug 09 05:20:39 PM PDT 24
Finished Aug 09 05:20:42 PM PDT 24
Peak memory 208552 kb
Host smart-9fdafc0f-6e4a-4daa-9c73-519ac6210b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083359045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.4083359045
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.154335415
Short name T834
Test name
Test status
Simulation time 2318342731 ps
CPU time 28.79 seconds
Started Aug 09 05:20:42 PM PDT 24
Finished Aug 09 05:21:11 PM PDT 24
Peak memory 215732 kb
Host smart-3e8d912e-6ee6-4696-baff-0d4d7c2bcdb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154335415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.154335415
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3159944970
Short name T171
Test name
Test status
Simulation time 1327888101 ps
CPU time 13.3 seconds
Started Aug 09 05:20:44 PM PDT 24
Finished Aug 09 05:20:57 PM PDT 24
Peak memory 222484 kb
Host smart-48af01cc-16ab-4bed-aca0-71facf50e63a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159944970 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3159944970
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1335854306
Short name T412
Test name
Test status
Simulation time 243942912 ps
CPU time 6.02 seconds
Started Aug 09 05:20:43 PM PDT 24
Finished Aug 09 05:20:49 PM PDT 24
Peak memory 208396 kb
Host smart-8492f81a-fafb-4bf4-8b1e-f5813209a592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335854306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1335854306
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.882549080
Short name T54
Test name
Test status
Simulation time 109672089 ps
CPU time 2.43 seconds
Started Aug 09 05:20:43 PM PDT 24
Finished Aug 09 05:20:46 PM PDT 24
Peak memory 210096 kb
Host smart-2a63cc69-de15-4c33-a83a-d94673c811e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882549080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.882549080
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.900939005
Short name T788
Test name
Test status
Simulation time 17090953 ps
CPU time 0.78 seconds
Started Aug 09 05:20:50 PM PDT 24
Finished Aug 09 05:20:50 PM PDT 24
Peak memory 205932 kb
Host smart-68184ace-640f-42e1-9dbf-a12409048ee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900939005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.900939005
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.308603334
Short name T708
Test name
Test status
Simulation time 97962337 ps
CPU time 1.79 seconds
Started Aug 09 05:20:51 PM PDT 24
Finished Aug 09 05:20:53 PM PDT 24
Peak memory 214256 kb
Host smart-865a0509-c091-4c22-81aa-1350658aca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308603334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.308603334
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3698909650
Short name T322
Test name
Test status
Simulation time 214267498 ps
CPU time 4.19 seconds
Started Aug 09 05:20:50 PM PDT 24
Finished Aug 09 05:20:54 PM PDT 24
Peak memory 214268 kb
Host smart-117b5e09-5645-440d-bb77-ea4d1214184a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698909650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3698909650
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3133958517
Short name T67
Test name
Test status
Simulation time 57853061 ps
CPU time 3.47 seconds
Started Aug 09 05:20:55 PM PDT 24
Finished Aug 09 05:20:59 PM PDT 24
Peak memory 214248 kb
Host smart-aef7722c-8ad1-4cec-8cfc-23cab0de2662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133958517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3133958517
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1973174494
Short name T439
Test name
Test status
Simulation time 232444238 ps
CPU time 3.71 seconds
Started Aug 09 05:20:51 PM PDT 24
Finished Aug 09 05:20:55 PM PDT 24
Peak memory 208244 kb
Host smart-34b3f1ca-f7e2-43fe-8bc0-2fc28a003385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973174494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1973174494
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3399648390
Short name T12
Test name
Test status
Simulation time 232170585 ps
CPU time 7.41 seconds
Started Aug 09 05:20:51 PM PDT 24
Finished Aug 09 05:20:58 PM PDT 24
Peak memory 233584 kb
Host smart-5e6dfca1-73f8-40da-9510-2c05d6c67194
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399648390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3399648390
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2415785768
Short name T609
Test name
Test status
Simulation time 22264086 ps
CPU time 1.76 seconds
Started Aug 09 05:20:44 PM PDT 24
Finished Aug 09 05:20:46 PM PDT 24
Peak memory 206760 kb
Host smart-d2267bfb-353f-4ffc-a20f-7f6a7a18973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415785768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2415785768
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.510470323
Short name T685
Test name
Test status
Simulation time 5614139142 ps
CPU time 36.78 seconds
Started Aug 09 05:20:50 PM PDT 24
Finished Aug 09 05:21:27 PM PDT 24
Peak memory 208004 kb
Host smart-576c9cd6-6feb-44aa-a939-f5e73190ae55
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510470323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.510470323
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3425215113
Short name T487
Test name
Test status
Simulation time 389645874 ps
CPU time 2.11 seconds
Started Aug 09 05:20:44 PM PDT 24
Finished Aug 09 05:20:46 PM PDT 24
Peak memory 208560 kb
Host smart-4b40b09b-40f3-4800-910c-b9d3d267ffa3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425215113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3425215113
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.430313000
Short name T231
Test name
Test status
Simulation time 253397756 ps
CPU time 3.14 seconds
Started Aug 09 05:20:55 PM PDT 24
Finished Aug 09 05:20:58 PM PDT 24
Peak memory 206872 kb
Host smart-025b93a7-5ad9-49a8-8f6b-bc4e53e9d7bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430313000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.430313000
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4009565260
Short name T109
Test name
Test status
Simulation time 147484549 ps
CPU time 1.94 seconds
Started Aug 09 05:20:52 PM PDT 24
Finished Aug 09 05:20:54 PM PDT 24
Peak memory 214204 kb
Host smart-10e9b01c-6f1a-42e1-94dc-34dbda375182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009565260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4009565260
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3843151137
Short name T198
Test name
Test status
Simulation time 592588490 ps
CPU time 2.45 seconds
Started Aug 09 05:20:43 PM PDT 24
Finished Aug 09 05:20:46 PM PDT 24
Peak memory 206708 kb
Host smart-e16370b2-ce12-4deb-8ed3-0634c76dc4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843151137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3843151137
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1179217133
Short name T197
Test name
Test status
Simulation time 282754879 ps
CPU time 4.13 seconds
Started Aug 09 05:20:50 PM PDT 24
Finished Aug 09 05:20:55 PM PDT 24
Peak memory 208228 kb
Host smart-704ddeee-9b83-46e5-9218-783aa2faa66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179217133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1179217133
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2876796983
Short name T850
Test name
Test status
Simulation time 61289004 ps
CPU time 1.88 seconds
Started Aug 09 05:20:54 PM PDT 24
Finished Aug 09 05:20:56 PM PDT 24
Peak memory 210236 kb
Host smart-3ad6a8a9-6ceb-4a38-81ef-a5cb8de3a829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876796983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2876796983
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1990728047
Short name T216
Test name
Test status
Simulation time 72543751 ps
CPU time 2.11 seconds
Started Aug 09 05:21:35 PM PDT 24
Finished Aug 09 05:21:37 PM PDT 24
Peak memory 214392 kb
Host smart-fec8ea1d-dc06-4264-b881-8bb8a4c1887c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990728047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1990728047
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2334590560
Short name T841
Test name
Test status
Simulation time 68882066 ps
CPU time 2 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:38 PM PDT 24
Peak memory 219564 kb
Host smart-0cffd02e-c7da-4e19-bdb9-4ae0f7d06ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334590560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2334590560
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1341421905
Short name T616
Test name
Test status
Simulation time 123106670 ps
CPU time 3.54 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:40 PM PDT 24
Peak memory 214336 kb
Host smart-d118b192-1a45-436e-b016-d6903b287d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341421905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1341421905
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1415182060
Short name T283
Test name
Test status
Simulation time 80241108 ps
CPU time 3.32 seconds
Started Aug 09 05:21:35 PM PDT 24
Finished Aug 09 05:21:38 PM PDT 24
Peak memory 214248 kb
Host smart-58fa4149-3022-46fb-a32e-49237d98f562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415182060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1415182060
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1675325266
Short name T836
Test name
Test status
Simulation time 89942494 ps
CPU time 2.63 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:39 PM PDT 24
Peak memory 222468 kb
Host smart-ec5b92d3-6e1d-4175-a766-20391b6b0f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675325266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1675325266
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3723386990
Short name T695
Test name
Test status
Simulation time 238100305 ps
CPU time 3.3 seconds
Started Aug 09 05:21:35 PM PDT 24
Finished Aug 09 05:21:38 PM PDT 24
Peak memory 209148 kb
Host smart-7a5b082c-b663-4161-b784-7f478f5c13bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723386990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3723386990
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1376534273
Short name T759
Test name
Test status
Simulation time 48882048 ps
CPU time 2.03 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:38 PM PDT 24
Peak memory 208308 kb
Host smart-882c017a-017e-4a5d-9ae5-96d2567bb3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376534273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1376534273
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2588537866
Short name T598
Test name
Test status
Simulation time 38048653 ps
CPU time 2.39 seconds
Started Aug 09 05:21:38 PM PDT 24
Finished Aug 09 05:21:40 PM PDT 24
Peak memory 206904 kb
Host smart-08b7887b-0122-41ec-bafa-512a6750c962
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588537866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2588537866
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.208905706
Short name T835
Test name
Test status
Simulation time 294399763 ps
CPU time 3.52 seconds
Started Aug 09 05:21:35 PM PDT 24
Finished Aug 09 05:21:38 PM PDT 24
Peak memory 208364 kb
Host smart-0720de72-92af-4cbc-9923-0db51edd1b88
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208905706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.208905706
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1236034151
Short name T589
Test name
Test status
Simulation time 138307725 ps
CPU time 2.26 seconds
Started Aug 09 05:21:41 PM PDT 24
Finished Aug 09 05:21:44 PM PDT 24
Peak memory 207044 kb
Host smart-0747a826-d22e-4513-a67d-b865598b4190
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236034151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1236034151
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.346195849
Short name T555
Test name
Test status
Simulation time 117263016 ps
CPU time 2.23 seconds
Started Aug 09 05:21:37 PM PDT 24
Finished Aug 09 05:21:39 PM PDT 24
Peak memory 209764 kb
Host smart-1a08a4a1-0735-4458-b350-76115be2dcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346195849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.346195849
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3258079487
Short name T395
Test name
Test status
Simulation time 66893939 ps
CPU time 3.04 seconds
Started Aug 09 05:21:35 PM PDT 24
Finished Aug 09 05:21:38 PM PDT 24
Peak memory 207932 kb
Host smart-0474a76b-8b55-42b3-8e05-8da43ecb605c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258079487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3258079487
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2059340797
Short name T210
Test name
Test status
Simulation time 254477629 ps
CPU time 4.88 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:41 PM PDT 24
Peak memory 209396 kb
Host smart-a5362569-09f2-4335-86b0-9d6e4f2630ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059340797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2059340797
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3018997677
Short name T401
Test name
Test status
Simulation time 139506174 ps
CPU time 5.57 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:41 PM PDT 24
Peak memory 214328 kb
Host smart-77f1c9ec-d99e-463c-9bcf-0314eab3cbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018997677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3018997677
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1080783123
Short name T741
Test name
Test status
Simulation time 188900574 ps
CPU time 3.72 seconds
Started Aug 09 05:21:39 PM PDT 24
Finished Aug 09 05:21:43 PM PDT 24
Peak memory 210404 kb
Host smart-393da930-65ea-4254-b748-181e925b07a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080783123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1080783123
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3327597562
Short name T562
Test name
Test status
Simulation time 13596839 ps
CPU time 0.76 seconds
Started Aug 09 05:21:45 PM PDT 24
Finished Aug 09 05:21:46 PM PDT 24
Peak memory 206172 kb
Host smart-64ccbe7e-a63c-4eab-8795-391f95570b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327597562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3327597562
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.243086548
Short name T827
Test name
Test status
Simulation time 77390717 ps
CPU time 3.1 seconds
Started Aug 09 05:21:40 PM PDT 24
Finished Aug 09 05:21:43 PM PDT 24
Peak memory 215164 kb
Host smart-85c8d349-338a-4c8f-b833-a165fa97c03d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243086548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.243086548
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3325547138
Short name T732
Test name
Test status
Simulation time 30439890 ps
CPU time 2.25 seconds
Started Aug 09 05:21:42 PM PDT 24
Finished Aug 09 05:21:45 PM PDT 24
Peak memory 207340 kb
Host smart-f2bbf16b-f210-49a6-ba84-d039acef6532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325547138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3325547138
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3291378619
Short name T485
Test name
Test status
Simulation time 876829870 ps
CPU time 4.44 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:41 PM PDT 24
Peak memory 218336 kb
Host smart-685ca54d-fd5f-488b-a83e-88d0ede518d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291378619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3291378619
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1385224860
Short name T102
Test name
Test status
Simulation time 62782789 ps
CPU time 2.6 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:38 PM PDT 24
Peak memory 222364 kb
Host smart-4f6f59cb-109c-47d2-b5a9-a7ee8c76db6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385224860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1385224860
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.4171694956
Short name T226
Test name
Test status
Simulation time 135365735 ps
CPU time 2.94 seconds
Started Aug 09 05:21:37 PM PDT 24
Finished Aug 09 05:21:40 PM PDT 24
Peak memory 220424 kb
Host smart-b1579831-4b17-471a-8ce6-fd4a7d501da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171694956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.4171694956
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1753902797
Short name T445
Test name
Test status
Simulation time 526952821 ps
CPU time 5.78 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:42 PM PDT 24
Peak memory 218340 kb
Host smart-83940950-0807-4bcb-a081-7845d6c03e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753902797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1753902797
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1193760837
Short name T510
Test name
Test status
Simulation time 1499310915 ps
CPU time 40.81 seconds
Started Aug 09 05:21:41 PM PDT 24
Finished Aug 09 05:22:22 PM PDT 24
Peak memory 208356 kb
Host smart-aa733481-ed36-4f17-8d88-1e813e5cd62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193760837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1193760837
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1371333825
Short name T436
Test name
Test status
Simulation time 2091850878 ps
CPU time 32.74 seconds
Started Aug 09 05:21:41 PM PDT 24
Finished Aug 09 05:22:14 PM PDT 24
Peak memory 207492 kb
Host smart-1dac3130-08cb-4aa7-b906-cbfe1748605d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371333825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1371333825
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1955203812
Short name T81
Test name
Test status
Simulation time 80797040 ps
CPU time 3.53 seconds
Started Aug 09 05:21:35 PM PDT 24
Finished Aug 09 05:21:39 PM PDT 24
Peak memory 206796 kb
Host smart-0c25c77b-2f02-4f0b-9c0d-f954e1d8af85
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955203812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1955203812
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3190913548
Short name T534
Test name
Test status
Simulation time 96147091 ps
CPU time 3.19 seconds
Started Aug 09 05:21:40 PM PDT 24
Finished Aug 09 05:21:43 PM PDT 24
Peak memory 207856 kb
Host smart-1160dae8-0ecd-4d06-88ae-0012c29fde5d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190913548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3190913548
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3157037754
Short name T789
Test name
Test status
Simulation time 150131385 ps
CPU time 3.06 seconds
Started Aug 09 05:21:42 PM PDT 24
Finished Aug 09 05:21:46 PM PDT 24
Peak memory 209336 kb
Host smart-5f11b8f8-d0eb-4716-9494-2de7e76c558f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157037754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3157037754
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3969561948
Short name T690
Test name
Test status
Simulation time 98189588 ps
CPU time 3.12 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:39 PM PDT 24
Peak memory 206704 kb
Host smart-ca39f349-8e8c-4ec8-9771-d088274ac5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969561948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3969561948
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2552943943
Short name T704
Test name
Test status
Simulation time 257666956 ps
CPU time 6.64 seconds
Started Aug 09 05:21:37 PM PDT 24
Finished Aug 09 05:21:44 PM PDT 24
Peak memory 208384 kb
Host smart-e319f5fb-8af4-4494-b064-55fae5329ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552943943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2552943943
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2949634023
Short name T502
Test name
Test status
Simulation time 52285994 ps
CPU time 0.79 seconds
Started Aug 09 05:21:49 PM PDT 24
Finished Aug 09 05:21:50 PM PDT 24
Peak memory 205936 kb
Host smart-002e05e5-f516-43c5-9d87-52588bf45798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949634023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2949634023
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.393791357
Short name T257
Test name
Test status
Simulation time 88183207 ps
CPU time 5.03 seconds
Started Aug 09 05:21:42 PM PDT 24
Finished Aug 09 05:21:48 PM PDT 24
Peak memory 214264 kb
Host smart-026837ac-c5b5-445e-81ae-a67a80bbd15f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=393791357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.393791357
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1496707828
Short name T28
Test name
Test status
Simulation time 29009278 ps
CPU time 1.35 seconds
Started Aug 09 05:21:45 PM PDT 24
Finished Aug 09 05:21:46 PM PDT 24
Peak memory 214296 kb
Host smart-8abfc700-4e09-4aa3-81f2-b4700d927a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496707828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1496707828
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3747458118
Short name T181
Test name
Test status
Simulation time 12494290 ps
CPU time 1.21 seconds
Started Aug 09 05:21:46 PM PDT 24
Finished Aug 09 05:21:47 PM PDT 24
Peak memory 207408 kb
Host smart-139d4ffc-9990-4b03-81f2-f6211a96a40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747458118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3747458118
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2050002872
Short name T271
Test name
Test status
Simulation time 1924875241 ps
CPU time 27.37 seconds
Started Aug 09 05:21:44 PM PDT 24
Finished Aug 09 05:22:12 PM PDT 24
Peak memory 214304 kb
Host smart-1c446d71-76d0-454e-bf25-58cf31b09b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050002872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2050002872
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1045091163
Short name T848
Test name
Test status
Simulation time 31495417 ps
CPU time 1.71 seconds
Started Aug 09 05:21:42 PM PDT 24
Finished Aug 09 05:21:44 PM PDT 24
Peak memory 214284 kb
Host smart-b3101439-180e-4447-b3be-5b2a47a41000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045091163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1045091163
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3228787716
Short name T897
Test name
Test status
Simulation time 76599097 ps
CPU time 2.56 seconds
Started Aug 09 05:21:43 PM PDT 24
Finished Aug 09 05:21:46 PM PDT 24
Peak memory 208652 kb
Host smart-bbd9a0eb-2de1-497a-899a-57c9e1d863a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228787716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3228787716
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3098037287
Short name T774
Test name
Test status
Simulation time 458288615 ps
CPU time 5.71 seconds
Started Aug 09 05:21:43 PM PDT 24
Finished Aug 09 05:21:48 PM PDT 24
Peak memory 209084 kb
Host smart-28019311-11c4-4a1a-ac73-0ed1dff15f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098037287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3098037287
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2106027676
Short name T798
Test name
Test status
Simulation time 395304166 ps
CPU time 3.73 seconds
Started Aug 09 05:21:44 PM PDT 24
Finished Aug 09 05:21:47 PM PDT 24
Peak memory 208708 kb
Host smart-3da5800d-f30f-4aa4-afc2-6a3aa99a2ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106027676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2106027676
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3230019148
Short name T822
Test name
Test status
Simulation time 677554605 ps
CPU time 4.38 seconds
Started Aug 09 05:21:43 PM PDT 24
Finished Aug 09 05:21:47 PM PDT 24
Peak memory 208812 kb
Host smart-abdc7432-8456-487e-a079-f997881fa976
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230019148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3230019148
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.383111803
Short name T604
Test name
Test status
Simulation time 88773847 ps
CPU time 3.68 seconds
Started Aug 09 05:21:44 PM PDT 24
Finished Aug 09 05:21:48 PM PDT 24
Peak memory 207972 kb
Host smart-c8bb294e-4430-4d74-a894-164a0ff774f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383111803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.383111803
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3230098644
Short name T679
Test name
Test status
Simulation time 891512066 ps
CPU time 6.96 seconds
Started Aug 09 05:21:44 PM PDT 24
Finished Aug 09 05:21:51 PM PDT 24
Peak memory 208156 kb
Host smart-30140428-1e9e-4e25-a74e-e597dbebd96c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230098644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3230098644
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.541417765
Short name T19
Test name
Test status
Simulation time 85623613 ps
CPU time 3.21 seconds
Started Aug 09 05:21:43 PM PDT 24
Finished Aug 09 05:21:47 PM PDT 24
Peak memory 214224 kb
Host smart-915078d9-9ef5-4262-9e20-ac1264327603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541417765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.541417765
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.542967212
Short name T784
Test name
Test status
Simulation time 1714755309 ps
CPU time 23.51 seconds
Started Aug 09 05:21:45 PM PDT 24
Finished Aug 09 05:22:08 PM PDT 24
Peak memory 208256 kb
Host smart-03e67ee0-7c9c-4981-b2ff-96b09ac248a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542967212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.542967212
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3144480877
Short name T302
Test name
Test status
Simulation time 1466927355 ps
CPU time 23.88 seconds
Started Aug 09 05:21:45 PM PDT 24
Finished Aug 09 05:22:09 PM PDT 24
Peak memory 221280 kb
Host smart-70a68d4e-e9ac-4525-ad73-a24cbc7a9e4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144480877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3144480877
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2332622401
Short name T705
Test name
Test status
Simulation time 503889254 ps
CPU time 20.64 seconds
Started Aug 09 05:21:44 PM PDT 24
Finished Aug 09 05:22:04 PM PDT 24
Peak memory 222468 kb
Host smart-2266fefd-1011-457a-8bb4-e1c0dd2b9041
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332622401 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2332622401
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1593547009
Short name T472
Test name
Test status
Simulation time 138892745 ps
CPU time 2.49 seconds
Started Aug 09 05:21:45 PM PDT 24
Finished Aug 09 05:21:48 PM PDT 24
Peak memory 207600 kb
Host smart-190c483c-cdd2-40c8-8cae-b57550354ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593547009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1593547009
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2344795965
Short name T514
Test name
Test status
Simulation time 44279190 ps
CPU time 0.84 seconds
Started Aug 09 05:21:51 PM PDT 24
Finished Aug 09 05:21:52 PM PDT 24
Peak memory 205876 kb
Host smart-49b1a96d-a44a-476b-8611-5f8970263474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344795965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2344795965
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.4055884570
Short name T804
Test name
Test status
Simulation time 309272788 ps
CPU time 3.4 seconds
Started Aug 09 05:21:54 PM PDT 24
Finished Aug 09 05:21:58 PM PDT 24
Peak memory 209428 kb
Host smart-b209afbd-b2fc-43af-864a-8ab7a1970470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055884570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4055884570
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2163225642
Short name T267
Test name
Test status
Simulation time 84626928 ps
CPU time 3.11 seconds
Started Aug 09 05:21:51 PM PDT 24
Finished Aug 09 05:21:54 PM PDT 24
Peak memory 209500 kb
Host smart-491923c8-c6b8-493b-9d19-36e53a1aeacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163225642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2163225642
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2890363903
Short name T917
Test name
Test status
Simulation time 114460444 ps
CPU time 5.26 seconds
Started Aug 09 05:21:50 PM PDT 24
Finished Aug 09 05:21:55 PM PDT 24
Peak memory 214376 kb
Host smart-96603538-f622-42f4-a3be-90790db86cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890363903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2890363903
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2211639233
Short name T56
Test name
Test status
Simulation time 109880342 ps
CPU time 2.75 seconds
Started Aug 09 05:21:51 PM PDT 24
Finished Aug 09 05:21:53 PM PDT 24
Peak memory 214312 kb
Host smart-9917b0c6-2255-43d7-a1ed-fd31b204b945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211639233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2211639233
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3139222588
Short name T585
Test name
Test status
Simulation time 1309564513 ps
CPU time 4.38 seconds
Started Aug 09 05:21:44 PM PDT 24
Finished Aug 09 05:21:48 PM PDT 24
Peak memory 214216 kb
Host smart-e93f7071-8e6f-46d8-956d-44a59fdd80d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139222588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3139222588
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2281093141
Short name T656
Test name
Test status
Simulation time 32209305 ps
CPU time 2.26 seconds
Started Aug 09 05:21:44 PM PDT 24
Finished Aug 09 05:21:46 PM PDT 24
Peak memory 206996 kb
Host smart-61dbbb72-c9fa-429c-9136-371dee80c6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281093141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2281093141
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.910447229
Short name T467
Test name
Test status
Simulation time 52283115 ps
CPU time 2.67 seconds
Started Aug 09 05:21:49 PM PDT 24
Finished Aug 09 05:21:52 PM PDT 24
Peak memory 208268 kb
Host smart-8687ea60-cb60-4a43-a6a8-3d48023844c5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910447229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.910447229
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1673201202
Short name T204
Test name
Test status
Simulation time 329447206 ps
CPU time 2.9 seconds
Started Aug 09 05:21:43 PM PDT 24
Finished Aug 09 05:21:46 PM PDT 24
Peak memory 206840 kb
Host smart-65e014a0-4ce7-4ec9-9824-a3152130cee5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673201202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1673201202
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1777251212
Short name T754
Test name
Test status
Simulation time 206975274 ps
CPU time 5.86 seconds
Started Aug 09 05:21:43 PM PDT 24
Finished Aug 09 05:21:48 PM PDT 24
Peak memory 207936 kb
Host smart-480ad76b-acf9-40e3-8628-4040f29b838d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777251212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1777251212
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.4007749948
Short name T352
Test name
Test status
Simulation time 99556116 ps
CPU time 3.44 seconds
Started Aug 09 05:21:49 PM PDT 24
Finished Aug 09 05:21:53 PM PDT 24
Peak memory 207904 kb
Host smart-ae23cdc7-c210-4620-99e2-af8a78512d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007749948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.4007749948
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.512359976
Short name T642
Test name
Test status
Simulation time 962197362 ps
CPU time 2.89 seconds
Started Aug 09 05:21:43 PM PDT 24
Finished Aug 09 05:21:46 PM PDT 24
Peak memory 206748 kb
Host smart-3e0e3d2b-3129-48a6-857f-2eb2e8174cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512359976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.512359976
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1700196228
Short name T243
Test name
Test status
Simulation time 1564287949 ps
CPU time 34.36 seconds
Started Aug 09 05:21:53 PM PDT 24
Finished Aug 09 05:22:28 PM PDT 24
Peak memory 220924 kb
Host smart-711a514c-2f37-4e08-a34b-15d0f750dc35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700196228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1700196228
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1593015018
Short name T811
Test name
Test status
Simulation time 128134120 ps
CPU time 5.48 seconds
Started Aug 09 05:21:50 PM PDT 24
Finished Aug 09 05:21:56 PM PDT 24
Peak memory 209896 kb
Host smart-0d6a72b4-5929-4619-bf27-e8924ae91e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593015018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1593015018
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2604857238
Short name T780
Test name
Test status
Simulation time 62853102 ps
CPU time 2.42 seconds
Started Aug 09 05:21:49 PM PDT 24
Finished Aug 09 05:21:51 PM PDT 24
Peak memory 210456 kb
Host smart-92657f76-baec-483b-b3ab-cc02d22ea4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604857238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2604857238
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.566767755
Short name T539
Test name
Test status
Simulation time 32836302 ps
CPU time 0.78 seconds
Started Aug 09 05:21:51 PM PDT 24
Finished Aug 09 05:21:52 PM PDT 24
Peak memory 205992 kb
Host smart-6d7fbd43-53cb-4c1f-9493-45d4fc2a7069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566767755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.566767755
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1062821151
Short name T301
Test name
Test status
Simulation time 52897013 ps
CPU time 2.48 seconds
Started Aug 09 05:21:54 PM PDT 24
Finished Aug 09 05:21:57 PM PDT 24
Peak memory 209628 kb
Host smart-3aacdcb9-58cd-4d91-90de-7d6408b68ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062821151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1062821151
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1549115605
Short name T303
Test name
Test status
Simulation time 122470395 ps
CPU time 4.64 seconds
Started Aug 09 05:21:48 PM PDT 24
Finished Aug 09 05:21:53 PM PDT 24
Peak memory 208752 kb
Host smart-00f8f924-e1c3-4713-a98f-1f54973dd7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549115605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1549115605
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.398891509
Short name T298
Test name
Test status
Simulation time 1659028260 ps
CPU time 6.95 seconds
Started Aug 09 05:21:54 PM PDT 24
Finished Aug 09 05:22:01 PM PDT 24
Peak memory 222500 kb
Host smart-03c5c493-4493-48ee-be91-52875df5fcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398891509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.398891509
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2990000018
Short name T640
Test name
Test status
Simulation time 47086190 ps
CPU time 3.2 seconds
Started Aug 09 05:21:49 PM PDT 24
Finished Aug 09 05:21:53 PM PDT 24
Peak memory 208484 kb
Host smart-ddb1cc74-302b-435c-b23a-eff7ad7179ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990000018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2990000018
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4113397665
Short name T790
Test name
Test status
Simulation time 259522487 ps
CPU time 4.83 seconds
Started Aug 09 05:21:52 PM PDT 24
Finished Aug 09 05:21:57 PM PDT 24
Peak memory 218936 kb
Host smart-78c7c092-9812-4d1e-811e-33dc91dbb89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113397665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4113397665
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1905124332
Short name T434
Test name
Test status
Simulation time 132936062 ps
CPU time 2.39 seconds
Started Aug 09 05:21:54 PM PDT 24
Finished Aug 09 05:21:56 PM PDT 24
Peak memory 206772 kb
Host smart-16605a54-873b-4dd4-a41d-acb568f710f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905124332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1905124332
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3071783971
Short name T560
Test name
Test status
Simulation time 211950212 ps
CPU time 6.73 seconds
Started Aug 09 05:21:55 PM PDT 24
Finished Aug 09 05:22:02 PM PDT 24
Peak memory 208000 kb
Host smart-1b166707-c8bd-4451-86ee-5a335a2a15bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071783971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3071783971
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1771768363
Short name T513
Test name
Test status
Simulation time 371401912 ps
CPU time 3.92 seconds
Started Aug 09 05:21:50 PM PDT 24
Finished Aug 09 05:21:55 PM PDT 24
Peak memory 208620 kb
Host smart-9f415389-228c-4d60-a8c1-2419cdfc911e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771768363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1771768363
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3511947037
Short name T896
Test name
Test status
Simulation time 109364849 ps
CPU time 4.02 seconds
Started Aug 09 05:21:51 PM PDT 24
Finished Aug 09 05:21:55 PM PDT 24
Peak memory 206772 kb
Host smart-f1e45411-0288-4d6f-b73b-0ef8a6e50cb2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511947037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3511947037
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2151055173
Short name T110
Test name
Test status
Simulation time 79207883 ps
CPU time 3.77 seconds
Started Aug 09 05:21:50 PM PDT 24
Finished Aug 09 05:21:54 PM PDT 24
Peak memory 214264 kb
Host smart-d1fd0a4e-30d2-46a4-a869-748f4a2468c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151055173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2151055173
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.792175617
Short name T633
Test name
Test status
Simulation time 3247071053 ps
CPU time 16.01 seconds
Started Aug 09 05:21:58 PM PDT 24
Finished Aug 09 05:22:14 PM PDT 24
Peak memory 208844 kb
Host smart-0bdd7ea6-3887-47c6-9a92-c3bf7da8d12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792175617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.792175617
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.937755956
Short name T189
Test name
Test status
Simulation time 3699237098 ps
CPU time 37.87 seconds
Started Aug 09 05:21:57 PM PDT 24
Finished Aug 09 05:22:35 PM PDT 24
Peak memory 217104 kb
Host smart-7e8ad8b1-204b-41ea-8d48-376639356dc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937755956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.937755956
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2917554122
Short name T172
Test name
Test status
Simulation time 491526111 ps
CPU time 18.01 seconds
Started Aug 09 05:21:50 PM PDT 24
Finished Aug 09 05:22:08 PM PDT 24
Peak memory 220120 kb
Host smart-1de87bb5-74c4-4ff5-9dbb-0d5ac3ae934c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917554122 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2917554122
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.520632778
Short name T337
Test name
Test status
Simulation time 106416105 ps
CPU time 2.87 seconds
Started Aug 09 05:21:54 PM PDT 24
Finished Aug 09 05:21:57 PM PDT 24
Peak memory 218112 kb
Host smart-5cfdb810-97fb-4502-8019-50dab029279b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520632778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.520632778
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1902532349
Short name T879
Test name
Test status
Simulation time 83773547 ps
CPU time 1.73 seconds
Started Aug 09 05:21:51 PM PDT 24
Finished Aug 09 05:21:53 PM PDT 24
Peak memory 214304 kb
Host smart-6e26aab6-ecce-41c4-ac3a-a74290551eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902532349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1902532349
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3352135861
Short name T840
Test name
Test status
Simulation time 55318148 ps
CPU time 0.8 seconds
Started Aug 09 05:22:02 PM PDT 24
Finished Aug 09 05:22:03 PM PDT 24
Peak memory 205888 kb
Host smart-d21d61e8-c7c8-4616-b56c-6e0a0c8d577a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352135861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3352135861
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.673435659
Short name T838
Test name
Test status
Simulation time 37972583 ps
CPU time 2.95 seconds
Started Aug 09 05:21:55 PM PDT 24
Finished Aug 09 05:21:58 PM PDT 24
Peak memory 214244 kb
Host smart-93a7ca4c-9dcf-42ce-8e77-f88e1772ab6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673435659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.673435659
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.203854546
Short name T845
Test name
Test status
Simulation time 198901349 ps
CPU time 3.13 seconds
Started Aug 09 05:21:55 PM PDT 24
Finished Aug 09 05:21:58 PM PDT 24
Peak memory 221284 kb
Host smart-da0d1244-4f66-4fa7-91ee-a3d662a202b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203854546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.203854546
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.583966675
Short name T837
Test name
Test status
Simulation time 136400131 ps
CPU time 3.36 seconds
Started Aug 09 05:22:02 PM PDT 24
Finished Aug 09 05:22:06 PM PDT 24
Peak memory 209460 kb
Host smart-d13fc57a-2e84-4597-ad58-201f919eaa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583966675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.583966675
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.345419751
Short name T95
Test name
Test status
Simulation time 616733088 ps
CPU time 7.89 seconds
Started Aug 09 05:21:56 PM PDT 24
Finished Aug 09 05:22:04 PM PDT 24
Peak memory 209400 kb
Host smart-677fa203-5574-4313-ad2f-2be95349adbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345419751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.345419751
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.218616962
Short name T738
Test name
Test status
Simulation time 84356833 ps
CPU time 2.24 seconds
Started Aug 09 05:21:58 PM PDT 24
Finished Aug 09 05:22:00 PM PDT 24
Peak memory 222616 kb
Host smart-a699c87d-cffa-4ddd-8198-c8ef1da14d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218616962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.218616962
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.4216141999
Short name T752
Test name
Test status
Simulation time 255530494 ps
CPU time 3.65 seconds
Started Aug 09 05:21:57 PM PDT 24
Finished Aug 09 05:22:01 PM PDT 24
Peak memory 209448 kb
Host smart-3a3dfa27-987f-4da4-886d-5c7103fece63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216141999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.4216141999
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1105032855
Short name T888
Test name
Test status
Simulation time 142757471 ps
CPU time 3.94 seconds
Started Aug 09 05:21:56 PM PDT 24
Finished Aug 09 05:22:00 PM PDT 24
Peak memory 207640 kb
Host smart-801be2b7-5d02-4405-a296-e559e03464cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105032855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1105032855
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3134647498
Short name T420
Test name
Test status
Simulation time 12625623904 ps
CPU time 27.62 seconds
Started Aug 09 05:21:57 PM PDT 24
Finished Aug 09 05:22:25 PM PDT 24
Peak memory 207956 kb
Host smart-fe73e233-bda1-4560-a77a-0784e28ba1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134647498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3134647498
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3564251466
Short name T720
Test name
Test status
Simulation time 922483041 ps
CPU time 5.81 seconds
Started Aug 09 05:21:56 PM PDT 24
Finished Aug 09 05:22:02 PM PDT 24
Peak memory 208604 kb
Host smart-30a2b81d-1669-4483-807c-934584403ead
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564251466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3564251466
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.635476245
Short name T229
Test name
Test status
Simulation time 1679915278 ps
CPU time 41.49 seconds
Started Aug 09 05:21:55 PM PDT 24
Finished Aug 09 05:22:37 PM PDT 24
Peak memory 208544 kb
Host smart-b3650655-794d-4185-b7d0-c16e7cd1d39d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635476245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.635476245
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3439886936
Short name T232
Test name
Test status
Simulation time 259656133 ps
CPU time 4.46 seconds
Started Aug 09 05:21:58 PM PDT 24
Finished Aug 09 05:22:02 PM PDT 24
Peak memory 208364 kb
Host smart-7054a571-59f8-4abf-8d83-ad027ad37edc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439886936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3439886936
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1249877217
Short name T308
Test name
Test status
Simulation time 114563216 ps
CPU time 2.55 seconds
Started Aug 09 05:21:58 PM PDT 24
Finished Aug 09 05:22:00 PM PDT 24
Peak memory 218224 kb
Host smart-e6664838-75c8-4dad-b8b3-38170731688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249877217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1249877217
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3327690966
Short name T440
Test name
Test status
Simulation time 80816757 ps
CPU time 1.86 seconds
Started Aug 09 05:21:58 PM PDT 24
Finished Aug 09 05:22:00 PM PDT 24
Peak memory 207236 kb
Host smart-20846bb4-6e14-4109-bde2-f0b6608a6b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327690966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3327690966
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1359414301
Short name T118
Test name
Test status
Simulation time 713322454 ps
CPU time 7.55 seconds
Started Aug 09 05:21:55 PM PDT 24
Finished Aug 09 05:22:03 PM PDT 24
Peak memory 221612 kb
Host smart-de7a5428-7fde-4103-87cc-310d502286a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359414301 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1359414301
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1715757625
Short name T123
Test name
Test status
Simulation time 52451487 ps
CPU time 3.32 seconds
Started Aug 09 05:21:55 PM PDT 24
Finished Aug 09 05:21:58 PM PDT 24
Peak memory 207908 kb
Host smart-de5655d9-6c76-4cdf-9c78-fda15b344811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715757625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1715757625
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.367296154
Short name T156
Test name
Test status
Simulation time 102453692 ps
CPU time 3.4 seconds
Started Aug 09 05:21:54 PM PDT 24
Finished Aug 09 05:21:57 PM PDT 24
Peak memory 210388 kb
Host smart-aa693524-b468-4fc4-a621-76d3da2edb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367296154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.367296154
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3969274646
Short name T99
Test name
Test status
Simulation time 42784407 ps
CPU time 0.87 seconds
Started Aug 09 05:22:02 PM PDT 24
Finished Aug 09 05:22:03 PM PDT 24
Peak memory 205876 kb
Host smart-4129017c-870b-4af0-9833-1286a88c6daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969274646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3969274646
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3244464784
Short name T451
Test name
Test status
Simulation time 268705227 ps
CPU time 2.81 seconds
Started Aug 09 05:21:57 PM PDT 24
Finished Aug 09 05:22:00 PM PDT 24
Peak memory 214456 kb
Host smart-28afe161-f5d2-480c-9279-63fb3feb3ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244464784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3244464784
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3728642959
Short name T750
Test name
Test status
Simulation time 129503164 ps
CPU time 2.56 seconds
Started Aug 09 05:21:57 PM PDT 24
Finished Aug 09 05:22:00 PM PDT 24
Peak memory 210544 kb
Host smart-3bc42938-2f8a-4b96-9869-eda0d6e8c246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728642959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3728642959
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1500266915
Short name T90
Test name
Test status
Simulation time 86176061 ps
CPU time 4.48 seconds
Started Aug 09 05:21:56 PM PDT 24
Finished Aug 09 05:22:01 PM PDT 24
Peak memory 214372 kb
Host smart-8b733dfd-32ce-4ad5-89e3-508bc507db85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500266915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1500266915
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.896475252
Short name T300
Test name
Test status
Simulation time 411669637 ps
CPU time 4.58 seconds
Started Aug 09 05:21:57 PM PDT 24
Finished Aug 09 05:22:02 PM PDT 24
Peak memory 214464 kb
Host smart-abbfc81e-5d00-4909-8c38-47a44af0a882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896475252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.896475252
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.871024360
Short name T863
Test name
Test status
Simulation time 153565928 ps
CPU time 3.11 seconds
Started Aug 09 05:21:57 PM PDT 24
Finished Aug 09 05:22:01 PM PDT 24
Peak memory 214284 kb
Host smart-c7df191d-a8fa-4fcb-9001-fd2f7794e783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871024360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.871024360
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3667204658
Short name T842
Test name
Test status
Simulation time 120105933 ps
CPU time 5.08 seconds
Started Aug 09 05:22:02 PM PDT 24
Finished Aug 09 05:22:07 PM PDT 24
Peak memory 214220 kb
Host smart-8fddce58-5b47-4670-9dc8-8ae07ae35be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667204658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3667204658
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2773126626
Short name T504
Test name
Test status
Simulation time 247580741 ps
CPU time 3.17 seconds
Started Aug 09 05:21:57 PM PDT 24
Finished Aug 09 05:22:00 PM PDT 24
Peak memory 207184 kb
Host smart-9a29e9b9-d072-46dc-aeab-ab2c0fe291e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773126626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2773126626
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1183327394
Short name T437
Test name
Test status
Simulation time 1158072578 ps
CPU time 8.11 seconds
Started Aug 09 05:21:55 PM PDT 24
Finished Aug 09 05:22:03 PM PDT 24
Peak memory 208708 kb
Host smart-07262ae0-903c-45e7-8d4c-590b422c0c6f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183327394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1183327394
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.731902360
Short name T912
Test name
Test status
Simulation time 2319492418 ps
CPU time 17.93 seconds
Started Aug 09 05:21:54 PM PDT 24
Finished Aug 09 05:22:12 PM PDT 24
Peak memory 208024 kb
Host smart-8aaf09df-00a0-4aa3-a563-5b8cf0a82e83
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731902360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.731902360
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1021682641
Short name T658
Test name
Test status
Simulation time 93910115 ps
CPU time 2.61 seconds
Started Aug 09 05:21:55 PM PDT 24
Finished Aug 09 05:21:58 PM PDT 24
Peak memory 208776 kb
Host smart-73bc057f-9699-4c09-9108-cc67be10e736
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021682641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1021682641
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.155228629
Short name T139
Test name
Test status
Simulation time 1105419322 ps
CPU time 14.47 seconds
Started Aug 09 05:21:58 PM PDT 24
Finished Aug 09 05:22:12 PM PDT 24
Peak memory 209484 kb
Host smart-57599fae-e177-47b0-9fa8-619b9f29e861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155228629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.155228629
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2305657087
Short name T755
Test name
Test status
Simulation time 280833270 ps
CPU time 3.5 seconds
Started Aug 09 05:21:57 PM PDT 24
Finished Aug 09 05:22:01 PM PDT 24
Peak memory 208428 kb
Host smart-400f9def-7ffc-4565-ab04-04c0d5d98ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305657087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2305657087
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.687585511
Short name T277
Test name
Test status
Simulation time 7901625941 ps
CPU time 133.13 seconds
Started Aug 09 05:22:01 PM PDT 24
Finished Aug 09 05:24:15 PM PDT 24
Peak memory 222468 kb
Host smart-bf1fa022-9f59-471b-9ed3-981ddd255dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687585511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.687585511
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.663612247
Short name T597
Test name
Test status
Simulation time 1388326934 ps
CPU time 20.6 seconds
Started Aug 09 05:21:58 PM PDT 24
Finished Aug 09 05:22:19 PM PDT 24
Peak memory 220380 kb
Host smart-961a549a-391f-4e50-ae62-ae45cd27e817
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663612247 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.663612247
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1699142503
Short name T892
Test name
Test status
Simulation time 1279676746 ps
CPU time 27.88 seconds
Started Aug 09 05:21:56 PM PDT 24
Finished Aug 09 05:22:24 PM PDT 24
Peak memory 208416 kb
Host smart-c2ff2107-6227-452f-9ac2-30563845a8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699142503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1699142503
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3033303448
Short name T769
Test name
Test status
Simulation time 43872716 ps
CPU time 2.23 seconds
Started Aug 09 05:21:57 PM PDT 24
Finished Aug 09 05:21:59 PM PDT 24
Peak memory 209860 kb
Host smart-2f8f7ce6-17e9-4c39-a014-83566c4ee668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033303448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3033303448
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2110139484
Short name T669
Test name
Test status
Simulation time 15041025 ps
CPU time 0.92 seconds
Started Aug 09 05:22:03 PM PDT 24
Finished Aug 09 05:22:04 PM PDT 24
Peak memory 206108 kb
Host smart-f7e571ed-2dc8-436d-94e8-7f21881cbcb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110139484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2110139484
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3924633281
Short name T14
Test name
Test status
Simulation time 34107785 ps
CPU time 1.99 seconds
Started Aug 09 05:22:04 PM PDT 24
Finished Aug 09 05:22:06 PM PDT 24
Peak memory 216616 kb
Host smart-36016254-6067-4636-b1c8-659cf33660b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924633281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3924633281
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.4014970253
Short name T557
Test name
Test status
Simulation time 72495367 ps
CPU time 3.37 seconds
Started Aug 09 05:22:05 PM PDT 24
Finished Aug 09 05:22:09 PM PDT 24
Peak memory 210252 kb
Host smart-bc29bc65-f829-4c24-960a-ba11a11876ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014970253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.4014970253
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1001249731
Short name T637
Test name
Test status
Simulation time 73892720 ps
CPU time 2.47 seconds
Started Aug 09 05:22:03 PM PDT 24
Finished Aug 09 05:22:06 PM PDT 24
Peak memory 214732 kb
Host smart-20f40f52-c002-485b-8635-6e124d99a0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001249731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1001249731
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2376638945
Short name T910
Test name
Test status
Simulation time 140838179 ps
CPU time 3.3 seconds
Started Aug 09 05:22:05 PM PDT 24
Finished Aug 09 05:22:09 PM PDT 24
Peak memory 222484 kb
Host smart-76c9be62-411f-4abb-b024-681149a2cd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376638945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2376638945
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1211499824
Short name T680
Test name
Test status
Simulation time 122576502 ps
CPU time 5.88 seconds
Started Aug 09 05:22:05 PM PDT 24
Finished Aug 09 05:22:11 PM PDT 24
Peak memory 214280 kb
Host smart-608e0c4c-2e65-4449-a897-4972d24ae806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211499824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1211499824
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1879512389
Short name T269
Test name
Test status
Simulation time 13328520731 ps
CPU time 39.37 seconds
Started Aug 09 05:22:07 PM PDT 24
Finished Aug 09 05:22:47 PM PDT 24
Peak memory 207856 kb
Host smart-dee159cf-3c3e-43ba-9b31-a8f173b0871b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879512389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1879512389
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1678981020
Short name T747
Test name
Test status
Simulation time 93166562 ps
CPU time 4.29 seconds
Started Aug 09 05:22:05 PM PDT 24
Finished Aug 09 05:22:10 PM PDT 24
Peak memory 208652 kb
Host smart-8f5efca7-b771-4347-b2c5-e487dabb0375
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678981020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1678981020
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3246806354
Short name T481
Test name
Test status
Simulation time 76069427 ps
CPU time 3.52 seconds
Started Aug 09 05:22:03 PM PDT 24
Finished Aug 09 05:22:06 PM PDT 24
Peak memory 207876 kb
Host smart-de9de081-8f40-424a-b3f8-6ea8b04563e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246806354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3246806354
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1748247746
Short name T480
Test name
Test status
Simulation time 93701431 ps
CPU time 2.23 seconds
Started Aug 09 05:22:04 PM PDT 24
Finished Aug 09 05:22:07 PM PDT 24
Peak memory 208776 kb
Host smart-738ee7ef-f903-4c6a-ba41-d60d7cb615dd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748247746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1748247746
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3100124461
Short name T737
Test name
Test status
Simulation time 128550142 ps
CPU time 1.7 seconds
Started Aug 09 05:22:04 PM PDT 24
Finished Aug 09 05:22:06 PM PDT 24
Peak memory 208236 kb
Host smart-d95f1a1e-53cb-4088-af0c-8e252f9c83b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100124461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3100124461
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.205306505
Short name T855
Test name
Test status
Simulation time 266796111 ps
CPU time 3.15 seconds
Started Aug 09 05:21:58 PM PDT 24
Finished Aug 09 05:22:02 PM PDT 24
Peak memory 208604 kb
Host smart-94ad32ec-b0c3-401b-8a6c-05b9e29333bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205306505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.205306505
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3459230917
Short name T196
Test name
Test status
Simulation time 95525969 ps
CPU time 4.81 seconds
Started Aug 09 05:22:03 PM PDT 24
Finished Aug 09 05:22:08 PM PDT 24
Peak memory 209464 kb
Host smart-10754b9a-1115-43af-a296-37e4e309a917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459230917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3459230917
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2322165939
Short name T457
Test name
Test status
Simulation time 19489752 ps
CPU time 0.87 seconds
Started Aug 09 05:22:11 PM PDT 24
Finished Aug 09 05:22:12 PM PDT 24
Peak memory 205996 kb
Host smart-7715db07-8fdc-4555-a738-6d1d3ff70f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322165939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2322165939
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.629042161
Short name T578
Test name
Test status
Simulation time 239298913 ps
CPU time 3.02 seconds
Started Aug 09 05:22:10 PM PDT 24
Finished Aug 09 05:22:13 PM PDT 24
Peak memory 214516 kb
Host smart-e6908b7b-502a-4d7f-b8ae-99f03461a942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629042161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.629042161
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.812011707
Short name T310
Test name
Test status
Simulation time 36329982 ps
CPU time 2.43 seconds
Started Aug 09 05:22:06 PM PDT 24
Finished Aug 09 05:22:08 PM PDT 24
Peak memory 209720 kb
Host smart-a2c632b9-d482-47d0-98cb-51745535b27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812011707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.812011707
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3565613043
Short name T286
Test name
Test status
Simulation time 55814014 ps
CPU time 2.22 seconds
Started Aug 09 05:22:03 PM PDT 24
Finished Aug 09 05:22:05 PM PDT 24
Peak memory 214200 kb
Host smart-6a20118a-a0a2-4972-b89d-9d81b2050a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565613043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3565613043
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.62327805
Short name T250
Test name
Test status
Simulation time 489439051 ps
CPU time 4.19 seconds
Started Aug 09 05:22:05 PM PDT 24
Finished Aug 09 05:22:09 PM PDT 24
Peak memory 215000 kb
Host smart-e777abaa-5542-40b6-b6a3-1f7fe7b37fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62327805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.62327805
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.771932636
Short name T894
Test name
Test status
Simulation time 2654552481 ps
CPU time 5.05 seconds
Started Aug 09 05:22:02 PM PDT 24
Finished Aug 09 05:22:07 PM PDT 24
Peak memory 214468 kb
Host smart-ba015fde-9cd9-481f-b1fe-3179ef2126de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771932636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.771932636
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1245962316
Short name T561
Test name
Test status
Simulation time 582071714 ps
CPU time 3.44 seconds
Started Aug 09 05:22:06 PM PDT 24
Finished Aug 09 05:22:09 PM PDT 24
Peak memory 209232 kb
Host smart-ab5b65f4-40a5-44af-8122-d7ceebcd4c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245962316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1245962316
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2753016302
Short name T782
Test name
Test status
Simulation time 126365466 ps
CPU time 2.33 seconds
Started Aug 09 05:22:04 PM PDT 24
Finished Aug 09 05:22:07 PM PDT 24
Peak memory 206804 kb
Host smart-bc8193da-1de0-4bbc-97be-eeb0ff20b3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753016302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2753016302
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3079560248
Short name T612
Test name
Test status
Simulation time 774265365 ps
CPU time 4.33 seconds
Started Aug 09 05:22:03 PM PDT 24
Finished Aug 09 05:22:07 PM PDT 24
Peak memory 207936 kb
Host smart-c52ee04c-1724-4b90-95c4-aa706a012e51
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079560248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3079560248
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.124574898
Short name T463
Test name
Test status
Simulation time 1689297375 ps
CPU time 58.95 seconds
Started Aug 09 05:22:04 PM PDT 24
Finished Aug 09 05:23:03 PM PDT 24
Peak memory 208148 kb
Host smart-b5879914-cf0f-486e-ac16-6f6d086ae259
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124574898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.124574898
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.78863564
Short name T763
Test name
Test status
Simulation time 167183210 ps
CPU time 3.62 seconds
Started Aug 09 05:22:05 PM PDT 24
Finished Aug 09 05:22:09 PM PDT 24
Peak memory 208736 kb
Host smart-66d77af5-c3c9-449f-a179-5f250f7dc4f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78863564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.78863564
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2467565030
Short name T683
Test name
Test status
Simulation time 101056916 ps
CPU time 2.45 seconds
Started Aug 09 05:22:10 PM PDT 24
Finished Aug 09 05:22:13 PM PDT 24
Peak memory 209552 kb
Host smart-0df39361-6e13-4acb-9c21-fbcc91806bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467565030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2467565030
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1584147011
Short name T898
Test name
Test status
Simulation time 394065897 ps
CPU time 7.73 seconds
Started Aug 09 05:22:04 PM PDT 24
Finished Aug 09 05:22:12 PM PDT 24
Peak memory 207948 kb
Host smart-f9b5ffe1-5ae5-4ab7-ab86-df2c2ce339a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584147011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1584147011
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2602658640
Short name T518
Test name
Test status
Simulation time 626410924 ps
CPU time 15.14 seconds
Started Aug 09 05:22:12 PM PDT 24
Finished Aug 09 05:22:27 PM PDT 24
Peak memory 222468 kb
Host smart-5563ad47-b15d-4de2-b118-9495b2bcd1eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602658640 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2602658640
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2294893568
Short name T742
Test name
Test status
Simulation time 176580681 ps
CPU time 3.48 seconds
Started Aug 09 05:22:04 PM PDT 24
Finished Aug 09 05:22:07 PM PDT 24
Peak memory 208024 kb
Host smart-c0f00c93-27a0-42fa-a86d-bc793d9e1d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294893568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2294893568
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.264092383
Short name T718
Test name
Test status
Simulation time 79907749 ps
CPU time 3.07 seconds
Started Aug 09 05:22:10 PM PDT 24
Finished Aug 09 05:22:13 PM PDT 24
Peak memory 210196 kb
Host smart-ba084288-8fa7-408d-8d88-f87f0918b172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264092383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.264092383
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.121287158
Short name T435
Test name
Test status
Simulation time 53574011 ps
CPU time 0.91 seconds
Started Aug 09 05:22:10 PM PDT 24
Finished Aug 09 05:22:11 PM PDT 24
Peak memory 206016 kb
Host smart-1197d244-ea09-455f-8122-8085e687e9ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121287158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.121287158
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1274945773
Short name T415
Test name
Test status
Simulation time 35291643 ps
CPU time 2.91 seconds
Started Aug 09 05:22:12 PM PDT 24
Finished Aug 09 05:22:15 PM PDT 24
Peak memory 214236 kb
Host smart-029ba0e5-443d-46aa-a09f-c97c376d2bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1274945773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1274945773
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4049262854
Short name T522
Test name
Test status
Simulation time 105314020 ps
CPU time 2.35 seconds
Started Aug 09 05:22:13 PM PDT 24
Finished Aug 09 05:22:15 PM PDT 24
Peak memory 214328 kb
Host smart-0033afbc-13e7-4880-8be4-67a57c5b4053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049262854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4049262854
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1026663502
Short name T333
Test name
Test status
Simulation time 748910165 ps
CPU time 7.08 seconds
Started Aug 09 05:22:12 PM PDT 24
Finished Aug 09 05:22:19 PM PDT 24
Peak memory 214200 kb
Host smart-28351fb5-fbfb-416a-ba20-eacd22e397ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026663502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1026663502
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1302289507
Short name T826
Test name
Test status
Simulation time 101405823 ps
CPU time 3.25 seconds
Started Aug 09 05:22:14 PM PDT 24
Finished Aug 09 05:22:17 PM PDT 24
Peak memory 208188 kb
Host smart-fb9119d5-7050-4fb4-93e0-380de6c72086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302289507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1302289507
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.172380757
Short name T532
Test name
Test status
Simulation time 361863197 ps
CPU time 5.24 seconds
Started Aug 09 05:22:11 PM PDT 24
Finished Aug 09 05:22:16 PM PDT 24
Peak memory 208088 kb
Host smart-c3e8e3a3-f298-458e-ba19-282af841df67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172380757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.172380757
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1517004179
Short name T565
Test name
Test status
Simulation time 64126010 ps
CPU time 3.1 seconds
Started Aug 09 05:22:12 PM PDT 24
Finished Aug 09 05:22:15 PM PDT 24
Peak memory 208560 kb
Host smart-295b32f3-4ec1-429b-afb3-883db12d9853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517004179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1517004179
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.118506158
Short name T201
Test name
Test status
Simulation time 209952601 ps
CPU time 8.05 seconds
Started Aug 09 05:22:11 PM PDT 24
Finished Aug 09 05:22:19 PM PDT 24
Peak memory 208608 kb
Host smart-4fa4f537-8c01-463b-8eb7-e21a21f76e87
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118506158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.118506158
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.257547432
Short name T596
Test name
Test status
Simulation time 128752698 ps
CPU time 3.83 seconds
Started Aug 09 05:22:11 PM PDT 24
Finished Aug 09 05:22:15 PM PDT 24
Peak memory 206824 kb
Host smart-8aeb962b-231f-47e1-9169-afaefbbb43cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257547432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.257547432
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.431694665
Short name T730
Test name
Test status
Simulation time 72597209 ps
CPU time 1.73 seconds
Started Aug 09 05:22:10 PM PDT 24
Finished Aug 09 05:22:11 PM PDT 24
Peak memory 205612 kb
Host smart-98909463-2859-478f-b57d-bf4ade0b8966
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431694665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.431694665
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.661462917
Short name T703
Test name
Test status
Simulation time 201556728 ps
CPU time 5.4 seconds
Started Aug 09 05:22:14 PM PDT 24
Finished Aug 09 05:22:19 PM PDT 24
Peak memory 209596 kb
Host smart-76f8b0c2-d688-4f80-aa88-151e24561220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661462917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.661462917
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1378111825
Short name T915
Test name
Test status
Simulation time 59055220 ps
CPU time 2.23 seconds
Started Aug 09 05:22:13 PM PDT 24
Finished Aug 09 05:22:15 PM PDT 24
Peak memory 206728 kb
Host smart-7bfe277a-2e6e-403e-a0f7-a4070eaa2ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378111825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1378111825
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.4209983380
Short name T887
Test name
Test status
Simulation time 3220331044 ps
CPU time 16.32 seconds
Started Aug 09 05:22:11 PM PDT 24
Finished Aug 09 05:22:27 PM PDT 24
Peak memory 217012 kb
Host smart-a92a151a-1ba4-4e99-8d3a-096e48d9afaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209983380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.4209983380
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.178209385
Short name T296
Test name
Test status
Simulation time 369834009 ps
CPU time 13.65 seconds
Started Aug 09 05:22:10 PM PDT 24
Finished Aug 09 05:22:24 PM PDT 24
Peak memory 222752 kb
Host smart-40eddb78-e745-4690-8dad-e44439d38a04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178209385 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.178209385
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.490091312
Short name T1
Test name
Test status
Simulation time 53674723 ps
CPU time 2.28 seconds
Started Aug 09 05:22:11 PM PDT 24
Finished Aug 09 05:22:14 PM PDT 24
Peak memory 208324 kb
Host smart-2ad7f4cb-11bd-4c34-8d1a-0571750b6642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490091312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.490091312
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.160649996
Short name T805
Test name
Test status
Simulation time 49891797 ps
CPU time 2.3 seconds
Started Aug 09 05:22:10 PM PDT 24
Finished Aug 09 05:22:13 PM PDT 24
Peak memory 209564 kb
Host smart-2dcd52b3-be32-4137-a4d2-e7bd2aa63451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160649996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.160649996
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1169615338
Short name T553
Test name
Test status
Simulation time 15214694 ps
CPU time 0.79 seconds
Started Aug 09 05:20:57 PM PDT 24
Finished Aug 09 05:20:58 PM PDT 24
Peak memory 206148 kb
Host smart-fe001985-1378-4988-88e9-5b824cb60728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169615338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1169615338
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3511869011
Short name T727
Test name
Test status
Simulation time 71193934 ps
CPU time 2.26 seconds
Started Aug 09 05:20:56 PM PDT 24
Finished Aug 09 05:20:59 PM PDT 24
Peak memory 208976 kb
Host smart-6dc0fc20-a09f-47c7-9f08-94217cef2978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511869011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3511869011
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.637987313
Short name T465
Test name
Test status
Simulation time 163907273 ps
CPU time 2.8 seconds
Started Aug 09 05:20:57 PM PDT 24
Finished Aug 09 05:21:00 PM PDT 24
Peak memory 208028 kb
Host smart-bb45077f-2139-4046-b945-dd7c13d6215d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637987313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.637987313
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1183841634
Short name T563
Test name
Test status
Simulation time 179421744 ps
CPU time 4.39 seconds
Started Aug 09 05:20:57 PM PDT 24
Finished Aug 09 05:21:02 PM PDT 24
Peak memory 222328 kb
Host smart-08c25828-0b2b-4ec2-be01-ad857e44b357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183841634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1183841634
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2619837032
Short name T749
Test name
Test status
Simulation time 174078935 ps
CPU time 4.59 seconds
Started Aug 09 05:20:58 PM PDT 24
Finished Aug 09 05:21:03 PM PDT 24
Peak memory 222556 kb
Host smart-bbbff952-a91c-41af-bd15-e608ca3afecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619837032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2619837032
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3813237542
Short name T523
Test name
Test status
Simulation time 168497568 ps
CPU time 6.53 seconds
Started Aug 09 05:20:58 PM PDT 24
Finished Aug 09 05:21:04 PM PDT 24
Peak memory 214412 kb
Host smart-33c17f51-2b9a-4cdd-a6ac-f6e7f28921c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813237542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3813237542
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2374698089
Short name T610
Test name
Test status
Simulation time 19279761 ps
CPU time 1.64 seconds
Started Aug 09 05:20:57 PM PDT 24
Finished Aug 09 05:20:58 PM PDT 24
Peak memory 206868 kb
Host smart-5a58b8c5-fd26-4f6a-90e5-891438185555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374698089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2374698089
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.4285083181
Short name T717
Test name
Test status
Simulation time 19850814 ps
CPU time 1.76 seconds
Started Aug 09 05:20:57 PM PDT 24
Finished Aug 09 05:20:58 PM PDT 24
Peak memory 207008 kb
Host smart-9654e4eb-04bd-4285-a520-c676f8906c91
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285083181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.4285083181
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1655807134
Short name T454
Test name
Test status
Simulation time 2987064033 ps
CPU time 53.9 seconds
Started Aug 09 05:21:00 PM PDT 24
Finished Aug 09 05:21:54 PM PDT 24
Peak memory 208504 kb
Host smart-1d568960-4700-4a38-ae94-8763618fcad0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655807134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1655807134
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.924622825
Short name T618
Test name
Test status
Simulation time 121891824 ps
CPU time 3.6 seconds
Started Aug 09 05:20:57 PM PDT 24
Finished Aug 09 05:21:01 PM PDT 24
Peak memory 206792 kb
Host smart-5909abd7-2ebb-4610-8cfa-7b9fd65aadb5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924622825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.924622825
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3708708821
Short name T394
Test name
Test status
Simulation time 101053537 ps
CPU time 2.26 seconds
Started Aug 09 05:20:57 PM PDT 24
Finished Aug 09 05:20:59 PM PDT 24
Peak memory 208884 kb
Host smart-8d60ac44-e133-4930-8de9-bfec65c6c504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708708821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3708708821
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1214400525
Short name T82
Test name
Test status
Simulation time 517100066 ps
CPU time 11.12 seconds
Started Aug 09 05:20:49 PM PDT 24
Finished Aug 09 05:21:00 PM PDT 24
Peak memory 208796 kb
Host smart-1dac408d-334a-4c17-b708-1aa1a073a0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214400525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1214400525
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1177595604
Short name T824
Test name
Test status
Simulation time 55061300 ps
CPU time 3.55 seconds
Started Aug 09 05:20:58 PM PDT 24
Finished Aug 09 05:21:02 PM PDT 24
Peak memory 214332 kb
Host smart-b0127559-37c5-44d2-94cd-4979c612f347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177595604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1177595604
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3355334558
Short name T380
Test name
Test status
Simulation time 60956068 ps
CPU time 2.51 seconds
Started Aug 09 05:20:59 PM PDT 24
Finished Aug 09 05:21:02 PM PDT 24
Peak memory 210884 kb
Host smart-e5c494dd-4c37-49a4-973a-e248bd5a978f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355334558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3355334558
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2815748833
Short name T424
Test name
Test status
Simulation time 24385807 ps
CPU time 0.78 seconds
Started Aug 09 05:22:17 PM PDT 24
Finished Aug 09 05:22:18 PM PDT 24
Peak memory 205964 kb
Host smart-316bacb3-2005-4914-87e4-7193251eaebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815748833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2815748833
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3666127433
Short name T416
Test name
Test status
Simulation time 56060623 ps
CPU time 2.43 seconds
Started Aug 09 05:22:12 PM PDT 24
Finished Aug 09 05:22:15 PM PDT 24
Peak memory 214312 kb
Host smart-6d19ba2e-65b8-4da2-b9dd-ce055e91126e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3666127433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3666127433
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4285213699
Short name T579
Test name
Test status
Simulation time 58157936 ps
CPU time 2.87 seconds
Started Aug 09 05:22:11 PM PDT 24
Finished Aug 09 05:22:14 PM PDT 24
Peak memory 214240 kb
Host smart-873d453e-ef56-4e1f-9ba7-f9f08876bf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285213699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4285213699
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1250270962
Short name T89
Test name
Test status
Simulation time 266410301 ps
CPU time 2.69 seconds
Started Aug 09 05:22:10 PM PDT 24
Finished Aug 09 05:22:13 PM PDT 24
Peak memory 214332 kb
Host smart-b248437d-89c6-4408-b5f4-73f72bf1aab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250270962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1250270962
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1086108086
Short name T876
Test name
Test status
Simulation time 65443856 ps
CPU time 3.06 seconds
Started Aug 09 05:22:11 PM PDT 24
Finished Aug 09 05:22:14 PM PDT 24
Peak memory 222396 kb
Host smart-e041b983-eb48-4a12-ba1b-8db40fc43afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086108086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1086108086
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3288950838
Short name T208
Test name
Test status
Simulation time 263718366 ps
CPU time 4.25 seconds
Started Aug 09 05:22:09 PM PDT 24
Finished Aug 09 05:22:14 PM PDT 24
Peak memory 219732 kb
Host smart-1f733d78-79ee-4996-a288-22a73bbaf363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288950838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3288950838
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1332068444
Short name T629
Test name
Test status
Simulation time 54413607 ps
CPU time 3.24 seconds
Started Aug 09 05:22:10 PM PDT 24
Finished Aug 09 05:22:14 PM PDT 24
Peak memory 210124 kb
Host smart-56629864-9f8d-4279-9573-3988a38f2d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332068444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1332068444
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3595461191
Short name T847
Test name
Test status
Simulation time 62604912 ps
CPU time 2.78 seconds
Started Aug 09 05:22:13 PM PDT 24
Finished Aug 09 05:22:16 PM PDT 24
Peak memory 206864 kb
Host smart-aec95650-c454-4c2d-af94-2007172d2aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595461191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3595461191
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.778157380
Short name T265
Test name
Test status
Simulation time 37905148 ps
CPU time 2.45 seconds
Started Aug 09 05:22:10 PM PDT 24
Finished Aug 09 05:22:13 PM PDT 24
Peak memory 208808 kb
Host smart-27c83301-781c-4fa3-8607-93b007331a3c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778157380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.778157380
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.482856896
Short name T828
Test name
Test status
Simulation time 272712392 ps
CPU time 2.81 seconds
Started Aug 09 05:22:11 PM PDT 24
Finished Aug 09 05:22:14 PM PDT 24
Peak memory 208388 kb
Host smart-1f4a5df4-ee0e-4c8f-b577-1e990ac8e89d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482856896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.482856896
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2858389463
Short name T84
Test name
Test status
Simulation time 205815453 ps
CPU time 5.39 seconds
Started Aug 09 05:22:11 PM PDT 24
Finished Aug 09 05:22:16 PM PDT 24
Peak memory 208204 kb
Host smart-848408fe-2f0a-47ee-afcd-f04cc0ce4394
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858389463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2858389463
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.306205116
Short name T499
Test name
Test status
Simulation time 97557406 ps
CPU time 4.3 seconds
Started Aug 09 05:22:14 PM PDT 24
Finished Aug 09 05:22:19 PM PDT 24
Peak memory 218380 kb
Host smart-7df69931-e9b7-4da1-ba8d-395a3bd73166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306205116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.306205116
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.297123932
Short name T865
Test name
Test status
Simulation time 782164776 ps
CPU time 9.34 seconds
Started Aug 09 05:22:12 PM PDT 24
Finished Aug 09 05:22:21 PM PDT 24
Peak memory 208432 kb
Host smart-9c3d1d14-fdea-45a8-a909-6927e9d633c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297123932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.297123932
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2340642342
Short name T59
Test name
Test status
Simulation time 660761912 ps
CPU time 12.9 seconds
Started Aug 09 05:22:10 PM PDT 24
Finished Aug 09 05:22:23 PM PDT 24
Peak memory 214072 kb
Host smart-87cc4bdf-617c-4d70-b950-6101408b0fb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340642342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2340642342
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2269883770
Short name T871
Test name
Test status
Simulation time 7263135274 ps
CPU time 60.9 seconds
Started Aug 09 05:22:09 PM PDT 24
Finished Aug 09 05:23:10 PM PDT 24
Peak memory 208752 kb
Host smart-8ca444b3-c89a-4ffe-8bd4-e535456d3a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269883770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2269883770
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.767203047
Short name T63
Test name
Test status
Simulation time 904720070 ps
CPU time 4.46 seconds
Started Aug 09 05:22:11 PM PDT 24
Finished Aug 09 05:22:16 PM PDT 24
Peak memory 210312 kb
Host smart-61bf6555-21bd-461c-b2a1-4ee5889eaa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767203047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.767203047
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1166328797
Short name T726
Test name
Test status
Simulation time 14165143 ps
CPU time 0.74 seconds
Started Aug 09 05:22:19 PM PDT 24
Finished Aug 09 05:22:20 PM PDT 24
Peak memory 205960 kb
Host smart-872f732e-16b4-42a9-afc5-b287c8c732ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166328797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1166328797
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.4052295269
Short name T350
Test name
Test status
Simulation time 993935726 ps
CPU time 4.71 seconds
Started Aug 09 05:22:16 PM PDT 24
Finished Aug 09 05:22:21 PM PDT 24
Peak memory 214344 kb
Host smart-1809c771-e8ea-4b5c-830f-997efe4b775d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4052295269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.4052295269
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3030672852
Short name T27
Test name
Test status
Simulation time 130431188 ps
CPU time 2.72 seconds
Started Aug 09 05:22:16 PM PDT 24
Finished Aug 09 05:22:19 PM PDT 24
Peak memory 206236 kb
Host smart-be121121-1a26-4afc-85a1-bfe2cb78abe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030672852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3030672852
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.4028069877
Short name T48
Test name
Test status
Simulation time 724588981 ps
CPU time 2.99 seconds
Started Aug 09 05:22:17 PM PDT 24
Finished Aug 09 05:22:21 PM PDT 24
Peak memory 214308 kb
Host smart-c7dea9bb-f96f-49cc-8549-fea4ce452bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028069877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.4028069877
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1995287686
Short name T94
Test name
Test status
Simulation time 215868113 ps
CPU time 6.89 seconds
Started Aug 09 05:22:18 PM PDT 24
Finished Aug 09 05:22:26 PM PDT 24
Peak memory 214324 kb
Host smart-2238362e-38be-44bf-9bde-273f99d99fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995287686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1995287686
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.645337615
Short name T357
Test name
Test status
Simulation time 40197585 ps
CPU time 2.36 seconds
Started Aug 09 05:22:18 PM PDT 24
Finished Aug 09 05:22:21 PM PDT 24
Peak memory 214256 kb
Host smart-a7510e31-ca73-4c73-aa17-c787b501f606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645337615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.645337615
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2377299528
Short name T791
Test name
Test status
Simulation time 124719198 ps
CPU time 2.51 seconds
Started Aug 09 05:22:18 PM PDT 24
Finished Aug 09 05:22:21 PM PDT 24
Peak memory 219864 kb
Host smart-1c4558de-013e-4a4f-a745-152efa2ddded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377299528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2377299528
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3640275723
Short name T857
Test name
Test status
Simulation time 515421740 ps
CPU time 5.87 seconds
Started Aug 09 05:22:20 PM PDT 24
Finished Aug 09 05:22:26 PM PDT 24
Peak memory 209056 kb
Host smart-8b487fe9-118d-4b98-892e-7337b6d6fc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640275723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3640275723
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2598213987
Short name T665
Test name
Test status
Simulation time 437729247 ps
CPU time 5.91 seconds
Started Aug 09 05:22:17 PM PDT 24
Finished Aug 09 05:22:23 PM PDT 24
Peak memory 209196 kb
Host smart-d3b27d32-7c2e-4a8e-a401-4ab8186c61bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598213987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2598213987
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3022056197
Short name T778
Test name
Test status
Simulation time 93828345 ps
CPU time 3.88 seconds
Started Aug 09 05:22:19 PM PDT 24
Finished Aug 09 05:22:23 PM PDT 24
Peak memory 208572 kb
Host smart-b4559e13-60ba-4e77-9cd5-d9d8e7855acb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022056197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3022056197
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2971811809
Short name T776
Test name
Test status
Simulation time 1375900411 ps
CPU time 33.55 seconds
Started Aug 09 05:22:15 PM PDT 24
Finished Aug 09 05:22:48 PM PDT 24
Peak memory 208124 kb
Host smart-ea8784f3-3cd0-4fbc-a860-52cfa8a9cd3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971811809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2971811809
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2662804174
Short name T638
Test name
Test status
Simulation time 336572510 ps
CPU time 3.81 seconds
Started Aug 09 05:22:20 PM PDT 24
Finished Aug 09 05:22:24 PM PDT 24
Peak memory 206904 kb
Host smart-7820ae7b-eddb-4b0a-92bf-c1cd9cde58fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662804174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2662804174
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2823031270
Short name T332
Test name
Test status
Simulation time 97696843 ps
CPU time 3.9 seconds
Started Aug 09 05:22:24 PM PDT 24
Finished Aug 09 05:22:28 PM PDT 24
Peak memory 208912 kb
Host smart-abc4db50-f0e2-4322-9bff-cfcd0c11e1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823031270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2823031270
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3022892114
Short name T466
Test name
Test status
Simulation time 227613710 ps
CPU time 5.3 seconds
Started Aug 09 05:22:19 PM PDT 24
Finished Aug 09 05:22:25 PM PDT 24
Peak memory 208464 kb
Host smart-a58623cb-d1bd-4c44-a842-a0020098c42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022892114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3022892114
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2325010277
Short name T178
Test name
Test status
Simulation time 270771207 ps
CPU time 3.89 seconds
Started Aug 09 05:22:18 PM PDT 24
Finished Aug 09 05:22:22 PM PDT 24
Peak memory 209424 kb
Host smart-37e6a620-bef6-4c67-9660-0ec88aaa2ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325010277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2325010277
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.920353970
Short name T153
Test name
Test status
Simulation time 142302060 ps
CPU time 2.31 seconds
Started Aug 09 05:22:17 PM PDT 24
Finished Aug 09 05:22:19 PM PDT 24
Peak memory 210128 kb
Host smart-071190f4-a6f6-430e-9736-d96b290afe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920353970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.920353970
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2122770332
Short name T421
Test name
Test status
Simulation time 15235535 ps
CPU time 0.76 seconds
Started Aug 09 05:22:17 PM PDT 24
Finished Aug 09 05:22:18 PM PDT 24
Peak memory 205956 kb
Host smart-94319a7c-0d2b-4abe-9e0f-60beeddba266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122770332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2122770332
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.56478169
Short name T66
Test name
Test status
Simulation time 386003367 ps
CPU time 3.82 seconds
Started Aug 09 05:22:17 PM PDT 24
Finished Aug 09 05:22:21 PM PDT 24
Peak memory 222684 kb
Host smart-eca8764e-036d-4560-a313-71b2c939a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56478169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.56478169
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2210099926
Short name T772
Test name
Test status
Simulation time 378366692 ps
CPU time 4.27 seconds
Started Aug 09 05:22:19 PM PDT 24
Finished Aug 09 05:22:23 PM PDT 24
Peak memory 207504 kb
Host smart-a90c55e3-c11d-4501-8140-9e9594df7aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210099926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2210099926
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2209449280
Short name T93
Test name
Test status
Simulation time 440921357 ps
CPU time 5.29 seconds
Started Aug 09 05:22:24 PM PDT 24
Finished Aug 09 05:22:30 PM PDT 24
Peak memory 214280 kb
Host smart-dd3363eb-be37-4a93-b94f-0a8b6430fcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209449280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2209449280
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.879684316
Short name T323
Test name
Test status
Simulation time 73332468 ps
CPU time 1.67 seconds
Started Aug 09 05:22:23 PM PDT 24
Finished Aug 09 05:22:25 PM PDT 24
Peak memory 214144 kb
Host smart-eced7b43-b879-4aa4-891c-31096c1b50e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879684316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.879684316
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.433904670
Short name T883
Test name
Test status
Simulation time 101185909 ps
CPU time 3.08 seconds
Started Aug 09 05:22:17 PM PDT 24
Finished Aug 09 05:22:20 PM PDT 24
Peak memory 219916 kb
Host smart-069cb8b3-0f32-4790-844b-7d7c0b8c0270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433904670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.433904670
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1452617464
Short name T713
Test name
Test status
Simulation time 102067782 ps
CPU time 5.06 seconds
Started Aug 09 05:22:18 PM PDT 24
Finished Aug 09 05:22:23 PM PDT 24
Peak memory 209904 kb
Host smart-f452a789-6568-4265-8df7-fdcf65f70726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452617464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1452617464
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.248127222
Short name T844
Test name
Test status
Simulation time 439473446 ps
CPU time 5.42 seconds
Started Aug 09 05:22:18 PM PDT 24
Finished Aug 09 05:22:23 PM PDT 24
Peak memory 208332 kb
Host smart-7948b459-7dd5-4cb5-bf12-61040f999199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248127222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.248127222
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.407037526
Short name T344
Test name
Test status
Simulation time 78692275 ps
CPU time 2.96 seconds
Started Aug 09 05:22:17 PM PDT 24
Finished Aug 09 05:22:20 PM PDT 24
Peak memory 208200 kb
Host smart-88b0514d-ee72-494b-bd36-fead3a774d7c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407037526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.407037526
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1961297164
Short name T535
Test name
Test status
Simulation time 173026956 ps
CPU time 2.79 seconds
Started Aug 09 05:22:21 PM PDT 24
Finished Aug 09 05:22:24 PM PDT 24
Peak memory 206772 kb
Host smart-17c9f4c7-d818-4921-ad72-ee3703ba1df3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961297164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1961297164
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.598610165
Short name T554
Test name
Test status
Simulation time 51634220 ps
CPU time 2.88 seconds
Started Aug 09 05:22:17 PM PDT 24
Finished Aug 09 05:22:20 PM PDT 24
Peak memory 207012 kb
Host smart-49fe4c62-16b7-4ef2-afc3-c90402340924
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598610165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.598610165
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3081039508
Short name T819
Test name
Test status
Simulation time 1661942015 ps
CPU time 16.18 seconds
Started Aug 09 05:22:17 PM PDT 24
Finished Aug 09 05:22:33 PM PDT 24
Peak memory 209828 kb
Host smart-055685c9-e3b7-4ea1-8649-9c83c78e7144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081039508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3081039508
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.688144758
Short name T484
Test name
Test status
Simulation time 101864076 ps
CPU time 2.51 seconds
Started Aug 09 05:22:16 PM PDT 24
Finished Aug 09 05:22:18 PM PDT 24
Peak memory 206776 kb
Host smart-4bc9a8ad-33b6-44a8-8d44-32b101171a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688144758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.688144758
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3718528237
Short name T169
Test name
Test status
Simulation time 5367670235 ps
CPU time 20.99 seconds
Started Aug 09 05:22:15 PM PDT 24
Finished Aug 09 05:22:36 PM PDT 24
Peak memory 216136 kb
Host smart-d012a1a6-136b-4dbb-9856-12025393aedd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718528237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3718528237
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3023482842
Short name T832
Test name
Test status
Simulation time 94471713 ps
CPU time 3.97 seconds
Started Aug 09 05:22:17 PM PDT 24
Finished Aug 09 05:22:21 PM PDT 24
Peak memory 207416 kb
Host smart-4397e669-8702-4ec5-b7ed-318bac413f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023482842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3023482842
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.853918306
Short name T397
Test name
Test status
Simulation time 400608691 ps
CPU time 8.9 seconds
Started Aug 09 05:22:16 PM PDT 24
Finished Aug 09 05:22:25 PM PDT 24
Peak memory 210744 kb
Host smart-318cdd2e-3a22-4ba6-929f-b8ff2d98652e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853918306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.853918306
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3743472374
Short name T446
Test name
Test status
Simulation time 37948878 ps
CPU time 0.81 seconds
Started Aug 09 05:22:27 PM PDT 24
Finished Aug 09 05:22:28 PM PDT 24
Peak memory 205952 kb
Host smart-8e68a258-62cc-48a4-8df6-6cdc55434ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743472374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3743472374
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2080471154
Short name T122
Test name
Test status
Simulation time 66069086 ps
CPU time 3.78 seconds
Started Aug 09 05:22:19 PM PDT 24
Finished Aug 09 05:22:23 PM PDT 24
Peak memory 214348 kb
Host smart-16580796-81fa-417f-879e-0f0578b4f142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080471154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2080471154
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3189889073
Short name T796
Test name
Test status
Simulation time 143324417 ps
CPU time 3.8 seconds
Started Aug 09 05:22:24 PM PDT 24
Finished Aug 09 05:22:28 PM PDT 24
Peak memory 214108 kb
Host smart-44dbcffb-0092-480b-bcf3-ddedba9b838d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189889073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3189889073
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3900917195
Short name T447
Test name
Test status
Simulation time 49958699 ps
CPU time 2.98 seconds
Started Aug 09 05:22:19 PM PDT 24
Finished Aug 09 05:22:22 PM PDT 24
Peak memory 213504 kb
Host smart-7aaf1eb3-7ee3-41e2-8402-8e4296f0cf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900917195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3900917195
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4201874829
Short name T419
Test name
Test status
Simulation time 525939847 ps
CPU time 3.67 seconds
Started Aug 09 05:22:19 PM PDT 24
Finished Aug 09 05:22:23 PM PDT 24
Peak memory 207788 kb
Host smart-2a3a4456-264a-40b1-845e-f2f9233e4dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201874829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4201874829
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1946146407
Short name T733
Test name
Test status
Simulation time 100302193 ps
CPU time 3.02 seconds
Started Aug 09 05:22:24 PM PDT 24
Finished Aug 09 05:22:27 PM PDT 24
Peak memory 214264 kb
Host smart-29a9500f-fa6e-47de-88cd-f22b32c6e9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946146407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1946146407
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1953620096
Short name T468
Test name
Test status
Simulation time 841824278 ps
CPU time 5.55 seconds
Started Aug 09 05:22:18 PM PDT 24
Finished Aug 09 05:22:24 PM PDT 24
Peak memory 214184 kb
Host smart-2eacabed-7e06-47a4-a43d-8d71d046342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953620096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1953620096
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1324281841
Short name T648
Test name
Test status
Simulation time 117938458 ps
CPU time 4.08 seconds
Started Aug 09 05:22:17 PM PDT 24
Finished Aug 09 05:22:21 PM PDT 24
Peak memory 209228 kb
Host smart-049c517c-7026-425d-b275-66d9c4b6b17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324281841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1324281841
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2031781666
Short name T490
Test name
Test status
Simulation time 42737156 ps
CPU time 2.45 seconds
Started Aug 09 05:22:23 PM PDT 24
Finished Aug 09 05:22:26 PM PDT 24
Peak memory 207364 kb
Host smart-afcfdbc0-6183-4389-9ef4-c57600768f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031781666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2031781666
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3504970921
Short name T666
Test name
Test status
Simulation time 116090698 ps
CPU time 3.13 seconds
Started Aug 09 05:22:19 PM PDT 24
Finished Aug 09 05:22:23 PM PDT 24
Peak memory 206948 kb
Host smart-f1a45d05-ff07-421a-8e35-49bc78c4a2e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504970921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3504970921
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.858821789
Short name T688
Test name
Test status
Simulation time 78570645 ps
CPU time 2.99 seconds
Started Aug 09 05:22:24 PM PDT 24
Finished Aug 09 05:22:27 PM PDT 24
Peak memory 206876 kb
Host smart-f0366a00-76b7-4fe9-aee8-8ee4e8ef4b6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858821789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.858821789
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3350599475
Short name T580
Test name
Test status
Simulation time 66056109 ps
CPU time 2.47 seconds
Started Aug 09 05:22:18 PM PDT 24
Finished Aug 09 05:22:21 PM PDT 24
Peak memory 206968 kb
Host smart-45dfd451-db58-44e9-a083-efc6af59aa68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350599475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3350599475
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3336647887
Short name T559
Test name
Test status
Simulation time 381130124 ps
CPU time 3.39 seconds
Started Aug 09 05:22:24 PM PDT 24
Finished Aug 09 05:22:27 PM PDT 24
Peak memory 208192 kb
Host smart-a818bbf4-44fc-4ad1-8f2a-45e5543f617b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336647887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3336647887
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3037683325
Short name T777
Test name
Test status
Simulation time 2567845907 ps
CPU time 12.49 seconds
Started Aug 09 05:22:18 PM PDT 24
Finished Aug 09 05:22:31 PM PDT 24
Peak memory 208560 kb
Host smart-9a43a9e9-551a-485a-91ac-d7ba692b73cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037683325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3037683325
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3546438191
Short name T217
Test name
Test status
Simulation time 2502815330 ps
CPU time 44.21 seconds
Started Aug 09 05:22:25 PM PDT 24
Finished Aug 09 05:23:09 PM PDT 24
Peak memory 215180 kb
Host smart-0ec7e20d-2020-4b37-b079-7b32637a5515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546438191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3546438191
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3805951090
Short name T177
Test name
Test status
Simulation time 292273647 ps
CPU time 8.59 seconds
Started Aug 09 05:22:24 PM PDT 24
Finished Aug 09 05:22:33 PM PDT 24
Peak memory 222556 kb
Host smart-29e7979b-fd3c-4e4e-a862-f84792655363
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805951090 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3805951090
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2080091642
Short name T736
Test name
Test status
Simulation time 106519184 ps
CPU time 3.61 seconds
Started Aug 09 05:22:19 PM PDT 24
Finished Aug 09 05:22:23 PM PDT 24
Peak memory 207568 kb
Host smart-b6263ba2-138e-45d5-9412-6221dec98fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080091642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2080091642
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2064522880
Short name T751
Test name
Test status
Simulation time 1536155751 ps
CPU time 9.67 seconds
Started Aug 09 05:22:21 PM PDT 24
Finished Aug 09 05:22:31 PM PDT 24
Peak memory 210332 kb
Host smart-bbc40fb4-18f5-4207-989c-bd3ab651cfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064522880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2064522880
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3902846332
Short name T859
Test name
Test status
Simulation time 10274642 ps
CPU time 0.87 seconds
Started Aug 09 05:22:23 PM PDT 24
Finished Aug 09 05:22:24 PM PDT 24
Peak memory 205848 kb
Host smart-00416576-68f6-4cb9-b6b0-8bfc8f8ddc29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902846332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3902846332
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2528702661
Short name T106
Test name
Test status
Simulation time 48353848 ps
CPU time 3.61 seconds
Started Aug 09 05:22:22 PM PDT 24
Finished Aug 09 05:22:26 PM PDT 24
Peak memory 214924 kb
Host smart-64ad47af-94d2-4537-87ab-9c4fdbabca7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528702661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2528702661
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3060613953
Short name T818
Test name
Test status
Simulation time 340680659 ps
CPU time 2.72 seconds
Started Aug 09 05:22:25 PM PDT 24
Finished Aug 09 05:22:28 PM PDT 24
Peak memory 214492 kb
Host smart-e5860a7c-cd8f-452c-abde-2052f0d5dd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060613953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3060613953
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.4120698991
Short name T496
Test name
Test status
Simulation time 56093114 ps
CPU time 1.98 seconds
Started Aug 09 05:22:22 PM PDT 24
Finished Aug 09 05:22:24 PM PDT 24
Peak memory 207880 kb
Host smart-3fb6497a-fe66-4fd9-8a92-ef6ae679516f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120698991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.4120698991
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3788545572
Short name T829
Test name
Test status
Simulation time 179971219 ps
CPU time 4.64 seconds
Started Aug 09 05:22:25 PM PDT 24
Finished Aug 09 05:22:30 PM PDT 24
Peak memory 214416 kb
Host smart-7dfa4012-2acf-4dc1-b711-559f1421db15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788545572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3788545572
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.157146113
Short name T372
Test name
Test status
Simulation time 250208393 ps
CPU time 2.64 seconds
Started Aug 09 05:22:27 PM PDT 24
Finished Aug 09 05:22:30 PM PDT 24
Peak memory 219820 kb
Host smart-0b90cc18-ea61-422c-af92-be853dc53547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157146113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.157146113
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3314898597
Short name T753
Test name
Test status
Simulation time 134290751 ps
CPU time 2.49 seconds
Started Aug 09 05:22:27 PM PDT 24
Finished Aug 09 05:22:29 PM PDT 24
Peak memory 214216 kb
Host smart-5998c810-8237-4f92-b051-c62152624141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314898597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3314898597
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2954062183
Short name T268
Test name
Test status
Simulation time 130580132 ps
CPU time 5.25 seconds
Started Aug 09 05:22:22 PM PDT 24
Finished Aug 09 05:22:28 PM PDT 24
Peak memory 218428 kb
Host smart-5763ddda-0cce-4eea-af95-97b58f5f8973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954062183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2954062183
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1720769001
Short name T228
Test name
Test status
Simulation time 41560574 ps
CPU time 2.32 seconds
Started Aug 09 05:22:23 PM PDT 24
Finished Aug 09 05:22:25 PM PDT 24
Peak memory 206712 kb
Host smart-ebaedf97-990d-453b-9f44-fa77289459e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720769001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1720769001
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.754881996
Short name T627
Test name
Test status
Simulation time 186801958 ps
CPU time 3.65 seconds
Started Aug 09 05:22:22 PM PDT 24
Finished Aug 09 05:22:26 PM PDT 24
Peak memory 208640 kb
Host smart-0c303c84-4bcc-4e91-93f4-2db67e2c7a7d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754881996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.754881996
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3381434026
Short name T460
Test name
Test status
Simulation time 81769364 ps
CPU time 3.84 seconds
Started Aug 09 05:22:23 PM PDT 24
Finished Aug 09 05:22:27 PM PDT 24
Peak memory 208640 kb
Host smart-12fdf9a9-dd1c-4299-b2d4-326779ae95b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381434026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3381434026
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2616110321
Short name T924
Test name
Test status
Simulation time 6513715808 ps
CPU time 60.79 seconds
Started Aug 09 05:22:21 PM PDT 24
Finished Aug 09 05:23:22 PM PDT 24
Peak memory 209340 kb
Host smart-1d7ae149-9e22-4076-8b96-ab053a28dec8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616110321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2616110321
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3158286539
Short name T621
Test name
Test status
Simulation time 201668136 ps
CPU time 2.36 seconds
Started Aug 09 05:22:23 PM PDT 24
Finished Aug 09 05:22:26 PM PDT 24
Peak memory 209192 kb
Host smart-764e7472-9bb0-4ea0-a911-9f534bf21b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158286539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3158286539
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2060828176
Short name T919
Test name
Test status
Simulation time 119714522 ps
CPU time 3.14 seconds
Started Aug 09 05:22:27 PM PDT 24
Finished Aug 09 05:22:30 PM PDT 24
Peak memory 208208 kb
Host smart-0aaa1551-b069-46c4-bbcb-984311d736cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060828176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2060828176
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1727021226
Short name T176
Test name
Test status
Simulation time 5160232560 ps
CPU time 13.19 seconds
Started Aug 09 05:22:25 PM PDT 24
Finished Aug 09 05:22:38 PM PDT 24
Peak memory 222712 kb
Host smart-2484e373-3803-452b-bfdc-53a788a5614c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727021226 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1727021226
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1557152245
Short name T715
Test name
Test status
Simulation time 108770425 ps
CPU time 5.08 seconds
Started Aug 09 05:22:21 PM PDT 24
Finished Aug 09 05:22:27 PM PDT 24
Peak memory 218456 kb
Host smart-7447eaec-2b8f-45af-b20f-ddff3cf2adfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557152245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1557152245
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3327172486
Short name T470
Test name
Test status
Simulation time 327701275 ps
CPU time 2.33 seconds
Started Aug 09 05:22:23 PM PDT 24
Finished Aug 09 05:22:25 PM PDT 24
Peak memory 209792 kb
Host smart-8a79d1b5-0e84-4fd4-9b82-ed18b66a563c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327172486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3327172486
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3568616429
Short name T427
Test name
Test status
Simulation time 47894506 ps
CPU time 0.78 seconds
Started Aug 09 05:22:30 PM PDT 24
Finished Aug 09 05:22:31 PM PDT 24
Peak memory 205852 kb
Host smart-ae73e23f-99fa-4f47-94f9-6108210f6ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568616429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3568616429
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1267496984
Short name T418
Test name
Test status
Simulation time 165416264 ps
CPU time 3.32 seconds
Started Aug 09 05:22:23 PM PDT 24
Finished Aug 09 05:22:27 PM PDT 24
Peak memory 214324 kb
Host smart-51d1cb43-7002-4cdb-b569-304c3c6f4fe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267496984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1267496984
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1835663855
Short name T483
Test name
Test status
Simulation time 124905292 ps
CPU time 1.84 seconds
Started Aug 09 05:22:25 PM PDT 24
Finished Aug 09 05:22:27 PM PDT 24
Peak memory 208096 kb
Host smart-31c104cd-7327-4ffe-bf70-9dff9a78a245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835663855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1835663855
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3766052699
Short name T37
Test name
Test status
Simulation time 89319965 ps
CPU time 4.32 seconds
Started Aug 09 05:22:27 PM PDT 24
Finished Aug 09 05:22:31 PM PDT 24
Peak memory 214400 kb
Host smart-6513913f-7356-45ca-8c43-cddd07e48d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766052699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3766052699
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3626706676
Short name T377
Test name
Test status
Simulation time 135212446 ps
CPU time 3.05 seconds
Started Aug 09 05:22:25 PM PDT 24
Finished Aug 09 05:22:28 PM PDT 24
Peak memory 222440 kb
Host smart-f373294c-ca72-4fdf-882c-65edbd7da950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626706676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3626706676
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3245015229
Short name T870
Test name
Test status
Simulation time 103750440 ps
CPU time 3.1 seconds
Started Aug 09 05:22:23 PM PDT 24
Finished Aug 09 05:22:26 PM PDT 24
Peak memory 209060 kb
Host smart-f4bedd8d-ba1c-4e4e-8405-9411ced617a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245015229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3245015229
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3338796359
Short name T126
Test name
Test status
Simulation time 781920891 ps
CPU time 8.2 seconds
Started Aug 09 05:22:23 PM PDT 24
Finished Aug 09 05:22:32 PM PDT 24
Peak memory 218156 kb
Host smart-0fa47b3e-8ede-4526-bba2-053becf41975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338796359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3338796359
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.4090979084
Short name T524
Test name
Test status
Simulation time 202598140 ps
CPU time 2.89 seconds
Started Aug 09 05:22:25 PM PDT 24
Finished Aug 09 05:22:28 PM PDT 24
Peak memory 206104 kb
Host smart-fb0be8aa-3dab-4a19-b79d-a67414c92303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090979084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4090979084
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1134913977
Short name T902
Test name
Test status
Simulation time 1429068853 ps
CPU time 33.01 seconds
Started Aug 09 05:22:26 PM PDT 24
Finished Aug 09 05:22:59 PM PDT 24
Peak memory 207780 kb
Host smart-1e352e9b-11d4-4e1b-a976-106ccba581fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134913977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1134913977
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1892915246
Short name T615
Test name
Test status
Simulation time 59552964 ps
CPU time 2.78 seconds
Started Aug 09 05:22:26 PM PDT 24
Finished Aug 09 05:22:29 PM PDT 24
Peak memory 208552 kb
Host smart-12ce0862-8820-40bf-9819-a28ea63b5886
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892915246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1892915246
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2773125761
Short name T816
Test name
Test status
Simulation time 237361448 ps
CPU time 6.71 seconds
Started Aug 09 05:22:24 PM PDT 24
Finished Aug 09 05:22:31 PM PDT 24
Peak memory 208348 kb
Host smart-e15f3e76-3cb6-4ba1-a20a-ae1b418c2708
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773125761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2773125761
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3387154829
Short name T288
Test name
Test status
Simulation time 109565397 ps
CPU time 1.8 seconds
Started Aug 09 05:22:29 PM PDT 24
Finished Aug 09 05:22:30 PM PDT 24
Peak memory 209664 kb
Host smart-dd62e9ba-fb11-495b-9c18-40a8acf9b9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387154829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3387154829
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.231560464
Short name T723
Test name
Test status
Simulation time 281883985 ps
CPU time 2.21 seconds
Started Aug 09 05:22:24 PM PDT 24
Finished Aug 09 05:22:26 PM PDT 24
Peak memory 206800 kb
Host smart-8e8c799b-b2cf-495f-bd92-04ae455271ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231560464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.231560464
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3399238058
Short name T65
Test name
Test status
Simulation time 1158854441 ps
CPU time 41.59 seconds
Started Aug 09 05:22:29 PM PDT 24
Finished Aug 09 05:23:11 PM PDT 24
Peak memory 216280 kb
Host smart-637a33b8-0086-46e8-817e-1f7135288527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399238058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3399238058
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.4099726654
Short name T743
Test name
Test status
Simulation time 132686772 ps
CPU time 3.86 seconds
Started Aug 09 05:22:24 PM PDT 24
Finished Aug 09 05:22:28 PM PDT 24
Peak memory 209036 kb
Host smart-41af0de2-a630-48b7-9b73-6295650a496d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099726654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.4099726654
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.494711061
Short name T599
Test name
Test status
Simulation time 76284762 ps
CPU time 2.33 seconds
Started Aug 09 05:22:28 PM PDT 24
Finished Aug 09 05:22:31 PM PDT 24
Peak memory 210056 kb
Host smart-bb235064-1ef9-4642-896c-8645d7638e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494711061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.494711061
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1555448713
Short name T426
Test name
Test status
Simulation time 8462382 ps
CPU time 0.72 seconds
Started Aug 09 05:22:34 PM PDT 24
Finished Aug 09 05:22:35 PM PDT 24
Peak memory 205928 kb
Host smart-03dbe7b0-99e8-4298-9bed-ae8e5294f247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555448713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1555448713
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3710479642
Short name T403
Test name
Test status
Simulation time 6329646316 ps
CPU time 88.31 seconds
Started Aug 09 05:22:30 PM PDT 24
Finished Aug 09 05:23:58 PM PDT 24
Peak memory 214400 kb
Host smart-b01f99d4-e728-49ba-b3c6-4992cf862bfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710479642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3710479642
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2210652044
Short name T728
Test name
Test status
Simulation time 366567218 ps
CPU time 10.57 seconds
Started Aug 09 05:22:26 PM PDT 24
Finished Aug 09 05:22:37 PM PDT 24
Peak memory 221196 kb
Host smart-b8d3b58e-01a9-4c05-af3a-72d712b58e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210652044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2210652044
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2130000054
Short name T276
Test name
Test status
Simulation time 18874950 ps
CPU time 1.49 seconds
Started Aug 09 05:22:28 PM PDT 24
Finished Aug 09 05:22:30 PM PDT 24
Peak memory 208464 kb
Host smart-79503bfc-67bc-483d-8afd-2b3489704cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130000054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2130000054
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1541808908
Short name T806
Test name
Test status
Simulation time 203965349 ps
CPU time 6.1 seconds
Started Aug 09 05:22:30 PM PDT 24
Finished Aug 09 05:22:36 PM PDT 24
Peak memory 209676 kb
Host smart-cf7364a5-0e4e-4aac-b5e9-0836d7242bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541808908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1541808908
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2961176021
Short name T258
Test name
Test status
Simulation time 442703764 ps
CPU time 5.73 seconds
Started Aug 09 05:22:29 PM PDT 24
Finished Aug 09 05:22:35 PM PDT 24
Peak memory 222112 kb
Host smart-d846785d-bb7b-474f-a58b-067c93936400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961176021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2961176021
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1604732084
Short name T127
Test name
Test status
Simulation time 81741904 ps
CPU time 2.55 seconds
Started Aug 09 05:22:31 PM PDT 24
Finished Aug 09 05:22:34 PM PDT 24
Peak memory 219464 kb
Host smart-d6506eed-f2cf-4ff3-a8e3-d2b8112d61cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604732084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1604732084
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1210763837
Short name T675
Test name
Test status
Simulation time 689837602 ps
CPU time 5.79 seconds
Started Aug 09 05:22:29 PM PDT 24
Finished Aug 09 05:22:35 PM PDT 24
Peak memory 207464 kb
Host smart-41bda239-684b-48fb-b7a9-d2c02ed5d5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210763837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1210763837
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3173405957
Short name T745
Test name
Test status
Simulation time 207149685 ps
CPU time 2.83 seconds
Started Aug 09 05:22:29 PM PDT 24
Finished Aug 09 05:22:32 PM PDT 24
Peak memory 208584 kb
Host smart-4da3b1d3-ff55-4d4b-9839-d033c607d964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173405957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3173405957
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2378776166
Short name T486
Test name
Test status
Simulation time 810198855 ps
CPU time 6.49 seconds
Started Aug 09 05:22:30 PM PDT 24
Finished Aug 09 05:22:37 PM PDT 24
Peak memory 208056 kb
Host smart-7248ef94-a3b4-4fdd-822b-7640ac5eb4d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378776166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2378776166
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2853115585
Short name T567
Test name
Test status
Simulation time 695096185 ps
CPU time 8.92 seconds
Started Aug 09 05:22:29 PM PDT 24
Finished Aug 09 05:22:38 PM PDT 24
Peak memory 208576 kb
Host smart-0ab80ef9-c03f-44a6-b8c0-76d8186cfbeb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853115585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2853115585
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2560631917
Short name T758
Test name
Test status
Simulation time 6059159451 ps
CPU time 66.28 seconds
Started Aug 09 05:22:33 PM PDT 24
Finished Aug 09 05:23:39 PM PDT 24
Peak memory 209236 kb
Host smart-41db4266-3394-497b-a6fe-78ff6e3bb3bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560631917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2560631917
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1200023662
Short name T290
Test name
Test status
Simulation time 213090967 ps
CPU time 2.97 seconds
Started Aug 09 05:22:34 PM PDT 24
Finished Aug 09 05:22:37 PM PDT 24
Peak memory 214280 kb
Host smart-41bc8b9b-26f1-4c0f-ae11-e66a3dc11d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200023662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1200023662
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1255433661
Short name T651
Test name
Test status
Simulation time 143130622 ps
CPU time 2.62 seconds
Started Aug 09 05:22:30 PM PDT 24
Finished Aug 09 05:22:32 PM PDT 24
Peak memory 208692 kb
Host smart-c98e34bc-09b0-476f-ad7a-f210f838837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255433661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1255433661
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2657008069
Short name T825
Test name
Test status
Simulation time 222600347 ps
CPU time 6.3 seconds
Started Aug 09 05:22:28 PM PDT 24
Finished Aug 09 05:22:35 PM PDT 24
Peak memory 209184 kb
Host smart-3e844742-82ca-4cec-b43f-c2ed8b978b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657008069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2657008069
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1118615609
Short name T191
Test name
Test status
Simulation time 185614001 ps
CPU time 1.37 seconds
Started Aug 09 05:22:31 PM PDT 24
Finished Aug 09 05:22:33 PM PDT 24
Peak memory 208544 kb
Host smart-84c10056-a506-48bc-8f0c-37a4d03398e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118615609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1118615609
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.273398950
Short name T182
Test name
Test status
Simulation time 13062649 ps
CPU time 0.73 seconds
Started Aug 09 05:22:36 PM PDT 24
Finished Aug 09 05:22:37 PM PDT 24
Peak memory 205848 kb
Host smart-cd8ba189-877a-40ad-b8d1-4a4d8acf20fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273398950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.273398950
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.4102124306
Short name T388
Test name
Test status
Simulation time 245540539 ps
CPU time 13.06 seconds
Started Aug 09 05:22:34 PM PDT 24
Finished Aug 09 05:22:47 PM PDT 24
Peak memory 214868 kb
Host smart-74acf761-54c7-4428-81c9-8c6d8d3be069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102124306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4102124306
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1681163856
Short name T652
Test name
Test status
Simulation time 2274402502 ps
CPU time 9.5 seconds
Started Aug 09 05:22:34 PM PDT 24
Finished Aug 09 05:22:44 PM PDT 24
Peak memory 214644 kb
Host smart-1bf51160-bd6f-4d4d-8295-70dea1c2e537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681163856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1681163856
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2485422115
Short name T343
Test name
Test status
Simulation time 113605838 ps
CPU time 3.89 seconds
Started Aug 09 05:22:36 PM PDT 24
Finished Aug 09 05:22:40 PM PDT 24
Peak memory 222388 kb
Host smart-575e07f9-e0e7-4e01-a01b-7c9e4ba58f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485422115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2485422115
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3152755306
Short name T24
Test name
Test status
Simulation time 258443526 ps
CPU time 8.76 seconds
Started Aug 09 05:22:34 PM PDT 24
Finished Aug 09 05:22:43 PM PDT 24
Peak memory 214324 kb
Host smart-fc7b5eb6-94d8-4286-af07-4ed329870e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152755306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3152755306
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3294536083
Short name T885
Test name
Test status
Simulation time 77822175 ps
CPU time 1.61 seconds
Started Aug 09 05:22:35 PM PDT 24
Finished Aug 09 05:22:36 PM PDT 24
Peak memory 214236 kb
Host smart-65f7dc43-5767-4f6a-b9bf-254c668d0203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294536083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3294536083
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_random.2009838956
Short name T783
Test name
Test status
Simulation time 4333460370 ps
CPU time 37.26 seconds
Started Aug 09 05:22:37 PM PDT 24
Finished Aug 09 05:23:15 PM PDT 24
Peak memory 209156 kb
Host smart-e345e99d-0b04-4b2d-9cda-4d1e5072b5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009838956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2009838956
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4270965166
Short name T294
Test name
Test status
Simulation time 37984442 ps
CPU time 2.53 seconds
Started Aug 09 05:22:37 PM PDT 24
Finished Aug 09 05:22:40 PM PDT 24
Peak memory 208572 kb
Host smart-5ff6012c-a7c3-4548-a730-4848838287df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270965166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4270965166
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1331509662
Short name T664
Test name
Test status
Simulation time 923394461 ps
CPU time 22.74 seconds
Started Aug 09 05:22:35 PM PDT 24
Finished Aug 09 05:22:58 PM PDT 24
Peak memory 208100 kb
Host smart-9caa75c1-854a-4a0a-8201-f88005a163b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331509662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1331509662
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2626687197
Short name T569
Test name
Test status
Simulation time 91759608 ps
CPU time 2.67 seconds
Started Aug 09 05:22:36 PM PDT 24
Finished Aug 09 05:22:39 PM PDT 24
Peak memory 206712 kb
Host smart-efd26ead-7d58-4299-9b14-cef2d13b0590
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626687197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2626687197
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3927702930
Short name T583
Test name
Test status
Simulation time 308793739 ps
CPU time 4.98 seconds
Started Aug 09 05:22:35 PM PDT 24
Finished Aug 09 05:22:40 PM PDT 24
Peak memory 208856 kb
Host smart-c32c3ef9-635b-4975-9702-1dd021ecffdb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927702930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3927702930
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2677475169
Short name T643
Test name
Test status
Simulation time 146129762 ps
CPU time 4.4 seconds
Started Aug 09 05:22:35 PM PDT 24
Finished Aug 09 05:22:40 PM PDT 24
Peak memory 214320 kb
Host smart-2834bb70-8fc3-4ce4-8fe8-7282436894bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677475169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2677475169
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3373219800
Short name T442
Test name
Test status
Simulation time 67726766 ps
CPU time 2.98 seconds
Started Aug 09 05:22:39 PM PDT 24
Finished Aug 09 05:22:42 PM PDT 24
Peak memory 208660 kb
Host smart-fb6bbf18-9884-4114-8fcc-a9cdbd027cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373219800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3373219800
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2984187705
Short name T366
Test name
Test status
Simulation time 640487758 ps
CPU time 26.99 seconds
Started Aug 09 05:22:39 PM PDT 24
Finished Aug 09 05:23:06 PM PDT 24
Peak memory 216720 kb
Host smart-e77d71d3-367c-44e9-a5c8-a73de2f6d081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984187705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2984187705
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3651146421
Short name T74
Test name
Test status
Simulation time 867151600 ps
CPU time 14.35 seconds
Started Aug 09 05:22:36 PM PDT 24
Finished Aug 09 05:22:50 PM PDT 24
Peak memory 222420 kb
Host smart-9173def6-5caf-46b1-8bc0-e34c15dcf2ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651146421 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3651146421
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1421072792
Short name T230
Test name
Test status
Simulation time 402953342 ps
CPU time 5.01 seconds
Started Aug 09 05:22:36 PM PDT 24
Finished Aug 09 05:22:41 PM PDT 24
Peak memory 209852 kb
Host smart-332ad692-2c43-46c2-bf58-516c2daa2655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421072792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1421072792
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2510319664
Short name T605
Test name
Test status
Simulation time 327591888 ps
CPU time 2.74 seconds
Started Aug 09 05:22:37 PM PDT 24
Finished Aug 09 05:22:40 PM PDT 24
Peak memory 209728 kb
Host smart-5f51b6fd-149c-40e0-8c67-b73c000db531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510319664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2510319664
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.874634183
Short name T908
Test name
Test status
Simulation time 15994473 ps
CPU time 1.07 seconds
Started Aug 09 05:22:44 PM PDT 24
Finished Aug 09 05:22:45 PM PDT 24
Peak memory 206124 kb
Host smart-ccb5693f-1556-4db1-8335-8d489dbf2e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874634183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.874634183
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3058187075
Short name T773
Test name
Test status
Simulation time 1680183097 ps
CPU time 19.11 seconds
Started Aug 09 05:22:36 PM PDT 24
Finished Aug 09 05:22:56 PM PDT 24
Peak memory 222680 kb
Host smart-421c9f4e-acbf-4147-b7dc-2456bc00935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058187075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3058187075
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.377038318
Short name T601
Test name
Test status
Simulation time 82592820 ps
CPU time 2.44 seconds
Started Aug 09 05:22:34 PM PDT 24
Finished Aug 09 05:22:37 PM PDT 24
Peak memory 209680 kb
Host smart-a807df11-2f14-4dc1-ac3c-bbbdec2f398c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377038318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.377038318
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.708015203
Short name T320
Test name
Test status
Simulation time 62039871 ps
CPU time 2.67 seconds
Started Aug 09 05:22:39 PM PDT 24
Finished Aug 09 05:22:41 PM PDT 24
Peak memory 214360 kb
Host smart-1c622d45-8c85-465c-a3b6-29189d8b06a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708015203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.708015203
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1382909159
Short name T692
Test name
Test status
Simulation time 59343826 ps
CPU time 2.57 seconds
Started Aug 09 05:22:39 PM PDT 24
Finished Aug 09 05:22:41 PM PDT 24
Peak memory 214332 kb
Host smart-a42e2b30-fead-4f6b-a4d6-93c4104162e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382909159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1382909159
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3718002083
Short name T353
Test name
Test status
Simulation time 86486672 ps
CPU time 4.46 seconds
Started Aug 09 05:22:37 PM PDT 24
Finished Aug 09 05:22:42 PM PDT 24
Peak memory 218136 kb
Host smart-fcbf7551-6d2a-447a-98e8-6c0757d51ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718002083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3718002083
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1360842956
Short name T653
Test name
Test status
Simulation time 125697916 ps
CPU time 3.3 seconds
Started Aug 09 05:22:36 PM PDT 24
Finished Aug 09 05:22:39 PM PDT 24
Peak memory 208620 kb
Host smart-b67ee94b-f7c9-49d5-b0cd-1c99f096057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360842956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1360842956
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1082699951
Short name T647
Test name
Test status
Simulation time 213965947 ps
CPU time 4.93 seconds
Started Aug 09 05:22:35 PM PDT 24
Finished Aug 09 05:22:40 PM PDT 24
Peak memory 206852 kb
Host smart-3fdbb5ac-ba43-45ce-a13d-47040bcfe7f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082699951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1082699951
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1942643774
Short name T714
Test name
Test status
Simulation time 41372912 ps
CPU time 1.74 seconds
Started Aug 09 05:22:35 PM PDT 24
Finished Aug 09 05:22:36 PM PDT 24
Peak memory 206948 kb
Host smart-603d9016-4ecf-40cb-934e-08dbfad13266
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942643774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1942643774
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3497243935
Short name T686
Test name
Test status
Simulation time 38403663 ps
CPU time 1.74 seconds
Started Aug 09 05:22:36 PM PDT 24
Finished Aug 09 05:22:38 PM PDT 24
Peak memory 207424 kb
Host smart-70b71912-7735-4897-b0c0-dc7ea4829d54
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497243935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3497243935
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1828928923
Short name T183
Test name
Test status
Simulation time 115520866 ps
CPU time 4.32 seconds
Started Aug 09 05:22:44 PM PDT 24
Finished Aug 09 05:22:48 PM PDT 24
Peak memory 208764 kb
Host smart-c0addad6-554b-447d-826c-cd0ac94f5a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828928923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1828928923
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3552888378
Short name T641
Test name
Test status
Simulation time 163946393 ps
CPU time 4.28 seconds
Started Aug 09 05:22:37 PM PDT 24
Finished Aug 09 05:22:41 PM PDT 24
Peak memory 207752 kb
Host smart-ee83b3d6-4a25-4d6d-8a24-23984ef376dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552888378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3552888378
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1673630987
Short name T76
Test name
Test status
Simulation time 23415549267 ps
CPU time 146.64 seconds
Started Aug 09 05:22:42 PM PDT 24
Finished Aug 09 05:25:09 PM PDT 24
Peak memory 222420 kb
Host smart-91b504e7-48a9-4775-93f6-2d0fba4ad625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673630987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1673630987
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1560498069
Short name T175
Test name
Test status
Simulation time 445640045 ps
CPU time 17.1 seconds
Started Aug 09 05:22:43 PM PDT 24
Finished Aug 09 05:23:01 PM PDT 24
Peak memory 222548 kb
Host smart-3417a283-3545-4efc-a3e1-3801d9032f60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560498069 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1560498069
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2752657043
Short name T735
Test name
Test status
Simulation time 7394844054 ps
CPU time 61.95 seconds
Started Aug 09 05:22:38 PM PDT 24
Finished Aug 09 05:23:40 PM PDT 24
Peak memory 209532 kb
Host smart-b187d41f-74bd-4f97-bb47-10830e724117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752657043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2752657043
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3089749960
Short name T672
Test name
Test status
Simulation time 81228138 ps
CPU time 1.72 seconds
Started Aug 09 05:22:43 PM PDT 24
Finished Aug 09 05:22:44 PM PDT 24
Peak memory 209908 kb
Host smart-55dbd6bf-8d82-4ff9-b733-035cdc22c183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089749960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3089749960
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1703743953
Short name T452
Test name
Test status
Simulation time 78855759 ps
CPU time 0.76 seconds
Started Aug 09 05:22:42 PM PDT 24
Finished Aug 09 05:22:43 PM PDT 24
Peak memory 205960 kb
Host smart-441d3fad-6c5a-434e-be9a-205cc8066b7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703743953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1703743953
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.814595131
Short name T384
Test name
Test status
Simulation time 146875807 ps
CPU time 2.99 seconds
Started Aug 09 05:22:45 PM PDT 24
Finished Aug 09 05:22:48 PM PDT 24
Peak memory 222564 kb
Host smart-17c5eab6-ec9d-43be-a00b-2741d90b41d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814595131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.814595131
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.763228188
Short name T792
Test name
Test status
Simulation time 64211095 ps
CPU time 2.83 seconds
Started Aug 09 05:22:45 PM PDT 24
Finished Aug 09 05:22:48 PM PDT 24
Peak memory 220992 kb
Host smart-3106bb14-4600-4b9b-9b21-5eaf422c821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763228188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.763228188
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1173620550
Short name T573
Test name
Test status
Simulation time 319574132 ps
CPU time 3.38 seconds
Started Aug 09 05:22:46 PM PDT 24
Finished Aug 09 05:22:50 PM PDT 24
Peak memory 207808 kb
Host smart-8d9bb74a-be56-4c1d-9005-88d34a08d7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173620550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1173620550
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2735302062
Short name T23
Test name
Test status
Simulation time 129801982 ps
CPU time 4.13 seconds
Started Aug 09 05:22:42 PM PDT 24
Finished Aug 09 05:22:46 PM PDT 24
Peak memory 209288 kb
Host smart-15830ac4-7931-4827-a1df-7ccfd84f836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735302062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2735302062
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.255349159
Short name T254
Test name
Test status
Simulation time 34609207 ps
CPU time 2.41 seconds
Started Aug 09 05:22:44 PM PDT 24
Finished Aug 09 05:22:47 PM PDT 24
Peak memory 214216 kb
Host smart-6b82213c-d1ac-4a0c-9274-891969b63e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255349159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.255349159
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2439566248
Short name T622
Test name
Test status
Simulation time 72047696 ps
CPU time 3.13 seconds
Started Aug 09 05:22:44 PM PDT 24
Finished Aug 09 05:22:47 PM PDT 24
Peak memory 209520 kb
Host smart-7f7b3531-e81b-48ed-8d2b-893ff542233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439566248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2439566248
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4075887574
Short name T584
Test name
Test status
Simulation time 393461304 ps
CPU time 4.42 seconds
Started Aug 09 05:22:42 PM PDT 24
Finished Aug 09 05:22:47 PM PDT 24
Peak memory 207592 kb
Host smart-aeb9d4fc-a970-447b-8de6-541528c6cc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075887574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4075887574
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.4061374454
Short name T775
Test name
Test status
Simulation time 60996843 ps
CPU time 2.98 seconds
Started Aug 09 05:22:41 PM PDT 24
Finished Aug 09 05:22:44 PM PDT 24
Peak memory 206936 kb
Host smart-f44db16a-f98e-43b1-b12b-4318fe48bf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061374454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.4061374454
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3181243205
Short name T600
Test name
Test status
Simulation time 483928947 ps
CPU time 3.72 seconds
Started Aug 09 05:22:42 PM PDT 24
Finished Aug 09 05:22:46 PM PDT 24
Peak memory 208500 kb
Host smart-5a071dfe-deb2-480b-8a6f-902d8ac3131b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181243205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3181243205
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1158809712
Short name T693
Test name
Test status
Simulation time 238474155 ps
CPU time 3.32 seconds
Started Aug 09 05:22:43 PM PDT 24
Finished Aug 09 05:22:47 PM PDT 24
Peak memory 206760 kb
Host smart-d16ccaf3-5429-41ef-a71b-0913b4b86bfa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158809712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1158809712
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3768063546
Short name T901
Test name
Test status
Simulation time 2406378314 ps
CPU time 15.32 seconds
Started Aug 09 05:22:43 PM PDT 24
Finished Aug 09 05:22:58 PM PDT 24
Peak memory 208496 kb
Host smart-9c00f30f-a203-4f6e-83cb-1c623666f3e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768063546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3768063546
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.149138118
Short name T185
Test name
Test status
Simulation time 112483522 ps
CPU time 4.4 seconds
Started Aug 09 05:22:43 PM PDT 24
Finished Aug 09 05:22:48 PM PDT 24
Peak memory 214224 kb
Host smart-4f719ad8-8ab7-404b-a108-774dded36066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149138118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.149138118
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3694705875
Short name T900
Test name
Test status
Simulation time 81323635 ps
CPU time 1.66 seconds
Started Aug 09 05:22:43 PM PDT 24
Finished Aug 09 05:22:45 PM PDT 24
Peak memory 207252 kb
Host smart-1a0209da-4db8-4808-9db9-6edd4a8c3818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694705875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3694705875
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1624614197
Short name T215
Test name
Test status
Simulation time 747869510 ps
CPU time 10.37 seconds
Started Aug 09 05:22:45 PM PDT 24
Finished Aug 09 05:22:56 PM PDT 24
Peak memory 222436 kb
Host smart-b00e229b-0282-42e6-b5bd-b8542bd0bcd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624614197 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1624614197
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2907739685
Short name T400
Test name
Test status
Simulation time 1532064731 ps
CPU time 29.77 seconds
Started Aug 09 05:22:46 PM PDT 24
Finished Aug 09 05:23:16 PM PDT 24
Peak memory 214356 kb
Host smart-c5ea13ff-28b9-4013-ad5e-e2afb289b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907739685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2907739685
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2030870485
Short name T781
Test name
Test status
Simulation time 3355349979 ps
CPU time 18.56 seconds
Started Aug 09 05:22:46 PM PDT 24
Finished Aug 09 05:23:05 PM PDT 24
Peak memory 210920 kb
Host smart-c97ca317-0115-42a3-a8ed-baa53214ec5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030870485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2030870485
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3518838212
Short name T821
Test name
Test status
Simulation time 50248056 ps
CPU time 0.85 seconds
Started Aug 09 05:21:10 PM PDT 24
Finished Aug 09 05:21:10 PM PDT 24
Peak memory 205976 kb
Host smart-7851a144-9eeb-486f-ba14-8bee4fd1fce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518838212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3518838212
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2378518699
Short name T263
Test name
Test status
Simulation time 250674313 ps
CPU time 4.67 seconds
Started Aug 09 05:21:05 PM PDT 24
Finished Aug 09 05:21:10 PM PDT 24
Peak memory 215744 kb
Host smart-7aaeb544-fd9d-4701-a99b-a50886a6f736
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2378518699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2378518699
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2215043502
Short name T70
Test name
Test status
Simulation time 256335383 ps
CPU time 2.17 seconds
Started Aug 09 05:21:09 PM PDT 24
Finished Aug 09 05:21:11 PM PDT 24
Peak memory 207224 kb
Host smart-025f6ed7-a32f-4349-ae7f-899f3c28c1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215043502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2215043502
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3769234463
Short name T843
Test name
Test status
Simulation time 86783601 ps
CPU time 2.74 seconds
Started Aug 09 05:21:07 PM PDT 24
Finished Aug 09 05:21:10 PM PDT 24
Peak memory 220672 kb
Host smart-17bf11ca-1bda-48d2-91e7-83a36c0797c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769234463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3769234463
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.937190509
Short name T516
Test name
Test status
Simulation time 376043512 ps
CPU time 5.15 seconds
Started Aug 09 05:21:05 PM PDT 24
Finished Aug 09 05:21:10 PM PDT 24
Peak memory 209824 kb
Host smart-4977451c-e7e9-4d60-a5da-14735b06c6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937190509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.937190509
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3944870071
Short name T3
Test name
Test status
Simulation time 26494010 ps
CPU time 2.05 seconds
Started Aug 09 05:21:06 PM PDT 24
Finished Aug 09 05:21:08 PM PDT 24
Peak memory 214312 kb
Host smart-1c6afcf1-91bd-4645-b970-9033fcbb7e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944870071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3944870071
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3776717861
Short name T32
Test name
Test status
Simulation time 555991904 ps
CPU time 13.55 seconds
Started Aug 09 05:21:04 PM PDT 24
Finished Aug 09 05:21:18 PM PDT 24
Peak memory 231664 kb
Host smart-59a52511-9ef7-42b2-87f8-62621d127c0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776717861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3776717861
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3029613618
Short name T880
Test name
Test status
Simulation time 117233818 ps
CPU time 3.27 seconds
Started Aug 09 05:21:06 PM PDT 24
Finished Aug 09 05:21:09 PM PDT 24
Peak memory 208516 kb
Host smart-3752c218-5093-4ff6-b2cd-d1eb88ecf402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029613618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3029613618
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2882482259
Short name T536
Test name
Test status
Simulation time 1242167841 ps
CPU time 14.13 seconds
Started Aug 09 05:21:04 PM PDT 24
Finished Aug 09 05:21:19 PM PDT 24
Peak memory 208192 kb
Host smart-a05d7064-7d7a-4371-916a-4fc4158b3d66
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882482259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2882482259
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1460557661
Short name T507
Test name
Test status
Simulation time 48393045 ps
CPU time 2.67 seconds
Started Aug 09 05:21:06 PM PDT 24
Finished Aug 09 05:21:08 PM PDT 24
Peak memory 206928 kb
Host smart-a0859c54-3958-42cc-9e52-d47e3d2b68d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460557661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1460557661
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.181393684
Short name T617
Test name
Test status
Simulation time 134971239 ps
CPU time 2.63 seconds
Started Aug 09 05:21:05 PM PDT 24
Finished Aug 09 05:21:08 PM PDT 24
Peak memory 208380 kb
Host smart-0f3326fa-fa4d-45a6-afb1-6613d084b3fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181393684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.181393684
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2697637859
Short name T739
Test name
Test status
Simulation time 240325524 ps
CPU time 3.09 seconds
Started Aug 09 05:21:08 PM PDT 24
Finished Aug 09 05:21:11 PM PDT 24
Peak memory 208624 kb
Host smart-62d2be92-365f-4477-a725-2adc45875696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697637859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2697637859
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1534123829
Short name T500
Test name
Test status
Simulation time 34789983 ps
CPU time 2.01 seconds
Started Aug 09 05:21:04 PM PDT 24
Finished Aug 09 05:21:06 PM PDT 24
Peak memory 206744 kb
Host smart-fd36bc87-c2fb-4808-b923-3097f92ef341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534123829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1534123829
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1798241011
Short name T668
Test name
Test status
Simulation time 12132553812 ps
CPU time 274.41 seconds
Started Aug 09 05:21:10 PM PDT 24
Finished Aug 09 05:25:44 PM PDT 24
Peak memory 214408 kb
Host smart-16d41e00-3c9b-4b7d-a620-1a24794fe95a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798241011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1798241011
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3240799370
Short name T52
Test name
Test status
Simulation time 517927797 ps
CPU time 10.94 seconds
Started Aug 09 05:21:06 PM PDT 24
Finished Aug 09 05:21:17 PM PDT 24
Peak memory 220488 kb
Host smart-ba02ceee-d766-44d2-8604-dc059a7466f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240799370 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3240799370
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1590471717
Short name T547
Test name
Test status
Simulation time 388282621 ps
CPU time 6.6 seconds
Started Aug 09 05:21:09 PM PDT 24
Finished Aug 09 05:21:16 PM PDT 24
Peak memory 209160 kb
Host smart-21625ef2-783f-41dd-aca5-94b6718aa1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590471717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1590471717
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1194904569
Short name T381
Test name
Test status
Simulation time 86378176 ps
CPU time 1.36 seconds
Started Aug 09 05:21:06 PM PDT 24
Finished Aug 09 05:21:07 PM PDT 24
Peak memory 208656 kb
Host smart-d866953d-6b61-44d5-92b7-06a67bc7fef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194904569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1194904569
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2222203065
Short name T491
Test name
Test status
Simulation time 27181500 ps
CPU time 0.96 seconds
Started Aug 09 05:22:48 PM PDT 24
Finished Aug 09 05:22:49 PM PDT 24
Peak memory 205992 kb
Host smart-6391b46e-1efe-4133-b732-b3b2e69fd8d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222203065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2222203065
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3105346945
Short name T324
Test name
Test status
Simulation time 141681530 ps
CPU time 3.05 seconds
Started Aug 09 05:22:45 PM PDT 24
Finished Aug 09 05:22:48 PM PDT 24
Peak memory 215152 kb
Host smart-35571abb-73df-4b32-a0b7-23785b8eeeba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105346945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3105346945
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1148758881
Short name T595
Test name
Test status
Simulation time 285166387 ps
CPU time 6.14 seconds
Started Aug 09 05:22:42 PM PDT 24
Finished Aug 09 05:22:48 PM PDT 24
Peak memory 208408 kb
Host smart-a522f578-a11c-48ec-a088-87c379d2ddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148758881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1148758881
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3029243303
Short name T326
Test name
Test status
Simulation time 227168408 ps
CPU time 6.95 seconds
Started Aug 09 05:22:42 PM PDT 24
Finished Aug 09 05:22:49 PM PDT 24
Peak memory 214328 kb
Host smart-15e2d777-4eb2-47f6-870a-983522974d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029243303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3029243303
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1159062902
Short name T373
Test name
Test status
Simulation time 201905350 ps
CPU time 2.51 seconds
Started Aug 09 05:22:43 PM PDT 24
Finished Aug 09 05:22:46 PM PDT 24
Peak memory 214260 kb
Host smart-76598ff1-736f-43ea-9285-74ccd1812408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159062902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1159062902
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2429265476
Short name T786
Test name
Test status
Simulation time 216981880 ps
CPU time 2.2 seconds
Started Aug 09 05:22:42 PM PDT 24
Finished Aug 09 05:22:44 PM PDT 24
Peak memory 208056 kb
Host smart-75ff4f2d-afa1-4809-935a-06928411a943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429265476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2429265476
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2457417028
Short name T645
Test name
Test status
Simulation time 120314825 ps
CPU time 4.66 seconds
Started Aug 09 05:22:43 PM PDT 24
Finished Aug 09 05:22:48 PM PDT 24
Peak memory 218328 kb
Host smart-972c3894-1ae7-4745-85b8-dcda93564c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457417028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2457417028
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3416627744
Short name T760
Test name
Test status
Simulation time 303700968 ps
CPU time 3.2 seconds
Started Aug 09 05:22:41 PM PDT 24
Finished Aug 09 05:22:44 PM PDT 24
Peak memory 208828 kb
Host smart-3530364e-135c-4830-94cd-db6ddd4cebb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416627744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3416627744
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.779535535
Short name T812
Test name
Test status
Simulation time 135231135 ps
CPU time 1.97 seconds
Started Aug 09 05:22:43 PM PDT 24
Finished Aug 09 05:22:45 PM PDT 24
Peak memory 208736 kb
Host smart-f4d6b4ad-e95c-4963-8dcb-db697de05fbd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779535535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.779535535
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2854583138
Short name T922
Test name
Test status
Simulation time 1562762590 ps
CPU time 41.37 seconds
Started Aug 09 05:22:43 PM PDT 24
Finished Aug 09 05:23:24 PM PDT 24
Peak memory 208344 kb
Host smart-1e461d07-0a51-4933-8734-b06ac6cf9349
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854583138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2854583138
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2569482618
Short name T678
Test name
Test status
Simulation time 348120489 ps
CPU time 2.63 seconds
Started Aug 09 05:22:44 PM PDT 24
Finished Aug 09 05:22:46 PM PDT 24
Peak memory 208604 kb
Host smart-1635b117-6264-4389-ae8b-e3623e84ab0c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569482618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2569482618
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.222001978
Short name T521
Test name
Test status
Simulation time 268439887 ps
CPU time 4.4 seconds
Started Aug 09 05:22:43 PM PDT 24
Finished Aug 09 05:22:48 PM PDT 24
Peak memory 209980 kb
Host smart-f53b97c5-206d-4adb-882e-f2e275fc8d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222001978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.222001978
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2784385528
Short name T462
Test name
Test status
Simulation time 184536764 ps
CPU time 5.27 seconds
Started Aug 09 05:22:41 PM PDT 24
Finished Aug 09 05:22:47 PM PDT 24
Peak memory 206928 kb
Host smart-3d2593d4-2696-4902-81e6-0d4a733a597f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784385528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2784385528
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1780522522
Short name T338
Test name
Test status
Simulation time 698871030 ps
CPU time 11.32 seconds
Started Aug 09 05:22:53 PM PDT 24
Finished Aug 09 05:23:05 PM PDT 24
Peak memory 215116 kb
Host smart-d40b5d12-6064-4084-a9dc-3ba065704ecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780522522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1780522522
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.551941783
Short name T13
Test name
Test status
Simulation time 224142902 ps
CPU time 13.56 seconds
Started Aug 09 05:22:51 PM PDT 24
Finished Aug 09 05:23:04 PM PDT 24
Peak memory 222560 kb
Host smart-a529943d-d6be-444e-a046-380ffe448317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551941783 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.551941783
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3021201285
Short name T644
Test name
Test status
Simulation time 456601204 ps
CPU time 7.09 seconds
Started Aug 09 05:22:49 PM PDT 24
Finished Aug 09 05:22:57 PM PDT 24
Peak memory 211128 kb
Host smart-40990612-2393-4cb8-a553-e7b700264f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021201285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3021201285
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1363317674
Short name T493
Test name
Test status
Simulation time 60094817 ps
CPU time 0.8 seconds
Started Aug 09 05:22:47 PM PDT 24
Finished Aug 09 05:22:48 PM PDT 24
Peak memory 205988 kb
Host smart-cbab36a7-c2b9-49b3-8d28-8c60dd48eb9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363317674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1363317674
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.173781553
Short name T9
Test name
Test status
Simulation time 166371074 ps
CPU time 3.5 seconds
Started Aug 09 05:22:50 PM PDT 24
Finished Aug 09 05:22:54 PM PDT 24
Peak memory 214432 kb
Host smart-79878b16-4ffa-4231-b712-902332036a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173781553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.173781553
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.772232679
Short name T577
Test name
Test status
Simulation time 559506406 ps
CPU time 2.77 seconds
Started Aug 09 05:22:50 PM PDT 24
Finished Aug 09 05:22:53 PM PDT 24
Peak memory 214320 kb
Host smart-6dcc7977-2420-4fce-9348-0cb09b27f30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772232679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.772232679
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.992491291
Short name T711
Test name
Test status
Simulation time 44865012 ps
CPU time 3.05 seconds
Started Aug 09 05:22:53 PM PDT 24
Finished Aug 09 05:22:56 PM PDT 24
Peak memory 214296 kb
Host smart-578e8ec5-e245-4baf-99a4-c420206bf434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992491291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.992491291
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.4192605970
Short name T220
Test name
Test status
Simulation time 412152559 ps
CPU time 6.76 seconds
Started Aug 09 05:22:50 PM PDT 24
Finished Aug 09 05:22:57 PM PDT 24
Peak memory 210012 kb
Host smart-3d4fa6ab-6bdf-41a6-a1ef-97ed0ce5eddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192605970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.4192605970
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2845614771
Short name T512
Test name
Test status
Simulation time 90746867 ps
CPU time 2.24 seconds
Started Aug 09 05:22:56 PM PDT 24
Finished Aug 09 05:22:59 PM PDT 24
Peak memory 208128 kb
Host smart-6ee1050a-8c2e-4a3f-81e7-e76fd6905221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845614771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2845614771
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3285935463
Short name T768
Test name
Test status
Simulation time 77994060 ps
CPU time 3.16 seconds
Started Aug 09 05:22:50 PM PDT 24
Finished Aug 09 05:22:54 PM PDT 24
Peak memory 206884 kb
Host smart-25d2b765-b626-44eb-a1b5-943cb6450da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285935463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3285935463
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3867135436
Short name T390
Test name
Test status
Simulation time 35035749 ps
CPU time 2.53 seconds
Started Aug 09 05:22:50 PM PDT 24
Finished Aug 09 05:22:53 PM PDT 24
Peak memory 208872 kb
Host smart-d18da914-37e4-425b-a812-25131a97f04f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867135436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3867135436
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.552538400
Short name T361
Test name
Test status
Simulation time 248784706 ps
CPU time 3.9 seconds
Started Aug 09 05:22:48 PM PDT 24
Finished Aug 09 05:22:52 PM PDT 24
Peak memory 208300 kb
Host smart-20ac3ba1-657b-4c40-82f9-83e41591db3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552538400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.552538400
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3520680599
Short name T459
Test name
Test status
Simulation time 438739500 ps
CPU time 4.15 seconds
Started Aug 09 05:22:47 PM PDT 24
Finished Aug 09 05:22:52 PM PDT 24
Peak memory 206844 kb
Host smart-12b0ee92-e055-4696-85c6-a68ca4c000cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520680599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3520680599
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.980351678
Short name T262
Test name
Test status
Simulation time 44390081 ps
CPU time 1.83 seconds
Started Aug 09 05:22:50 PM PDT 24
Finished Aug 09 05:22:52 PM PDT 24
Peak memory 218300 kb
Host smart-0e429064-9ba6-4128-a337-2c89c2a88dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980351678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.980351678
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2480918151
Short name T833
Test name
Test status
Simulation time 24033149 ps
CPU time 1.95 seconds
Started Aug 09 05:22:49 PM PDT 24
Finished Aug 09 05:22:51 PM PDT 24
Peak memory 208432 kb
Host smart-fc9093c0-feb1-4232-b124-54332dcec11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480918151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2480918151
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.654692339
Short name T529
Test name
Test status
Simulation time 110546791 ps
CPU time 6.34 seconds
Started Aug 09 05:22:49 PM PDT 24
Finished Aug 09 05:22:56 PM PDT 24
Peak memory 215912 kb
Host smart-5b368b6c-8ae0-4a14-bb26-d07fa05b2e49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654692339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.654692339
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2536281109
Short name T345
Test name
Test status
Simulation time 208995613 ps
CPU time 7.05 seconds
Started Aug 09 05:22:51 PM PDT 24
Finished Aug 09 05:22:58 PM PDT 24
Peak memory 209132 kb
Host smart-9a3c61e3-0c3e-4d80-bdea-5787e67a0192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536281109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2536281109
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2370607096
Short name T433
Test name
Test status
Simulation time 140635344 ps
CPU time 1.86 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:22:57 PM PDT 24
Peak memory 209944 kb
Host smart-086f14ce-7049-488c-b559-cf6778c76119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370607096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2370607096
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2446877180
Short name T590
Test name
Test status
Simulation time 13980548 ps
CPU time 0.77 seconds
Started Aug 09 05:22:48 PM PDT 24
Finished Aug 09 05:22:49 PM PDT 24
Peak memory 205964 kb
Host smart-88417cd6-9edd-4255-9d5b-b9a8a31514f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446877180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2446877180
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1598072811
Short name T77
Test name
Test status
Simulation time 96492860 ps
CPU time 3.36 seconds
Started Aug 09 05:22:48 PM PDT 24
Finished Aug 09 05:22:52 PM PDT 24
Peak memory 210220 kb
Host smart-3ac9032b-2ac5-42e3-b21e-c5eda6074112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598072811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1598072811
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3136888872
Short name T287
Test name
Test status
Simulation time 29639094 ps
CPU time 2.5 seconds
Started Aug 09 05:22:49 PM PDT 24
Finished Aug 09 05:22:52 PM PDT 24
Peak memory 214336 kb
Host smart-7fe67573-bf9f-4bf9-9bfb-ca887a8ed6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136888872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3136888872
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2797454975
Short name T918
Test name
Test status
Simulation time 75004091 ps
CPU time 3.17 seconds
Started Aug 09 05:22:47 PM PDT 24
Finished Aug 09 05:22:51 PM PDT 24
Peak memory 221760 kb
Host smart-f663be97-4bae-48fd-abe9-8144ec4b3f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797454975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2797454975
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3593048560
Short name T799
Test name
Test status
Simulation time 116041956 ps
CPU time 4.58 seconds
Started Aug 09 05:22:52 PM PDT 24
Finished Aug 09 05:22:56 PM PDT 24
Peak memory 220184 kb
Host smart-3f7706d2-e83d-4380-9a36-dfc7eb4b9a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593048560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3593048560
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.4138720372
Short name T701
Test name
Test status
Simulation time 102088135 ps
CPU time 3.99 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:22:59 PM PDT 24
Peak memory 209876 kb
Host smart-73e7fa71-3b75-46a1-a2ad-6fc0de403f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138720372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.4138720372
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2110055001
Short name T492
Test name
Test status
Simulation time 55054847 ps
CPU time 2.66 seconds
Started Aug 09 05:22:49 PM PDT 24
Finished Aug 09 05:22:51 PM PDT 24
Peak memory 206816 kb
Host smart-2313f73b-8d2f-434d-88a1-bbb023af3614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110055001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2110055001
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2392645538
Short name T240
Test name
Test status
Simulation time 1756939277 ps
CPU time 26.46 seconds
Started Aug 09 05:22:49 PM PDT 24
Finished Aug 09 05:23:16 PM PDT 24
Peak memory 208880 kb
Host smart-4eab509f-edb0-4a54-a82b-822a919b9661
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392645538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2392645538
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1563972403
Short name T849
Test name
Test status
Simulation time 90537821 ps
CPU time 3.66 seconds
Started Aug 09 05:22:50 PM PDT 24
Finished Aug 09 05:22:54 PM PDT 24
Peak memory 208592 kb
Host smart-a737aaf6-9a6d-49f8-b851-9c2086ba5069
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563972403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1563972403
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3580104292
Short name T449
Test name
Test status
Simulation time 188129257 ps
CPU time 3.1 seconds
Started Aug 09 05:22:50 PM PDT 24
Finished Aug 09 05:22:54 PM PDT 24
Peak memory 206972 kb
Host smart-694fb447-765e-4d5d-ad09-fc21257c927b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580104292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3580104292
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2627094497
Short name T347
Test name
Test status
Simulation time 240253763 ps
CPU time 3.3 seconds
Started Aug 09 05:22:48 PM PDT 24
Finished Aug 09 05:22:51 PM PDT 24
Peak memory 216028 kb
Host smart-f7d80613-309b-4f41-ac96-6483247167f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627094497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2627094497
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.18931707
Short name T475
Test name
Test status
Simulation time 177973870 ps
CPU time 4.34 seconds
Started Aug 09 05:22:51 PM PDT 24
Finished Aug 09 05:22:55 PM PDT 24
Peak memory 208392 kb
Host smart-2166bdbf-56a8-4955-8413-9549096b2814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18931707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.18931707
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3782197113
Short name T219
Test name
Test status
Simulation time 308734728 ps
CPU time 15.49 seconds
Started Aug 09 05:22:50 PM PDT 24
Finished Aug 09 05:23:06 PM PDT 24
Peak memory 216900 kb
Host smart-baf470c7-f3e4-4a13-9d83-5e38c914440a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782197113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3782197113
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2034006283
Short name T603
Test name
Test status
Simulation time 1024072299 ps
CPU time 11.78 seconds
Started Aug 09 05:22:53 PM PDT 24
Finished Aug 09 05:23:05 PM PDT 24
Peak memory 218556 kb
Host smart-307c0115-f76f-4a06-af64-383c523df1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034006283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2034006283
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1233789742
Short name T881
Test name
Test status
Simulation time 798501454 ps
CPU time 18.77 seconds
Started Aug 09 05:22:50 PM PDT 24
Finished Aug 09 05:23:09 PM PDT 24
Peak memory 210904 kb
Host smart-c3e77617-82dc-4583-9286-32ed8e87a876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233789742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1233789742
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.980351545
Short name T649
Test name
Test status
Simulation time 12322549 ps
CPU time 0.8 seconds
Started Aug 09 05:23:01 PM PDT 24
Finished Aug 09 05:23:02 PM PDT 24
Peak memory 205884 kb
Host smart-42b8091a-0ec3-4c50-af74-7a2739cf4da6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980351545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.980351545
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.4056752061
Short name T410
Test name
Test status
Simulation time 121143610 ps
CPU time 6.12 seconds
Started Aug 09 05:22:53 PM PDT 24
Finished Aug 09 05:23:00 PM PDT 24
Peak memory 214360 kb
Host smart-b9eea76f-3dea-483b-ac6f-475c117b2a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056752061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.4056752061
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.929859740
Short name T830
Test name
Test status
Simulation time 1193158903 ps
CPU time 21.63 seconds
Started Aug 09 05:22:49 PM PDT 24
Finished Aug 09 05:23:11 PM PDT 24
Peak memory 218556 kb
Host smart-eeafbdee-7005-4577-b3be-817681a87f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929859740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.929859740
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.126935461
Short name T233
Test name
Test status
Simulation time 119011147 ps
CPU time 3.32 seconds
Started Aug 09 05:22:57 PM PDT 24
Finished Aug 09 05:23:01 PM PDT 24
Peak memory 214324 kb
Host smart-4398c8d9-b344-4351-82df-11a1b43d9bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126935461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.126935461
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2422047405
Short name T360
Test name
Test status
Simulation time 38604668 ps
CPU time 2.86 seconds
Started Aug 09 05:22:53 PM PDT 24
Finished Aug 09 05:22:56 PM PDT 24
Peak memory 218960 kb
Host smart-98ee035b-d1b6-4ef3-aa2d-5616d46d4dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422047405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2422047405
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.119714767
Short name T411
Test name
Test status
Simulation time 2476184158 ps
CPU time 13.73 seconds
Started Aug 09 05:22:49 PM PDT 24
Finished Aug 09 05:23:03 PM PDT 24
Peak memory 208972 kb
Host smart-5d370206-3aa2-49ad-83f7-a9da219d9b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119714767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.119714767
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1017237851
Short name T914
Test name
Test status
Simulation time 29156455 ps
CPU time 2.23 seconds
Started Aug 09 05:22:49 PM PDT 24
Finished Aug 09 05:22:52 PM PDT 24
Peak memory 208864 kb
Host smart-e8144710-5984-4286-b379-95d63921db5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017237851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1017237851
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.969900715
Short name T868
Test name
Test status
Simulation time 1200091435 ps
CPU time 14.58 seconds
Started Aug 09 05:22:48 PM PDT 24
Finished Aug 09 05:23:03 PM PDT 24
Peak memory 208572 kb
Host smart-cb62de06-1e91-42d3-9469-06545257b5b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969900715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.969900715
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3725130120
Short name T498
Test name
Test status
Simulation time 6302958829 ps
CPU time 62.3 seconds
Started Aug 09 05:22:50 PM PDT 24
Finished Aug 09 05:23:52 PM PDT 24
Peak memory 209256 kb
Host smart-674e8f47-07e4-4252-b66c-a225aa2df748
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725130120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3725130120
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1778947788
Short name T574
Test name
Test status
Simulation time 27604260 ps
CPU time 1.92 seconds
Started Aug 09 05:22:50 PM PDT 24
Finished Aug 09 05:22:53 PM PDT 24
Peak memory 207996 kb
Host smart-a98a3290-9d10-44d1-bdd6-dd3b5a2cfe15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778947788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1778947788
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1207063192
Short name T722
Test name
Test status
Simulation time 1468054037 ps
CPU time 3.21 seconds
Started Aug 09 05:22:56 PM PDT 24
Finished Aug 09 05:22:59 PM PDT 24
Peak memory 209108 kb
Host smart-b19de70d-0160-48ca-8c04-facbacc03b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207063192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1207063192
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1777173589
Short name T646
Test name
Test status
Simulation time 55924902 ps
CPU time 2.03 seconds
Started Aug 09 05:22:48 PM PDT 24
Finished Aug 09 05:22:50 PM PDT 24
Peak memory 206788 kb
Host smart-24ffb3af-c2a6-448f-9404-17c4ee5f08a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777173589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1777173589
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2066831610
Short name T293
Test name
Test status
Simulation time 64576090 ps
CPU time 3.31 seconds
Started Aug 09 05:22:56 PM PDT 24
Finished Aug 09 05:23:00 PM PDT 24
Peak memory 207916 kb
Host smart-9af4832f-b5a9-40be-a61b-9bb992e020da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066831610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2066831610
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1877967933
Short name T162
Test name
Test status
Simulation time 241009025 ps
CPU time 5.51 seconds
Started Aug 09 05:23:01 PM PDT 24
Finished Aug 09 05:23:06 PM PDT 24
Peak memory 210940 kb
Host smart-fbc6bd32-b470-4e97-96b6-d215191937ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877967933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1877967933
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3419002891
Short name T572
Test name
Test status
Simulation time 139555237 ps
CPU time 0.82 seconds
Started Aug 09 05:22:56 PM PDT 24
Finished Aug 09 05:22:57 PM PDT 24
Peak memory 205800 kb
Host smart-097eef69-b4c7-4e7c-9cc3-7c2ba5ced846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419002891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3419002891
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3531970532
Short name T409
Test name
Test status
Simulation time 120511843 ps
CPU time 6.13 seconds
Started Aug 09 05:22:57 PM PDT 24
Finished Aug 09 05:23:03 PM PDT 24
Peak memory 214216 kb
Host smart-b22722dd-a568-4113-96cb-3bad27edb3f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531970532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3531970532
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2162601497
Short name T591
Test name
Test status
Simulation time 66104095 ps
CPU time 3.11 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:22:59 PM PDT 24
Peak memory 214528 kb
Host smart-9ec61cb1-d400-4cf1-98b8-b96cb00e89f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162601497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2162601497
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3227859473
Short name T278
Test name
Test status
Simulation time 242753239 ps
CPU time 2.2 seconds
Started Aug 09 05:22:56 PM PDT 24
Finished Aug 09 05:22:58 PM PDT 24
Peak memory 208112 kb
Host smart-70be3341-5f3a-4c3f-b49c-83a33ea4587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227859473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3227859473
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.938065568
Short name T906
Test name
Test status
Simulation time 43945010 ps
CPU time 3.07 seconds
Started Aug 09 05:22:57 PM PDT 24
Finished Aug 09 05:23:00 PM PDT 24
Peak memory 214320 kb
Host smart-b57c2c42-93c3-4d1e-9ea4-9c21f7aac3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938065568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.938065568
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3397821075
Short name T103
Test name
Test status
Simulation time 233824110 ps
CPU time 3.41 seconds
Started Aug 09 05:22:57 PM PDT 24
Finished Aug 09 05:23:00 PM PDT 24
Peak memory 221112 kb
Host smart-04125397-2d4d-4aae-921f-f94d4e6d2196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397821075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3397821075
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.4211773395
Short name T864
Test name
Test status
Simulation time 121031927 ps
CPU time 2.58 seconds
Started Aug 09 05:23:01 PM PDT 24
Finished Aug 09 05:23:03 PM PDT 24
Peak memory 220052 kb
Host smart-70f168b1-e052-4bc1-a745-18422d264cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211773395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.4211773395
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.381377959
Short name T889
Test name
Test status
Simulation time 35898652 ps
CPU time 2.77 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:22:58 PM PDT 24
Peak memory 207644 kb
Host smart-a94fc8d7-8001-472c-a374-d9504ee0d4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381377959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.381377959
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2445543705
Short name T511
Test name
Test status
Simulation time 648084389 ps
CPU time 16.34 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:23:11 PM PDT 24
Peak memory 208820 kb
Host smart-e025a346-ae68-404a-a5a8-4bf47049a083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445543705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2445543705
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1802128272
Short name T15
Test name
Test status
Simulation time 55590199 ps
CPU time 2.85 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:22:58 PM PDT 24
Peak memory 207068 kb
Host smart-9e3dfe1d-7d3c-46ce-a9ae-383dc38871d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802128272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1802128272
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.593402710
Short name T630
Test name
Test status
Simulation time 1066732704 ps
CPU time 8.26 seconds
Started Aug 09 05:22:57 PM PDT 24
Finished Aug 09 05:23:06 PM PDT 24
Peak memory 208344 kb
Host smart-f9bad253-13f4-46ff-a3e0-4a73e6012f7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593402710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.593402710
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2898358742
Short name T582
Test name
Test status
Simulation time 613595382 ps
CPU time 3.13 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:22:59 PM PDT 24
Peak memory 207280 kb
Host smart-f97a33f4-a36e-4aa8-bdc0-c4a20f7880a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898358742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2898358742
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.562539499
Short name T80
Test name
Test status
Simulation time 393457181 ps
CPU time 5.13 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:23:00 PM PDT 24
Peak memory 209156 kb
Host smart-346b11bd-2fcb-442a-a7f6-54d6f8a92aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562539499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.562539499
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.447458015
Short name T443
Test name
Test status
Simulation time 316588051 ps
CPU time 3.67 seconds
Started Aug 09 05:22:58 PM PDT 24
Finished Aug 09 05:23:01 PM PDT 24
Peak memory 208464 kb
Host smart-237baf03-9451-4b7d-a8bd-2c48b906a907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447458015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.447458015
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3080048591
Short name T369
Test name
Test status
Simulation time 1425184932 ps
CPU time 19.46 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:23:14 PM PDT 24
Peak memory 215572 kb
Host smart-048d5986-aee4-4c75-b1af-5ad584cd7301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080048591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3080048591
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2284038407
Short name T636
Test name
Test status
Simulation time 83819931 ps
CPU time 5.92 seconds
Started Aug 09 05:22:57 PM PDT 24
Finished Aug 09 05:23:03 PM PDT 24
Peak memory 222660 kb
Host smart-e05910c0-7fa7-48a2-acce-e57b3c23856f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284038407 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2284038407
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.4154825100
Short name T546
Test name
Test status
Simulation time 239808470 ps
CPU time 6.58 seconds
Started Aug 09 05:22:56 PM PDT 24
Finished Aug 09 05:23:02 PM PDT 24
Peak memory 209160 kb
Host smart-54276fd2-4959-4653-9bc3-676c7f099489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154825100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.4154825100
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.320903255
Short name T39
Test name
Test status
Simulation time 275245498 ps
CPU time 2.81 seconds
Started Aug 09 05:22:58 PM PDT 24
Finished Aug 09 05:23:00 PM PDT 24
Peak memory 210016 kb
Host smart-aca42361-84db-4ba8-b52e-3543f62545d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320903255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.320903255
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.753844619
Short name T623
Test name
Test status
Simulation time 14547064 ps
CPU time 0.93 seconds
Started Aug 09 05:23:01 PM PDT 24
Finished Aug 09 05:23:02 PM PDT 24
Peak memory 206124 kb
Host smart-91794b64-a0e8-454c-94c4-ba8ba9330411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753844619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.753844619
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.277377339
Short name T853
Test name
Test status
Simulation time 1055948335 ps
CPU time 3.97 seconds
Started Aug 09 05:23:01 PM PDT 24
Finished Aug 09 05:23:05 PM PDT 24
Peak memory 209596 kb
Host smart-6d95f1db-c829-4da7-9e0c-87ebedd35bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277377339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.277377339
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2955403929
Short name T72
Test name
Test status
Simulation time 72422620 ps
CPU time 2.02 seconds
Started Aug 09 05:22:58 PM PDT 24
Finished Aug 09 05:23:00 PM PDT 24
Peak memory 207064 kb
Host smart-4bfbe664-a85f-47f4-b35e-ee3689949827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955403929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2955403929
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1070545755
Short name T890
Test name
Test status
Simulation time 37750160 ps
CPU time 2.42 seconds
Started Aug 09 05:22:58 PM PDT 24
Finished Aug 09 05:23:00 PM PDT 24
Peak memory 215264 kb
Host smart-460655b8-3cd4-4ff8-b4c7-d89b11f5fbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070545755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1070545755
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.480051731
Short name T280
Test name
Test status
Simulation time 247984438 ps
CPU time 3.84 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:22:59 PM PDT 24
Peak memory 222496 kb
Host smart-e9f14553-d628-4ddf-a383-422505c34673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480051731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.480051731
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2246125574
Short name T662
Test name
Test status
Simulation time 85886254 ps
CPU time 3.35 seconds
Started Aug 09 05:22:58 PM PDT 24
Finished Aug 09 05:23:01 PM PDT 24
Peak memory 206044 kb
Host smart-4ce44c46-0f82-4c37-af72-930981fa5a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246125574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2246125574
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1578682696
Short name T899
Test name
Test status
Simulation time 8924318646 ps
CPU time 30.79 seconds
Started Aug 09 05:22:58 PM PDT 24
Finished Aug 09 05:23:29 PM PDT 24
Peak memory 208784 kb
Host smart-1e466362-6724-4337-bce9-ca32260cb1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578682696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1578682696
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1872180430
Short name T740
Test name
Test status
Simulation time 230085314 ps
CPU time 5.19 seconds
Started Aug 09 05:22:55 PM PDT 24
Finished Aug 09 05:23:00 PM PDT 24
Peak memory 208240 kb
Host smart-23b09439-ac34-4b8f-9be1-2e9de9786391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872180430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1872180430
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3806396720
Short name T550
Test name
Test status
Simulation time 437686801 ps
CPU time 3.84 seconds
Started Aug 09 05:22:54 PM PDT 24
Finished Aug 09 05:22:58 PM PDT 24
Peak memory 208472 kb
Host smart-a42eef33-dfdc-4669-b156-0202624e8c7c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806396720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3806396720
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2916749008
Short name T489
Test name
Test status
Simulation time 67747321 ps
CPU time 3.25 seconds
Started Aug 09 05:22:56 PM PDT 24
Finished Aug 09 05:23:00 PM PDT 24
Peak memory 207024 kb
Host smart-b2bdb093-6c3d-4af0-b70e-3a8d3047f410
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916749008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2916749008
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2028863833
Short name T697
Test name
Test status
Simulation time 347082132 ps
CPU time 4.16 seconds
Started Aug 09 05:22:56 PM PDT 24
Finished Aug 09 05:23:00 PM PDT 24
Peak memory 208648 kb
Host smart-336aafb0-7067-4a1b-b48d-3c0e13f6ad7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028863833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2028863833
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3165493455
Short name T671
Test name
Test status
Simulation time 661885348 ps
CPU time 3.79 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:07 PM PDT 24
Peak memory 214252 kb
Host smart-c1427f3d-be40-4c63-a694-3b7b58f01e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165493455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3165493455
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2682890836
Short name T734
Test name
Test status
Simulation time 167252550 ps
CPU time 4.6 seconds
Started Aug 09 05:22:57 PM PDT 24
Finished Aug 09 05:23:02 PM PDT 24
Peak memory 208432 kb
Host smart-81547699-2a50-442e-8541-2bbb303f9b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682890836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2682890836
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.201912816
Short name T358
Test name
Test status
Simulation time 15833720343 ps
CPU time 246.24 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 222564 kb
Host smart-3720a89d-bb80-4e2f-9f39-504b256d695a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201912816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.201912816
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3784062105
Short name T543
Test name
Test status
Simulation time 365767279 ps
CPU time 14.24 seconds
Started Aug 09 05:23:04 PM PDT 24
Finished Aug 09 05:23:19 PM PDT 24
Peak memory 220680 kb
Host smart-d37e0b84-a494-4076-ab82-535d0374bf6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784062105 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3784062105
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1801472460
Short name T494
Test name
Test status
Simulation time 74103143 ps
CPU time 4.55 seconds
Started Aug 09 05:23:00 PM PDT 24
Finished Aug 09 05:23:05 PM PDT 24
Peak memory 214332 kb
Host smart-8a56c138-6a92-4761-8a52-48143f2fef84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801472460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1801472460
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1687816082
Short name T706
Test name
Test status
Simulation time 1883811308 ps
CPU time 5.03 seconds
Started Aug 09 05:23:06 PM PDT 24
Finished Aug 09 05:23:11 PM PDT 24
Peak memory 210480 kb
Host smart-5a1f12a5-426b-470a-896a-5ef6d47d2ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687816082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1687816082
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2738353505
Short name T184
Test name
Test status
Simulation time 10203662 ps
CPU time 0.75 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:04 PM PDT 24
Peak memory 206172 kb
Host smart-304ba49f-a7ca-4217-b6c3-9df52dc9dfce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738353505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2738353505
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2192104102
Short name T42
Test name
Test status
Simulation time 101459691 ps
CPU time 1.85 seconds
Started Aug 09 05:23:04 PM PDT 24
Finished Aug 09 05:23:06 PM PDT 24
Peak memory 209360 kb
Host smart-ac5d9572-f2c5-4b24-93e1-b75d336a8a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192104102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2192104102
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2981033604
Short name T519
Test name
Test status
Simulation time 112438250 ps
CPU time 2.54 seconds
Started Aug 09 05:23:04 PM PDT 24
Finished Aug 09 05:23:07 PM PDT 24
Peak memory 207584 kb
Host smart-8ed68b4f-2139-4185-a790-f114a269b4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981033604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2981033604
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4097393325
Short name T884
Test name
Test status
Simulation time 166126554 ps
CPU time 3.1 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:07 PM PDT 24
Peak memory 209688 kb
Host smart-93942f63-bdda-464a-90bf-5e2e8a38b599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097393325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4097393325
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.826602566
Short name T698
Test name
Test status
Simulation time 286974835 ps
CPU time 4.39 seconds
Started Aug 09 05:23:06 PM PDT 24
Finished Aug 09 05:23:11 PM PDT 24
Peak memory 220464 kb
Host smart-146bd850-d2a9-4a8d-8af6-953be67776d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826602566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.826602566
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1554322751
Short name T61
Test name
Test status
Simulation time 200084998 ps
CPU time 3.06 seconds
Started Aug 09 05:23:12 PM PDT 24
Finished Aug 09 05:23:15 PM PDT 24
Peak memory 208648 kb
Host smart-961219fe-9358-46ff-93ab-049426082796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554322751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1554322751
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2581187825
Short name T854
Test name
Test status
Simulation time 148470001 ps
CPU time 4.99 seconds
Started Aug 09 05:23:05 PM PDT 24
Finished Aug 09 05:23:10 PM PDT 24
Peak memory 208836 kb
Host smart-e9205b90-8f05-419a-9f51-f6706abe3562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581187825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2581187825
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1736438106
Short name T634
Test name
Test status
Simulation time 132181441 ps
CPU time 5.2 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:08 PM PDT 24
Peak memory 208932 kb
Host smart-fa7d8691-dc07-4fc6-95d2-45ad1a9cb30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736438106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1736438106
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.4053662906
Short name T104
Test name
Test status
Simulation time 31311348 ps
CPU time 2.44 seconds
Started Aug 09 05:23:08 PM PDT 24
Finished Aug 09 05:23:11 PM PDT 24
Peak memory 206992 kb
Host smart-a746446e-5e09-4586-a354-4274cb81ce6d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053662906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.4053662906
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.904311288
Short name T831
Test name
Test status
Simulation time 238049497 ps
CPU time 6.84 seconds
Started Aug 09 05:23:04 PM PDT 24
Finished Aug 09 05:23:11 PM PDT 24
Peak memory 208836 kb
Host smart-7f2a3dfb-350c-4fa3-8ed7-8e76aed02182
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904311288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.904311288
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.250073296
Short name T448
Test name
Test status
Simulation time 298108038 ps
CPU time 3.88 seconds
Started Aug 09 05:23:08 PM PDT 24
Finished Aug 09 05:23:11 PM PDT 24
Peak memory 208860 kb
Host smart-34f82e3a-2269-42f0-a807-9b3dd5016c47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250073296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.250073296
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1951084520
Short name T428
Test name
Test status
Simulation time 48340409 ps
CPU time 2.56 seconds
Started Aug 09 05:23:06 PM PDT 24
Finished Aug 09 05:23:09 PM PDT 24
Peak memory 208564 kb
Host smart-4096d75c-8390-4aa2-b5ad-bd1b7f424c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951084520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1951084520
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.4074627456
Short name T533
Test name
Test status
Simulation time 9898663184 ps
CPU time 33.39 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:36 PM PDT 24
Peak memory 209024 kb
Host smart-4b392a73-d068-4a3f-a4f1-007958e46989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074627456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.4074627456
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2099311940
Short name T292
Test name
Test status
Simulation time 3449720703 ps
CPU time 19.64 seconds
Started Aug 09 05:23:01 PM PDT 24
Finished Aug 09 05:23:21 PM PDT 24
Peak memory 221240 kb
Host smart-a2d79dac-4dc4-40bf-ad0c-d0e764547bf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099311940 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2099311940
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.591644112
Short name T273
Test name
Test status
Simulation time 434443465 ps
CPU time 7.22 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:10 PM PDT 24
Peak memory 210128 kb
Host smart-6bdb8fc5-613c-4857-8b4a-3aba20de5c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591644112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.591644112
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2857531819
Short name T43
Test name
Test status
Simulation time 109973018 ps
CPU time 1.79 seconds
Started Aug 09 05:23:02 PM PDT 24
Finished Aug 09 05:23:04 PM PDT 24
Peak memory 210064 kb
Host smart-2e48c0e9-49f8-4142-809e-9fd4a8e10991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857531819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2857531819
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.186401374
Short name T423
Test name
Test status
Simulation time 26368869 ps
CPU time 0.92 seconds
Started Aug 09 05:23:04 PM PDT 24
Finished Aug 09 05:23:05 PM PDT 24
Peak memory 205984 kb
Host smart-2ac0d388-eb49-48bb-bff3-e5e78aaeb7f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186401374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.186401374
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.390260388
Short name T41
Test name
Test status
Simulation time 541105031 ps
CPU time 3.35 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:06 PM PDT 24
Peak memory 214284 kb
Host smart-b6d05782-5515-4c3e-8247-a3ab02962564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390260388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.390260388
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.591025775
Short name T592
Test name
Test status
Simulation time 138911601 ps
CPU time 1.96 seconds
Started Aug 09 05:23:06 PM PDT 24
Finished Aug 09 05:23:08 PM PDT 24
Peak memory 208124 kb
Host smart-6c816a30-4a6d-46d1-8327-0bd29b0f3645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591025775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.591025775
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2448631486
Short name T823
Test name
Test status
Simulation time 61631654 ps
CPU time 2.59 seconds
Started Aug 09 05:23:04 PM PDT 24
Finished Aug 09 05:23:07 PM PDT 24
Peak memory 214332 kb
Host smart-e92c0206-676c-4cae-ba84-6c9fed1d63f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448631486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2448631486
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3317082816
Short name T284
Test name
Test status
Simulation time 149593451 ps
CPU time 2.95 seconds
Started Aug 09 05:23:06 PM PDT 24
Finished Aug 09 05:23:09 PM PDT 24
Peak memory 214156 kb
Host smart-829c22b2-55d6-4e77-ae0b-143377967059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317082816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3317082816
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_random.2774539460
Short name T687
Test name
Test status
Simulation time 267274640 ps
CPU time 6.36 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:09 PM PDT 24
Peak memory 214320 kb
Host smart-e1b7cad0-b308-496d-8b9b-5b508e72051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774539460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2774539460
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2259668061
Short name T341
Test name
Test status
Simulation time 273214263 ps
CPU time 4.37 seconds
Started Aug 09 05:23:02 PM PDT 24
Finished Aug 09 05:23:07 PM PDT 24
Peak memory 208528 kb
Host smart-c4177ee2-776d-48fd-b6dd-86794cbd17c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259668061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2259668061
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3738990267
Short name T712
Test name
Test status
Simulation time 1391456253 ps
CPU time 35.13 seconds
Started Aug 09 05:23:04 PM PDT 24
Finished Aug 09 05:23:39 PM PDT 24
Peak memory 208160 kb
Host smart-a1223640-628f-4994-84d6-5e74d98c98c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738990267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3738990267
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1280158403
Short name T355
Test name
Test status
Simulation time 145864669 ps
CPU time 2.21 seconds
Started Aug 09 05:23:02 PM PDT 24
Finished Aug 09 05:23:04 PM PDT 24
Peak memory 206944 kb
Host smart-06e8086c-5660-4f0c-a754-e2f9917739e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280158403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1280158403
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.957166735
Short name T846
Test name
Test status
Simulation time 190072759 ps
CPU time 5.42 seconds
Started Aug 09 05:23:06 PM PDT 24
Finished Aug 09 05:23:12 PM PDT 24
Peak memory 208196 kb
Host smart-49fa7b3d-b2cd-4c12-92f4-3f9762c47c19
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957166735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.957166735
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.273224553
Short name T538
Test name
Test status
Simulation time 272222367 ps
CPU time 2.18 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:05 PM PDT 24
Peak memory 207720 kb
Host smart-b10df8d9-d283-4f8d-baa7-1798d24e1846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273224553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.273224553
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3372276671
Short name T392
Test name
Test status
Simulation time 55045505 ps
CPU time 2.75 seconds
Started Aug 09 05:23:02 PM PDT 24
Finished Aug 09 05:23:05 PM PDT 24
Peak memory 206676 kb
Host smart-f0377a11-63a9-42fa-959b-b2c90793e4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372276671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3372276671
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3116766630
Short name T329
Test name
Test status
Simulation time 10979136740 ps
CPU time 49.28 seconds
Started Aug 09 05:23:04 PM PDT 24
Finished Aug 09 05:23:54 PM PDT 24
Peak memory 216352 kb
Host smart-a64a96d0-100e-4b5f-a33c-c50f0bcc41a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116766630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3116766630
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.172230037
Short name T748
Test name
Test status
Simulation time 1316862652 ps
CPU time 10.43 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:14 PM PDT 24
Peak memory 222580 kb
Host smart-aef93b0f-db12-49a9-9d69-7afe3e1b8b40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172230037 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.172230037
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1912017834
Short name T351
Test name
Test status
Simulation time 774843088 ps
CPU time 20.47 seconds
Started Aug 09 05:23:05 PM PDT 24
Finished Aug 09 05:23:25 PM PDT 24
Peak memory 218240 kb
Host smart-9a435cbf-a236-45a3-9182-5983a7713108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912017834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1912017834
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.4020962009
Short name T107
Test name
Test status
Simulation time 93003329 ps
CPU time 2.14 seconds
Started Aug 09 05:23:04 PM PDT 24
Finished Aug 09 05:23:06 PM PDT 24
Peak memory 209988 kb
Host smart-966df09a-126d-4107-a923-c4c7403a7aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020962009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.4020962009
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2849262316
Short name T455
Test name
Test status
Simulation time 12097970 ps
CPU time 0.86 seconds
Started Aug 09 05:23:05 PM PDT 24
Finished Aug 09 05:23:06 PM PDT 24
Peak memory 205852 kb
Host smart-c90d23ad-8d25-4373-91f0-ee9386ad3725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849262316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2849262316
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3647044254
Short name T239
Test name
Test status
Simulation time 7065370667 ps
CPU time 101.08 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:24:44 PM PDT 24
Peak memory 219112 kb
Host smart-648b21b1-69db-4b34-9353-875588da7ef8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647044254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3647044254
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3196794566
Short name T710
Test name
Test status
Simulation time 113838660 ps
CPU time 3.68 seconds
Started Aug 09 05:23:04 PM PDT 24
Finished Aug 09 05:23:07 PM PDT 24
Peak memory 218548 kb
Host smart-1ba667ae-740b-4c11-8d19-8f3929c551d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196794566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3196794566
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3138641148
Short name T393
Test name
Test status
Simulation time 126818044 ps
CPU time 2.93 seconds
Started Aug 09 05:23:08 PM PDT 24
Finished Aug 09 05:23:11 PM PDT 24
Peak memory 209132 kb
Host smart-b5774dc1-eeea-480f-8f46-6eb864865020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138641148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3138641148
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2005622876
Short name T251
Test name
Test status
Simulation time 376903758 ps
CPU time 2.81 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:06 PM PDT 24
Peak memory 212924 kb
Host smart-af5d814d-2f1c-47e5-a9ef-9c36f77a62fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005622876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2005622876
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3484029157
Short name T50
Test name
Test status
Simulation time 272705525 ps
CPU time 2.37 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:06 PM PDT 24
Peak memory 214332 kb
Host smart-d96ac6c3-3f98-4286-8b25-c0dea491c99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484029157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3484029157
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1363762610
Short name T526
Test name
Test status
Simulation time 264660437 ps
CPU time 3.43 seconds
Started Aug 09 05:23:06 PM PDT 24
Finished Aug 09 05:23:09 PM PDT 24
Peak memory 208364 kb
Host smart-df295076-421c-4e6c-a569-92d88eac34d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363762610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1363762610
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2497472442
Short name T815
Test name
Test status
Simulation time 1392817821 ps
CPU time 34.55 seconds
Started Aug 09 05:23:12 PM PDT 24
Finished Aug 09 05:23:47 PM PDT 24
Peak memory 208936 kb
Host smart-367418c8-6881-4b63-a0e7-057a739000e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497472442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2497472442
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3991122066
Short name T566
Test name
Test status
Simulation time 23723202 ps
CPU time 1.97 seconds
Started Aug 09 05:23:06 PM PDT 24
Finished Aug 09 05:23:08 PM PDT 24
Peak memory 208812 kb
Host smart-a198932e-7ec2-498b-803c-35bf1cd0ef45
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991122066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3991122066
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3342343052
Short name T367
Test name
Test status
Simulation time 105017796 ps
CPU time 2.32 seconds
Started Aug 09 05:23:07 PM PDT 24
Finished Aug 09 05:23:10 PM PDT 24
Peak memory 206944 kb
Host smart-90c40750-9837-402a-b988-9886e80e243e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342343052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3342343052
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1427494536
Short name T670
Test name
Test status
Simulation time 49526720 ps
CPU time 2.01 seconds
Started Aug 09 05:23:08 PM PDT 24
Finished Aug 09 05:23:10 PM PDT 24
Peak memory 207688 kb
Host smart-e79db9e5-a931-4c56-8352-d4c5c689c99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427494536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1427494536
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3447245312
Short name T766
Test name
Test status
Simulation time 509743829 ps
CPU time 2.08 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:05 PM PDT 24
Peak memory 206924 kb
Host smart-90cdc0b6-f202-4d1a-99a7-1b223be51bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447245312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3447245312
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.175086214
Short name T923
Test name
Test status
Simulation time 348124156 ps
CPU time 6.61 seconds
Started Aug 09 05:23:11 PM PDT 24
Finished Aug 09 05:23:18 PM PDT 24
Peak memory 222452 kb
Host smart-77f70f49-fb2a-4965-9df2-7769dfd60649
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175086214 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.175086214
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1907963827
Short name T624
Test name
Test status
Simulation time 158398030 ps
CPU time 2.83 seconds
Started Aug 09 05:23:05 PM PDT 24
Finished Aug 09 05:23:08 PM PDT 24
Peak memory 209980 kb
Host smart-b5010b3e-5c88-4c16-95b3-72a4a0916bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907963827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1907963827
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3800715738
Short name T399
Test name
Test status
Simulation time 149357742 ps
CPU time 2.77 seconds
Started Aug 09 05:23:11 PM PDT 24
Finished Aug 09 05:23:14 PM PDT 24
Peak memory 209908 kb
Host smart-904ef5ba-82b9-4ece-9e62-43f6a0cc0f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800715738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3800715738
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1738725182
Short name T820
Test name
Test status
Simulation time 144735984 ps
CPU time 0.83 seconds
Started Aug 09 05:23:11 PM PDT 24
Finished Aug 09 05:23:12 PM PDT 24
Peak memory 205880 kb
Host smart-3ed1fc9e-578e-458a-ad69-9b1ee816695a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738725182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1738725182
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3964736084
Short name T387
Test name
Test status
Simulation time 52516760 ps
CPU time 3.68 seconds
Started Aug 09 05:23:08 PM PDT 24
Finished Aug 09 05:23:12 PM PDT 24
Peak memory 214268 kb
Host smart-fe4a2cfc-a66d-4998-aded-0ea59aa85f0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964736084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3964736084
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3218503376
Short name T22
Test name
Test status
Simulation time 150394165 ps
CPU time 4.49 seconds
Started Aug 09 05:23:10 PM PDT 24
Finished Aug 09 05:23:15 PM PDT 24
Peak memory 218492 kb
Host smart-5308a2a8-c664-4065-b01d-6ab38f50773c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218503376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3218503376
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1925716962
Short name T471
Test name
Test status
Simulation time 20318384 ps
CPU time 1.58 seconds
Started Aug 09 05:23:11 PM PDT 24
Finished Aug 09 05:23:12 PM PDT 24
Peak memory 206960 kb
Host smart-eb54a0d9-7b92-45a5-8bea-2b7665cbedd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925716962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1925716962
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3619764338
Short name T51
Test name
Test status
Simulation time 89182689 ps
CPU time 3.13 seconds
Started Aug 09 05:23:10 PM PDT 24
Finished Aug 09 05:23:13 PM PDT 24
Peak memory 215388 kb
Host smart-70c03505-7c84-487b-9195-b66f21ea2cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619764338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3619764338
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2998298449
Short name T192
Test name
Test status
Simulation time 161330128 ps
CPU time 3.99 seconds
Started Aug 09 05:23:12 PM PDT 24
Finished Aug 09 05:23:16 PM PDT 24
Peak memory 215108 kb
Host smart-d2c31ce5-6da5-4cfc-ace1-b2e4dcdea603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998298449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2998298449
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1402698797
Short name T631
Test name
Test status
Simulation time 396131780 ps
CPU time 5.04 seconds
Started Aug 09 05:23:13 PM PDT 24
Finished Aug 09 05:23:19 PM PDT 24
Peak memory 218336 kb
Host smart-7724eacb-90d3-4bfb-847a-b42fe2bf9c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402698797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1402698797
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1855789359
Short name T348
Test name
Test status
Simulation time 9664351820 ps
CPU time 35.96 seconds
Started Aug 09 05:23:03 PM PDT 24
Finished Aug 09 05:23:39 PM PDT 24
Peak memory 207760 kb
Host smart-89ddb33d-87b8-423b-b23e-c577dbbc12f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855789359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1855789359
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.4074076781
Short name T576
Test name
Test status
Simulation time 73882173 ps
CPU time 3.44 seconds
Started Aug 09 05:23:07 PM PDT 24
Finished Aug 09 05:23:10 PM PDT 24
Peak memory 208776 kb
Host smart-a3a2a548-1521-4965-8d22-12449a66ffa8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074076781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.4074076781
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2076324946
Short name T548
Test name
Test status
Simulation time 72551022 ps
CPU time 3.7 seconds
Started Aug 09 05:23:12 PM PDT 24
Finished Aug 09 05:23:15 PM PDT 24
Peak memory 208504 kb
Host smart-965df6a1-9240-42f2-836c-9a5dee533640
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076324946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2076324946
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3449475377
Short name T245
Test name
Test status
Simulation time 77794255 ps
CPU time 1.79 seconds
Started Aug 09 05:23:19 PM PDT 24
Finished Aug 09 05:23:21 PM PDT 24
Peak memory 206912 kb
Host smart-a2c80904-bed9-42d1-b0a5-4ad5cb793848
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449475377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3449475377
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3740148543
Short name T873
Test name
Test status
Simulation time 506930419 ps
CPU time 3.25 seconds
Started Aug 09 05:23:10 PM PDT 24
Finished Aug 09 05:23:13 PM PDT 24
Peak memory 208888 kb
Host smart-054f4a87-cc22-4954-8070-c7267c0f15de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740148543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3740148543
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1015696335
Short name T432
Test name
Test status
Simulation time 19910308 ps
CPU time 1.59 seconds
Started Aug 09 05:23:08 PM PDT 24
Finished Aug 09 05:23:09 PM PDT 24
Peak memory 206608 kb
Host smart-38f7c591-5d5d-4fd6-bf3c-124b04b44c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015696335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1015696335
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1682763168
Short name T866
Test name
Test status
Simulation time 375095773 ps
CPU time 9.22 seconds
Started Aug 09 05:23:11 PM PDT 24
Finished Aug 09 05:23:21 PM PDT 24
Peak memory 214420 kb
Host smart-0a00b4dd-a2a3-4f93-b93c-30c2b46cc5d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682763168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1682763168
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.321965294
Short name T105
Test name
Test status
Simulation time 1710761604 ps
CPU time 16.43 seconds
Started Aug 09 05:23:09 PM PDT 24
Finished Aug 09 05:23:26 PM PDT 24
Peak memory 210352 kb
Host smart-95e5585a-4837-4f75-b2ca-2b125f7f64db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321965294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.321965294
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1653371110
Short name T729
Test name
Test status
Simulation time 57490893 ps
CPU time 0.78 seconds
Started Aug 09 05:21:14 PM PDT 24
Finished Aug 09 05:21:15 PM PDT 24
Peak memory 205804 kb
Host smart-0e86f8b6-b947-409d-b22c-0d0de39b2aa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653371110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1653371110
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1971700460
Short name T877
Test name
Test status
Simulation time 223550200 ps
CPU time 3.73 seconds
Started Aug 09 05:21:14 PM PDT 24
Finished Aug 09 05:21:18 PM PDT 24
Peak memory 222764 kb
Host smart-cf08900c-2c2b-4957-989f-e3663c4efcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971700460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1971700460
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2236926673
Short name T549
Test name
Test status
Simulation time 17792374 ps
CPU time 1.3 seconds
Started Aug 09 05:21:15 PM PDT 24
Finished Aug 09 05:21:16 PM PDT 24
Peak memory 208280 kb
Host smart-0dd51aff-a41b-463d-b144-0a827d7aac1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236926673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2236926673
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3023479172
Short name T677
Test name
Test status
Simulation time 120095828 ps
CPU time 2.97 seconds
Started Aug 09 05:21:14 PM PDT 24
Finished Aug 09 05:21:17 PM PDT 24
Peak memory 214228 kb
Host smart-3cbd8022-9252-43b1-a795-99c1e0d16694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023479172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3023479172
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2411608479
Short name T209
Test name
Test status
Simulation time 30069670 ps
CPU time 1.74 seconds
Started Aug 09 05:21:12 PM PDT 24
Finished Aug 09 05:21:14 PM PDT 24
Peak memory 214588 kb
Host smart-3a963c50-b0b1-485a-90cc-1ab4be7d4b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411608479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2411608479
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2450345681
Short name T764
Test name
Test status
Simulation time 1252076263 ps
CPU time 6.5 seconds
Started Aug 09 05:21:15 PM PDT 24
Finished Aug 09 05:21:22 PM PDT 24
Peak memory 208644 kb
Host smart-f5eaca37-46d7-48f1-9c0f-8394f4c6cdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450345681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2450345681
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.197029540
Short name T33
Test name
Test status
Simulation time 512148834 ps
CPU time 12.93 seconds
Started Aug 09 05:21:12 PM PDT 24
Finished Aug 09 05:21:25 PM PDT 24
Peak memory 238632 kb
Host smart-7e453cca-3684-4691-8071-20a8de5e40f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197029540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.197029540
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1554454680
Short name T506
Test name
Test status
Simulation time 427304219 ps
CPU time 6.44 seconds
Started Aug 09 05:21:11 PM PDT 24
Finished Aug 09 05:21:17 PM PDT 24
Peak memory 208052 kb
Host smart-0bb0599a-cf31-428b-bfab-036e9be97fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554454680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1554454680
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2720510192
Short name T544
Test name
Test status
Simulation time 290733647 ps
CPU time 3.02 seconds
Started Aug 09 05:21:12 PM PDT 24
Finished Aug 09 05:21:15 PM PDT 24
Peak memory 206924 kb
Host smart-3e6c099b-49d4-4397-ab4e-01cc83757ffa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720510192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2720510192
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1563834245
Short name T478
Test name
Test status
Simulation time 67296550 ps
CPU time 3.24 seconds
Started Aug 09 05:21:11 PM PDT 24
Finished Aug 09 05:21:15 PM PDT 24
Peak memory 208680 kb
Host smart-742d9844-e48f-4a8c-9a6f-6103c062f1ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563834245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1563834245
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.943551059
Short name T556
Test name
Test status
Simulation time 657779293 ps
CPU time 7.05 seconds
Started Aug 09 05:21:14 PM PDT 24
Finished Aug 09 05:21:21 PM PDT 24
Peak memory 207996 kb
Host smart-42375877-b133-4929-83d7-2c57aac0db2a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943551059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.943551059
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4277395049
Short name T676
Test name
Test status
Simulation time 31432852 ps
CPU time 1.59 seconds
Started Aug 09 05:21:14 PM PDT 24
Finished Aug 09 05:21:16 PM PDT 24
Peak memory 208300 kb
Host smart-16f10d56-61c8-4d69-b4af-2d9a40fbe609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277395049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4277395049
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.106500218
Short name T611
Test name
Test status
Simulation time 150007159 ps
CPU time 4.77 seconds
Started Aug 09 05:21:07 PM PDT 24
Finished Aug 09 05:21:11 PM PDT 24
Peak memory 206720 kb
Host smart-a684a8bd-110f-43c1-a303-78449d4ea44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106500218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.106500218
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2844665943
Short name T903
Test name
Test status
Simulation time 247547923 ps
CPU time 5.93 seconds
Started Aug 09 05:21:14 PM PDT 24
Finished Aug 09 05:21:20 PM PDT 24
Peak memory 214336 kb
Host smart-824b906b-46f4-4d04-8665-42b8a2df7a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844665943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2844665943
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.988520938
Short name T379
Test name
Test status
Simulation time 61090778 ps
CPU time 2.34 seconds
Started Aug 09 05:21:14 PM PDT 24
Finished Aug 09 05:21:16 PM PDT 24
Peak memory 209668 kb
Host smart-62b277e1-92a0-495d-a06b-df9206fee32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988520938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.988520938
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1289639962
Short name T660
Test name
Test status
Simulation time 83143424 ps
CPU time 0.72 seconds
Started Aug 09 05:23:18 PM PDT 24
Finished Aug 09 05:23:18 PM PDT 24
Peak memory 205900 kb
Host smart-33fd9b2e-0266-4434-bce2-2af6a3a65637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289639962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1289639962
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.15835541
Short name T238
Test name
Test status
Simulation time 618473818 ps
CPU time 9.57 seconds
Started Aug 09 05:23:18 PM PDT 24
Finished Aug 09 05:23:27 PM PDT 24
Peak memory 215452 kb
Host smart-af24e7cb-5b93-44c2-9b69-a09b2fb8385e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15835541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.15835541
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.4093206164
Short name T716
Test name
Test status
Simulation time 76543743 ps
CPU time 1.78 seconds
Started Aug 09 05:23:11 PM PDT 24
Finished Aug 09 05:23:13 PM PDT 24
Peak memory 214328 kb
Host smart-e2c5db36-a524-47dc-b48a-9beb8e1824fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093206164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.4093206164
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1427839717
Short name T809
Test name
Test status
Simulation time 256312670 ps
CPU time 1.88 seconds
Started Aug 09 05:23:10 PM PDT 24
Finished Aug 09 05:23:13 PM PDT 24
Peak memory 215504 kb
Host smart-1da0874f-3628-4c23-9a4a-4fba1caed3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427839717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1427839717
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2610436115
Short name T891
Test name
Test status
Simulation time 71903593 ps
CPU time 2.05 seconds
Started Aug 09 05:23:10 PM PDT 24
Finished Aug 09 05:23:12 PM PDT 24
Peak memory 214556 kb
Host smart-2ffc06a8-c291-4655-a138-b068c9c1b08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610436115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2610436115
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1900451982
Short name T797
Test name
Test status
Simulation time 325792219 ps
CPU time 3.9 seconds
Started Aug 09 05:23:19 PM PDT 24
Finished Aug 09 05:23:23 PM PDT 24
Peak memory 209592 kb
Host smart-190785c4-14f0-46d3-852c-308771cb2a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900451982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1900451982
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1123236049
Short name T505
Test name
Test status
Simulation time 808544022 ps
CPU time 6.14 seconds
Started Aug 09 05:23:10 PM PDT 24
Finished Aug 09 05:23:16 PM PDT 24
Peak memory 209416 kb
Host smart-da8c9f99-c630-4cc1-a7f3-a80823cfe096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123236049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1123236049
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3703219349
Short name T541
Test name
Test status
Simulation time 342103922 ps
CPU time 2.51 seconds
Started Aug 09 05:23:11 PM PDT 24
Finished Aug 09 05:23:13 PM PDT 24
Peak memory 206788 kb
Host smart-fc96d4c1-e709-4dc0-98a4-eea5451140c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703219349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3703219349
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3655466814
Short name T330
Test name
Test status
Simulation time 6625597269 ps
CPU time 62.16 seconds
Started Aug 09 05:23:13 PM PDT 24
Finished Aug 09 05:24:16 PM PDT 24
Peak memory 208916 kb
Host smart-6c26d6bb-1261-44c9-bf28-31ae813caf4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655466814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3655466814
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.226245858
Short name T349
Test name
Test status
Simulation time 125976929 ps
CPU time 4.86 seconds
Started Aug 09 05:23:18 PM PDT 24
Finished Aug 09 05:23:23 PM PDT 24
Peak memory 208668 kb
Host smart-2b1a7412-f093-4d8a-8298-9e49989eaa5a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226245858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.226245858
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1143237628
Short name T334
Test name
Test status
Simulation time 189917456 ps
CPU time 2.47 seconds
Started Aug 09 05:23:19 PM PDT 24
Finished Aug 09 05:23:21 PM PDT 24
Peak memory 208676 kb
Host smart-dc73bf53-2212-40ec-be78-1faa92fd32b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143237628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1143237628
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.248472936
Short name T869
Test name
Test status
Simulation time 76108945 ps
CPU time 2.48 seconds
Started Aug 09 05:23:12 PM PDT 24
Finished Aug 09 05:23:14 PM PDT 24
Peak memory 209444 kb
Host smart-678de414-d3cd-455c-a439-e3577de1b463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248472936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.248472936
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.422801565
Short name T431
Test name
Test status
Simulation time 169721023 ps
CPU time 2.53 seconds
Started Aug 09 05:23:11 PM PDT 24
Finished Aug 09 05:23:14 PM PDT 24
Peak memory 206756 kb
Host smart-72ddbaf9-5187-4246-a72f-aefc96cbdc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422801565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.422801565
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.995225516
Short name T316
Test name
Test status
Simulation time 744804318 ps
CPU time 8.77 seconds
Started Aug 09 05:23:10 PM PDT 24
Finished Aug 09 05:23:19 PM PDT 24
Peak memory 214996 kb
Host smart-eb2f5527-48fd-4a8a-ba75-6da3e57a6f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995225516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.995225516
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.13513347
Short name T477
Test name
Test status
Simulation time 370471320 ps
CPU time 13.52 seconds
Started Aug 09 05:23:16 PM PDT 24
Finished Aug 09 05:23:30 PM PDT 24
Peak memory 222444 kb
Host smart-6233e7d7-4797-4e07-91d6-3af862c41715
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13513347 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.13513347
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.4243718344
Short name T311
Test name
Test status
Simulation time 2134439090 ps
CPU time 27.52 seconds
Started Aug 09 05:23:17 PM PDT 24
Finished Aug 09 05:23:45 PM PDT 24
Peak memory 209000 kb
Host smart-87d65419-e028-433d-8066-1210279c97d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243718344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.4243718344
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1095487796
Short name T190
Test name
Test status
Simulation time 1105703739 ps
CPU time 7.28 seconds
Started Aug 09 05:23:08 PM PDT 24
Finished Aug 09 05:23:16 PM PDT 24
Peak memory 210792 kb
Host smart-561dfe99-9862-4256-b6e6-ea19074604c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095487796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1095487796
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1582474861
Short name T101
Test name
Test status
Simulation time 104669167 ps
CPU time 1.13 seconds
Started Aug 09 05:23:17 PM PDT 24
Finished Aug 09 05:23:19 PM PDT 24
Peak memory 206112 kb
Host smart-51c7a24b-e775-427a-8289-54e88bf04aa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582474861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1582474861
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2039225242
Short name T414
Test name
Test status
Simulation time 39674958 ps
CPU time 2.96 seconds
Started Aug 09 05:23:17 PM PDT 24
Finished Aug 09 05:23:20 PM PDT 24
Peak memory 215696 kb
Host smart-b3b3f085-8db2-4c1d-a165-c96ef51c94cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2039225242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2039225242
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3640687487
Short name T893
Test name
Test status
Simulation time 156011316 ps
CPU time 4.24 seconds
Started Aug 09 05:23:15 PM PDT 24
Finished Aug 09 05:23:19 PM PDT 24
Peak memory 219056 kb
Host smart-ea6f7136-5ee3-4aec-9505-014fd3bebf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640687487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3640687487
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3202911410
Short name T356
Test name
Test status
Simulation time 518338597 ps
CPU time 4.54 seconds
Started Aug 09 05:23:14 PM PDT 24
Finished Aug 09 05:23:19 PM PDT 24
Peak memory 218724 kb
Host smart-5d0432a3-f48d-4d1d-8629-bfdc628bb297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202911410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3202911410
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1777643749
Short name T281
Test name
Test status
Simulation time 317371206 ps
CPU time 3.94 seconds
Started Aug 09 05:23:17 PM PDT 24
Finished Aug 09 05:23:21 PM PDT 24
Peak memory 222480 kb
Host smart-8ab7b0c8-f382-425c-a4d7-837988930c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777643749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1777643749
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3664631980
Short name T875
Test name
Test status
Simulation time 479521958 ps
CPU time 10.22 seconds
Started Aug 09 05:23:17 PM PDT 24
Finished Aug 09 05:23:27 PM PDT 24
Peak memory 214220 kb
Host smart-cfe0ba85-7baa-44d8-95c1-cbaeeed282b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664631980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3664631980
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2338097266
Short name T275
Test name
Test status
Simulation time 1179281986 ps
CPU time 14.38 seconds
Started Aug 09 05:23:18 PM PDT 24
Finished Aug 09 05:23:32 PM PDT 24
Peak memory 218408 kb
Host smart-76e6ce4b-d51a-4844-b4b9-d7d859a31675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338097266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2338097266
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.516405606
Short name T920
Test name
Test status
Simulation time 540585584 ps
CPU time 4.2 seconds
Started Aug 09 05:23:09 PM PDT 24
Finished Aug 09 05:23:14 PM PDT 24
Peak memory 207996 kb
Host smart-e1408462-f9e7-4c81-a617-ea33a64db015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516405606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.516405606
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.930820464
Short name T295
Test name
Test status
Simulation time 1328344642 ps
CPU time 4.39 seconds
Started Aug 09 05:23:13 PM PDT 24
Finished Aug 09 05:23:18 PM PDT 24
Peak memory 206832 kb
Host smart-ad353eb2-233f-46e8-9617-71c126bbefa2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930820464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.930820464
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.689188767
Short name T313
Test name
Test status
Simulation time 5759680876 ps
CPU time 32.32 seconds
Started Aug 09 05:23:12 PM PDT 24
Finished Aug 09 05:23:44 PM PDT 24
Peak memory 208116 kb
Host smart-9e90d209-7a5b-4b8f-bb74-944442136741
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689188767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.689188767
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2212178960
Short name T872
Test name
Test status
Simulation time 1383780867 ps
CPU time 24.75 seconds
Started Aug 09 05:23:10 PM PDT 24
Finished Aug 09 05:23:35 PM PDT 24
Peak memory 208972 kb
Host smart-130e4fe5-8105-49ce-801e-34a4e265d8eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212178960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2212178960
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.281827275
Short name T482
Test name
Test status
Simulation time 191090420 ps
CPU time 2.61 seconds
Started Aug 09 05:23:15 PM PDT 24
Finished Aug 09 05:23:17 PM PDT 24
Peak memory 209520 kb
Host smart-25097389-7c5a-4209-b059-f1ad1eba6c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281827275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.281827275
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4260680690
Short name T422
Test name
Test status
Simulation time 4970574784 ps
CPU time 41.11 seconds
Started Aug 09 05:23:10 PM PDT 24
Finished Aug 09 05:23:51 PM PDT 24
Peak memory 208096 kb
Host smart-b2726c5d-f938-40b4-a950-a9fab83977b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260680690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4260680690
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3370990699
Short name T625
Test name
Test status
Simulation time 14643408129 ps
CPU time 54.9 seconds
Started Aug 09 05:23:16 PM PDT 24
Finished Aug 09 05:24:11 PM PDT 24
Peak memory 222336 kb
Host smart-46f0f89d-6450-4169-955c-ec9d4b4a517b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370990699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3370990699
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2566171873
Short name T69
Test name
Test status
Simulation time 506720284 ps
CPU time 17.11 seconds
Started Aug 09 05:23:20 PM PDT 24
Finished Aug 09 05:23:37 PM PDT 24
Peak memory 222488 kb
Host smart-8f97b8f5-14e2-4b25-b5e3-4ced582648cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566171873 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2566171873
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1117877323
Short name T461
Test name
Test status
Simulation time 141731334 ps
CPU time 2.82 seconds
Started Aug 09 05:23:16 PM PDT 24
Finished Aug 09 05:23:19 PM PDT 24
Peak memory 207624 kb
Host smart-c43d0616-c3f7-4a9d-9fe4-84adda937bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117877323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1117877323
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1819381547
Short name T453
Test name
Test status
Simulation time 199022773 ps
CPU time 3.63 seconds
Started Aug 09 05:23:19 PM PDT 24
Finished Aug 09 05:23:22 PM PDT 24
Peak memory 210200 kb
Host smart-d75fe325-336f-4e36-8a39-c459c7a3c461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819381547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1819381547
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2218760511
Short name T450
Test name
Test status
Simulation time 43040611 ps
CPU time 0.83 seconds
Started Aug 09 05:23:18 PM PDT 24
Finished Aug 09 05:23:19 PM PDT 24
Peak memory 205856 kb
Host smart-fa1913c5-3c95-4e8c-ab07-064d84748cee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218760511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2218760511
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.4030934706
Short name T128
Test name
Test status
Simulation time 396542044 ps
CPU time 2.73 seconds
Started Aug 09 05:23:18 PM PDT 24
Finished Aug 09 05:23:20 PM PDT 24
Peak memory 215392 kb
Host smart-8d61f124-eb3f-4538-9c1c-921ba7d9cf67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4030934706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.4030934706
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3143900775
Short name T26
Test name
Test status
Simulation time 7041143241 ps
CPU time 19.22 seconds
Started Aug 09 05:23:21 PM PDT 24
Finished Aug 09 05:23:40 PM PDT 24
Peak memory 222520 kb
Host smart-fd24f22d-38b5-4e8a-8f66-5bba7814f6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143900775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3143900775
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1372676555
Short name T247
Test name
Test status
Simulation time 93262025 ps
CPU time 3.29 seconds
Started Aug 09 05:23:17 PM PDT 24
Finished Aug 09 05:23:20 PM PDT 24
Peak memory 207836 kb
Host smart-beb503e7-2a33-436a-a17c-5f210e4f78b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372676555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1372676555
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3510586679
Short name T98
Test name
Test status
Simulation time 204979052 ps
CPU time 4.9 seconds
Started Aug 09 05:23:15 PM PDT 24
Finished Aug 09 05:23:20 PM PDT 24
Peak memory 214292 kb
Host smart-c10d68ca-c552-43a4-8a4f-c00fb9945580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510586679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3510586679
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.973768807
Short name T282
Test name
Test status
Simulation time 104596489 ps
CPU time 3.01 seconds
Started Aug 09 05:23:14 PM PDT 24
Finished Aug 09 05:23:17 PM PDT 24
Peak memory 214188 kb
Host smart-c0b5fba4-4064-4831-aca7-2158180b8d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973768807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.973768807
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1625805204
Short name T60
Test name
Test status
Simulation time 278507811 ps
CPU time 5.38 seconds
Started Aug 09 05:23:15 PM PDT 24
Finished Aug 09 05:23:20 PM PDT 24
Peak memory 222372 kb
Host smart-2ca60a36-8acf-49f4-9a94-9ba3cc40b919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625805204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1625805204
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.979777220
Short name T913
Test name
Test status
Simulation time 140965690 ps
CPU time 3.65 seconds
Started Aug 09 05:23:16 PM PDT 24
Finished Aug 09 05:23:20 PM PDT 24
Peak memory 207332 kb
Host smart-953ca2c4-2053-4a2f-867c-856acf30c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979777220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.979777220
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.591207435
Short name T193
Test name
Test status
Simulation time 768556500 ps
CPU time 12.85 seconds
Started Aug 09 05:23:16 PM PDT 24
Finished Aug 09 05:23:29 PM PDT 24
Peak memory 208844 kb
Host smart-2150637f-20fa-4255-9baf-48fb06b386c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591207435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.591207435
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.602107094
Short name T305
Test name
Test status
Simulation time 201339218 ps
CPU time 4.65 seconds
Started Aug 09 05:23:15 PM PDT 24
Finished Aug 09 05:23:20 PM PDT 24
Peak memory 208728 kb
Host smart-6730988f-0c2d-4f6f-96b2-531f4d23d342
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602107094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.602107094
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.429065603
Short name T856
Test name
Test status
Simulation time 210714854 ps
CPU time 2.84 seconds
Started Aug 09 05:23:15 PM PDT 24
Finished Aug 09 05:23:18 PM PDT 24
Peak memory 206900 kb
Host smart-c7670dab-7e4a-47b9-aa69-273267157a97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429065603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.429065603
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3323848913
Short name T707
Test name
Test status
Simulation time 34052518 ps
CPU time 2.37 seconds
Started Aug 09 05:23:14 PM PDT 24
Finished Aug 09 05:23:16 PM PDT 24
Peak memory 206944 kb
Host smart-6e286dbd-5c12-4d4c-9bb0-724149d54305
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323848913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3323848913
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2324970512
Short name T721
Test name
Test status
Simulation time 196287542 ps
CPU time 5.28 seconds
Started Aug 09 05:23:16 PM PDT 24
Finished Aug 09 05:23:21 PM PDT 24
Peak memory 214304 kb
Host smart-4671480d-5368-4a3c-8323-7e7404359d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324970512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2324970512
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2522772226
Short name T17
Test name
Test status
Simulation time 71642796 ps
CPU time 2.88 seconds
Started Aug 09 05:23:15 PM PDT 24
Finished Aug 09 05:23:18 PM PDT 24
Peak memory 207884 kb
Host smart-129782d4-5f5d-4ecd-ad56-00e2e5d6cd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522772226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2522772226
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2285096662
Short name T878
Test name
Test status
Simulation time 559367420 ps
CPU time 23.55 seconds
Started Aug 09 05:23:13 PM PDT 24
Finished Aug 09 05:23:37 PM PDT 24
Peak memory 222424 kb
Host smart-ad87ae1b-c46c-4627-87b6-cd7c17d556f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285096662 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2285096662
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3466052524
Short name T699
Test name
Test status
Simulation time 773559873 ps
CPU time 6.37 seconds
Started Aug 09 05:23:21 PM PDT 24
Finished Aug 09 05:23:27 PM PDT 24
Peak memory 209508 kb
Host smart-74d13690-e7e9-4c83-aa4b-5785ebfe2cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466052524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3466052524
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.42066834
Short name T120
Test name
Test status
Simulation time 224387143 ps
CPU time 3.42 seconds
Started Aug 09 05:23:18 PM PDT 24
Finished Aug 09 05:23:21 PM PDT 24
Peak memory 209944 kb
Host smart-48e87688-0023-4588-9a5e-5072c486a281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42066834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.42066834
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.208541272
Short name T444
Test name
Test status
Simulation time 30414065 ps
CPU time 0.75 seconds
Started Aug 09 05:23:23 PM PDT 24
Finished Aug 09 05:23:24 PM PDT 24
Peak memory 205888 kb
Host smart-b800fe7f-9bb5-4997-b1af-7878f2b12445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208541272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.208541272
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3640365002
Short name T385
Test name
Test status
Simulation time 170420597 ps
CPU time 3.45 seconds
Started Aug 09 05:23:23 PM PDT 24
Finished Aug 09 05:23:26 PM PDT 24
Peak memory 214512 kb
Host smart-30df9596-70f1-451d-998b-a25880a96ae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640365002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3640365002
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1462465775
Short name T20
Test name
Test status
Simulation time 224348697 ps
CPU time 2.7 seconds
Started Aug 09 05:23:22 PM PDT 24
Finished Aug 09 05:23:25 PM PDT 24
Peak memory 209988 kb
Host smart-2cd0d3d6-a357-4eb7-8ac2-2363de2fd5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462465775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1462465775
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1984734548
Short name T79
Test name
Test status
Simulation time 43391680 ps
CPU time 2.34 seconds
Started Aug 09 05:23:20 PM PDT 24
Finished Aug 09 05:23:22 PM PDT 24
Peak memory 209252 kb
Host smart-0da2608c-712a-4bb9-83f0-f13ddd79de33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984734548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1984734548
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.798347007
Short name T376
Test name
Test status
Simulation time 1985737680 ps
CPU time 5.52 seconds
Started Aug 09 05:23:20 PM PDT 24
Finished Aug 09 05:23:25 PM PDT 24
Peak memory 214208 kb
Host smart-accf54c6-22ca-4ee8-aa7d-c42389f624d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798347007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.798347007
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3818791212
Short name T725
Test name
Test status
Simulation time 78828720 ps
CPU time 2.88 seconds
Started Aug 09 05:23:23 PM PDT 24
Finished Aug 09 05:23:26 PM PDT 24
Peak memory 214276 kb
Host smart-88483475-9a41-4a60-85cc-c0aae4b16c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818791212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3818791212
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.109012731
Short name T702
Test name
Test status
Simulation time 148874409 ps
CPU time 2.63 seconds
Started Aug 09 05:23:21 PM PDT 24
Finished Aug 09 05:23:24 PM PDT 24
Peak memory 217516 kb
Host smart-65bf9b83-a01c-4ba9-8be7-63ccc9a5099e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109012731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.109012731
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2767153235
Short name T552
Test name
Test status
Simulation time 13254300125 ps
CPU time 37.24 seconds
Started Aug 09 05:23:20 PM PDT 24
Finished Aug 09 05:23:58 PM PDT 24
Peak memory 208812 kb
Host smart-c9c599f9-0d0c-4f1d-81c1-06a5ff053b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767153235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2767153235
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.520668309
Short name T696
Test name
Test status
Simulation time 47783860 ps
CPU time 2.57 seconds
Started Aug 09 05:23:21 PM PDT 24
Finished Aug 09 05:23:24 PM PDT 24
Peak memory 208000 kb
Host smart-771fcb74-a238-44ca-aa3f-944905fd4169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520668309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.520668309
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3288992041
Short name T202
Test name
Test status
Simulation time 254944651 ps
CPU time 2.95 seconds
Started Aug 09 05:23:20 PM PDT 24
Finished Aug 09 05:23:24 PM PDT 24
Peak memory 206996 kb
Host smart-743588e8-3716-4e18-a2a9-98c24845cec8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288992041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3288992041
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4218644303
Short name T587
Test name
Test status
Simulation time 273950508 ps
CPU time 4.46 seconds
Started Aug 09 05:23:24 PM PDT 24
Finished Aug 09 05:23:28 PM PDT 24
Peak memory 206844 kb
Host smart-853bb13d-199c-40c9-bccd-d3db7309e7d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218644303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4218644303
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3225376936
Short name T770
Test name
Test status
Simulation time 204556541 ps
CPU time 2.87 seconds
Started Aug 09 05:23:21 PM PDT 24
Finished Aug 09 05:23:24 PM PDT 24
Peak memory 206928 kb
Host smart-bbc2c77a-8108-454e-ae21-3fa6a1a42a3b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225376936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3225376936
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1791636942
Short name T270
Test name
Test status
Simulation time 75201527 ps
CPU time 2.24 seconds
Started Aug 09 05:23:22 PM PDT 24
Finished Aug 09 05:23:24 PM PDT 24
Peak memory 208644 kb
Host smart-fb49bb7e-ae5f-4af6-a1b3-1b4c395f1a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791636942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1791636942
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.926447657
Short name T689
Test name
Test status
Simulation time 5962519783 ps
CPU time 47.6 seconds
Started Aug 09 05:23:17 PM PDT 24
Finished Aug 09 05:24:04 PM PDT 24
Peak memory 208140 kb
Host smart-b924bedd-9b9a-463c-87da-8ac06ffe7861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926447657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.926447657
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2755633448
Short name T331
Test name
Test status
Simulation time 110516276 ps
CPU time 2.47 seconds
Started Aug 09 05:23:25 PM PDT 24
Finished Aug 09 05:23:27 PM PDT 24
Peak memory 208344 kb
Host smart-dcbbcb0d-fc5b-40e1-b67a-148a6e934bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755633448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2755633448
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1379580301
Short name T57
Test name
Test status
Simulation time 34689196 ps
CPU time 2.31 seconds
Started Aug 09 05:23:21 PM PDT 24
Finished Aug 09 05:23:24 PM PDT 24
Peak memory 210288 kb
Host smart-e0db4232-0b29-4a54-a6c5-4de7c297b495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379580301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1379580301
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3726773384
Short name T430
Test name
Test status
Simulation time 29208234 ps
CPU time 0.73 seconds
Started Aug 09 05:23:27 PM PDT 24
Finished Aug 09 05:23:28 PM PDT 24
Peak memory 205884 kb
Host smart-e324c5be-690e-4624-8dc3-d0d72a2c6c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726773384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3726773384
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3255170814
Short name T911
Test name
Test status
Simulation time 106433994 ps
CPU time 2.39 seconds
Started Aug 09 05:23:23 PM PDT 24
Finished Aug 09 05:23:26 PM PDT 24
Peak memory 214176 kb
Host smart-1a636057-ffc8-4856-873b-8592d4c3f91b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255170814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3255170814
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.131675182
Short name T614
Test name
Test status
Simulation time 228456692 ps
CPU time 2.78 seconds
Started Aug 09 05:23:23 PM PDT 24
Finished Aug 09 05:23:26 PM PDT 24
Peak memory 214272 kb
Host smart-b8c0d55a-d466-4e0b-8219-4d33254e7c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131675182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.131675182
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3488650963
Short name T654
Test name
Test status
Simulation time 228591976 ps
CPU time 4.35 seconds
Started Aug 09 05:23:22 PM PDT 24
Finished Aug 09 05:23:26 PM PDT 24
Peak memory 214300 kb
Host smart-eacaeeff-c28b-43a4-bb3f-1904238c9ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488650963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3488650963
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1539305240
Short name T851
Test name
Test status
Simulation time 35669506 ps
CPU time 2.85 seconds
Started Aug 09 05:23:25 PM PDT 24
Finished Aug 09 05:23:28 PM PDT 24
Peak memory 214240 kb
Host smart-be95f158-2308-4804-a915-5149223dc8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539305240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1539305240
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2010704881
Short name T253
Test name
Test status
Simulation time 77673020 ps
CPU time 3.07 seconds
Started Aug 09 05:23:24 PM PDT 24
Finished Aug 09 05:23:27 PM PDT 24
Peak memory 214176 kb
Host smart-bc80e6f6-a863-4bb9-867c-128db5b20418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010704881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2010704881
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2559796985
Short name T509
Test name
Test status
Simulation time 138552427 ps
CPU time 3.2 seconds
Started Aug 09 05:23:21 PM PDT 24
Finished Aug 09 05:23:24 PM PDT 24
Peak memory 214352 kb
Host smart-da84fc38-2ed0-4670-a6d3-5a9e68b62931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559796985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2559796985
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.494689874
Short name T762
Test name
Test status
Simulation time 92161369 ps
CPU time 3.17 seconds
Started Aug 09 05:23:21 PM PDT 24
Finished Aug 09 05:23:24 PM PDT 24
Peak memory 207968 kb
Host smart-797c6e5f-6945-4295-96af-5f24eb5b93d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494689874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.494689874
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.245753207
Short name T307
Test name
Test status
Simulation time 79320230 ps
CPU time 2.88 seconds
Started Aug 09 05:23:23 PM PDT 24
Finished Aug 09 05:23:26 PM PDT 24
Peak memory 206892 kb
Host smart-91810726-b13f-4474-94a9-27195dcf5eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245753207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.245753207
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1653606341
Short name T607
Test name
Test status
Simulation time 65980253 ps
CPU time 3.18 seconds
Started Aug 09 05:23:22 PM PDT 24
Finished Aug 09 05:23:26 PM PDT 24
Peak memory 208648 kb
Host smart-c054d0be-56f8-4442-90c8-168a25836d59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653606341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1653606341
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2886214330
Short name T588
Test name
Test status
Simulation time 232549527 ps
CPU time 2.66 seconds
Started Aug 09 05:23:20 PM PDT 24
Finished Aug 09 05:23:23 PM PDT 24
Peak memory 208904 kb
Host smart-cfb60a55-c519-4943-bfba-32cb9ef51257
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886214330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2886214330
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3155325598
Short name T761
Test name
Test status
Simulation time 917238610 ps
CPU time 3.63 seconds
Started Aug 09 05:23:28 PM PDT 24
Finished Aug 09 05:23:32 PM PDT 24
Peak memory 207264 kb
Host smart-ba172ccd-0c2b-4993-bbd5-7b327e1bcd21
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155325598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3155325598
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2837560540
Short name T785
Test name
Test status
Simulation time 119459580 ps
CPU time 3.54 seconds
Started Aug 09 05:23:23 PM PDT 24
Finished Aug 09 05:23:27 PM PDT 24
Peak memory 209152 kb
Host smart-190e6e25-5df9-4aae-9313-5ddd874261d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837560540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2837560540
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1539010062
Short name T814
Test name
Test status
Simulation time 62371032 ps
CPU time 2.51 seconds
Started Aug 09 05:23:22 PM PDT 24
Finished Aug 09 05:23:25 PM PDT 24
Peak memory 207176 kb
Host smart-67285755-4b40-4df7-915f-26672f88e6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539010062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1539010062
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1780252664
Short name T354
Test name
Test status
Simulation time 684982313 ps
CPU time 11.6 seconds
Started Aug 09 05:23:20 PM PDT 24
Finished Aug 09 05:23:32 PM PDT 24
Peak memory 222408 kb
Host smart-52895911-9297-467d-b903-6e2fbc8131bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780252664 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1780252664
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1461427702
Short name T199
Test name
Test status
Simulation time 1447949648 ps
CPU time 28.84 seconds
Started Aug 09 05:23:27 PM PDT 24
Finished Aug 09 05:23:56 PM PDT 24
Peak memory 209316 kb
Host smart-fdebd362-694f-40be-b8fb-8e0a27a17af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461427702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1461427702
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3890931919
Short name T558
Test name
Test status
Simulation time 133628254 ps
CPU time 1.86 seconds
Started Aug 09 05:23:27 PM PDT 24
Finished Aug 09 05:23:29 PM PDT 24
Peak memory 209816 kb
Host smart-9d3761b2-e227-4835-953e-14f44dabe84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890931919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3890931919
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.498916326
Short name T488
Test name
Test status
Simulation time 53320616 ps
CPU time 0.87 seconds
Started Aug 09 05:23:25 PM PDT 24
Finished Aug 09 05:23:26 PM PDT 24
Peak memory 205956 kb
Host smart-94ef0654-3328-489b-9bb2-704c29a18c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498916326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.498916326
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3435905514
Short name T312
Test name
Test status
Simulation time 39885984 ps
CPU time 2.97 seconds
Started Aug 09 05:23:27 PM PDT 24
Finished Aug 09 05:23:30 PM PDT 24
Peak memory 214704 kb
Host smart-d2116a6c-3c9d-4a04-85c2-48270fe2a488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435905514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3435905514
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.826833611
Short name T907
Test name
Test status
Simulation time 286439652 ps
CPU time 3.26 seconds
Started Aug 09 05:23:27 PM PDT 24
Finished Aug 09 05:23:31 PM PDT 24
Peak memory 210124 kb
Host smart-cd2ab9d6-22fd-4155-8640-31b610f7299c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826833611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.826833611
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2929619153
Short name T632
Test name
Test status
Simulation time 958206639 ps
CPU time 28.05 seconds
Started Aug 09 05:23:27 PM PDT 24
Finished Aug 09 05:23:55 PM PDT 24
Peak memory 214312 kb
Host smart-09fd92ba-74dc-4b78-a445-d2c00145e71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929619153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2929619153
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1771313017
Short name T235
Test name
Test status
Simulation time 326880735 ps
CPU time 2.86 seconds
Started Aug 09 05:23:27 PM PDT 24
Finished Aug 09 05:23:30 PM PDT 24
Peak memory 220344 kb
Host smart-66040423-05e2-45a2-ae7f-21234991d9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771313017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1771313017
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1091036441
Short name T593
Test name
Test status
Simulation time 280003734 ps
CPU time 3.15 seconds
Started Aug 09 05:23:28 PM PDT 24
Finished Aug 09 05:23:31 PM PDT 24
Peak memory 207468 kb
Host smart-f069867c-64ec-4308-a3e7-d1276422d767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091036441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1091036441
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.768384781
Short name T613
Test name
Test status
Simulation time 824570244 ps
CPU time 4.45 seconds
Started Aug 09 05:23:23 PM PDT 24
Finished Aug 09 05:23:28 PM PDT 24
Peak memory 208160 kb
Host smart-fdc877a6-087d-4981-b79a-0e30775b9996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768384781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.768384781
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2487130189
Short name T464
Test name
Test status
Simulation time 86336847 ps
CPU time 1.95 seconds
Started Aug 09 05:23:22 PM PDT 24
Finished Aug 09 05:23:24 PM PDT 24
Peak memory 206940 kb
Host smart-3b185bec-d200-415a-a766-d521eb74cec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487130189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2487130189
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.78119330
Short name T362
Test name
Test status
Simulation time 391777484 ps
CPU time 8.08 seconds
Started Aug 09 05:23:26 PM PDT 24
Finished Aug 09 05:23:34 PM PDT 24
Peak memory 208644 kb
Host smart-ec532308-fe60-4fb3-b174-e491df1398a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78119330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.78119330
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3005752085
Short name T274
Test name
Test status
Simulation time 106839824 ps
CPU time 2.36 seconds
Started Aug 09 05:23:26 PM PDT 24
Finished Aug 09 05:23:28 PM PDT 24
Peak memory 206896 kb
Host smart-6882c0a3-06fc-4030-a515-321295d55241
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005752085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3005752085
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3682093783
Short name T531
Test name
Test status
Simulation time 43470879 ps
CPU time 2.53 seconds
Started Aug 09 05:23:28 PM PDT 24
Finished Aug 09 05:23:30 PM PDT 24
Peak memory 208152 kb
Host smart-b9e3df5f-c55f-44f0-b313-f8c02a57a35c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682093783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3682093783
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1414305224
Short name T34
Test name
Test status
Simulation time 32453836 ps
CPU time 2.5 seconds
Started Aug 09 05:23:28 PM PDT 24
Finished Aug 09 05:23:31 PM PDT 24
Peak memory 210328 kb
Host smart-d8e2d45b-ca98-48d9-88cf-1bdbb3216788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414305224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1414305224
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2899271078
Short name T746
Test name
Test status
Simulation time 84695070 ps
CPU time 2.47 seconds
Started Aug 09 05:23:23 PM PDT 24
Finished Aug 09 05:23:26 PM PDT 24
Peak memory 206684 kb
Host smart-2233894b-b569-47d5-b190-917164beb360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899271078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2899271078
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.724544677
Short name T515
Test name
Test status
Simulation time 1359709121 ps
CPU time 33.69 seconds
Started Aug 09 05:23:28 PM PDT 24
Finished Aug 09 05:24:02 PM PDT 24
Peak memory 221808 kb
Host smart-3948ae91-1ec4-49a5-afe9-4798689efcea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724544677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.724544677
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1866790556
Short name T537
Test name
Test status
Simulation time 1086051222 ps
CPU time 6.38 seconds
Started Aug 09 05:23:26 PM PDT 24
Finished Aug 09 05:23:33 PM PDT 24
Peak memory 208140 kb
Host smart-deda0bc4-53b7-4c43-a944-3f35c87da545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866790556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1866790556
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4226710564
Short name T55
Test name
Test status
Simulation time 3201928900 ps
CPU time 19 seconds
Started Aug 09 05:23:27 PM PDT 24
Finished Aug 09 05:23:46 PM PDT 24
Peak memory 211296 kb
Host smart-461bf1d3-96d1-4af0-be95-3b5a0f19d844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226710564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4226710564
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2794333599
Short name T425
Test name
Test status
Simulation time 29494641 ps
CPU time 0.73 seconds
Started Aug 09 05:23:34 PM PDT 24
Finished Aug 09 05:23:35 PM PDT 24
Peak memory 205848 kb
Host smart-b86e2fa7-d432-474c-a03d-e1f499e08b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794333599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2794333599
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.928069962
Short name T413
Test name
Test status
Simulation time 83417118 ps
CPU time 5.16 seconds
Started Aug 09 05:23:28 PM PDT 24
Finished Aug 09 05:23:33 PM PDT 24
Peak memory 214360 kb
Host smart-5b150bdf-aab7-46e3-934c-778b3a68e73f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928069962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.928069962
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3344189801
Short name T839
Test name
Test status
Simulation time 206067438 ps
CPU time 3.03 seconds
Started Aug 09 05:23:32 PM PDT 24
Finished Aug 09 05:23:35 PM PDT 24
Peak memory 214408 kb
Host smart-efcc9e85-bb0d-408c-91d8-2690aa71d840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344189801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3344189801
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2335533468
Short name T317
Test name
Test status
Simulation time 123379250 ps
CPU time 1.92 seconds
Started Aug 09 05:23:26 PM PDT 24
Finished Aug 09 05:23:28 PM PDT 24
Peak memory 207308 kb
Host smart-994ecd68-db60-448b-83e6-bf94166fb616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335533468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2335533468
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3825096281
Short name T299
Test name
Test status
Simulation time 109812110 ps
CPU time 2.4 seconds
Started Aug 09 05:23:26 PM PDT 24
Finished Aug 09 05:23:28 PM PDT 24
Peak memory 222244 kb
Host smart-317e540b-9a75-4633-b358-e820bf68f151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825096281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3825096281
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2238235620
Short name T64
Test name
Test status
Simulation time 119412167 ps
CPU time 4.55 seconds
Started Aug 09 05:23:32 PM PDT 24
Finished Aug 09 05:23:36 PM PDT 24
Peak memory 220240 kb
Host smart-5df6609c-bc17-4fe9-b421-124fcb9595c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238235620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2238235620
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.738678888
Short name T124
Test name
Test status
Simulation time 256555169 ps
CPU time 4.44 seconds
Started Aug 09 05:23:27 PM PDT 24
Finished Aug 09 05:23:32 PM PDT 24
Peak memory 208204 kb
Host smart-3f32b55e-3006-4f50-bb09-1073f49dde96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738678888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.738678888
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1023408543
Short name T858
Test name
Test status
Simulation time 351766656 ps
CPU time 3.56 seconds
Started Aug 09 05:23:26 PM PDT 24
Finished Aug 09 05:23:30 PM PDT 24
Peak memory 208712 kb
Host smart-2f9d7ace-aa25-4495-b2c9-5e70ee3a86c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023408543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1023408543
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1266033972
Short name T83
Test name
Test status
Simulation time 528729672 ps
CPU time 5.37 seconds
Started Aug 09 05:23:28 PM PDT 24
Finished Aug 09 05:23:34 PM PDT 24
Peak memory 207960 kb
Host smart-6c46ae60-c0f0-4be7-aecf-08d4947daf86
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266033972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1266033972
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.383355569
Short name T571
Test name
Test status
Simulation time 50441515 ps
CPU time 2.74 seconds
Started Aug 09 05:23:27 PM PDT 24
Finished Aug 09 05:23:30 PM PDT 24
Peak memory 208352 kb
Host smart-b28febfd-9c7e-493e-904d-2b27af626607
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383355569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.383355569
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2871672668
Short name T335
Test name
Test status
Simulation time 38345078 ps
CPU time 2.29 seconds
Started Aug 09 05:23:26 PM PDT 24
Finished Aug 09 05:23:28 PM PDT 24
Peak memory 207104 kb
Host smart-a777bf40-6f34-4aeb-b786-9da8fde7ec2e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871672668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2871672668
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1537268437
Short name T684
Test name
Test status
Simulation time 551578042 ps
CPU time 4.76 seconds
Started Aug 09 05:23:26 PM PDT 24
Finished Aug 09 05:23:31 PM PDT 24
Peak memory 209520 kb
Host smart-5f247b5d-726e-4435-9165-ae5b0af6640a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537268437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1537268437
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.812996533
Short name T767
Test name
Test status
Simulation time 712322399 ps
CPU time 6.5 seconds
Started Aug 09 05:23:26 PM PDT 24
Finished Aug 09 05:23:32 PM PDT 24
Peak memory 207820 kb
Host smart-506090f0-d50e-4691-b02f-f9ec05ac7fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812996533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.812996533
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3478417464
Short name T370
Test name
Test status
Simulation time 218343385 ps
CPU time 6.04 seconds
Started Aug 09 05:23:25 PM PDT 24
Finished Aug 09 05:23:31 PM PDT 24
Peak memory 209152 kb
Host smart-9f524057-3d0d-4d69-a3d3-ef16b8f24c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478417464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3478417464
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.236262276
Short name T895
Test name
Test status
Simulation time 32056637 ps
CPU time 2.03 seconds
Started Aug 09 05:23:27 PM PDT 24
Finished Aug 09 05:23:30 PM PDT 24
Peak memory 209824 kb
Host smart-7490cf19-925b-46c0-bd08-98fbc3cd9bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236262276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.236262276
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2066284869
Short name T674
Test name
Test status
Simulation time 13867347 ps
CPU time 0.86 seconds
Started Aug 09 05:23:35 PM PDT 24
Finished Aug 09 05:23:36 PM PDT 24
Peak memory 205864 kb
Host smart-b2db472b-b31b-4cee-8dac-d67e75814486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066284869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2066284869
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1053789412
Short name T619
Test name
Test status
Simulation time 131490640 ps
CPU time 2.97 seconds
Started Aug 09 05:23:33 PM PDT 24
Finished Aug 09 05:23:36 PM PDT 24
Peak memory 209500 kb
Host smart-4c6d658a-8c15-4f6f-a704-4bff65cd135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053789412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1053789412
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3713314133
Short name T700
Test name
Test status
Simulation time 511476883 ps
CPU time 5.78 seconds
Started Aug 09 05:23:35 PM PDT 24
Finished Aug 09 05:23:41 PM PDT 24
Peak memory 209612 kb
Host smart-74156db9-1657-4f61-9b22-1512a6941769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713314133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3713314133
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.929799832
Short name T319
Test name
Test status
Simulation time 81139458 ps
CPU time 3.68 seconds
Started Aug 09 05:23:35 PM PDT 24
Finished Aug 09 05:23:39 PM PDT 24
Peak memory 222364 kb
Host smart-dcd5d909-44c0-4b3b-829b-af9b6e700c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929799832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.929799832
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2482459283
Short name T527
Test name
Test status
Simulation time 244044878 ps
CPU time 5.46 seconds
Started Aug 09 05:23:34 PM PDT 24
Finished Aug 09 05:23:40 PM PDT 24
Peak memory 220344 kb
Host smart-e649d947-79b0-4ffd-8a5a-7ae0aca55803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482459283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2482459283
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3292732573
Short name T771
Test name
Test status
Simulation time 736367321 ps
CPU time 19.88 seconds
Started Aug 09 05:23:34 PM PDT 24
Finished Aug 09 05:23:54 PM PDT 24
Peak memory 209224 kb
Host smart-da1ece38-4bf7-4734-b2c1-5e72432df283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292732573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3292732573
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3701185649
Short name T497
Test name
Test status
Simulation time 73292771 ps
CPU time 1.76 seconds
Started Aug 09 05:23:33 PM PDT 24
Finished Aug 09 05:23:35 PM PDT 24
Peak memory 206912 kb
Host smart-5a69c807-e3ed-49f1-9bce-9a12eaf6b2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701185649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3701185649
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1393597437
Short name T368
Test name
Test status
Simulation time 56520289 ps
CPU time 2.9 seconds
Started Aug 09 05:23:31 PM PDT 24
Finished Aug 09 05:23:34 PM PDT 24
Peak memory 208156 kb
Host smart-d3330ff7-2b1c-4953-8d78-e3920600c859
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393597437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1393597437
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3870677500
Short name T744
Test name
Test status
Simulation time 182542785 ps
CPU time 2.49 seconds
Started Aug 09 05:23:36 PM PDT 24
Finished Aug 09 05:23:38 PM PDT 24
Peak memory 206856 kb
Host smart-f7fc7566-63d2-44d8-8964-8b007eccecf5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870677500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3870677500
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.203768613
Short name T540
Test name
Test status
Simulation time 109630946 ps
CPU time 2.84 seconds
Started Aug 09 05:23:33 PM PDT 24
Finished Aug 09 05:23:36 PM PDT 24
Peak memory 208528 kb
Host smart-a2259eb0-062a-41dc-aaf3-d260d5c6e356
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203768613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.203768613
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.781107099
Short name T456
Test name
Test status
Simulation time 72918285 ps
CPU time 2.34 seconds
Started Aug 09 05:23:32 PM PDT 24
Finished Aug 09 05:23:35 PM PDT 24
Peak memory 206716 kb
Host smart-fbeeb7b9-d292-41d9-9d1f-69f50ea209c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781107099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.781107099
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1024965190
Short name T570
Test name
Test status
Simulation time 106171143 ps
CPU time 3.02 seconds
Started Aug 09 05:23:34 PM PDT 24
Finished Aug 09 05:23:37 PM PDT 24
Peak memory 207996 kb
Host smart-965a5d77-3aea-45f7-887f-b5d8da2007af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024965190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1024965190
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1941127281
Short name T223
Test name
Test status
Simulation time 2292025496 ps
CPU time 22.98 seconds
Started Aug 09 05:23:33 PM PDT 24
Finished Aug 09 05:23:57 PM PDT 24
Peak memory 222476 kb
Host smart-a09ec048-152a-4b31-a7b5-2958a4f5f0b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941127281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1941127281
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1499478434
Short name T365
Test name
Test status
Simulation time 1346975354 ps
CPU time 20.78 seconds
Started Aug 09 05:23:33 PM PDT 24
Finished Aug 09 05:23:54 PM PDT 24
Peak memory 222484 kb
Host smart-123fdae6-7ab9-4208-a52e-2de8b19af1ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499478434 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1499478434
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2259280644
Short name T813
Test name
Test status
Simulation time 505982640 ps
CPU time 8.01 seconds
Started Aug 09 05:23:32 PM PDT 24
Finished Aug 09 05:23:40 PM PDT 24
Peak memory 209304 kb
Host smart-20ef5017-f44a-4eeb-9b3c-e0f2ddb499aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259280644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2259280644
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1484845288
Short name T58
Test name
Test status
Simulation time 204301684 ps
CPU time 4.09 seconds
Started Aug 09 05:23:33 PM PDT 24
Finished Aug 09 05:23:37 PM PDT 24
Peak memory 211076 kb
Host smart-6854fa09-c12d-40fb-8ec1-58da5c7e4d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484845288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1484845288
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.285733232
Short name T694
Test name
Test status
Simulation time 20573369 ps
CPU time 0.71 seconds
Started Aug 09 05:23:37 PM PDT 24
Finished Aug 09 05:23:38 PM PDT 24
Peak memory 205868 kb
Host smart-7180e2d9-e40d-4abc-b3c0-21374f26a89e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285733232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.285733232
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2728550859
Short name T8
Test name
Test status
Simulation time 147518770 ps
CPU time 2.74 seconds
Started Aug 09 05:23:34 PM PDT 24
Finished Aug 09 05:23:37 PM PDT 24
Peak memory 222436 kb
Host smart-88980d7d-3838-46da-89f7-0cdd6dcd330c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728550859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2728550859
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1870185412
Short name T731
Test name
Test status
Simulation time 207389970 ps
CPU time 2.42 seconds
Started Aug 09 05:23:33 PM PDT 24
Finished Aug 09 05:23:35 PM PDT 24
Peak memory 214312 kb
Host smart-b8034d53-57fb-4958-b17a-99089b434f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870185412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1870185412
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.617769871
Short name T874
Test name
Test status
Simulation time 8280059181 ps
CPU time 69.09 seconds
Started Aug 09 05:23:31 PM PDT 24
Finished Aug 09 05:24:41 PM PDT 24
Peak memory 214488 kb
Host smart-dd227b0c-d93a-4e00-b842-e0e104b78168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617769871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.617769871
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3141385996
Short name T62
Test name
Test status
Simulation time 643633210 ps
CPU time 5.34 seconds
Started Aug 09 05:23:35 PM PDT 24
Finished Aug 09 05:23:40 PM PDT 24
Peak memory 214188 kb
Host smart-b050a1a8-65ef-48e7-b743-d66fd1d5f4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141385996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3141385996
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2848517441
Short name T551
Test name
Test status
Simulation time 2031152482 ps
CPU time 17.9 seconds
Started Aug 09 05:23:33 PM PDT 24
Finished Aug 09 05:23:51 PM PDT 24
Peak memory 214400 kb
Host smart-d1ae69b8-dd0a-4d18-839f-b22c74475990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848517441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2848517441
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1113455706
Short name T476
Test name
Test status
Simulation time 101273486 ps
CPU time 3.23 seconds
Started Aug 09 05:23:36 PM PDT 24
Finished Aug 09 05:23:39 PM PDT 24
Peak memory 207676 kb
Host smart-8d70c700-dbec-436c-9f00-f2c7f200da15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113455706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1113455706
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3277863410
Short name T861
Test name
Test status
Simulation time 236806030 ps
CPU time 3.19 seconds
Started Aug 09 05:23:34 PM PDT 24
Finished Aug 09 05:23:38 PM PDT 24
Peak memory 207372 kb
Host smart-6118c9ef-1b66-466f-88de-39f8685ab7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277863410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3277863410
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.4193161289
Short name T801
Test name
Test status
Simulation time 405951563 ps
CPU time 2.47 seconds
Started Aug 09 05:23:33 PM PDT 24
Finished Aug 09 05:23:36 PM PDT 24
Peak memory 206780 kb
Host smart-7d1d0aa0-c63b-41a3-9ae4-ac72cbf17826
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193161289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.4193161289
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3916560066
Short name T886
Test name
Test status
Simulation time 89063397 ps
CPU time 2.96 seconds
Started Aug 09 05:23:35 PM PDT 24
Finished Aug 09 05:23:38 PM PDT 24
Peak memory 208932 kb
Host smart-8b568fe6-12e3-47a6-8dbf-d17f6146078a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916560066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3916560066
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1860635254
Short name T661
Test name
Test status
Simulation time 2603838302 ps
CPU time 19.39 seconds
Started Aug 09 05:23:35 PM PDT 24
Finished Aug 09 05:23:54 PM PDT 24
Peak memory 207900 kb
Host smart-7846cf5b-6bb8-49e8-8a8f-4f19fe84e8e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860635254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1860635254
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3424155094
Short name T803
Test name
Test status
Simulation time 51043373 ps
CPU time 2.6 seconds
Started Aug 09 05:23:39 PM PDT 24
Finished Aug 09 05:23:42 PM PDT 24
Peak memory 215292 kb
Host smart-172cda5c-321e-4c2f-a0de-0d2090fdbb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424155094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3424155094
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3569581192
Short name T606
Test name
Test status
Simulation time 246070509 ps
CPU time 2.87 seconds
Started Aug 09 05:23:35 PM PDT 24
Finished Aug 09 05:23:38 PM PDT 24
Peak memory 207104 kb
Host smart-14d10a68-2b66-4042-acd4-b61849f61bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569581192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3569581192
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1788687971
Short name T212
Test name
Test status
Simulation time 1986400072 ps
CPU time 45.61 seconds
Started Aug 09 05:23:38 PM PDT 24
Finished Aug 09 05:24:24 PM PDT 24
Peak memory 216196 kb
Host smart-bb11e03b-7ffc-4ece-8b87-bf43dcd80bc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788687971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1788687971
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2522928015
Short name T673
Test name
Test status
Simulation time 213112672 ps
CPU time 8.63 seconds
Started Aug 09 05:23:41 PM PDT 24
Finished Aug 09 05:23:50 PM PDT 24
Peak memory 222488 kb
Host smart-38230ffc-aef8-4381-b3cc-b4a22982eb67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522928015 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2522928015
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.922269145
Short name T200
Test name
Test status
Simulation time 57391544 ps
CPU time 2.27 seconds
Started Aug 09 05:23:35 PM PDT 24
Finished Aug 09 05:23:37 PM PDT 24
Peak memory 207352 kb
Host smart-fcd596e8-054d-4358-8550-6730f62f73eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922269145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.922269145
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.4245937643
Short name T921
Test name
Test status
Simulation time 757716106 ps
CPU time 11.74 seconds
Started Aug 09 05:23:39 PM PDT 24
Finished Aug 09 05:23:51 PM PDT 24
Peak memory 210448 kb
Host smart-353408cb-6391-4c2e-a92c-e5619e3cd324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245937643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.4245937643
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4205658016
Short name T756
Test name
Test status
Simulation time 14826519 ps
CPU time 0.78 seconds
Started Aug 09 05:23:38 PM PDT 24
Finished Aug 09 05:23:39 PM PDT 24
Peak memory 205928 kb
Host smart-89cd9588-95a3-4171-b454-27b209b1e420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205658016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4205658016
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2589639347
Short name T405
Test name
Test status
Simulation time 213391356 ps
CPU time 4.41 seconds
Started Aug 09 05:23:42 PM PDT 24
Finished Aug 09 05:23:46 PM PDT 24
Peak memory 215344 kb
Host smart-8721044e-782e-41b0-8e3e-9b2e0fa8c1f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2589639347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2589639347
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.638308129
Short name T479
Test name
Test status
Simulation time 303559263 ps
CPU time 2.27 seconds
Started Aug 09 05:23:41 PM PDT 24
Finished Aug 09 05:23:44 PM PDT 24
Peak memory 221360 kb
Host smart-7de85c72-9485-4e77-8b29-eeaa1a6532e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638308129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.638308129
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1797848776
Short name T246
Test name
Test status
Simulation time 176727587 ps
CPU time 2.29 seconds
Started Aug 09 05:23:39 PM PDT 24
Finished Aug 09 05:23:41 PM PDT 24
Peak memory 218140 kb
Host smart-f5293552-b32a-4300-b3b3-6e543601b311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797848776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1797848776
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1840425962
Short name T91
Test name
Test status
Simulation time 91736022 ps
CPU time 1.66 seconds
Started Aug 09 05:23:40 PM PDT 24
Finished Aug 09 05:23:42 PM PDT 24
Peak memory 214428 kb
Host smart-9aace302-0d53-406b-9481-26b703ea224b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840425962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1840425962
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3831782991
Short name T242
Test name
Test status
Simulation time 104461879 ps
CPU time 4.77 seconds
Started Aug 09 05:23:39 PM PDT 24
Finished Aug 09 05:23:43 PM PDT 24
Peak memory 222384 kb
Host smart-45a77e45-9b2f-44ba-b755-6d41c2ae8b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831782991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3831782991
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2683954103
Short name T402
Test name
Test status
Simulation time 972875929 ps
CPU time 7.48 seconds
Started Aug 09 05:23:37 PM PDT 24
Finished Aug 09 05:23:45 PM PDT 24
Peak memory 208408 kb
Host smart-fdaf64db-5336-43f9-a71e-78915b69b29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683954103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2683954103
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1144993642
Short name T391
Test name
Test status
Simulation time 3804380483 ps
CPU time 24.26 seconds
Started Aug 09 05:23:38 PM PDT 24
Finished Aug 09 05:24:03 PM PDT 24
Peak memory 208184 kb
Host smart-3c26393d-4758-4453-91b7-0cd628536851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144993642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1144993642
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.706334779
Short name T396
Test name
Test status
Simulation time 197033534 ps
CPU time 5.54 seconds
Started Aug 09 05:23:39 PM PDT 24
Finished Aug 09 05:23:44 PM PDT 24
Peak memory 208484 kb
Host smart-afc88320-c635-4f07-a7b1-29a04f68388a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706334779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.706334779
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.175893202
Short name T203
Test name
Test status
Simulation time 117091396 ps
CPU time 2.3 seconds
Started Aug 09 05:23:39 PM PDT 24
Finished Aug 09 05:23:41 PM PDT 24
Peak memory 206944 kb
Host smart-08784390-e273-42a7-afbe-99fa04d4caa8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175893202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.175893202
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1308860103
Short name T568
Test name
Test status
Simulation time 147944139 ps
CPU time 2.28 seconds
Started Aug 09 05:23:39 PM PDT 24
Finished Aug 09 05:23:41 PM PDT 24
Peak memory 207004 kb
Host smart-9d3be8c0-8386-41b4-9061-7012f67e7c17
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308860103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1308860103
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.881873037
Short name T724
Test name
Test status
Simulation time 575888919 ps
CPU time 2.37 seconds
Started Aug 09 05:23:38 PM PDT 24
Finished Aug 09 05:23:40 PM PDT 24
Peak memory 215528 kb
Host smart-cdcb9557-6e01-4c39-a498-b970b55981a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881873037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.881873037
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2951664462
Short name T655
Test name
Test status
Simulation time 5230412188 ps
CPU time 45.89 seconds
Started Aug 09 05:23:38 PM PDT 24
Finished Aug 09 05:24:24 PM PDT 24
Peak memory 208752 kb
Host smart-fd769023-b731-4a63-a2a6-69e4ab2fec11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951664462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2951664462
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.517998131
Short name T173
Test name
Test status
Simulation time 300608655 ps
CPU time 11.2 seconds
Started Aug 09 05:23:44 PM PDT 24
Finished Aug 09 05:23:55 PM PDT 24
Peak memory 222736 kb
Host smart-1068f918-e57f-4aad-af4e-1bf8db8409a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517998131 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.517998131
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3341867310
Short name T336
Test name
Test status
Simulation time 4547422434 ps
CPU time 61.83 seconds
Started Aug 09 05:23:39 PM PDT 24
Finished Aug 09 05:24:41 PM PDT 24
Peak memory 222360 kb
Host smart-460057ac-14c7-40ef-9f8d-3607116d93d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341867310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3341867310
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.798884835
Short name T545
Test name
Test status
Simulation time 186062774 ps
CPU time 2.52 seconds
Started Aug 09 05:23:38 PM PDT 24
Finished Aug 09 05:23:40 PM PDT 24
Peak memory 210176 kb
Host smart-16a004a6-bd54-4cfa-a045-084f93250d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798884835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.798884835
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.716334957
Short name T495
Test name
Test status
Simulation time 65467169 ps
CPU time 0.85 seconds
Started Aug 09 05:21:22 PM PDT 24
Finished Aug 09 05:21:22 PM PDT 24
Peak memory 205836 kb
Host smart-3234d584-36e8-4d57-b4a6-9359b45e179b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716334957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.716334957
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.544195450
Short name T291
Test name
Test status
Simulation time 110308679 ps
CPU time 5.77 seconds
Started Aug 09 05:21:24 PM PDT 24
Finished Aug 09 05:21:30 PM PDT 24
Peak memory 215456 kb
Host smart-0af9de37-dd3f-4043-9cdb-ef63f2169b25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544195450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.544195450
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3988860876
Short name T602
Test name
Test status
Simulation time 156213117 ps
CPU time 2.21 seconds
Started Aug 09 05:21:22 PM PDT 24
Finished Aug 09 05:21:24 PM PDT 24
Peak memory 209600 kb
Host smart-0a14f37c-fa71-4fea-9f32-fb0079614be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988860876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3988860876
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.261740326
Short name T73
Test name
Test status
Simulation time 73214725 ps
CPU time 3.51 seconds
Started Aug 09 05:21:22 PM PDT 24
Finished Aug 09 05:21:25 PM PDT 24
Peak memory 208176 kb
Host smart-e4f45870-0ded-42f1-b977-e9a9788c4737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261740326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.261740326
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3229912692
Short name T659
Test name
Test status
Simulation time 329376115 ps
CPU time 3.96 seconds
Started Aug 09 05:21:26 PM PDT 24
Finished Aug 09 05:21:30 PM PDT 24
Peak memory 208776 kb
Host smart-ef01e1f9-6e16-4a95-8af6-89e306d894bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229912692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3229912692
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.4247529392
Short name T339
Test name
Test status
Simulation time 857917287 ps
CPU time 3.09 seconds
Started Aug 09 05:21:23 PM PDT 24
Finished Aug 09 05:21:26 PM PDT 24
Peak memory 222428 kb
Host smart-68de437e-c5e3-4f5c-8b12-c9482942d19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247529392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4247529392
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1374131493
Short name T429
Test name
Test status
Simulation time 89244853 ps
CPU time 2.18 seconds
Started Aug 09 05:21:24 PM PDT 24
Finished Aug 09 05:21:26 PM PDT 24
Peak memory 206360 kb
Host smart-a1d0ca90-0f91-4663-a169-c424cc1c97d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374131493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1374131493
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1271798731
Short name T520
Test name
Test status
Simulation time 109518621 ps
CPU time 2.47 seconds
Started Aug 09 05:21:14 PM PDT 24
Finished Aug 09 05:21:17 PM PDT 24
Peak memory 207988 kb
Host smart-474df04d-320d-4b9d-a851-009b04488406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271798731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1271798731
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1744734973
Short name T810
Test name
Test status
Simulation time 785835942 ps
CPU time 3.43 seconds
Started Aug 09 05:21:14 PM PDT 24
Finished Aug 09 05:21:17 PM PDT 24
Peak memory 206652 kb
Host smart-fc02e720-058a-43d9-94c8-8a61a61b6ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744734973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1744734973
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1471460497
Short name T306
Test name
Test status
Simulation time 3935456246 ps
CPU time 23.61 seconds
Started Aug 09 05:21:12 PM PDT 24
Finished Aug 09 05:21:36 PM PDT 24
Peak memory 208684 kb
Host smart-599542a9-b939-4eeb-81fa-52ae1187a547
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471460497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1471460497
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2630795938
Short name T564
Test name
Test status
Simulation time 98557717 ps
CPU time 3.23 seconds
Started Aug 09 05:21:13 PM PDT 24
Finished Aug 09 05:21:17 PM PDT 24
Peak memory 206916 kb
Host smart-a4d07c5f-7c22-4723-8f4e-86c095448df3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630795938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2630795938
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3089778541
Short name T508
Test name
Test status
Simulation time 127261511 ps
CPU time 2.43 seconds
Started Aug 09 05:21:13 PM PDT 24
Finished Aug 09 05:21:15 PM PDT 24
Peak memory 206844 kb
Host smart-cbd990de-dee6-4e46-ab16-f8a0b129f740
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089778541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3089778541
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3199569621
Short name T125
Test name
Test status
Simulation time 208999695 ps
CPU time 5.34 seconds
Started Aug 09 05:21:23 PM PDT 24
Finished Aug 09 05:21:28 PM PDT 24
Peak memory 209216 kb
Host smart-11a7726b-c79f-4763-a7b9-5c3ce4a484fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199569621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3199569621
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2055898391
Short name T635
Test name
Test status
Simulation time 213434085 ps
CPU time 5.64 seconds
Started Aug 09 05:21:12 PM PDT 24
Finished Aug 09 05:21:18 PM PDT 24
Peak memory 208112 kb
Host smart-d2c50db5-4026-49db-bb60-6eec7241f147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055898391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2055898391
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1440592199
Short name T787
Test name
Test status
Simulation time 6743125422 ps
CPU time 38.88 seconds
Started Aug 09 05:21:25 PM PDT 24
Finished Aug 09 05:22:04 PM PDT 24
Peak memory 216524 kb
Host smart-00eea175-da99-4a51-a378-9e485d39bef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440592199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1440592199
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1041755608
Short name T170
Test name
Test status
Simulation time 279677435 ps
CPU time 11.18 seconds
Started Aug 09 05:21:22 PM PDT 24
Finished Aug 09 05:21:33 PM PDT 24
Peak memory 222456 kb
Host smart-7c0feb32-7181-4ab6-bc3b-4f2c5c457429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041755608 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1041755608
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2334374852
Short name T808
Test name
Test status
Simulation time 290417895 ps
CPU time 2.96 seconds
Started Aug 09 05:21:22 PM PDT 24
Finished Aug 09 05:21:25 PM PDT 24
Peak memory 207856 kb
Host smart-5de5a010-9d9e-4023-b7ed-4bf09431810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334374852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2334374852
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3153727921
Short name T441
Test name
Test status
Simulation time 108709074 ps
CPU time 1.27 seconds
Started Aug 09 05:21:22 PM PDT 24
Finished Aug 09 05:21:23 PM PDT 24
Peak memory 209752 kb
Host smart-513ed936-f083-4094-8a55-c00f70e9701d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153727921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3153727921
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3054701663
Short name T765
Test name
Test status
Simulation time 12151843 ps
CPU time 0.76 seconds
Started Aug 09 05:21:23 PM PDT 24
Finished Aug 09 05:21:24 PM PDT 24
Peak memory 205832 kb
Host smart-413e7d57-f43b-4372-aa07-27564f71aab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054701663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3054701663
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2937447516
Short name T386
Test name
Test status
Simulation time 8914859326 ps
CPU time 92.65 seconds
Started Aug 09 05:21:23 PM PDT 24
Finished Aug 09 05:22:56 PM PDT 24
Peak memory 222664 kb
Host smart-24a484c0-75bf-4f91-af77-609fa3535b66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937447516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2937447516
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2105892911
Short name T663
Test name
Test status
Simulation time 540936267 ps
CPU time 3.92 seconds
Started Aug 09 05:21:24 PM PDT 24
Finished Aug 09 05:21:28 PM PDT 24
Peak memory 218296 kb
Host smart-110ee7e4-0f0d-4211-8157-3cb7781f687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105892911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2105892911
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2199718787
Short name T542
Test name
Test status
Simulation time 142538816 ps
CPU time 3.61 seconds
Started Aug 09 05:21:22 PM PDT 24
Finished Aug 09 05:21:26 PM PDT 24
Peak memory 214336 kb
Host smart-34d66012-04b5-4ce9-a2c1-c6b62d7ec15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199718787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2199718787
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1474835238
Short name T628
Test name
Test status
Simulation time 54380561 ps
CPU time 1.7 seconds
Started Aug 09 05:21:24 PM PDT 24
Finished Aug 09 05:21:26 PM PDT 24
Peak memory 214248 kb
Host smart-142932ba-d305-4d34-8fc6-ebece675de1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474835238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1474835238
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3258732421
Short name T657
Test name
Test status
Simulation time 730158449 ps
CPU time 3.27 seconds
Started Aug 09 05:21:24 PM PDT 24
Finished Aug 09 05:21:27 PM PDT 24
Peak memory 216440 kb
Host smart-f4540a51-bdc4-4ba8-ad91-310ef57446d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258732421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3258732421
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2317752716
Short name T88
Test name
Test status
Simulation time 155655140 ps
CPU time 3.96 seconds
Started Aug 09 05:21:23 PM PDT 24
Finished Aug 09 05:21:27 PM PDT 24
Peak memory 207388 kb
Host smart-4198183c-bbb9-4179-8ef7-d0760233d9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317752716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2317752716
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.982575395
Short name T581
Test name
Test status
Simulation time 253039961 ps
CPU time 7 seconds
Started Aug 09 05:21:22 PM PDT 24
Finished Aug 09 05:21:29 PM PDT 24
Peak memory 208020 kb
Host smart-2f3ce30a-8335-43bb-9505-57ba5438defd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982575395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.982575395
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4266119471
Short name T709
Test name
Test status
Simulation time 205446134 ps
CPU time 3.5 seconds
Started Aug 09 05:21:23 PM PDT 24
Finished Aug 09 05:21:27 PM PDT 24
Peak memory 206960 kb
Host smart-b99a03f0-0011-47c8-bdd9-5f070b914c06
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266119471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4266119471
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1004869973
Short name T241
Test name
Test status
Simulation time 3885669319 ps
CPU time 54.73 seconds
Started Aug 09 05:21:23 PM PDT 24
Finished Aug 09 05:22:18 PM PDT 24
Peak memory 208988 kb
Host smart-8be8ef07-19b0-4b66-805f-bb7262e59bd6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004869973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1004869973
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.591265078
Short name T682
Test name
Test status
Simulation time 110325047 ps
CPU time 2.42 seconds
Started Aug 09 05:21:23 PM PDT 24
Finished Aug 09 05:21:25 PM PDT 24
Peak memory 206804 kb
Host smart-7799914f-4437-4c41-94c8-b1096c8924ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591265078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.591265078
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1462872957
Short name T681
Test name
Test status
Simulation time 803796924 ps
CPU time 13.4 seconds
Started Aug 09 05:21:23 PM PDT 24
Finished Aug 09 05:21:36 PM PDT 24
Peak memory 214216 kb
Host smart-a1ee8b4e-56ee-4aca-9aa5-c9a22b606d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462872957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1462872957
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2736011424
Short name T719
Test name
Test status
Simulation time 20174398 ps
CPU time 1.61 seconds
Started Aug 09 05:21:23 PM PDT 24
Finished Aug 09 05:21:24 PM PDT 24
Peak memory 206596 kb
Host smart-ca33bcef-b065-4aab-aa64-1cb626bc4537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736011424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2736011424
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2882250649
Short name T608
Test name
Test status
Simulation time 5603297363 ps
CPU time 63.6 seconds
Started Aug 09 05:21:22 PM PDT 24
Finished Aug 09 05:22:26 PM PDT 24
Peak memory 222456 kb
Host smart-e070d9fa-da7f-4035-a0af-47fdad0e07d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882250649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2882250649
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3552864660
Short name T164
Test name
Test status
Simulation time 527129257 ps
CPU time 9.74 seconds
Started Aug 09 05:21:22 PM PDT 24
Finished Aug 09 05:21:32 PM PDT 24
Peak memory 210960 kb
Host smart-e58ace00-fd9f-4cdd-ac3a-9136f004448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552864660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3552864660
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2650196125
Short name T469
Test name
Test status
Simulation time 125524319 ps
CPU time 0.89 seconds
Started Aug 09 05:21:34 PM PDT 24
Finished Aug 09 05:21:35 PM PDT 24
Peak memory 206092 kb
Host smart-75499a5f-6bdd-4ece-8ceb-8d4d7a563b4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650196125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2650196125
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.348707847
Short name T130
Test name
Test status
Simulation time 6412212216 ps
CPU time 92.67 seconds
Started Aug 09 05:21:31 PM PDT 24
Finished Aug 09 05:23:03 PM PDT 24
Peak memory 215796 kb
Host smart-b633231f-6223-4f7b-a6a5-df07d742580b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=348707847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.348707847
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3421222569
Short name T30
Test name
Test status
Simulation time 86113067 ps
CPU time 3.16 seconds
Started Aug 09 05:21:28 PM PDT 24
Finished Aug 09 05:21:32 PM PDT 24
Peak memory 219852 kb
Host smart-af73e7c9-7dd7-438f-8994-c0b743fe93db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421222569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3421222569
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2034064629
Short name T667
Test name
Test status
Simulation time 170490982 ps
CPU time 4.31 seconds
Started Aug 09 05:21:29 PM PDT 24
Finished Aug 09 05:21:33 PM PDT 24
Peak memory 214228 kb
Host smart-1af8c413-0975-4403-bdc3-588bd0f54d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034064629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2034064629
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.79817994
Short name T260
Test name
Test status
Simulation time 9858092288 ps
CPU time 71.09 seconds
Started Aug 09 05:21:30 PM PDT 24
Finished Aug 09 05:22:41 PM PDT 24
Peak memory 222416 kb
Host smart-6c37ef33-945f-4d73-acc3-33ba894e9cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79817994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.79817994
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3051642603
Short name T252
Test name
Test status
Simulation time 204836810 ps
CPU time 5.03 seconds
Started Aug 09 05:21:31 PM PDT 24
Finished Aug 09 05:21:36 PM PDT 24
Peak memory 215148 kb
Host smart-4a109e74-3046-4376-862d-793d693839f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051642603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3051642603
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3793406307
Short name T205
Test name
Test status
Simulation time 378714565 ps
CPU time 3.95 seconds
Started Aug 09 05:21:31 PM PDT 24
Finished Aug 09 05:21:35 PM PDT 24
Peak memory 207540 kb
Host smart-251ab3b8-f362-4e6b-8ade-a2b7f6df6f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793406307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3793406307
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.496256311
Short name T342
Test name
Test status
Simulation time 178246230 ps
CPU time 4.39 seconds
Started Aug 09 05:21:28 PM PDT 24
Finished Aug 09 05:21:33 PM PDT 24
Peak memory 209464 kb
Host smart-7d4a4d4d-dc0a-4d49-b77d-e9365ce17466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496256311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.496256311
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1849896762
Short name T882
Test name
Test status
Simulation time 51811253 ps
CPU time 2.47 seconds
Started Aug 09 05:21:21 PM PDT 24
Finished Aug 09 05:21:24 PM PDT 24
Peak memory 208312 kb
Host smart-dc1ae6b8-c7de-4a55-ae7e-bcf8899598c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849896762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1849896762
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.287794328
Short name T517
Test name
Test status
Simulation time 4886212419 ps
CPU time 30.27 seconds
Started Aug 09 05:21:29 PM PDT 24
Finished Aug 09 05:21:59 PM PDT 24
Peak memory 208016 kb
Host smart-177aa259-3127-475b-8dd3-fb7075e04d52
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287794328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.287794328
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1194668730
Short name T916
Test name
Test status
Simulation time 656403339 ps
CPU time 5.04 seconds
Started Aug 09 05:21:24 PM PDT 24
Finished Aug 09 05:21:29 PM PDT 24
Peak memory 208084 kb
Host smart-f7aa9cf5-6ae0-4cf3-a1da-3a0351b3b72d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194668730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1194668730
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2051952341
Short name T586
Test name
Test status
Simulation time 50928297 ps
CPU time 2.73 seconds
Started Aug 09 05:21:33 PM PDT 24
Finished Aug 09 05:21:36 PM PDT 24
Peak memory 208484 kb
Host smart-10ed665f-deab-405d-a3f9-e8fba7816e83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051952341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2051952341
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3775794227
Short name T194
Test name
Test status
Simulation time 225852048 ps
CPU time 3.36 seconds
Started Aug 09 05:21:29 PM PDT 24
Finished Aug 09 05:21:33 PM PDT 24
Peak memory 208660 kb
Host smart-4b88c946-49f3-4166-b493-93da6c0d54c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775794227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3775794227
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.799175379
Short name T389
Test name
Test status
Simulation time 25641719 ps
CPU time 1.88 seconds
Started Aug 09 05:21:21 PM PDT 24
Finished Aug 09 05:21:23 PM PDT 24
Peak memory 208268 kb
Host smart-a595d347-af11-4fff-ac8e-be1a37e9b2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799175379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.799175379
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1397103255
Short name T188
Test name
Test status
Simulation time 417432728 ps
CPU time 8.6 seconds
Started Aug 09 05:21:30 PM PDT 24
Finished Aug 09 05:21:38 PM PDT 24
Peak memory 222460 kb
Host smart-eaeb8117-86b1-45a3-914a-cbc08f4270a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397103255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1397103255
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.427243735
Short name T214
Test name
Test status
Simulation time 3948628845 ps
CPU time 24.43 seconds
Started Aug 09 05:21:31 PM PDT 24
Finished Aug 09 05:21:56 PM PDT 24
Peak memory 222548 kb
Host smart-caac1b73-db9c-45c3-a9a2-ce0cbe516ba4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427243735 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.427243735
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2959334255
Short name T794
Test name
Test status
Simulation time 60164863 ps
CPU time 3.28 seconds
Started Aug 09 05:21:27 PM PDT 24
Finished Aug 09 05:21:30 PM PDT 24
Peak memory 207980 kb
Host smart-7aa13c3c-7a60-4c15-9e51-95dcd658206c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959334255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2959334255
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3210468053
Short name T620
Test name
Test status
Simulation time 91481151 ps
CPU time 2.01 seconds
Started Aug 09 05:21:32 PM PDT 24
Finished Aug 09 05:21:34 PM PDT 24
Peak memory 210028 kb
Host smart-889de665-b48c-4d59-b6fe-de62f61ad1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210468053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3210468053
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.533021097
Short name T501
Test name
Test status
Simulation time 18001475 ps
CPU time 0.99 seconds
Started Aug 09 05:21:31 PM PDT 24
Finished Aug 09 05:21:32 PM PDT 24
Peak memory 206036 kb
Host smart-4c53d9ea-e445-42e6-b346-d47629362cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533021097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.533021097
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.855386384
Short name T417
Test name
Test status
Simulation time 86865419 ps
CPU time 3.41 seconds
Started Aug 09 05:21:29 PM PDT 24
Finished Aug 09 05:21:33 PM PDT 24
Peak memory 215176 kb
Host smart-2715f3f6-acec-49d4-a006-23584f21dad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855386384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.855386384
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.645732588
Short name T29
Test name
Test status
Simulation time 201439502 ps
CPU time 2.59 seconds
Started Aug 09 05:21:30 PM PDT 24
Finished Aug 09 05:21:33 PM PDT 24
Peak memory 209536 kb
Host smart-cd4d1fe5-7a2d-4a6b-b15a-86a553b1e98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645732588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.645732588
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3592362214
Short name T458
Test name
Test status
Simulation time 104726782 ps
CPU time 1.67 seconds
Started Aug 09 05:21:33 PM PDT 24
Finished Aug 09 05:21:35 PM PDT 24
Peak memory 207004 kb
Host smart-78304bfa-2015-4bcb-9c35-6626c125939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592362214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3592362214
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3679825079
Short name T793
Test name
Test status
Simulation time 741298328 ps
CPU time 10.51 seconds
Started Aug 09 05:21:31 PM PDT 24
Finished Aug 09 05:21:41 PM PDT 24
Peak memory 214152 kb
Host smart-739dffa5-b79e-480e-8c12-fddae902cb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679825079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3679825079
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2315058025
Short name T207
Test name
Test status
Simulation time 70486650 ps
CPU time 2.37 seconds
Started Aug 09 05:21:31 PM PDT 24
Finished Aug 09 05:21:34 PM PDT 24
Peak memory 216648 kb
Host smart-020e0809-65c0-41b8-b674-d40ee63f59d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315058025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2315058025
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3509147814
Short name T904
Test name
Test status
Simulation time 4323218598 ps
CPU time 47.57 seconds
Started Aug 09 05:21:31 PM PDT 24
Finished Aug 09 05:22:19 PM PDT 24
Peak memory 209292 kb
Host smart-180a2d6c-1ee0-4fc8-85ab-7dc8adcb8ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509147814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3509147814
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2425039668
Short name T340
Test name
Test status
Simulation time 222402485 ps
CPU time 3.62 seconds
Started Aug 09 05:21:32 PM PDT 24
Finished Aug 09 05:21:36 PM PDT 24
Peak memory 208652 kb
Host smart-c35cebc5-a0cf-45ea-be04-934cefaf5172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425039668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2425039668
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.936739847
Short name T304
Test name
Test status
Simulation time 618726785 ps
CPU time 5.38 seconds
Started Aug 09 05:21:30 PM PDT 24
Finished Aug 09 05:21:35 PM PDT 24
Peak memory 208440 kb
Host smart-ddbadc72-9ec8-4389-9ebe-571e0e2ecbce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936739847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.936739847
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1760199455
Short name T261
Test name
Test status
Simulation time 83839506 ps
CPU time 2.39 seconds
Started Aug 09 05:21:33 PM PDT 24
Finished Aug 09 05:21:35 PM PDT 24
Peak memory 208608 kb
Host smart-bf513fdd-9696-4759-9ef6-3f3a8cc73625
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760199455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1760199455
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1529742490
Short name T691
Test name
Test status
Simulation time 5081970562 ps
CPU time 15.79 seconds
Started Aug 09 05:21:30 PM PDT 24
Finished Aug 09 05:21:46 PM PDT 24
Peak memory 207904 kb
Host smart-b73ce8dd-a6ae-437b-9223-29fd184949e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529742490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1529742490
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1057869045
Short name T575
Test name
Test status
Simulation time 385530658 ps
CPU time 2.82 seconds
Started Aug 09 05:21:30 PM PDT 24
Finished Aug 09 05:21:33 PM PDT 24
Peak memory 208448 kb
Host smart-c7413b0b-fc8e-422a-a624-52db47f9e52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057869045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1057869045
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.4106014264
Short name T180
Test name
Test status
Simulation time 174990111 ps
CPU time 3.73 seconds
Started Aug 09 05:21:30 PM PDT 24
Finished Aug 09 05:21:34 PM PDT 24
Peak memory 206776 kb
Host smart-d94f694f-0192-442f-90fd-e551f6e268dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106014264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.4106014264
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3495640938
Short name T860
Test name
Test status
Simulation time 735934023 ps
CPU time 8.73 seconds
Started Aug 09 05:21:28 PM PDT 24
Finished Aug 09 05:21:37 PM PDT 24
Peak memory 215176 kb
Host smart-f3a4c0fb-43de-4d2c-bcc9-6fa1ba8465b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495640938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3495640938
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1883968649
Short name T639
Test name
Test status
Simulation time 525371325 ps
CPU time 21.01 seconds
Started Aug 09 05:21:33 PM PDT 24
Finished Aug 09 05:21:54 PM PDT 24
Peak memory 222520 kb
Host smart-ab93a59c-ea43-41f8-8042-35d046a53a2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883968649 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1883968649
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.834961997
Short name T363
Test name
Test status
Simulation time 98788083 ps
CPU time 3.24 seconds
Started Aug 09 05:21:32 PM PDT 24
Finished Aug 09 05:21:35 PM PDT 24
Peak memory 207980 kb
Host smart-21834044-4b5b-44af-9af0-f1f3929095e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834961997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.834961997
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2712233421
Short name T503
Test name
Test status
Simulation time 94991468 ps
CPU time 1.93 seconds
Started Aug 09 05:21:30 PM PDT 24
Finished Aug 09 05:21:32 PM PDT 24
Peak memory 209920 kb
Host smart-e4146989-02fb-4e1d-84fe-3a274b371e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712233421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2712233421
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2654366653
Short name T474
Test name
Test status
Simulation time 36378798 ps
CPU time 0.74 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:36 PM PDT 24
Peak memory 205944 kb
Host smart-335a79ee-ee88-4013-b9f0-089a56451dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654366653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2654366653
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.647155251
Short name T398
Test name
Test status
Simulation time 913595854 ps
CPU time 13.2 seconds
Started Aug 09 05:21:30 PM PDT 24
Finished Aug 09 05:21:44 PM PDT 24
Peak memory 215512 kb
Host smart-d2786f75-86ae-4de2-9de6-ab60c73d34ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=647155251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.647155251
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2527025536
Short name T594
Test name
Test status
Simulation time 1393591467 ps
CPU time 5.51 seconds
Started Aug 09 05:21:37 PM PDT 24
Finished Aug 09 05:21:43 PM PDT 24
Peak memory 214628 kb
Host smart-840a4063-a109-4be3-a6a1-7e153723c897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527025536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2527025536
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3852608164
Short name T779
Test name
Test status
Simulation time 130455784 ps
CPU time 2.23 seconds
Started Aug 09 05:21:31 PM PDT 24
Finished Aug 09 05:21:34 PM PDT 24
Peak memory 209296 kb
Host smart-f5e4e8d0-6415-44f2-b662-eed71075679b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852608164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3852608164
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.930926353
Short name T374
Test name
Test status
Simulation time 58363061 ps
CPU time 2.24 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:21:38 PM PDT 24
Peak memory 222336 kb
Host smart-17f4234c-c280-4b8c-af6d-1c447df99ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930926353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.930926353
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2927265846
Short name T867
Test name
Test status
Simulation time 192721012 ps
CPU time 3.31 seconds
Started Aug 09 05:21:37 PM PDT 24
Finished Aug 09 05:21:40 PM PDT 24
Peak memory 214256 kb
Host smart-a58a163f-9b2d-424a-b3a6-de71f8e61513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927265846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2927265846
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.26499894
Short name T49
Test name
Test status
Simulation time 376837912 ps
CPU time 3.61 seconds
Started Aug 09 05:21:30 PM PDT 24
Finished Aug 09 05:21:34 PM PDT 24
Peak memory 219948 kb
Host smart-11fbb9e6-8193-4db6-af88-c5e975acc566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26499894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.26499894
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3882972882
Short name T909
Test name
Test status
Simulation time 111434832 ps
CPU time 5.72 seconds
Started Aug 09 05:21:30 PM PDT 24
Finished Aug 09 05:21:35 PM PDT 24
Peak memory 208876 kb
Host smart-1309155a-6d5c-4c43-8caf-a91ee785c783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882972882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3882972882
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2296946517
Short name T359
Test name
Test status
Simulation time 399329682 ps
CPU time 4.51 seconds
Started Aug 09 05:21:33 PM PDT 24
Finished Aug 09 05:21:37 PM PDT 24
Peak memory 208476 kb
Host smart-5b51527f-fdf4-4e5b-a383-73c92726e6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296946517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2296946517
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2053450496
Short name T438
Test name
Test status
Simulation time 201775555 ps
CPU time 3.78 seconds
Started Aug 09 05:21:31 PM PDT 24
Finished Aug 09 05:21:35 PM PDT 24
Peak memory 206880 kb
Host smart-cd20f7d3-7af3-41b8-a18e-c806cf51c09d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053450496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2053450496
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.618280967
Short name T626
Test name
Test status
Simulation time 190368683 ps
CPU time 2.74 seconds
Started Aug 09 05:21:29 PM PDT 24
Finished Aug 09 05:21:32 PM PDT 24
Peak memory 206796 kb
Host smart-ac012ed4-27b9-4276-9418-5d8348b109c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618280967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.618280967
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3282118047
Short name T757
Test name
Test status
Simulation time 129526413 ps
CPU time 4.8 seconds
Started Aug 09 05:21:30 PM PDT 24
Finished Aug 09 05:21:35 PM PDT 24
Peak memory 207980 kb
Host smart-45fa467c-09d1-4d2e-9730-4a4b0339b849
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282118047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3282118047
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.572794421
Short name T327
Test name
Test status
Simulation time 74789508 ps
CPU time 2.09 seconds
Started Aug 09 05:21:37 PM PDT 24
Finished Aug 09 05:21:39 PM PDT 24
Peak memory 222468 kb
Host smart-7d809c76-d0ce-45f3-9424-884d893e3822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572794421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.572794421
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3473447927
Short name T650
Test name
Test status
Simulation time 18716397 ps
CPU time 1.74 seconds
Started Aug 09 05:21:31 PM PDT 24
Finished Aug 09 05:21:33 PM PDT 24
Peak memory 206816 kb
Host smart-2cefc57d-c0e2-493b-a20d-3d71c8376592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473447927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3473447927
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3690732688
Short name T187
Test name
Test status
Simulation time 3944936078 ps
CPU time 33.19 seconds
Started Aug 09 05:21:35 PM PDT 24
Finished Aug 09 05:22:08 PM PDT 24
Peak memory 220788 kb
Host smart-26af18a2-29b7-47f0-93a0-b8d65a766998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690732688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3690732688
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.805169584
Short name T75
Test name
Test status
Simulation time 259350992 ps
CPU time 9.4 seconds
Started Aug 09 05:21:41 PM PDT 24
Finished Aug 09 05:21:51 PM PDT 24
Peak memory 222576 kb
Host smart-a4c52b07-c536-45da-9a62-621865348bd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805169584 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.805169584
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2028312822
Short name T87
Test name
Test status
Simulation time 4743349678 ps
CPU time 28.16 seconds
Started Aug 09 05:21:36 PM PDT 24
Finished Aug 09 05:22:05 PM PDT 24
Peak memory 208504 kb
Host smart-1413686e-3cd0-443c-8182-fc80a6ddacae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028312822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2028312822
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.499882062
Short name T800
Test name
Test status
Simulation time 68558992 ps
CPU time 1.96 seconds
Started Aug 09 05:21:35 PM PDT 24
Finished Aug 09 05:21:37 PM PDT 24
Peak memory 210008 kb
Host smart-c05f9b8a-4cf8-4bfe-a21b-a6424b59f486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499882062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.499882062
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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