Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.10	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	72	258	78.18

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	53	227	81.07	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4918

1

T1

7

T2

1

T3

6

auto[1]

629

1

T1

2

T4

1

T18

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4918

1

T1

7

T2

1

T3

6

auto[1]

629

1

T1

2

T4

1

T18

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4942

1

T1

9

T2

1

T3

6

auto[1]

605

1

T4

4

T15

1

T18

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4942

1

T1

9

T2

1

T3

6

auto[1]

605

1

T4

4

T15

1

T18

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	412	1			T2	1		T3	2		T4	1
auto[OpGenId]	1154	1			T1	3		T4	4		T16	1
auto[OpGenSwOut]	1223	1			T1	4		T3	3		T4	8
auto[OpGenHwOut]	2683	1			T1	2		T3	1		T4	7
auto[OpDisable]	75	1			T13	1		T4	1		T59	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	412	1			T2	1		T3	2		T4	1
auto[OpGenId]	1154	1			T1	3		T4	4		T16	1
auto[OpGenSwOut]	1223	1			T1	4		T3	3		T4	8
auto[OpGenHwOut]	2683	1			T1	2		T3	1		T4	7
auto[OpDisable]	75	1			T13	1		T4	1		T59	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4923

1

T1

2

T2

1

T3

5

auto[1]

624

1

T1

7

T3

1

T4

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4923

1

T1

2

T2

1

T3

5

auto[1]

624

1

T1

7

T3

1

T4

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5268

1

T1

6

T2

1

T3

6

auto[1]

279

1

T1

3

T146

11

T135

10

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1922	1			T1	2		T2	1		T3	3
auto[1]	722	1			T1	5		T3	1		T4	2
auto[2]	766	1			T1	2		T3	1		T4	2
auto[3]	694	1			T4	3		T15	1		T48	1
auto[4]	357	1			T3	1		T4	2		T15	1
auto[5]	337	1			T4	1		T16	1		T18	1
auto[6]	379	1			T15	2		T83	1		T20	1
auto[7]	370	1			T4	2		T15	2		T82	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1443	1			T3	1		T4	5		T15	5
clear_one[1]	722	1			T1	5		T3	1		T4	2
clear_one[2]	766	1			T1	2		T3	1		T4	2
clear_one[3]	694	1			T4	3		T15	1		T48	1
clear_none	1922	1			T1	2		T2	1		T3	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1014	1			T1	1		T3	3		T4	2
auto[StInit]	655	1			T1	1		T3	1		T4	2
auto[StCreatorRootKey]	578	1			T4	3		T15	1		T16	1
auto[StOwnerIntKey]	556	1			T2	1		T3	1		T4	3
auto[StOwnerKey]	488	1			T1	1		T4	3		T15	1
auto[StDisabled]	1952	1			T1	6		T3	1		T13	1
auto[StInvalid]	304	1			T55	6		T49	4		T50	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1014	1			T1	1		T3	3		T4	2
auto[StInit]	655	1			T1	1		T3	1		T4	2
auto[StCreatorRootKey]	578	1			T4	3		T15	1		T16	1
auto[StOwnerIntKey]	556	1			T2	1		T3	1		T4	3
auto[StOwnerKey]	488	1			T1	1		T4	3		T15	1
auto[StDisabled]	1952	1			T1	6		T3	1		T13	1
auto[StInvalid]	304	1			T55	6		T49	4		T50	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	53	227	81.07	53

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	15
[auto[0] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[3] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[3] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[3] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[3] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T229	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	151	1			T4	1		T202	1		T70	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	182	1			T1	1		T3	1		T44	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	260	1			T48	1		T103	3		T80	1
auto[0]	auto[StInit]	auto[OpAdvance]	36	1			T146	1		T230	1		T58	1
auto[0]	auto[StInit]	auto[OpGenId]	102	1			T16	1		T46	1		T26	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	87	1			T1	1		T4	2		T48	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	202	1			T15	1		T82	1		T103	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	23	1			T146	1		T190	1		T98	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	46	1			T4	1		T20	1		T57	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	57	1			T4	1		T16	1		T57	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	80	1			T57	1		T200	1		T67	2
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	17	1			T2	1		T3	1		T146	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	28	1			T231	1		T198	1		T67	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	29	1			T4	1		T18	1		T199	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	59	1			T82	1		T209	1		T70	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T124	1		T232	1		T216	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	24	1			T67	1		T61	1		T23	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	26	1			T201	1		T67	1		T58	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T103	1		T207	1		T208	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	32	1			T83	1		T201	1		T146	1
auto[0]	auto[StDisabled]	auto[OpGenId]	70	1			T57	1		T233	1		T67	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	77	1			T3	1		T4	1		T16	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	184	1			T4	2		T18	1		T82	1
auto[0]	auto[StDisabled]	auto[OpDisable]	15	1			T13	1		T191	1		T217	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	13	1			T213	1		T53	1		T234	1
auto[0]	auto[StInvalid]	auto[OpGenId]	23	1			T49	1		T213	2		T235	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	23	1			T50	1		T53	2		T236	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	27	1			T55	1		T49	1		T41	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T237	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	23	1			T209	1		T198	1		T67	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	23	1			T4	1		T56	1		T85	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	40	1			T67	1		T238	1		T58	1
auto[1]	auto[StInit]	auto[OpAdvance]	7	1			T3	1		T239	1		T223	1
auto[1]	auto[StInit]	auto[OpGenId]	8	1			T67	1		T138	1		T127	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	6	1			T240	1		T232	1		T237	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	23	1			T61	1		T138	1		T241	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T26	1		T135	1		T97	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T48	1		T136	1		T5	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	21	1			T242	1		T61	1		T72	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	33	1			T207	1		T208	1		T206	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T68	1		T243	1		T244	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T135	1		T23	1		T110	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T57	1		T135	5		T138	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T207	1		T135	1		T245	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T246	1		T247	3		T248	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	17	1			T249	1		T250	1		T251	4
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T57	2		T252	1		T74	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T4	1		T82	1		T80	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	15	1			T57	1		T138	1		T253	3
auto[1]	auto[StDisabled]	auto[OpGenId]	50	1			T1	3		T59	1		T20	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	72	1			T1	1		T135	1		T230	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	175	1			T1	1		T80	1		T207	1
auto[1]	auto[StDisabled]	auto[OpDisable]	13	1			T61	1		T254	1		T255	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	2	1			T53	1		T256	1		-	-
auto[1]	auto[StInvalid]	auto[OpGenId]	12	1			T50	1		T257	1		T186	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T55	1		T257	1		T258	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T55	1		T257	1		T187	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T259	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	14	1			T56	1		T260	1		T193	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	20	1			T3	1		T202	1		T261	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	44	1			T262	2		T263	1		T235	2
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T104	1		T251	1		T264	1
auto[2]	auto[StInit]	auto[OpGenId]	9	1			T57	1		T6	1		T265	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	4	1			T190	1		T266	1		T267	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	16	1			T268	1		T269	1		T75	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T136	1		T214	1		T270	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T191	1		T271	1		T217	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T195	1		T138	1		T214	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	36	1			T15	1		T82	1		T44	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T136	1		T272	1		T260	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T6	1		T273	1		T274	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T59	1		T6	1		T214	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	59	1			T4	1		T80	1		T208	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T275	1		T211	1		T246	2
auto[2]	auto[StOwnerKey]	auto[OpGenId]	24	1			T58	1		T61	1		T136	2
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T195	1		T276	1		T277	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T1	1		T278	1		T136	2
auto[2]	auto[StDisabled]	auto[OpAdvance]	35	1			T83	1		T279	2		T280	1
auto[2]	auto[StDisabled]	auto[OpGenId]	67	1			T83	1		T202	1		T57	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	68	1			T1	1		T4	1		T195	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	167	1			T80	1		T57	1		T195	1
auto[2]	auto[StDisabled]	auto[OpDisable]	11	1			T70	1		T67	2		T58	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	9	1			T234	1		T261	1		T281	1
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T55	1		T41	1		T282	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	19	1			T49	1		T53	1		T187	2
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T257	1		T104	1		T283	1
auto[3]	auto[StReset]	auto[OpGenId]	18	1			T70	1		T136	1		T214	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	19	1			T138	1		T235	1		T6	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	36	1			T70	1		T58	1		T5	1
auto[3]	auto[StInit]	auto[OpAdvance]	4	1			T284	1		T285	1		T286	1
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T67	1		T58	1		T252	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	6	1			T41	1		T190	1		T218	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	21	1			T208	1		T287	1		T245	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T288	2		T289	1		T290	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T47	1		T126	1		T127	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T280	1		T192	1		T291	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	51	1			T103	1		T80	1		T210	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T292	1		T293	1		T294	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T48	1		T276	1		T110	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	23	1			T57	1		T67	1		T58	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T15	1		T123	1		T26	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T252	1		T295	1		T244	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	15	1			T202	1		T231	1		T214	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	24	1			T194	1		T230	1		T58	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T206	1		T58	1		T296	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	25	1			T4	1		T57	1		T135	1
auto[3]	auto[StDisabled]	auto[OpGenId]	58	1			T199	1		T26	1		T5	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T20	1		T204	1		T57	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	157	1			T4	2		T103	2		T207	1
auto[3]	auto[StDisabled]	auto[OpDisable]	8	1			T138	1		T224	1		T297	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	4	1			T55	1		T298	1		T299	1
auto[3]	auto[StInvalid]	auto[OpGenId]	10	1			T41	1		T85	1		T300	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	18	1			T257	1		T235	1		T106	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T301	1		T283	1		T302	1
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T6	1		T303	1		T280	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	11	1			T198	1		T110	1		T250	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	27	1			T3	1		T238	1		T58	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T279	1		T260	1		T304	1
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T98	1		T305	1		T306	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T279	1		T191	1		T307	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	14	1			T308	1		T71	1		T262	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T260	1		T178	1		T309	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T70	1		T198	1		T310	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T58	1		T279	1		T214	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T308	1		T278	1		T311	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T275	1		T252	1		T244	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T196	1		T6	1		T126	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T67	1		T61	1		T127	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	27	1			T103	1		T57	1		T200	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T196	1		T312	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	9	1			T313	1		T192	1		T314	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T138	1		T279	2		T315	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T4	1		T15	1		T57	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T61	1		T183	1		T90	1
auto[4]	auto[StDisabled]	auto[OpGenId]	30	1			T48	1		T202	1		T67	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T58	1		T313	1		T86	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T82	1		T103	1		T207	1
auto[4]	auto[StDisabled]	auto[OpDisable]	4	1			T4	1		T316	1		T77	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	5	1			T235	1		T317	1		T318	1
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T235	1		T319	1		T320	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T186	1		T321	1		T304	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T282	1		T322	1		T323	1
auto[5]	auto[StReset]	auto[OpGenId]	12	1			T111	1		T124	1		T321	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	6	1			T239	1		T222	1		T178	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	22	1			T262	1		T324	1		T263	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T325	1		T326	1		T318	1
auto[5]	auto[StInit]	auto[OpGenId]	7	1			T204	1		T7	1		T33	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	6	1			T325	1		T177	1		T89	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	11	1			T202	1		T70	1		T278	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T327	1		T328	1		T181	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T110	1		T329	1		T95	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T254	1		T216	1		T228	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T330	1		T331	1		T241	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T252	1		T251	1		T217	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T4	1		T67	1		T332	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T72	1		T138	1		T332	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T57	1		T206	1		T333	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T309	1		-	-		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	4	1			T334	1		T335	1		T228	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T20	1		T336	1		T264	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T70	1		T330	1		T337	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	7	1			T192	1		T338	1		T339	1
auto[5]	auto[StDisabled]	auto[OpGenId]	29	1			T123	1		T194	1		T67	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	18	1			T16	1		T58	1		T138	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T18	1		T82	1		T103	1
auto[5]	auto[StDisabled]	auto[OpDisable]	9	1			T59	1		T6	1		T75	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T50	1		T302	1		T340	1
auto[5]	auto[StInvalid]	auto[OpGenId]	7	1			T104	1		T258	1		T304	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T341	1		T342	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T55	1		T105	1		T343	1
auto[6]	auto[StReset]	auto[OpGenId]	10	1			T235	1		T249	1		T126	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	12	1			T315	1		T344	1		T29	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	25	1			T19	1		T208	1		T308	1
auto[6]	auto[StInit]	auto[OpAdvance]	5	1			T188	1		T345	3		T346	1
auto[6]	auto[StInit]	auto[OpGenId]	5	1			T192	1		T193	1		T216	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	10	1			T19	1		T6	1		T99	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	8	1			T324	1		T347	1		T217	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T111	1		T269	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T265	1		T348	1		T349	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T188	1		T78	1		T247	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T194	1		T67	1		T58	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T350	1		T192	1		T351	4
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T214	1		T124	1		T352	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T5	1		T252	1		T191	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T214	1		T353	1		T315	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T354	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T351	1		T74	1		T355	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T126	1		T99	1		T192	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	27	1			T204	1		T210	1		T67	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	13	1			T110	1		T280	2		T356	1
auto[6]	auto[StDisabled]	auto[OpGenId]	27	1			T6	2		T190	1		T214	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T20	1		T57	1		T67	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T15	2		T83	1		T208	1
auto[6]	auto[StDisabled]	auto[OpDisable]	8	1			T73	1		T252	1		T357	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	6	1			T186	1		T261	1		T321	1
auto[6]	auto[StInvalid]	auto[OpGenId]	3	1			T358	1		T359	1		T360	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T41	1		T85	1		T235	2
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T49	1		T213	1		T236	1
auto[7]	auto[StReset]	auto[OpGenId]	9	1			T5	1		T38	1		T129	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	11	1			T202	1		T198	1		T62	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	26	1			T208	1		T70	1		T245	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T295	2		T152	1		T346	1
auto[7]	auto[StInit]	auto[OpGenId]	11	1			T67	1		T61	1		T315	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T195	1		T284	1		T361	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	11	1			T210	1		T192	1		T362	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T74	1		T78	1		T248	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T4	1		T61	1		T138	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T5	1		T129	1		T357	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T238	1		T333	1		T363	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T6	1		T288	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T138	1		T191	1		T228	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T214	1		T364	1		T365	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T308	1		T330	1		T6	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T272	1		T361	1		T366	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T67	1		T252	1		T217	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T4	1		T124	1		T217	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T308	1		T324	1		T367	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	19	1			T252	1		T288	2		T368	1
auto[7]	auto[StDisabled]	auto[OpGenId]	32	1			T58	1		T138	1		T369	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T67	1		T58	1		T370	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	65	1			T15	2		T82	1		T80	2
auto[7]	auto[StDisabled]	auto[OpDisable]	7	1			T78	1		T371	1		T372	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T50	1		T41	1		T373	1
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T257	1		T281	1		T343	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T85	1		T282	1		T374	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T53	1		T341	1		T375	2

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1443

1

T3

1

T4

5

T15

5

clear_one[1]

auto[0]

auto[0]

auto[0]

404

1

T3

1

T4

1

T48

1

clear_one[1]

auto[0]

auto[0]

auto[1]

142

1

T1

5

T4

1

T207

3

clear_one[1]

auto[0]

auto[1]

auto[0]

138

1

T82

1

T57

2

T206

2

clear_one[1]

auto[0]

auto[1]

auto[1]

38

1

T67

1

T58

1

T61

1

clear_one[2]

auto[0]

auto[0]

auto[0]

421

1

T3

1

T15

1

T82

1

clear_one[2]

auto[0]

auto[0]

auto[1]

137

1

T4

2

T59

1

T208

1

clear_one[2]

auto[1]

auto[0]

auto[0]

139

1

T80

2

T202

1

T313

1

clear_one[2]

auto[1]

auto[0]

auto[1]

69

1

T1

2

T57

2

T233

1

clear_one[3]

auto[0]

auto[0]

auto[0]

387

1

T4

2

T103

3

T123

1

clear_one[3]

auto[0]

auto[1]

auto[0]

129

1

T4

1

T15

1

T199

1

clear_one[3]

auto[1]

auto[0]

auto[0]

134

1

T48

1

T80

1

T201

1

clear_one[3]

auto[1]

auto[1]

auto[0]

44

1

T67

1

T138

1

T6

3

clear_none

auto[0]

auto[0]

auto[0]

1360

1

T1

2

T2

1

T3

2

clear_none

auto[0]

auto[0]

auto[1]

134

1

T3

1

T103

1

T207

1

clear_none

auto[0]

auto[1]

auto[0]

146

1

T4

3

T82

2

T199

1

clear_none

auto[0]

auto[1]

auto[1]

39

1

T57

1

T196

1

T146

1

clear_none

auto[1]

auto[0]

auto[0]

137

1

T4

1

T201

2

T67

2

clear_none

auto[1]

auto[0]

auto[1]

35

1

T67

3

T214

1

T332

1

clear_none

auto[1]

auto[1]

auto[0]

41

1

T18

1

T200

1

T233

1

clear_none

auto[1]

auto[1]

auto[1]

30

1

T203

1

T146

6

T233

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1370	1			T3	1		T4	5		T15	5
clear_all	auto[1]	73	1			T279	5		T280	2		T332	1
clear_one[1]	auto[0]	668	1			T1	2		T3	1		T4	2
clear_one[1]	auto[1]	54	1			T1	3		T135	8		T136	6
clear_one[2]	auto[0]	717	1			T1	2		T3	1		T4	2
clear_one[2]	auto[1]	49	1			T135	1		T136	5		T279	3
clear_one[3]	auto[0]	660	1			T4	3		T15	1		T48	1
clear_one[3]	auto[1]	34	1			T135	1		T205	3		T280	2
clear_none	auto[0]	1853	1			T1	2		T2	1		T3	3
clear_none	auto[1]	69	1			T146	11		T205	2		T279	1