Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11591

1

T1

14

T2

3

T3

14

auto[Attestation]

8184

1

T1

17

T2

8

T3

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2940	1			T1	5		T2	4		T3	2
auto[Aes]	3535	1			T1	5		T2	1		T3	7
auto[Kmac]	3496	1			T1	4		T2	3		T3	2
auto[Otbn]	3533	1			T1	7		T2	1		T3	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8063	1			T1	8		T2	4		T3	8
auto[OpGenId]	6271	1			T1	10		T2	2		T3	5
auto[OpGenSwOut]	6259	1			T1	11		T2	5		T3	7
auto[OpGenHwOut]	7245	1			T1	10		T2	4		T3	8
auto[OpDisable]	148	1			T13	1		T4	2		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11316

1

T1

14

T2

12

T3

7

auto[OpDoneFail]

16670

1

T1

25

T2

3

T3

21

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6629	1			T1	6		T2	1		T3	11
auto[StInit]	3845	1			T1	5		T2	4		T3	1
auto[StCreatorRootKey]	3418	1			T1	5		T2	6		T3	1
auto[StOwnerIntKey]	2979	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	2637	1			T1	6		T2	3		T3	3
auto[StDisabled]	8478	1			T1	16		T3	11		T13	2

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	355	1			T1	1		T16	1		T83	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	110	1			T1	1		T4	3		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	100	1			T13	1		T4	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T14	1		T4	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	78	1			T18	1		T57	2		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	247	1			T14	1		T4	3		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	350	1			T1	1		T3	2		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	113	1			T83	1		T35	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	102	1			T57	1		T196	1		T67	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	69	1			T4	1		T18	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	67	1			T3	1		T4	2		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	219	1			T1	2		T197	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	309	1			T16	2		T83	2		T197	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	87	1			T4	1		T198	1		T135	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	90	1			T2	1		T4	1		T58	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	80	1			T4	1		T199	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T16	1		T20	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	225	1			T3	1		T14	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	347	1			T3	2		T83	3		T197	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	104	1			T4	1		T48	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T1	1		T4	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	79	1			T4	1		T199	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	57	1			T57	3		T70	1		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	232	1			T1	1		T14	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	79	1			T4	2		T57	4		T67	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	80	1			T13	1		T123	1		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	110	1			T2	1		T4	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	87	1			T18	1		T200	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	70	1			T2	1		T14	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	215	1			T1	1		T17	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	87	1			T4	1		T70	1		T67	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	102	1			T4	1		T34	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	89	1			T2	1		T4	1		T202	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	84	1			T201	1		T194	1		T67	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	68	1			T4	1		T123	1		T203	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	234	1			T4	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	81	1			T57	1		T70	1		T58	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	132	1			T2	1		T4	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T1	1		T59	1		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T4	1		T17	1		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	60	1			T4	1		T17	1		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	233	1			T1	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	81	1			T4	2		T67	3		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	94	1			T18	1		T81	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T14	1		T48	1		T202	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	79	1			T20	1		T36	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	56	1			T199	1		T81	1		T57	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	248	1			T1	1		T4	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	284	1			T3	2		T48	2		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	98	1			T199	1		T54	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	89	1			T2	1		T199	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	85	1			T123	1		T57	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	52	1			T67	1		T58	2		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	180	1			T4	1		T18	3		T57	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	443	1			T3	2		T16	1		T83	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	100	1			T35	2		T80	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	124	1			T1	1		T20	2		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	108	1			T4	1		T48	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	99	1			T80	1		T67	2		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	298	1			T123	1		T80	3		T57	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	411	1			T83	1		T48	1		T44	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	112	1			T82	1		T199	1		T202	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	126	1			T15	1		T82	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	103	1			T82	1		T57	2		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	85	1			T48	1		T206	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	298	1			T4	1		T15	2		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	498	1			T1	2		T3	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	115	1			T13	1		T48	1		T103	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T103	1		T207	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	101	1			T4	2		T16	1		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	75	1			T4	2		T103	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	273	1			T3	1		T4	3		T103	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	72	1			T4	1		T57	2		T61	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	93	1			T1	1		T44	1		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	83	1			T4	1		T204	1		T67	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	56	1			T194	1		T146	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T2	1		T4	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	193	1			T1	1		T4	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	74	1			T57	1		T67	2		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	118	1			T4	1		T48	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	98	1			T80	1		T200	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	95	1			T80	1		T200	1		T209	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	102	1			T18	1		T196	2		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	292	1			T1	1		T3	2		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	71	1			T4	1		T57	1		T67	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	119	1			T4	1		T44	1		T20	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	122	1			T15	1		T204	1		T57	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	101	1			T1	1		T4	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	307	1			T4	4		T15	2		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	76	1			T57	1		T58	2		T61	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T26	2		T207	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	116	1			T210	1		T209	2		T146	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	101	1			T4	1		T59	1		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	92	1			T1	2		T2	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	313	1			T4	1		T103	2		T199	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	223	1			T13	1		T14	1		T4	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	735	1			T1	2		T14	1		T4	6
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	216	1			T3	1		T4	3		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	704	1			T1	3		T3	2		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	213	1			T2	1		T4	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	637	1			T3	1		T14	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	207	1			T1	1		T4	2		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	699	1			T1	1		T3	2		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	240	1			T2	2		T14	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	401	1			T1	1		T13	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	228	1			T2	1		T4	2		T123	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	436	1			T4	3		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	218	1			T1	1		T4	2		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	458	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	205	1			T14	1		T48	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	439	1			T1	1		T4	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	213	1			T2	1		T123	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	575	1			T3	2		T4	1		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	314	1			T1	1		T4	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	858	1			T3	2		T16	1		T83	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	298	1			T15	1		T82	2		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	837	1			T4	1		T15	2		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	264	1			T4	4		T16	1		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	902	1			T1	2		T3	2		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	178	1			T2	1		T4	2		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	375	1			T1	2		T4	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	269	1			T18	1		T80	2		T196	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	510	1			T1	1		T3	2		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	323	1			T1	1		T4	3		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	512	1			T1	1		T2	1		T4	6
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	291	1			T1	2		T2	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	526	1			T4	1		T103	2		T199	1