Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34100

1

T1

44

T2

18

T3

33

auto[1]

324

1

T1

6

T146

12

T135

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	34106	1			T1	44		T2	18		T3	33
auto[134217728:268435455]	10	1			T135	1		T205	1		T246	1
auto[268435456:402653183]	15	1			T146	2		T136	1		T385	2
auto[402653184:536870911]	14	1			T1	1		T146	1		T205	1
auto[536870912:671088639]	4	1			T135	1		T280	1		T345	1
auto[671088640:805306367]	10	1			T146	2		T205	1		T136	1
auto[805306368:939524095]	10	1			T146	1		T136	2		T351	1
auto[939524096:1073741823]	7	1			T136	1		T385	1		T237	1
auto[1073741824:1207959551]	7	1			T135	1		T136	1		T279	1
auto[1207959552:1342177279]	10	1			T183	1		T351	1		T398	1
auto[1342177280:1476395007]	6	1			T146	1		T135	1		T136	1
auto[1476395008:1610612735]	17	1			T136	2		T280	1		T399	1
auto[1610612736:1744830463]	13	1			T205	1		T183	1		T284	2
auto[1744830464:1879048191]	10	1			T1	1		T246	1		T253	1
auto[1879048192:2013265919]	14	1			T146	1		T135	1		T288	1
auto[2013265920:2147483647]	7	1			T1	1		T351	1		T398	1
auto[2147483648:2281701375]	7	1			T205	1		T284	1		T253	1
auto[2281701376:2415919103]	8	1			T1	1		T399	1		T351	1
auto[2415919104:2550136831]	12	1			T146	1		T399	1		T246	1
auto[2550136832:2684354559]	4	1			T288	1		T400	1		T401	1
auto[2684354560:2818572287]	13	1			T146	1		T135	1		T205	2
auto[2818572288:2952790015]	6	1			T351	1		T284	1		T366	1
auto[2952790016:3087007743]	6	1			T279	1		T351	1		T285	1
auto[3087007744:3221225471]	11	1			T146	1		T136	1		T279	2
auto[3221225472:3355443199]	5	1			T351	2		T289	1		T237	1
auto[3355443200:3489660927]	17	1			T136	1		T279	1		T280	2
auto[3489660928:3623878655]	11	1			T1	1		T146	1		T288	1
auto[3623878656:3758096383]	10	1			T280	1		T351	1		T284	1
auto[3758096384:3892314111]	11	1			T135	1		T351	2		T284	1
auto[3892314112:4026531839]	15	1			T205	1		T399	1		T351	1
auto[4026531840:4160749567]	14	1			T1	1		T332	1		T399	1
auto[4160749568:4294967295]	14	1			T205	2		T279	1		T280	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	34100	1			T1	44		T2	18		T3	33
auto[0:134217727]	auto[1]	6	1			T136	1		T285	1		T251	1
auto[134217728:268435455]	auto[1]	10	1			T135	1		T205	1		T246	1
auto[268435456:402653183]	auto[1]	15	1			T146	2		T136	1		T385	2
auto[402653184:536870911]	auto[1]	14	1			T1	1		T146	1		T205	1
auto[536870912:671088639]	auto[1]	4	1			T135	1		T280	1		T345	1
auto[671088640:805306367]	auto[1]	10	1			T146	2		T205	1		T136	1
auto[805306368:939524095]	auto[1]	10	1			T146	1		T136	2		T351	1
auto[939524096:1073741823]	auto[1]	7	1			T136	1		T385	1		T237	1
auto[1073741824:1207959551]	auto[1]	7	1			T135	1		T136	1		T279	1
auto[1207959552:1342177279]	auto[1]	10	1			T183	1		T351	1		T398	1
auto[1342177280:1476395007]	auto[1]	6	1			T146	1		T135	1		T136	1
auto[1476395008:1610612735]	auto[1]	17	1			T136	2		T280	1		T399	1
auto[1610612736:1744830463]	auto[1]	13	1			T205	1		T183	1		T284	2
auto[1744830464:1879048191]	auto[1]	10	1			T1	1		T246	1		T253	1
auto[1879048192:2013265919]	auto[1]	14	1			T146	1		T135	1		T288	1
auto[2013265920:2147483647]	auto[1]	7	1			T1	1		T351	1		T398	1
auto[2147483648:2281701375]	auto[1]	7	1			T205	1		T284	1		T253	1
auto[2281701376:2415919103]	auto[1]	8	1			T1	1		T399	1		T351	1
auto[2415919104:2550136831]	auto[1]	12	1			T146	1		T399	1		T246	1
auto[2550136832:2684354559]	auto[1]	4	1			T288	1		T400	1		T401	1
auto[2684354560:2818572287]	auto[1]	13	1			T146	1		T135	1		T205	2
auto[2818572288:2952790015]	auto[1]	6	1			T351	1		T284	1		T366	1
auto[2952790016:3087007743]	auto[1]	6	1			T279	1		T351	1		T285	1
auto[3087007744:3221225471]	auto[1]	11	1			T146	1		T136	1		T279	2
auto[3221225472:3355443199]	auto[1]	5	1			T351	2		T289	1		T237	1
auto[3355443200:3489660927]	auto[1]	17	1			T136	1		T279	1		T280	2
auto[3489660928:3623878655]	auto[1]	11	1			T1	1		T146	1		T288	1
auto[3623878656:3758096383]	auto[1]	10	1			T280	1		T351	1		T284	1
auto[3758096384:3892314111]	auto[1]	11	1			T135	1		T351	2		T284	1
auto[3892314112:4026531839]	auto[1]	15	1			T205	1		T399	1		T351	1
auto[4026531840:4160749567]	auto[1]	14	1			T1	1		T332	1		T399	1
auto[4160749568:4294967295]	auto[1]	14	1			T205	2		T279	1		T280	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1588

1

T1

3

T2

4

T3

3

auto[1]

1835

1

T1

6

T2

1

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	121	1			T16	1		T199	1		T67	2
auto[134217728:268435455]	115	1			T3	1		T13	1		T4	1
auto[268435456:402653183]	111	1			T44	1		T67	2		T230	1
auto[402653184:536870911]	96	1			T2	1		T199	1		T45	1
auto[536870912:671088639]	102	1			T59	1		T135	1		T67	1
auto[671088640:805306367]	113	1			T1	1		T48	1		T20	1
auto[805306368:939524095]	102	1			T1	1		T199	1		T20	1
auto[939524096:1073741823]	109	1			T4	3		T16	1		T45	1
auto[1073741824:1207959551]	90	1			T3	2		T4	2		T202	1
auto[1207959552:1342177279]	98	1			T4	2		T83	1		T199	1
auto[1342177280:1476395007]	106	1			T1	1		T4	1		T16	1
auto[1476395008:1610612735]	95	1			T4	2		T83	1		T202	1
auto[1610612736:1744830463]	106	1			T3	1		T202	1		T57	2
auto[1744830464:1879048191]	112	1			T2	1		T13	1		T201	1
auto[1879048192:2013265919]	130	1			T4	1		T19	1		T231	1
auto[2013265920:2147483647]	127	1			T4	2		T18	1		T46	1
auto[2147483648:2281701375]	95	1			T1	1		T2	1		T3	1
auto[2281701376:2415919103]	88	1			T1	2		T4	2		T55	1
auto[2415919104:2550136831]	102	1			T57	1		T201	3		T70	1
auto[2550136832:2684354559]	117	1			T4	1		T46	1		T26	2
auto[2684354560:2818572287]	104	1			T1	2		T18	1		T20	1
auto[2818572288:2952790015]	96	1			T3	1		T48	1		T231	1
auto[2952790016:3087007743]	113	1			T4	1		T16	1		T59	1
auto[3087007744:3221225471]	102	1			T2	1		T18	1		T59	1
auto[3221225472:3355443199]	97	1			T4	2		T83	1		T19	1
auto[3355443200:3489660927]	129	1			T4	2		T59	1		T57	2
auto[3489660928:3623878655]	124	1			T4	2		T20	1		T19	1
auto[3623878656:3758096383]	97	1			T2	1		T26	1		T57	1
auto[3758096384:3892314111]	107	1			T83	1		T20	1		T46	1
auto[3892314112:4026531839]	111	1			T1	1		T4	3		T202	1
auto[4026531840:4160749567]	114	1			T4	1		T20	1		T196	1
auto[4160749568:4294967295]	94	1			T4	1		T200	1		T194	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T16	1		T199	1		T67	1
auto[0:134217727]	auto[1]	65	1			T67	1		T252	1		T257	1
auto[134217728:268435455]	auto[0]	45	1			T46	1		T57	1		T58	1
auto[134217728:268435455]	auto[1]	70	1			T3	1		T13	1		T4	1
auto[268435456:402653183]	auto[0]	56	1			T67	1		T61	5		T252	1
auto[268435456:402653183]	auto[1]	55	1			T44	1		T67	1		T230	1
auto[402653184:536870911]	auto[0]	51	1			T2	1		T20	1		T204	1
auto[402653184:536870911]	auto[1]	45	1			T199	1		T45	1		T26	1
auto[536870912:671088639]	auto[0]	49	1			T59	1		T205	1		T71	1
auto[536870912:671088639]	auto[1]	53	1			T135	1		T67	1		T58	1
auto[671088640:805306367]	auto[0]	52	1			T50	1		T58	1		T71	1
auto[671088640:805306367]	auto[1]	61	1			T1	1		T48	1		T20	1
auto[805306368:939524095]	auto[0]	56	1			T1	1		T199	1		T57	1
auto[805306368:939524095]	auto[1]	46	1			T20	1		T204	1		T57	1
auto[939524096:1073741823]	auto[0]	59	1			T4	3		T57	1		T67	1
auto[939524096:1073741823]	auto[1]	50	1			T16	1		T45	1		T202	1
auto[1073741824:1207959551]	auto[0]	40	1			T3	1		T4	1		T202	1
auto[1073741824:1207959551]	auto[1]	50	1			T3	1		T4	1		T203	1
auto[1207959552:1342177279]	auto[0]	43	1			T4	1		T199	1		T44	1
auto[1207959552:1342177279]	auto[1]	55	1			T4	1		T83	1		T70	1
auto[1342177280:1476395007]	auto[0]	52	1			T1	1		T4	1		T19	1
auto[1342177280:1476395007]	auto[1]	54	1			T16	1		T83	1		T57	2
auto[1476395008:1610612735]	auto[0]	47	1			T83	1		T275	1		T53	1
auto[1476395008:1610612735]	auto[1]	48	1			T4	2		T202	1		T204	1
auto[1610612736:1744830463]	auto[0]	46	1			T57	2		T58	1		T61	2
auto[1610612736:1744830463]	auto[1]	60	1			T3	1		T202	1		T47	1
auto[1744830464:1879048191]	auto[0]	46	1			T2	1		T201	1		T67	1
auto[1744830464:1879048191]	auto[1]	66	1			T13	1		T67	2		T58	1
auto[1879048192:2013265919]	auto[0]	65	1			T19	1		T231	1		T58	2
auto[1879048192:2013265919]	auto[1]	65	1			T4	1		T67	2		T58	3
auto[2013265920:2147483647]	auto[0]	58	1			T4	2		T18	1		T46	1
auto[2013265920:2147483647]	auto[1]	69	1			T204	1		T201	1		T67	1
auto[2147483648:2281701375]	auto[0]	44	1			T2	1		T3	1		T235	1
auto[2147483648:2281701375]	auto[1]	51	1			T1	1		T67	1		T58	1
auto[2281701376:2415919103]	auto[0]	33	1			T1	1		T4	1		T67	1
auto[2281701376:2415919103]	auto[1]	55	1			T1	1		T4	1		T55	1
auto[2415919104:2550136831]	auto[0]	55	1			T57	1		T201	3		T70	1
auto[2415919104:2550136831]	auto[1]	47	1			T67	2		T58	3		T23	1
auto[2550136832:2684354559]	auto[0]	56	1			T202	1		T200	1		T194	1
auto[2550136832:2684354559]	auto[1]	61	1			T4	1		T46	1		T26	2
auto[2684354560:2818572287]	auto[0]	38	1			T204	1		T67	1		T47	1
auto[2684354560:2818572287]	auto[1]	66	1			T1	2		T18	1		T20	1
auto[2818572288:2952790015]	auto[0]	46	1			T3	1		T58	1		T61	1
auto[2818572288:2952790015]	auto[1]	50	1			T48	1		T231	1		T67	1
auto[2952790016:3087007743]	auto[0]	56	1			T4	1		T85	1		T252	2
auto[2952790016:3087007743]	auto[1]	57	1			T16	1		T59	1		T202	1
auto[3087007744:3221225471]	auto[0]	42	1			T46	1		T61	1		T138	3
auto[3087007744:3221225471]	auto[1]	60	1			T2	1		T18	1		T59	1
auto[3221225472:3355443199]	auto[0]	41	1			T4	1		T19	1		T209	1
auto[3221225472:3355443199]	auto[1]	56	1			T4	1		T83	1		T204	1
auto[3355443200:3489660927]	auto[0]	56	1			T4	2		T57	1		T58	1
auto[3355443200:3489660927]	auto[1]	73	1			T59	1		T57	1		T146	1
auto[3489660928:3623878655]	auto[0]	57	1			T4	1		T19	1		T202	1
auto[3489660928:3623878655]	auto[1]	67	1			T4	1		T20	1		T30	1
auto[3623878656:3758096383]	auto[0]	56	1			T2	1		T26	1		T57	1
auto[3623878656:3758096383]	auto[1]	41	1			T135	1		T233	1		T205	1
auto[3758096384:3892314111]	auto[0]	45	1			T83	1		T46	1		T67	2
auto[3758096384:3892314111]	auto[1]	62	1			T20	1		T41	1		T61	1
auto[3892314112:4026531839]	auto[0]	45	1			T4	2		T61	1		T138	2
auto[3892314112:4026531839]	auto[1]	66	1			T1	1		T4	1		T202	1
auto[4026531840:4160749567]	auto[0]	51	1			T41	1		T58	1		T61	2
auto[4026531840:4160749567]	auto[1]	63	1			T4	1		T20	1		T196	1
auto[4160749568:4294967295]	auto[0]	46	1			T200	1		T194	1		T5	1
auto[4160749568:4294967295]	auto[1]	48	1			T4	1		T58	1		T136	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1577

1

T1

3

T2

4

T3

3

auto[1]

1846

1

T1

6

T2

1

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T16	1		T59	1		T200	1
auto[134217728:268435455]	128	1			T57	2		T49	1		T135	1
auto[268435456:402653183]	124	1			T3	1		T57	1		T49	1
auto[402653184:536870911]	106	1			T48	2		T67	1		T61	2
auto[536870912:671088639]	97	1			T4	1		T83	1		T196	1
auto[671088640:805306367]	119	1			T4	1		T26	1		T30	1
auto[805306368:939524095]	92	1			T59	1		T57	1		T55	1
auto[939524096:1073741823]	105	1			T2	3		T4	2		T73	1
auto[1073741824:1207959551]	106	1			T4	1		T16	1		T46	1
auto[1207959552:1342177279]	110	1			T199	1		T202	1		T57	1
auto[1342177280:1476395007]	97	1			T4	2		T20	1		T26	1
auto[1476395008:1610612735]	109	1			T3	2		T13	1		T4	2
auto[1610612736:1744830463]	110	1			T4	2		T19	1		T204	1
auto[1744830464:1879048191]	102	1			T2	1		T4	1		T83	1
auto[1879048192:2013265919]	105	1			T26	1		T231	1		T194	1
auto[2013265920:2147483647]	106	1			T4	3		T18	1		T46	1
auto[2147483648:2281701375]	104	1			T1	1		T3	1		T4	1
auto[2281701376:2415919103]	107	1			T4	2		T44	1		T57	1
auto[2415919104:2550136831]	79	1			T1	2		T4	1		T20	1
auto[2550136832:2684354559]	100	1			T4	2		T45	2		T20	2
auto[2684354560:2818572287]	102	1			T1	1		T4	2		T16	1
auto[2818572288:2952790015]	116	1			T1	1		T3	1		T18	1
auto[2952790016:3087007743]	110	1			T1	1		T13	1		T4	2
auto[3087007744:3221225471]	102	1			T83	1		T20	1		T57	1
auto[3221225472:3355443199]	106	1			T4	1		T83	1		T19	1
auto[3355443200:3489660927]	95	1			T1	2		T2	1		T4	1
auto[3489660928:3623878655]	123	1			T3	1		T4	1		T57	2
auto[3623878656:3758096383]	110	1			T26	1		T202	1		T196	1
auto[3758096384:3892314111]	118	1			T48	1		T204	1		T70	1
auto[3892314112:4026531839]	110	1			T199	1		T26	1		T30	1
auto[4026531840:4160749567]	97	1			T1	1		T83	1		T20	1
auto[4160749568:4294967295]	125	1			T4	1		T20	1		T46	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	36	1			T59	1		T67	1		T53	1
auto[0:134217727]	auto[1]	67	1			T16	1		T200	1		T56	1
auto[134217728:268435455]	auto[0]	56	1			T57	1		T67	1		T58	1
auto[134217728:268435455]	auto[1]	72	1			T57	1		T49	1		T135	1
auto[268435456:402653183]	auto[0]	60	1			T57	1		T67	1		T41	1
auto[268435456:402653183]	auto[1]	64	1			T3	1		T49	1		T67	1
auto[402653184:536870911]	auto[0]	52	1			T61	2		T53	1		T85	1
auto[402653184:536870911]	auto[1]	54	1			T48	2		T67	1		T275	1
auto[536870912:671088639]	auto[0]	44	1			T196	1		T67	1		T58	1
auto[536870912:671088639]	auto[1]	53	1			T4	1		T83	1		T67	2
auto[671088640:805306367]	auto[0]	56	1			T4	1		T201	1		T67	1
auto[671088640:805306367]	auto[1]	63	1			T26	1		T30	1		T146	1
auto[805306368:939524095]	auto[0]	45	1			T58	1		T213	1		T138	2
auto[805306368:939524095]	auto[1]	47	1			T59	1		T57	1		T55	1
auto[939524096:1073741823]	auto[0]	52	1			T2	3		T4	1		T73	1
auto[939524096:1073741823]	auto[1]	53	1			T4	1		T252	1		T138	2
auto[1073741824:1207959551]	auto[0]	47	1			T46	1		T57	1		T198	1
auto[1073741824:1207959551]	auto[1]	59	1			T4	1		T16	1		T202	1
auto[1207959552:1342177279]	auto[0]	58	1			T41	1		T230	1		T58	1
auto[1207959552:1342177279]	auto[1]	52	1			T199	1		T202	1		T57	1
auto[1342177280:1476395007]	auto[0]	42	1			T4	1		T61	1		T6	1
auto[1342177280:1476395007]	auto[1]	55	1			T4	1		T20	1		T26	1
auto[1476395008:1610612735]	auto[0]	52	1			T3	1		T4	1		T16	1
auto[1476395008:1610612735]	auto[1]	57	1			T3	1		T13	1		T4	1
auto[1610612736:1744830463]	auto[0]	52	1			T19	1		T57	1		T70	1
auto[1610612736:1744830463]	auto[1]	58	1			T4	2		T204	1		T57	1
auto[1744830464:1879048191]	auto[0]	46	1			T2	1		T4	1		T83	1
auto[1744830464:1879048191]	auto[1]	56	1			T59	1		T201	1		T198	1
auto[1879048192:2013265919]	auto[0]	58	1			T61	2		T252	2		T138	1
auto[1879048192:2013265919]	auto[1]	47	1			T26	1		T231	1		T194	1
auto[2013265920:2147483647]	auto[0]	51	1			T4	2		T46	1		T19	2
auto[2013265920:2147483647]	auto[1]	55	1			T4	1		T18	1		T202	1
auto[2147483648:2281701375]	auto[0]	44	1			T3	1		T4	1		T199	1
auto[2147483648:2281701375]	auto[1]	60	1			T1	1		T202	1		T203	1
auto[2281701376:2415919103]	auto[0]	49	1			T4	1		T57	1		T201	1
auto[2281701376:2415919103]	auto[1]	58	1			T4	1		T44	1		T67	1
auto[2415919104:2550136831]	auto[0]	35	1			T1	1		T46	1		T67	1
auto[2415919104:2550136831]	auto[1]	44	1			T1	1		T4	1		T20	1
auto[2550136832:2684354559]	auto[0]	44	1			T4	1		T57	4		T194	1
auto[2550136832:2684354559]	auto[1]	56	1			T4	1		T45	2		T20	2
auto[2684354560:2818572287]	auto[0]	48	1			T1	1		T4	1		T202	1
auto[2684354560:2818572287]	auto[1]	54	1			T4	1		T16	1		T59	1
auto[2818572288:2952790015]	auto[0]	47	1			T3	1		T199	1		T46	1
auto[2818572288:2952790015]	auto[1]	69	1			T1	1		T18	1		T55	1
auto[2952790016:3087007743]	auto[0]	42	1			T4	1		T209	1		T231	1
auto[2952790016:3087007743]	auto[1]	68	1			T1	1		T13	1		T4	1
auto[3087007744:3221225471]	auto[0]	47	1			T83	1		T47	1		T58	1
auto[3087007744:3221225471]	auto[1]	55	1			T20	1		T57	1		T203	1
auto[3221225472:3355443199]	auto[0]	54	1			T4	1		T19	1		T200	1
auto[3221225472:3355443199]	auto[1]	52	1			T83	1		T57	1		T58	1
auto[3355443200:3489660927]	auto[0]	44	1			T1	1		T4	1		T41	1
auto[3355443200:3489660927]	auto[1]	51	1			T1	1		T2	1		T18	1
auto[3489660928:3623878655]	auto[0]	54	1			T57	1		T55	1		T67	1
auto[3489660928:3623878655]	auto[1]	69	1			T3	1		T4	1		T57	1
auto[3623878656:3758096383]	auto[0]	48	1			T50	1		T198	1		T5	1
auto[3623878656:3758096383]	auto[1]	62	1			T26	1		T202	1		T196	1
auto[3758096384:3892314111]	auto[0]	55	1			T204	1		T70	1		T41	1
auto[3758096384:3892314111]	auto[1]	63	1			T48	1		T67	2		T61	1
auto[3892314112:4026531839]	auto[0]	56	1			T26	1		T30	1		T200	1
auto[3892314112:4026531839]	auto[1]	54	1			T199	1		T58	2		T205	1
auto[4026531840:4160749567]	auto[0]	46	1			T83	1		T67	1		T242	1
auto[4026531840:4160749567]	auto[1]	51	1			T1	1		T20	1		T204	1
auto[4160749568:4294967295]	auto[0]	57	1			T4	1		T46	1		T47	1
auto[4160749568:4294967295]	auto[1]	68	1			T20	1		T204	1		T231	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1613

1

T1

3

T2

4

T3

3

auto[1]

1810

1

T1

6

T2

1

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T70	1		T135	1		T67	2
auto[134217728:268435455]	117	1			T46	1		T26	1		T57	1
auto[268435456:402653183]	108	1			T1	1		T4	2		T202	2
auto[402653184:536870911]	102	1			T13	1		T4	1		T16	1
auto[536870912:671088639]	103	1			T4	1		T202	1		T198	1
auto[671088640:805306367]	110	1			T1	1		T57	1		T201	1
auto[805306368:939524095]	107	1			T1	2		T4	1		T59	1
auto[939524096:1073741823]	97	1			T3	1		T4	1		T202	1
auto[1073741824:1207959551]	116	1			T2	1		T199	1		T202	1
auto[1207959552:1342177279]	113	1			T2	1		T3	1		T13	1
auto[1342177280:1476395007]	111	1			T1	1		T2	1		T4	1
auto[1476395008:1610612735]	108	1			T4	1		T26	1		T204	1
auto[1610612736:1744830463]	106	1			T45	1		T20	1		T46	1
auto[1744830464:1879048191]	95	1			T4	3		T57	1		T201	1
auto[1879048192:2013265919]	103	1			T1	2		T4	1		T83	1
auto[2013265920:2147483647]	101	1			T4	2		T16	1		T199	2
auto[2147483648:2281701375]	105	1			T4	1		T20	1		T57	1
auto[2281701376:2415919103]	112	1			T4	1		T18	1		T46	1
auto[2415919104:2550136831]	108	1			T1	1		T4	1		T16	1
auto[2550136832:2684354559]	103	1			T2	1		T4	2		T204	1
auto[2684354560:2818572287]	104	1			T3	1		T19	1		T57	1
auto[2818572288:2952790015]	100	1			T3	1		T4	1		T46	1
auto[2952790016:3087007743]	113	1			T4	1		T83	1		T199	1
auto[3087007744:3221225471]	101	1			T4	2		T59	1		T44	1
auto[3221225472:3355443199]	107	1			T204	1		T67	2		T58	1
auto[3355443200:3489660927]	116	1			T18	1		T48	1		T20	1
auto[3489660928:3623878655]	109	1			T1	1		T4	1		T59	1
auto[3623878656:3758096383]	111	1			T4	1		T16	1		T45	1
auto[3758096384:3892314111]	103	1			T48	1		T57	1		T47	1
auto[3892314112:4026531839]	107	1			T2	1		T48	1		T59	1
auto[4026531840:4160749567]	109	1			T3	1		T26	1		T202	1
auto[4160749568:4294967295]	111	1			T3	1		T4	1		T83	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T70	1		T136	1		T5	1
auto[0:134217727]	auto[1]	58	1			T135	1		T67	2		T230	1
auto[134217728:268435455]	auto[0]	46	1			T46	1		T57	1		T73	1
auto[134217728:268435455]	auto[1]	71	1			T26	1		T49	1		T146	1
auto[268435456:402653183]	auto[0]	52	1			T4	2		T202	1		T204	1
auto[268435456:402653183]	auto[1]	56	1			T1	1		T202	1		T57	1
auto[402653184:536870911]	auto[0]	47	1			T13	1		T16	1		T83	1
auto[402653184:536870911]	auto[1]	55	1			T4	1		T204	1		T57	1
auto[536870912:671088639]	auto[0]	48	1			T4	1		T202	1		T61	1
auto[536870912:671088639]	auto[1]	55	1			T198	1		T242	1		T61	2
auto[671088640:805306367]	auto[0]	46	1			T1	1		T201	1		T67	2
auto[671088640:805306367]	auto[1]	64	1			T57	1		T58	1		T61	3
auto[805306368:939524095]	auto[0]	43	1			T1	1		T30	1		T67	1
auto[805306368:939524095]	auto[1]	64	1			T1	1		T4	1		T59	1
auto[939524096:1073741823]	auto[0]	51	1			T3	1		T4	1		T198	1
auto[939524096:1073741823]	auto[1]	46	1			T202	1		T55	1		T203	1
auto[1073741824:1207959551]	auto[0]	54	1			T2	1		T202	1		T57	1
auto[1073741824:1207959551]	auto[1]	62	1			T199	1		T233	1		T58	1
auto[1207959552:1342177279]	auto[0]	59	1			T2	1		T3	1		T4	1
auto[1207959552:1342177279]	auto[1]	54	1			T13	1		T4	2		T146	1
auto[1342177280:1476395007]	auto[0]	50	1			T4	1		T233	1		T5	1
auto[1342177280:1476395007]	auto[1]	61	1			T1	1		T2	1		T18	1
auto[1476395008:1610612735]	auto[0]	46	1			T47	1		T242	1		T61	3
auto[1476395008:1610612735]	auto[1]	62	1			T4	1		T26	1		T204	1
auto[1610612736:1744830463]	auto[0]	60	1			T46	1		T58	2		T212	1
auto[1610612736:1744830463]	auto[1]	46	1			T45	1		T20	1		T204	1
auto[1744830464:1879048191]	auto[0]	52	1			T4	1		T57	1		T201	1
auto[1744830464:1879048191]	auto[1]	43	1			T4	2		T203	1		T58	1
auto[1879048192:2013265919]	auto[0]	49	1			T4	1		T83	1		T57	1
auto[1879048192:2013265919]	auto[1]	54	1			T1	2		T67	1		T58	2
auto[2013265920:2147483647]	auto[0]	50	1			T4	2		T199	1		T57	1
auto[2013265920:2147483647]	auto[1]	51	1			T16	1		T199	1		T85	1
auto[2147483648:2281701375]	auto[0]	43	1			T57	1		T56	1		T369	1
auto[2147483648:2281701375]	auto[1]	62	1			T4	1		T20	1		T55	1
auto[2281701376:2415919103]	auto[0]	55	1			T4	1		T18	1		T46	1
auto[2281701376:2415919103]	auto[1]	57	1			T58	1		T61	1		T53	1
auto[2415919104:2550136831]	auto[0]	51	1			T1	1		T4	1		T200	1
auto[2415919104:2550136831]	auto[1]	57	1			T16	1		T44	1		T41	1
auto[2550136832:2684354559]	auto[0]	51	1			T2	1		T4	1		T204	1
auto[2550136832:2684354559]	auto[1]	52	1			T4	1		T30	1		T67	1
auto[2684354560:2818572287]	auto[0]	44	1			T19	1		T67	1		T58	1
auto[2684354560:2818572287]	auto[1]	60	1			T3	1		T57	1		T196	1
auto[2818572288:2952790015]	auto[0]	40	1			T46	1		T57	2		T67	1
auto[2818572288:2952790015]	auto[1]	60	1			T3	1		T4	1		T200	1
auto[2952790016:3087007743]	auto[0]	55	1			T199	1		T46	1		T57	1
auto[2952790016:3087007743]	auto[1]	58	1			T4	1		T83	1		T26	1
auto[3087007744:3221225471]	auto[0]	51	1			T4	1		T59	1		T44	1
auto[3087007744:3221225471]	auto[1]	50	1			T4	1		T20	1		T146	1
auto[3221225472:3355443199]	auto[0]	52	1			T204	1		T67	1		T53	1
auto[3221225472:3355443199]	auto[1]	55	1			T67	1		T58	1		T254	1
auto[3355443200:3489660927]	auto[0]	49	1			T19	1		T194	1		T174	1
auto[3355443200:3489660927]	auto[1]	67	1			T18	1		T48	1		T20	1
auto[3489660928:3623878655]	auto[0]	54	1			T4	1		T20	1		T57	1
auto[3489660928:3623878655]	auto[1]	55	1			T1	1		T59	1		T20	1
auto[3623878656:3758096383]	auto[0]	51	1			T16	1		T19	1		T57	2
auto[3623878656:3758096383]	auto[1]	60	1			T4	1		T45	1		T26	1
auto[3758096384:3892314111]	auto[0]	49	1			T58	1		T5	1		T85	1
auto[3758096384:3892314111]	auto[1]	54	1			T48	1		T57	1		T47	1
auto[3892314112:4026531839]	auto[0]	53	1			T2	1		T59	1		T202	1
auto[3892314112:4026531839]	auto[1]	54	1			T48	1		T20	1		T202	1
auto[4026531840:4160749567]	auto[0]	54	1			T3	1		T209	1		T67	1
auto[4026531840:4160749567]	auto[1]	55	1			T26	1		T202	1		T70	1
auto[4160749568:4294967295]	auto[0]	59	1			T4	1		T83	1		T200	1
auto[4160749568:4294967295]	auto[1]	52	1			T3	1		T203	1		T233	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1596

1

T1

3

T2

4

T3

3

auto[1]

1827

1

T1

6

T2

1

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T13	1		T4	1		T20	1
auto[134217728:268435455]	101	1			T1	1		T16	1		T83	1
auto[268435456:402653183]	123	1			T1	2		T202	1		T204	1
auto[402653184:536870911]	113	1			T1	1		T44	1		T46	1
auto[536870912:671088639]	93	1			T4	2		T48	1		T26	1
auto[671088640:805306367]	97	1			T4	1		T59	1		T204	1
auto[805306368:939524095]	108	1			T2	2		T3	1		T4	2
auto[939524096:1073741823]	98	1			T4	2		T73	1		T41	1
auto[1073741824:1207959551]	97	1			T2	1		T4	3		T18	1
auto[1207959552:1342177279]	115	1			T1	1		T16	1		T199	1
auto[1342177280:1476395007]	103	1			T16	1		T59	1		T201	2
auto[1476395008:1610612735]	104	1			T46	2		T204	1		T57	1
auto[1610612736:1744830463]	113	1			T26	1		T204	1		T67	2
auto[1744830464:1879048191]	97	1			T3	1		T4	1		T83	1
auto[1879048192:2013265919]	106	1			T57	2		T67	1		T58	1
auto[2013265920:2147483647]	113	1			T57	1		T198	1		T146	1
auto[2147483648:2281701375]	124	1			T3	1		T4	3		T57	1
auto[2281701376:2415919103]	91	1			T231	1		T233	1		T67	1
auto[2415919104:2550136831]	106	1			T4	1		T83	1		T199	1
auto[2550136832:2684354559]	118	1			T2	1		T48	1		T44	1
auto[2684354560:2818572287]	112	1			T1	1		T3	1		T16	1
auto[2818572288:2952790015]	105	1			T59	1		T202	1		T57	1
auto[2952790016:3087007743]	105	1			T3	1		T20	1		T202	1
auto[3087007744:3221225471]	113	1			T4	3		T18	1		T46	2
auto[3221225472:3355443199]	113	1			T3	1		T4	1		T199	1
auto[3355443200:3489660927]	110	1			T1	1		T4	2		T45	1
auto[3489660928:3623878655]	96	1			T48	1		T59	1		T199	1
auto[3623878656:3758096383]	104	1			T4	2		T20	1		T202	1
auto[3758096384:3892314111]	112	1			T1	1		T2	1		T4	1
auto[3892314112:4026531839]	119	1			T4	2		T18	1		T83	1
auto[4026531840:4160749567]	108	1			T1	1		T13	1		T20	1
auto[4160749568:4294967295]	102	1			T4	2		T26	1		T57	3