Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3051

1

T1

9

T2

1

T3

6

auto[1]

283

1

T1

3

T146

14

T135

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T1	1		T3	1		T4	2
auto[134217728:268435455]	102	1			T3	1		T83	1		T50	1
auto[268435456:402653183]	105	1			T1	1		T3	1		T59	1
auto[402653184:536870911]	107	1			T83	1		T20	1		T135	2
auto[536870912:671088639]	100	1			T13	1		T231	2		T67	2
auto[671088640:805306367]	111	1			T1	1		T199	1		T204	1
auto[805306368:939524095]	97	1			T199	1		T20	1		T67	3
auto[939524096:1073741823]	121	1			T4	4		T26	1		T204	1
auto[1073741824:1207959551]	124	1			T4	1		T83	1		T59	1
auto[1207959552:1342177279]	100	1			T2	1		T4	2		T199	1
auto[1342177280:1476395007]	98	1			T204	2		T57	1		T67	1
auto[1476395008:1610612735]	90	1			T1	1		T18	1		T204	1
auto[1610612736:1744830463]	104	1			T1	2		T3	1		T4	1
auto[1744830464:1879048191]	94	1			T1	1		T16	1		T18	1
auto[1879048192:2013265919]	111	1			T4	1		T20	1		T204	1
auto[2013265920:2147483647]	130	1			T4	2		T57	1		T201	1
auto[2147483648:2281701375]	100	1			T48	1		T26	1		T30	1
auto[2281701376:2415919103]	102	1			T1	1		T4	3		T48	1
auto[2415919104:2550136831]	100	1			T13	1		T16	1		T20	2
auto[2550136832:2684354559]	117	1			T1	1		T3	2		T83	1
auto[2684354560:2818572287]	95	1			T4	2		T19	1		T202	1
auto[2818572288:2952790015]	110	1			T16	1		T18	1		T19	1
auto[2952790016:3087007743]	114	1			T4	1		T202	1		T57	1
auto[3087007744:3221225471]	85	1			T20	1		T26	2		T57	1
auto[3221225472:3355443199]	106	1			T4	2		T59	1		T202	1
auto[3355443200:3489660927]	91	1			T1	1		T202	1		T57	1
auto[3489660928:3623878655]	106	1			T1	1		T4	1		T46	1
auto[3623878656:3758096383]	88	1			T48	1		T202	1		T201	1
auto[3758096384:3892314111]	121	1			T1	1		T83	1		T57	1
auto[3892314112:4026531839]	102	1			T26	1		T49	1		T203	1
auto[4026531840:4160749567]	101	1			T44	1		T20	1		T57	1
auto[4160749568:4294967295]	99	1			T16	1		T59	1		T199	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	90	1			T3	1		T4	2		T202	1
auto[0:134217727]	auto[1]	13	1			T1	1		T146	1		T332	1
auto[134217728:268435455]	auto[0]	93	1			T3	1		T83	1		T50	1
auto[134217728:268435455]	auto[1]	9	1			T146	2		T332	1		T351	1
auto[268435456:402653183]	auto[0]	101	1			T1	1		T3	1		T59	1
auto[268435456:402653183]	auto[1]	4	1			T136	1		T279	1		T246	1
auto[402653184:536870911]	auto[0]	94	1			T83	1		T20	1		T67	1
auto[402653184:536870911]	auto[1]	13	1			T135	2		T399	1		T246	1
auto[536870912:671088639]	auto[0]	97	1			T13	1		T231	2		T67	2
auto[536870912:671088639]	auto[1]	3	1			T307	1		T366	1		T403	1
auto[671088640:805306367]	auto[0]	106	1			T1	1		T199	1		T204	1
auto[671088640:805306367]	auto[1]	5	1			T205	1		T398	2		T404	1
auto[805306368:939524095]	auto[0]	91	1			T199	1		T20	1		T67	3
auto[805306368:939524095]	auto[1]	6	1			T279	1		T183	1		T284	1
auto[939524096:1073741823]	auto[0]	111	1			T4	4		T26	1		T204	1
auto[939524096:1073741823]	auto[1]	10	1			T146	1		T136	1		T280	1
auto[1073741824:1207959551]	auto[0]	111	1			T4	1		T83	1		T59	1
auto[1073741824:1207959551]	auto[1]	13	1			T135	1		T279	2		T280	1
auto[1207959552:1342177279]	auto[0]	88	1			T2	1		T4	2		T199	1
auto[1207959552:1342177279]	auto[1]	12	1			T146	1		T385	1		T399	1
auto[1342177280:1476395007]	auto[0]	90	1			T204	2		T57	1		T67	1
auto[1342177280:1476395007]	auto[1]	8	1			T332	1		T399	1		T232	1
auto[1476395008:1610612735]	auto[0]	80	1			T1	1		T18	1		T204	1
auto[1476395008:1610612735]	auto[1]	10	1			T205	1		T279	1		T332	1
auto[1610612736:1744830463]	auto[0]	87	1			T1	1		T3	1		T4	1
auto[1610612736:1744830463]	auto[1]	17	1			T1	1		T146	1		T135	1
auto[1744830464:1879048191]	auto[0]	82	1			T16	1		T18	1		T46	1
auto[1744830464:1879048191]	auto[1]	12	1			T1	1		T332	1		T385	1
auto[1879048192:2013265919]	auto[0]	103	1			T4	1		T20	1		T204	1
auto[1879048192:2013265919]	auto[1]	8	1			T136	1		T285	1		T243	3
auto[2013265920:2147483647]	auto[0]	117	1			T4	2		T57	1		T201	1
auto[2013265920:2147483647]	auto[1]	13	1			T205	1		T350	1		T280	1
auto[2147483648:2281701375]	auto[0]	90	1			T48	1		T26	1		T30	1
auto[2147483648:2281701375]	auto[1]	10	1			T146	1		T246	1		T251	1
auto[2281701376:2415919103]	auto[0]	95	1			T1	1		T4	3		T48	1
auto[2281701376:2415919103]	auto[1]	7	1			T146	2		T251	1		T232	1
auto[2415919104:2550136831]	auto[0]	91	1			T13	1		T16	1		T20	2
auto[2415919104:2550136831]	auto[1]	9	1			T135	1		T279	1		T351	1
auto[2550136832:2684354559]	auto[0]	109	1			T1	1		T3	2		T83	1
auto[2550136832:2684354559]	auto[1]	8	1			T135	1		T279	1		T385	1
auto[2684354560:2818572287]	auto[0]	89	1			T4	2		T19	1		T202	1
auto[2684354560:2818572287]	auto[1]	6	1			T146	1		T135	2		T289	1
auto[2818572288:2952790015]	auto[0]	105	1			T16	1		T18	1		T19	1
auto[2818572288:2952790015]	auto[1]	5	1			T351	1		T253	1		T398	1
auto[2952790016:3087007743]	auto[0]	102	1			T4	1		T202	1		T57	1
auto[2952790016:3087007743]	auto[1]	12	1			T146	1		T351	2		T284	1
auto[3087007744:3221225471]	auto[0]	82	1			T20	1		T26	2		T57	1
auto[3087007744:3221225471]	auto[1]	3	1			T246	1		T405	1		T404	1
auto[3221225472:3355443199]	auto[0]	98	1			T4	2		T59	1		T202	1
auto[3221225472:3355443199]	auto[1]	8	1			T136	1		T285	1		T345	1
auto[3355443200:3489660927]	auto[0]	79	1			T1	1		T202	1		T57	1
auto[3355443200:3489660927]	auto[1]	12	1			T146	1		T136	1		T332	2
auto[3489660928:3623878655]	auto[0]	99	1			T1	1		T4	1		T46	1
auto[3489660928:3623878655]	auto[1]	7	1			T205	1		T332	1		T289	1
auto[3623878656:3758096383]	auto[0]	83	1			T48	1		T202	1		T201	1
auto[3623878656:3758096383]	auto[1]	5	1			T146	2		T136	1		T351	1
auto[3758096384:3892314111]	auto[0]	106	1			T1	1		T83	1		T57	1
auto[3758096384:3892314111]	auto[1]	15	1			T136	4		T351	1		T284	1
auto[3892314112:4026531839]	auto[0]	95	1			T26	1		T49	1		T203	1
auto[3892314112:4026531839]	auto[1]	7	1			T279	1		T289	2		T295	1
auto[4026531840:4160749567]	auto[0]	95	1			T44	1		T20	1		T57	1
auto[4026531840:4160749567]	auto[1]	6	1			T332	1		T183	1		T253	1
auto[4160749568:4294967295]	auto[0]	92	1			T16	1		T59	1		T199	1
auto[4160749568:4294967295]	auto[1]	7	1			T205	1		T279	1		T351	1