Unified Coverage Report :: Group Instance : attest_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1593

1

T1

2

T2

4

T3

3

auto[1]

1830

1

T1

7

T2

1

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T2	1		T4	1		T46	1
auto[134217728:268435455]	106	1			T3	1		T59	1		T46	1
auto[268435456:402653183]	124	1			T4	3		T59	1		T26	1
auto[402653184:536870911]	126	1			T1	1		T4	2		T199	1
auto[536870912:671088639]	95	1			T1	1		T83	1		T59	1
auto[671088640:805306367]	107	1			T4	1		T44	1		T57	2
auto[805306368:939524095]	110	1			T2	1		T4	2		T26	1
auto[939524096:1073741823]	110	1			T4	1		T57	1		T55	1
auto[1073741824:1207959551]	102	1			T4	2		T59	1		T199	1
auto[1207959552:1342177279]	108	1			T1	1		T4	1		T16	1
auto[1342177280:1476395007]	122	1			T3	1		T4	1		T48	1
auto[1476395008:1610612735]	101	1			T1	1		T2	1		T3	2
auto[1610612736:1744830463]	105	1			T13	1		T48	1		T200	1
auto[1744830464:1879048191]	122	1			T3	1		T4	2		T18	1
auto[1879048192:2013265919]	103	1			T2	1		T45	1		T26	1
auto[2013265920:2147483647]	101	1			T4	1		T83	1		T204	1
auto[2147483648:2281701375]	100	1			T83	1		T19	1		T204	1
auto[2281701376:2415919103]	109	1			T4	1		T20	1		T19	1
auto[2415919104:2550136831]	112	1			T1	1		T2	1		T3	1
auto[2550136832:2684354559]	101	1			T1	1		T13	1		T20	1
auto[2684354560:2818572287]	113	1			T4	1		T18	1		T83	1
auto[2818572288:2952790015]	97	1			T26	1		T57	1		T233	1
auto[2952790016:3087007743]	107	1			T1	1		T16	1		T18	1
auto[3087007744:3221225471]	100	1			T4	1		T20	1		T202	1
auto[3221225472:3355443199]	112	1			T1	1		T4	1		T57	1
auto[3355443200:3489660927]	102	1			T4	1		T20	1		T196	1
auto[3489660928:3623878655]	118	1			T4	1		T46	1		T202	1
auto[3623878656:3758096383]	96	1			T20	1		T57	1		T55	1
auto[3758096384:3892314111]	111	1			T199	1		T57	1		T231	1
auto[3892314112:4026531839]	106	1			T204	1		T57	1		T196	1
auto[4026531840:4160749567]	99	1			T4	2		T44	1		T57	1
auto[4160749568:4294967295]	101	1			T1	1		T4	2		T202	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T2	1		T4	1		T46	1
auto[0:134217727]	auto[1]	53	1			T57	3		T146	1		T67	1
auto[134217728:268435455]	auto[0]	53	1			T59	1		T46	1		T58	2
auto[134217728:268435455]	auto[1]	53	1			T3	1		T135	1		T67	1
auto[268435456:402653183]	auto[0]	66	1			T4	1		T26	1		T201	1
auto[268435456:402653183]	auto[1]	58	1			T4	2		T59	1		T67	1
auto[402653184:536870911]	auto[0]	61	1			T4	2		T212	1		T252	1
auto[402653184:536870911]	auto[1]	65	1			T1	1		T199	1		T204	1
auto[536870912:671088639]	auto[0]	44	1			T83	1		T59	1		T67	1
auto[536870912:671088639]	auto[1]	51	1			T1	1		T26	1		T204	1
auto[671088640:805306367]	auto[0]	61	1			T57	1		T135	1		T67	1
auto[671088640:805306367]	auto[1]	46	1			T4	1		T44	1		T57	1
auto[805306368:939524095]	auto[0]	48	1			T2	1		T200	1		T58	1
auto[805306368:939524095]	auto[1]	62	1			T4	2		T26	1		T70	1
auto[939524096:1073741823]	auto[0]	49	1			T57	1		T85	1		T138	1
auto[939524096:1073741823]	auto[1]	61	1			T4	1		T55	1		T56	1
auto[1073741824:1207959551]	auto[0]	44	1			T4	2		T199	1		T57	1
auto[1073741824:1207959551]	auto[1]	58	1			T59	1		T204	1		T203	1
auto[1207959552:1342177279]	auto[0]	54	1			T4	1		T46	2		T209	1
auto[1207959552:1342177279]	auto[1]	54	1			T1	1		T16	1		T67	1
auto[1342177280:1476395007]	auto[0]	57	1			T3	1		T4	1		T202	1
auto[1342177280:1476395007]	auto[1]	65	1			T48	1		T20	1		T26	1
auto[1476395008:1610612735]	auto[0]	43	1			T2	1		T3	1		T16	1
auto[1476395008:1610612735]	auto[1]	58	1			T1	1		T3	1		T61	1
auto[1610612736:1744830463]	auto[0]	42	1			T13	1		T73	1		T58	1
auto[1610612736:1744830463]	auto[1]	63	1			T48	1		T200	1		T231	1
auto[1744830464:1879048191]	auto[0]	40	1			T4	1		T202	1		T201	1
auto[1744830464:1879048191]	auto[1]	82	1			T3	1		T4	1		T18	1
auto[1879048192:2013265919]	auto[0]	44	1			T2	1		T58	2		T61	1
auto[1879048192:2013265919]	auto[1]	59	1			T45	1		T26	1		T57	2
auto[2013265920:2147483647]	auto[0]	46	1			T83	1		T57	1		T136	1
auto[2013265920:2147483647]	auto[1]	55	1			T4	1		T204	1		T57	1
auto[2147483648:2281701375]	auto[0]	47	1			T19	1		T204	1		T73	1
auto[2147483648:2281701375]	auto[1]	53	1			T83	1		T203	1		T67	2
auto[2281701376:2415919103]	auto[0]	56	1			T4	1		T19	1		T233	1
auto[2281701376:2415919103]	auto[1]	53	1			T20	1		T201	1		T56	1
auto[2415919104:2550136831]	auto[0]	44	1			T3	1		T4	1		T16	1
auto[2415919104:2550136831]	auto[1]	68	1			T1	1		T2	1		T4	1
auto[2550136832:2684354559]	auto[0]	43	1			T1	1		T19	1		T233	1
auto[2550136832:2684354559]	auto[1]	58	1			T13	1		T20	1		T41	2
auto[2684354560:2818572287]	auto[0]	50	1			T198	1		T61	1		T138	2
auto[2684354560:2818572287]	auto[1]	63	1			T4	1		T18	1		T83	1
auto[2818572288:2952790015]	auto[0]	50	1			T47	1		T58	1		T61	1
auto[2818572288:2952790015]	auto[1]	47	1			T26	1		T57	1		T233	1
auto[2952790016:3087007743]	auto[0]	48	1			T1	1		T18	1		T199	1
auto[2952790016:3087007743]	auto[1]	59	1			T16	1		T45	1		T57	1
auto[3087007744:3221225471]	auto[0]	43	1			T4	1		T20	1		T57	1
auto[3087007744:3221225471]	auto[1]	57	1			T202	1		T201	1		T67	3
auto[3221225472:3355443199]	auto[0]	58	1			T57	1		T67	1		T47	1
auto[3221225472:3355443199]	auto[1]	54	1			T1	1		T4	1		T393	1
auto[3355443200:3489660927]	auto[0]	43	1			T4	1		T50	1		T146	1
auto[3355443200:3489660927]	auto[1]	59	1			T20	1		T196	1		T47	1
auto[3489660928:3623878655]	auto[0]	61	1			T4	1		T46	1		T58	2
auto[3489660928:3623878655]	auto[1]	57	1			T202	1		T30	1		T67	2
auto[3623878656:3758096383]	auto[0]	42	1			T58	2		T138	1		T51	1
auto[3623878656:3758096383]	auto[1]	54	1			T20	1		T57	1		T55	1
auto[3758096384:3892314111]	auto[0]	60	1			T199	1		T57	1		T58	1
auto[3758096384:3892314111]	auto[1]	51	1			T231	1		T146	1		T58	1
auto[3892314112:4026531839]	auto[0]	48	1			T204	1		T67	1		T61	1
auto[3892314112:4026531839]	auto[1]	58	1			T57	1		T196	1		T41	1
auto[4026531840:4160749567]	auto[0]	57	1			T4	2		T44	1		T57	1
auto[4026531840:4160749567]	auto[1]	42	1			T67	1		T58	1		T242	1
auto[4160749568:4294967295]	auto[0]	47	1			T4	1		T202	1		T57	2
auto[4160749568:4294967295]	auto[1]	54	1			T1	1		T4	1		T55	1