Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7119

1

T1

16

T2

2

T3

11

auto[1]

304

1

T1

4

T146

16

T135

16

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2990	1			T1	7		T2	1		T3	5
auto[134217728:268435455]	162	1			T18	1		T204	1		T57	2
auto[268435456:402653183]	162	1			T1	1		T18	1		T44	1
auto[402653184:536870911]	150	1			T57	1		T231	1		T203	1
auto[536870912:671088639]	146	1			T3	1		T4	1		T59	1
auto[671088640:805306367]	147	1			T1	1		T3	1		T4	3
auto[805306368:939524095]	131	1			T4	1		T202	1		T55	1
auto[939524096:1073741823]	141	1			T199	1		T20	1		T46	1
auto[1073741824:1207959551]	141	1			T3	1		T4	1		T18	1
auto[1207959552:1342177279]	136	1			T18	1		T26	1		T202	1
auto[1342177280:1476395007]	131	1			T4	1		T16	1		T199	1
auto[1476395008:1610612735]	126	1			T4	1		T20	1		T55	1
auto[1610612736:1744830463]	164	1			T4	2		T18	1		T26	1
auto[1744830464:1879048191]	146	1			T1	1		T16	1		T18	1
auto[1879048192:2013265919]	145	1			T4	1		T26	1		T202	1
auto[2013265920:2147483647]	145	1			T1	1		T16	1		T59	2
auto[2147483648:2281701375]	130	1			T1	1		T4	1		T57	1
auto[2281701376:2415919103]	143	1			T2	1		T4	2		T199	1
auto[2415919104:2550136831]	132	1			T13	1		T4	3		T16	1
auto[2550136832:2684354559]	151	1			T4	3		T48	1		T20	1
auto[2684354560:2818572287]	126	1			T3	1		T4	1		T26	1
auto[2818572288:2952790015]	155	1			T13	1		T4	1		T200	1
auto[2952790016:3087007743]	142	1			T1	2		T18	1		T73	1
auto[3087007744:3221225471]	137	1			T4	1		T18	1		T83	1
auto[3221225472:3355443199]	145	1			T18	2		T20	1		T202	1
auto[3355443200:3489660927]	120	1			T1	2		T20	2		T26	1
auto[3489660928:3623878655]	153	1			T3	2		T26	1		T202	1
auto[3623878656:3758096383]	142	1			T1	1		T4	2		T16	1
auto[3758096384:3892314111]	151	1			T16	1		T20	1		T196	1
auto[3892314112:4026531839]	150	1			T1	1		T4	2		T26	1
auto[4026531840:4160749567]	134	1			T1	1		T4	1		T83	1
auto[4160749568:4294967295]	149	1			T1	1		T19	1		T49	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2980	1			T1	7		T2	1		T3	5
auto[0:134217727]	auto[1]	10	1			T146	1		T135	1		T136	1
auto[134217728:268435455]	auto[0]	157	1			T18	1		T204	1		T57	2
auto[134217728:268435455]	auto[1]	5	1			T146	1		T385	1		T246	1
auto[268435456:402653183]	auto[0]	155	1			T18	1		T44	1		T202	1
auto[268435456:402653183]	auto[1]	7	1			T1	1		T135	2		T246	1
auto[402653184:536870911]	auto[0]	142	1			T57	1		T231	1		T203	1
auto[402653184:536870911]	auto[1]	8	1			T135	1		T280	1		T284	1
auto[536870912:671088639]	auto[0]	136	1			T3	1		T4	1		T59	1
auto[536870912:671088639]	auto[1]	10	1			T146	2		T135	1		T350	1
auto[671088640:805306367]	auto[0]	139	1			T1	1		T3	1		T4	3
auto[671088640:805306367]	auto[1]	8	1			T135	1		T205	1		T136	1
auto[805306368:939524095]	auto[0]	125	1			T4	1		T202	1		T55	1
auto[805306368:939524095]	auto[1]	6	1			T279	1		T332	1		T251	1
auto[939524096:1073741823]	auto[0]	134	1			T199	1		T20	1		T46	1
auto[939524096:1073741823]	auto[1]	7	1			T146	1		T246	1		T289	1
auto[1073741824:1207959551]	auto[0]	132	1			T3	1		T4	1		T18	1
auto[1073741824:1207959551]	auto[1]	9	1			T332	1		T253	1		T260	1
auto[1207959552:1342177279]	auto[0]	129	1			T18	1		T26	1		T202	1
auto[1207959552:1342177279]	auto[1]	7	1			T146	1		T356	1		T253	1
auto[1342177280:1476395007]	auto[0]	120	1			T4	1		T16	1		T199	1
auto[1342177280:1476395007]	auto[1]	11	1			T332	1		T385	1		T399	1
auto[1476395008:1610612735]	auto[0]	114	1			T4	1		T20	1		T55	1
auto[1476395008:1610612735]	auto[1]	12	1			T135	2		T284	1		T398	1
auto[1610612736:1744830463]	auto[0]	154	1			T4	2		T18	1		T26	1
auto[1610612736:1744830463]	auto[1]	10	1			T146	2		T135	1		T332	1
auto[1744830464:1879048191]	auto[0]	138	1			T1	1		T16	1		T18	1
auto[1744830464:1879048191]	auto[1]	8	1			T136	1		T246	1		T260	1
auto[1879048192:2013265919]	auto[0]	136	1			T4	1		T26	1		T202	1
auto[1879048192:2013265919]	auto[1]	9	1			T136	2		T356	1		T398	1
auto[2013265920:2147483647]	auto[0]	139	1			T1	1		T16	1		T59	2
auto[2013265920:2147483647]	auto[1]	6	1			T284	1		T402	1		T295	1
auto[2147483648:2281701375]	auto[0]	116	1			T1	1		T4	1		T57	1
auto[2147483648:2281701375]	auto[1]	14	1			T146	2		T135	1		T205	1
auto[2281701376:2415919103]	auto[0]	132	1			T2	1		T4	2		T199	1
auto[2281701376:2415919103]	auto[1]	11	1			T146	1		T136	1		T280	1
auto[2415919104:2550136831]	auto[0]	124	1			T13	1		T4	3		T16	1
auto[2415919104:2550136831]	auto[1]	8	1			T146	1		T136	1		T350	1
auto[2550136832:2684354559]	auto[0]	143	1			T4	3		T48	1		T20	1
auto[2550136832:2684354559]	auto[1]	8	1			T246	2		T284	1		T253	1
auto[2684354560:2818572287]	auto[0]	118	1			T3	1		T4	1		T26	1
auto[2684354560:2818572287]	auto[1]	8	1			T136	2		T183	1		T253	1
auto[2818572288:2952790015]	auto[0]	144	1			T13	1		T4	1		T200	1
auto[2818572288:2952790015]	auto[1]	11	1			T332	2		T351	1		T295	1
auto[2952790016:3087007743]	auto[0]	132	1			T1	1		T18	1		T73	1
auto[2952790016:3087007743]	auto[1]	10	1			T1	1		T135	1		T136	1
auto[3087007744:3221225471]	auto[0]	127	1			T4	1		T18	1		T83	1
auto[3087007744:3221225471]	auto[1]	10	1			T146	1		T135	1		T345	1
auto[3221225472:3355443199]	auto[0]	131	1			T18	2		T20	1		T202	1
auto[3221225472:3355443199]	auto[1]	14	1			T146	2		T136	1		T279	1
auto[3355443200:3489660927]	auto[0]	110	1			T1	1		T20	2		T26	1
auto[3355443200:3489660927]	auto[1]	10	1			T1	1		T279	1		T351	1
auto[3489660928:3623878655]	auto[0]	144	1			T3	2		T26	1		T202	1
auto[3489660928:3623878655]	auto[1]	9	1			T136	1		T332	1		T351	1
auto[3623878656:3758096383]	auto[0]	129	1			T1	1		T4	2		T16	1
auto[3623878656:3758096383]	auto[1]	13	1			T183	1		T399	1		T260	2
auto[3758096384:3892314111]	auto[0]	140	1			T16	1		T20	1		T196	1
auto[3758096384:3892314111]	auto[1]	11	1			T135	1		T280	1		T246	1
auto[3892314112:4026531839]	auto[0]	138	1			T1	1		T4	2		T26	1
auto[3892314112:4026531839]	auto[1]	12	1			T146	1		T135	1		T332	1
auto[4026531840:4160749567]	auto[0]	119	1			T4	1		T83	1		T20	1
auto[4026531840:4160749567]	auto[1]	15	1			T1	1		T135	1		T136	1
auto[4160749568:4294967295]	auto[0]	142	1			T1	1		T19	1		T49	1
auto[4160749568:4294967295]	auto[1]	7	1			T135	1		T385	1		T251	3