Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4638

1

T1

14

T2

8

T3

10

auto[1]

2208

1

T1

4

T2

2

T3

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	202	1			T48	2		T204	2		T203	2
auto[134217728:268435455]	196	1			T1	2		T83	4		T204	2
auto[268435456:402653183]	230	1			T4	2		T202	2		T57	2
auto[402653184:536870911]	180	1			T1	2		T2	2		T18	2
auto[536870912:671088639]	208	1			T1	2		T44	2		T204	2
auto[671088640:805306367]	208	1			T4	2		T83	2		T196	2
auto[805306368:939524095]	212	1			T2	2		T4	2		T16	2
auto[939524096:1073741823]	222	1			T13	2		T4	4		T57	2
auto[1073741824:1207959551]	208	1			T3	2		T4	2		T46	2
auto[1207959552:1342177279]	210	1			T202	2		T57	2		T201	2
auto[1342177280:1476395007]	238	1			T4	2		T59	2		T20	2
auto[1476395008:1610612735]	232	1			T4	4		T19	2		T57	2
auto[1610612736:1744830463]	228	1			T16	2		T18	2		T59	2
auto[1744830464:1879048191]	216	1			T16	2		T46	2		T202	4
auto[1879048192:2013265919]	228	1			T4	2		T20	4		T30	2
auto[2013265920:2147483647]	212	1			T4	6		T16	2		T19	4
auto[2147483648:2281701375]	244	1			T83	2		T202	4		T50	2
auto[2281701376:2415919103]	256	1			T83	2		T46	2		T204	2
auto[2415919104:2550136831]	180	1			T4	2		T45	2		T20	2
auto[2550136832:2684354559]	214	1			T1	2		T2	2		T3	2
auto[2684354560:2818572287]	162	1			T20	2		T26	2		T57	2
auto[2818572288:2952790015]	230	1			T3	2		T4	4		T57	4
auto[2952790016:3087007743]	252	1			T4	4		T48	2		T46	2
auto[3087007744:3221225471]	190	1			T3	2		T4	2		T201	2
auto[3221225472:3355443199]	210	1			T1	2		T4	2		T199	2
auto[3355443200:3489660927]	210	1			T1	2		T199	2		T57	2
auto[3489660928:3623878655]	238	1			T48	2		T20	2		T26	2
auto[3623878656:3758096383]	212	1			T2	2		T4	4		T67	2
auto[3758096384:3892314111]	204	1			T1	2		T3	2		T4	2
auto[3892314112:4026531839]	190	1			T3	2		T4	2		T199	2
auto[4026531840:4160749567]	198	1			T13	2		T4	4		T57	2
auto[4160749568:4294967295]	226	1			T1	4		T2	2		T4	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	132	1			T48	2		T204	2		T67	2
auto[0:134217727]	auto[1]	70	1			T203	2		T233	2		T37	2
auto[134217728:268435455]	auto[0]	144	1			T1	2		T83	2		T204	2
auto[134217728:268435455]	auto[1]	52	1			T83	2		T61	2		T214	2
auto[268435456:402653183]	auto[0]	170	1			T4	2		T202	2		T55	2
auto[268435456:402653183]	auto[1]	60	1			T57	2		T41	2		T61	2
auto[402653184:536870911]	auto[0]	106	1			T1	2		T2	2		T202	2
auto[402653184:536870911]	auto[1]	74	1			T18	2		T44	2		T57	2
auto[536870912:671088639]	auto[0]	138	1			T1	2		T204	2		T200	2
auto[536870912:671088639]	auto[1]	70	1			T44	2		T67	2		T71	2
auto[671088640:805306367]	auto[0]	146	1			T4	2		T83	2		T198	2
auto[671088640:805306367]	auto[1]	62	1			T196	2		T61	2		T23	2
auto[805306368:939524095]	auto[0]	160	1			T2	2		T16	2		T20	2
auto[805306368:939524095]	auto[1]	52	1			T4	2		T61	2		T6	2
auto[939524096:1073741823]	auto[0]	148	1			T4	4		T57	2		T201	2
auto[939524096:1073741823]	auto[1]	74	1			T13	2		T235	2		T214	4
auto[1073741824:1207959551]	auto[0]	138	1			T3	2		T4	2		T46	2
auto[1073741824:1207959551]	auto[1]	70	1			T200	2		T70	2		T67	2
auto[1207959552:1342177279]	auto[0]	136	1			T202	2		T57	2		T201	2
auto[1207959552:1342177279]	auto[1]	74	1			T105	2		T252	2		T235	2
auto[1342177280:1476395007]	auto[0]	168	1			T59	2		T46	2		T57	2
auto[1342177280:1476395007]	auto[1]	70	1			T4	2		T20	2		T235	2
auto[1476395008:1610612735]	auto[0]	166	1			T4	2		T19	2		T57	2
auto[1476395008:1610612735]	auto[1]	66	1			T4	2		T61	2		T53	2
auto[1610612736:1744830463]	auto[0]	152	1			T59	2		T204	2		T230	2
auto[1610612736:1744830463]	auto[1]	76	1			T16	2		T18	2		T45	2
auto[1744830464:1879048191]	auto[0]	158	1			T16	2		T202	4		T57	2
auto[1744830464:1879048191]	auto[1]	58	1			T46	2		T196	2		T86	2
auto[1879048192:2013265919]	auto[0]	160	1			T4	2		T20	2		T30	2
auto[1879048192:2013265919]	auto[1]	68	1			T20	2		T196	2		T49	2
auto[2013265920:2147483647]	auto[0]	140	1			T4	6		T16	2		T19	4
auto[2013265920:2147483647]	auto[1]	72	1			T58	4		T369	2		T6	4
auto[2147483648:2281701375]	auto[0]	170	1			T202	2		T50	2		T198	2
auto[2147483648:2281701375]	auto[1]	74	1			T83	2		T202	2		T135	2
auto[2281701376:2415919103]	auto[0]	188	1			T83	2		T46	2		T204	2
auto[2281701376:2415919103]	auto[1]	68	1			T58	2		T5	2		T137	2
auto[2415919104:2550136831]	auto[0]	130	1			T4	2		T26	2		T47	2
auto[2415919104:2550136831]	auto[1]	50	1			T45	2		T20	2		T26	2
auto[2550136832:2684354559]	auto[0]	142	1			T2	2		T4	2		T59	2
auto[2550136832:2684354559]	auto[1]	72	1			T1	2		T3	2		T4	2
auto[2684354560:2818572287]	auto[0]	122	1			T26	2		T57	2		T58	4
auto[2684354560:2818572287]	auto[1]	40	1			T20	2		T213	2		T190	2
auto[2818572288:2952790015]	auto[0]	148	1			T3	2		T4	2		T57	2
auto[2818572288:2952790015]	auto[1]	82	1			T4	2		T57	2		T242	2
auto[2952790016:3087007743]	auto[0]	160	1			T4	2		T48	2		T46	2
auto[2952790016:3087007743]	auto[1]	92	1			T4	2		T204	2		T58	2
auto[3087007744:3221225471]	auto[0]	130	1			T3	2		T4	2		T201	2
auto[3087007744:3221225471]	auto[1]	60	1			T174	2		T252	2		T138	2
auto[3221225472:3355443199]	auto[0]	130	1			T1	2		T4	2		T19	2
auto[3221225472:3355443199]	auto[1]	80	1			T199	2		T73	2		T67	2
auto[3355443200:3489660927]	auto[0]	146	1			T1	2		T57	2		T198	2
auto[3355443200:3489660927]	auto[1]	64	1			T199	2		T395	2		T136	2
auto[3489660928:3623878655]	auto[0]	150	1			T20	2		T26	2		T202	2
auto[3489660928:3623878655]	auto[1]	88	1			T48	2		T194	2		T252	2
auto[3623878656:3758096383]	auto[0]	132	1			T2	2		T56	2		T58	2
auto[3623878656:3758096383]	auto[1]	80	1			T4	4		T67	2		T105	2
auto[3758096384:3892314111]	auto[0]	140	1			T1	2		T3	2		T59	2
auto[3758096384:3892314111]	auto[1]	64	1			T4	2		T18	2		T146	2
auto[3892314112:4026531839]	auto[0]	136	1			T3	2		T4	2		T204	2
auto[3892314112:4026531839]	auto[1]	54	1			T199	2		T57	2		T201	2
auto[4026531840:4160749567]	auto[0]	108	1			T13	2		T4	4		T200	2
auto[4026531840:4160749567]	auto[1]	90	1			T57	2		T233	2		T112	2
auto[4160749568:4294967295]	auto[0]	144	1			T1	2		T57	2		T201	2
auto[4160749568:4294967295]	auto[1]	82	1			T1	2		T2	2		T4	2