Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.04 97.99 98.37 100.00 99.02 98.41 91.22


Total test records in report: 1084
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1010 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3796603841 Aug 10 04:42:21 PM PDT 24 Aug 10 04:42:23 PM PDT 24 82625722 ps
T1011 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1389302571 Aug 10 04:42:23 PM PDT 24 Aug 10 04:42:26 PM PDT 24 84502324 ps
T1012 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1749118156 Aug 10 04:42:30 PM PDT 24 Aug 10 04:42:32 PM PDT 24 88853405 ps
T1013 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3970729392 Aug 10 04:42:33 PM PDT 24 Aug 10 04:42:36 PM PDT 24 139218628 ps
T1014 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1164365442 Aug 10 04:42:44 PM PDT 24 Aug 10 04:42:45 PM PDT 24 112463758 ps
T1015 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2634414063 Aug 10 04:42:19 PM PDT 24 Aug 10 04:42:20 PM PDT 24 92284810 ps
T1016 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1170291214 Aug 10 04:42:35 PM PDT 24 Aug 10 04:42:36 PM PDT 24 26583596 ps
T1017 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1530790007 Aug 10 04:42:33 PM PDT 24 Aug 10 04:42:35 PM PDT 24 128662577 ps
T1018 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.683473954 Aug 10 04:42:33 PM PDT 24 Aug 10 04:42:36 PM PDT 24 14390212 ps
T1019 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1214782232 Aug 10 04:42:42 PM PDT 24 Aug 10 04:42:43 PM PDT 24 20578622 ps
T1020 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.939941881 Aug 10 04:42:35 PM PDT 24 Aug 10 04:42:36 PM PDT 24 20664909 ps
T1021 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.985037485 Aug 10 04:42:06 PM PDT 24 Aug 10 04:42:10 PM PDT 24 413321900 ps
T159 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4129557787 Aug 10 04:42:31 PM PDT 24 Aug 10 04:42:35 PM PDT 24 215834737 ps
T1022 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3851521252 Aug 10 04:42:08 PM PDT 24 Aug 10 04:42:10 PM PDT 24 28625473 ps
T1023 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2754273591 Aug 10 04:42:32 PM PDT 24 Aug 10 04:42:38 PM PDT 24 1164761272 ps
T158 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2979486274 Aug 10 04:42:31 PM PDT 24 Aug 10 04:42:37 PM PDT 24 497340222 ps
T1024 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1145415941 Aug 10 04:42:43 PM PDT 24 Aug 10 04:42:43 PM PDT 24 39950589 ps
T163 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1627653649 Aug 10 04:42:20 PM PDT 24 Aug 10 04:42:25 PM PDT 24 390976711 ps
T1025 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3306400681 Aug 10 04:42:33 PM PDT 24 Aug 10 04:42:35 PM PDT 24 31982167 ps
T1026 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1060045408 Aug 10 04:42:49 PM PDT 24 Aug 10 04:42:50 PM PDT 24 11504110 ps
T1027 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1095325644 Aug 10 04:42:46 PM PDT 24 Aug 10 04:42:47 PM PDT 24 80003160 ps
T1028 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3560034485 Aug 10 04:42:34 PM PDT 24 Aug 10 04:42:36 PM PDT 24 631670811 ps
T1029 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2646547127 Aug 10 04:42:20 PM PDT 24 Aug 10 04:42:22 PM PDT 24 42857738 ps
T1030 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1649836608 Aug 10 04:42:30 PM PDT 24 Aug 10 04:42:33 PM PDT 24 255777555 ps
T1031 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2350450249 Aug 10 04:42:22 PM PDT 24 Aug 10 04:42:23 PM PDT 24 46276991 ps
T1032 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.596240335 Aug 10 04:42:36 PM PDT 24 Aug 10 04:42:38 PM PDT 24 153399728 ps
T1033 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1290693378 Aug 10 04:42:33 PM PDT 24 Aug 10 04:42:36 PM PDT 24 307952078 ps
T1034 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2489509090 Aug 10 04:42:37 PM PDT 24 Aug 10 04:42:38 PM PDT 24 27085911 ps
T1035 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.4211168219 Aug 10 04:42:23 PM PDT 24 Aug 10 04:42:26 PM PDT 24 111664353 ps
T1036 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2945683017 Aug 10 04:42:08 PM PDT 24 Aug 10 04:42:33 PM PDT 24 1779323154 ps
T164 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2503548088 Aug 10 04:42:35 PM PDT 24 Aug 10 04:42:39 PM PDT 24 233159450 ps
T1037 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2452017467 Aug 10 04:42:21 PM PDT 24 Aug 10 04:42:25 PM PDT 24 362936525 ps
T1038 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3255864551 Aug 10 04:42:07 PM PDT 24 Aug 10 04:42:09 PM PDT 24 20716480 ps
T1039 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2493761426 Aug 10 04:42:35 PM PDT 24 Aug 10 04:42:37 PM PDT 24 27619979 ps
T1040 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3697253069 Aug 10 04:42:44 PM PDT 24 Aug 10 04:42:45 PM PDT 24 42555985 ps
T1041 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3452280801 Aug 10 04:42:21 PM PDT 24 Aug 10 04:42:22 PM PDT 24 13398032 ps
T1042 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1185158353 Aug 10 04:42:35 PM PDT 24 Aug 10 04:42:36 PM PDT 24 23150043 ps
T1043 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3544149586 Aug 10 04:42:35 PM PDT 24 Aug 10 04:42:44 PM PDT 24 175290842 ps
T1044 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1047288604 Aug 10 04:42:24 PM PDT 24 Aug 10 04:42:25 PM PDT 24 138866598 ps
T1045 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3106942521 Aug 10 04:42:20 PM PDT 24 Aug 10 04:42:23 PM PDT 24 173148153 ps
T1046 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1553836035 Aug 10 04:42:32 PM PDT 24 Aug 10 04:42:37 PM PDT 24 2638688031 ps
T166 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2597823759 Aug 10 04:42:21 PM PDT 24 Aug 10 04:42:27 PM PDT 24 121742546 ps
T1047 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2466679989 Aug 10 04:42:46 PM PDT 24 Aug 10 04:42:46 PM PDT 24 19247073 ps
T1048 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1855087080 Aug 10 04:42:20 PM PDT 24 Aug 10 04:42:33 PM PDT 24 439967942 ps
T1049 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.233856267 Aug 10 04:42:48 PM PDT 24 Aug 10 04:42:51 PM PDT 24 925861844 ps
T1050 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3351558430 Aug 10 04:42:24 PM PDT 24 Aug 10 04:42:30 PM PDT 24 304921442 ps
T1051 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2714217778 Aug 10 04:42:20 PM PDT 24 Aug 10 04:42:24 PM PDT 24 366089545 ps
T1052 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3146386684 Aug 10 04:42:22 PM PDT 24 Aug 10 04:42:28 PM PDT 24 677539411 ps
T1053 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1041502970 Aug 10 04:42:20 PM PDT 24 Aug 10 04:42:22 PM PDT 24 25712735 ps
T1054 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.677449913 Aug 10 04:42:22 PM PDT 24 Aug 10 04:42:23 PM PDT 24 41109114 ps
T1055 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1707724087 Aug 10 04:42:37 PM PDT 24 Aug 10 04:42:42 PM PDT 24 166700373 ps
T170 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2901693997 Aug 10 04:42:38 PM PDT 24 Aug 10 04:42:41 PM PDT 24 112380778 ps
T1056 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.4289689575 Aug 10 04:42:32 PM PDT 24 Aug 10 04:42:36 PM PDT 24 89299531 ps
T1057 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.620777334 Aug 10 04:42:41 PM PDT 24 Aug 10 04:42:42 PM PDT 24 813223389 ps
T1058 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.349211296 Aug 10 04:41:57 PM PDT 24 Aug 10 04:42:09 PM PDT 24 3295562050 ps
T1059 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1010787094 Aug 10 04:42:21 PM PDT 24 Aug 10 04:42:24 PM PDT 24 82427189 ps
T1060 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2699448560 Aug 10 04:42:32 PM PDT 24 Aug 10 04:42:34 PM PDT 24 12546189 ps
T1061 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1258309655 Aug 10 04:42:44 PM PDT 24 Aug 10 04:42:44 PM PDT 24 38118678 ps
T1062 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3157065545 Aug 10 04:42:20 PM PDT 24 Aug 10 04:42:29 PM PDT 24 133548460 ps
T1063 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.731211612 Aug 10 04:42:25 PM PDT 24 Aug 10 04:42:27 PM PDT 24 68965805 ps
T1064 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3594305935 Aug 10 04:41:56 PM PDT 24 Aug 10 04:41:58 PM PDT 24 233681194 ps
T1065 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.315566839 Aug 10 04:42:21 PM PDT 24 Aug 10 04:42:23 PM PDT 24 33348547 ps
T1066 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.385216197 Aug 10 04:42:24 PM PDT 24 Aug 10 04:42:25 PM PDT 24 293167699 ps
T171 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3077681780 Aug 10 04:42:25 PM PDT 24 Aug 10 04:42:28 PM PDT 24 179814409 ps
T1067 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3134380115 Aug 10 04:42:40 PM PDT 24 Aug 10 04:42:41 PM PDT 24 11676753 ps
T173 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2993227620 Aug 10 04:42:20 PM PDT 24 Aug 10 04:42:25 PM PDT 24 101489979 ps
T1068 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.787604204 Aug 10 04:42:43 PM PDT 24 Aug 10 04:42:44 PM PDT 24 52586998 ps
T1069 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4289597571 Aug 10 04:42:51 PM PDT 24 Aug 10 04:42:52 PM PDT 24 10024467 ps
T1070 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3515034544 Aug 10 04:42:43 PM PDT 24 Aug 10 04:42:44 PM PDT 24 16311089 ps
T1071 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3745960621 Aug 10 04:42:32 PM PDT 24 Aug 10 04:42:44 PM PDT 24 2039440680 ps
T1072 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3034959958 Aug 10 04:42:48 PM PDT 24 Aug 10 04:42:50 PM PDT 24 14685980 ps
T1073 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.585449894 Aug 10 04:42:22 PM PDT 24 Aug 10 04:42:24 PM PDT 24 156316956 ps
T165 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1806309899 Aug 10 04:42:37 PM PDT 24 Aug 10 04:42:41 PM PDT 24 81999335 ps
T1074 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1858080764 Aug 10 04:42:07 PM PDT 24 Aug 10 04:42:08 PM PDT 24 55273005 ps
T1075 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3073180960 Aug 10 04:42:19 PM PDT 24 Aug 10 04:42:21 PM PDT 24 47078121 ps
T1076 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2429163226 Aug 10 04:42:20 PM PDT 24 Aug 10 04:42:25 PM PDT 24 210612332 ps
T1077 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.269956989 Aug 10 04:42:19 PM PDT 24 Aug 10 04:42:26 PM PDT 24 138696507 ps
T1078 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3117437493 Aug 10 04:42:21 PM PDT 24 Aug 10 04:42:26 PM PDT 24 143102769 ps
T1079 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3412184659 Aug 10 04:42:09 PM PDT 24 Aug 10 04:42:18 PM PDT 24 783991785 ps
T1080 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3329406561 Aug 10 04:42:34 PM PDT 24 Aug 10 04:42:46 PM PDT 24 3917386727 ps
T1081 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.281235874 Aug 10 04:42:47 PM PDT 24 Aug 10 04:42:49 PM PDT 24 28220322 ps
T1082 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3831193935 Aug 10 04:42:09 PM PDT 24 Aug 10 04:42:10 PM PDT 24 21734310 ps
T1083 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3718317606 Aug 10 04:42:21 PM PDT 24 Aug 10 04:42:23 PM PDT 24 70202115 ps
T1084 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.805721288 Aug 10 04:42:24 PM PDT 24 Aug 10 04:42:25 PM PDT 24 24668613 ps

Test location /workspace/coverage/default/21.keymgr_stress_all.873547383
Short name T4
Test name
Test status
Simulation time 4493499999 ps
CPU time 29.13 seconds
Started Aug 10 04:53:39 PM PDT 24
Finished Aug 10 04:54:09 PM PDT 24
Peak memory 215912 kb
Host smart-9092a685-991b-4c2b-8697-64995cd9e13e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873547383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.873547383
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.658005527
Short name T58
Test name
Test status
Simulation time 22471779644 ps
CPU time 77.19 seconds
Started Aug 10 04:54:13 PM PDT 24
Finished Aug 10 04:55:31 PM PDT 24
Peak memory 222532 kb
Host smart-58dadd3a-4d10-4511-82ee-913122d307ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658005527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.658005527
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2822615444
Short name T127
Test name
Test status
Simulation time 2277532501 ps
CPU time 12.48 seconds
Started Aug 10 04:55:51 PM PDT 24
Finished Aug 10 04:56:04 PM PDT 24
Peak memory 222440 kb
Host smart-675b1d82-930d-480b-b41b-b6207dfd10e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822615444 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2822615444
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3033759045
Short name T10
Test name
Test status
Simulation time 549112400 ps
CPU time 7.01 seconds
Started Aug 10 04:51:20 PM PDT 24
Finished Aug 10 04:51:27 PM PDT 24
Peak memory 238060 kb
Host smart-a19d6e28-0932-4778-b013-6cc13c23aa27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033759045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3033759045
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1186225466
Short name T16
Test name
Test status
Simulation time 251224164 ps
CPU time 9.84 seconds
Started Aug 10 04:55:05 PM PDT 24
Finished Aug 10 04:55:15 PM PDT 24
Peak memory 222456 kb
Host smart-ee2f65c7-d9aa-4444-862c-8305be003fd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186225466 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1186225466
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2816216437
Short name T67
Test name
Test status
Simulation time 3738645235 ps
CPU time 35.16 seconds
Started Aug 10 04:54:53 PM PDT 24
Finished Aug 10 04:55:29 PM PDT 24
Peak memory 222572 kb
Host smart-50b15662-4714-4a1a-a26e-14a5d77d46e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816216437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2816216437
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3678674790
Short name T146
Test name
Test status
Simulation time 4355710777 ps
CPU time 55.91 seconds
Started Aug 10 04:53:24 PM PDT 24
Finished Aug 10 04:54:20 PM PDT 24
Peak memory 215848 kb
Host smart-d9d0dcc7-10d3-4646-9523-ac4d824b7fdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3678674790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3678674790
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3313675630
Short name T53
Test name
Test status
Simulation time 120864103 ps
CPU time 2.61 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:38 PM PDT 24
Peak memory 221336 kb
Host smart-2d14b175-c3e6-4c7e-9afe-c88c0d01f45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313675630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3313675630
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2449783468
Short name T116
Test name
Test status
Simulation time 656064535 ps
CPU time 13.49 seconds
Started Aug 10 04:42:31 PM PDT 24
Finished Aug 10 04:42:45 PM PDT 24
Peak memory 214608 kb
Host smart-d0f711fa-4cfc-4a3a-a849-b0e37ea70e01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449783468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2449783468
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3604154949
Short name T8
Test name
Test status
Simulation time 746884164 ps
CPU time 4.92 seconds
Started Aug 10 04:54:39 PM PDT 24
Finished Aug 10 04:54:44 PM PDT 24
Peak memory 214516 kb
Host smart-0d28127f-9b01-4b6a-99b9-5ff046858ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604154949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3604154949
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1777222603
Short name T57
Test name
Test status
Simulation time 1362867704 ps
CPU time 18.2 seconds
Started Aug 10 04:55:13 PM PDT 24
Finished Aug 10 04:55:32 PM PDT 24
Peak memory 222416 kb
Host smart-325060a0-7512-4b96-bfa9-f96a8703b830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777222603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1777222603
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1234864803
Short name T351
Test name
Test status
Simulation time 130618734 ps
CPU time 7.15 seconds
Started Aug 10 04:55:15 PM PDT 24
Finished Aug 10 04:55:22 PM PDT 24
Peak memory 214192 kb
Host smart-f8041c59-3efc-4f07-94e1-331b8cae569e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1234864803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1234864803
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.915293404
Short name T61
Test name
Test status
Simulation time 840154977 ps
CPU time 33.87 seconds
Started Aug 10 04:52:43 PM PDT 24
Finished Aug 10 04:53:17 PM PDT 24
Peak memory 221468 kb
Host smart-f024a50d-cf32-41f6-918e-7fcfaf51bbaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915293404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.915293404
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2547842601
Short name T136
Test name
Test status
Simulation time 455137091 ps
CPU time 7.08 seconds
Started Aug 10 04:54:53 PM PDT 24
Finished Aug 10 04:55:00 PM PDT 24
Peak memory 215484 kb
Host smart-ef9ef51b-2186-46b8-8616-9f0c1a14fd65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2547842601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2547842601
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1653546779
Short name T41
Test name
Test status
Simulation time 420901794 ps
CPU time 5.07 seconds
Started Aug 10 04:53:51 PM PDT 24
Finished Aug 10 04:53:56 PM PDT 24
Peak memory 222360 kb
Host smart-b035e3df-7414-4a0a-966d-094326d05c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653546779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1653546779
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.874436174
Short name T87
Test name
Test status
Simulation time 1354772324 ps
CPU time 8.89 seconds
Started Aug 10 04:54:30 PM PDT 24
Finished Aug 10 04:54:39 PM PDT 24
Peak memory 222116 kb
Host smart-dcb61d33-2ec3-466d-884e-49b15686341e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874436174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.874436174
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3330940166
Short name T284
Test name
Test status
Simulation time 559321860 ps
CPU time 15.02 seconds
Started Aug 10 04:53:34 PM PDT 24
Finished Aug 10 04:53:49 PM PDT 24
Peak memory 215040 kb
Host smart-2d73cd01-c790-4433-924a-9e3170981289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3330940166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3330940166
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1598383517
Short name T214
Test name
Test status
Simulation time 2069760373 ps
CPU time 27.1 seconds
Started Aug 10 04:53:33 PM PDT 24
Finished Aug 10 04:54:01 PM PDT 24
Peak memory 215116 kb
Host smart-1aa8d45a-0694-4139-ae34-824982b53bd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598383517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1598383517
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2230029123
Short name T135
Test name
Test status
Simulation time 6025618837 ps
CPU time 61.62 seconds
Started Aug 10 04:55:24 PM PDT 24
Finished Aug 10 04:56:26 PM PDT 24
Peak memory 214300 kb
Host smart-4cddd64a-7940-412b-adc8-3a734765e7f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230029123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2230029123
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3580556775
Short name T56
Test name
Test status
Simulation time 162358190 ps
CPU time 3.55 seconds
Started Aug 10 04:54:55 PM PDT 24
Finished Aug 10 04:54:58 PM PDT 24
Peak memory 218000 kb
Host smart-1634ac46-4991-41c4-9158-e8c717c25fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580556775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3580556775
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2972226442
Short name T22
Test name
Test status
Simulation time 80125392 ps
CPU time 3.48 seconds
Started Aug 10 04:50:22 PM PDT 24
Finished Aug 10 04:50:25 PM PDT 24
Peak memory 221180 kb
Host smart-15e689a3-356d-47d0-8eaf-88394d2384b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972226442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2972226442
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_random.2624923977
Short name T3
Test name
Test status
Simulation time 97427806 ps
CPU time 3.68 seconds
Started Aug 10 04:53:09 PM PDT 24
Finished Aug 10 04:53:12 PM PDT 24
Peak memory 214340 kb
Host smart-2db9bafb-df7c-4f64-9fde-015d647d236a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624923977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2624923977
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1912935647
Short name T39
Test name
Test status
Simulation time 103035958 ps
CPU time 3.57 seconds
Started Aug 10 04:55:03 PM PDT 24
Finished Aug 10 04:55:07 PM PDT 24
Peak memory 218444 kb
Host smart-82de45cc-759d-46ed-841e-0ca8bda55f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912935647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1912935647
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.4059523860
Short name T144
Test name
Test status
Simulation time 1699351442 ps
CPU time 14.1 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:34 PM PDT 24
Peak memory 214508 kb
Host smart-58ab97e0-e383-44ac-86d4-5916e83ab204
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059523860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.4059523860
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1284788344
Short name T20
Test name
Test status
Simulation time 37988243 ps
CPU time 3.06 seconds
Started Aug 10 04:53:21 PM PDT 24
Finished Aug 10 04:53:24 PM PDT 24
Peak memory 209272 kb
Host smart-7a986e21-8f3a-476c-8d6d-a71e5453ec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284788344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1284788344
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3239696892
Short name T138
Test name
Test status
Simulation time 2030743621 ps
CPU time 27.14 seconds
Started Aug 10 04:50:27 PM PDT 24
Finished Aug 10 04:50:54 PM PDT 24
Peak memory 216656 kb
Host smart-021dc979-cc2a-4720-b8f0-aca28cd831df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239696892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3239696892
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.429250960
Short name T246
Test name
Test status
Simulation time 358887687 ps
CPU time 5.49 seconds
Started Aug 10 04:52:23 PM PDT 24
Finished Aug 10 04:52:29 PM PDT 24
Peak memory 222248 kb
Host smart-02e95874-2fc0-4d4b-9887-de6fd022fa0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429250960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.429250960
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1532946857
Short name T30
Test name
Test status
Simulation time 345658589 ps
CPU time 7.26 seconds
Started Aug 10 04:54:39 PM PDT 24
Finished Aug 10 04:54:46 PM PDT 24
Peak memory 207644 kb
Host smart-908b9d2c-9957-4cb6-b100-a7448f4edd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532946857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1532946857
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.501036789
Short name T260
Test name
Test status
Simulation time 263723280 ps
CPU time 8 seconds
Started Aug 10 04:53:47 PM PDT 24
Finished Aug 10 04:53:55 PM PDT 24
Peak memory 215564 kb
Host smart-e5f4253b-2a23-4d18-883b-6bd1e75b5ecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=501036789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.501036789
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.961867755
Short name T252
Test name
Test status
Simulation time 3257339241 ps
CPU time 27.77 seconds
Started Aug 10 04:54:22 PM PDT 24
Finished Aug 10 04:54:50 PM PDT 24
Peak memory 216800 kb
Host smart-b863ec1d-50f0-472c-980f-5d0120a5dd10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961867755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.961867755
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1133065655
Short name T401
Test name
Test status
Simulation time 1573984601 ps
CPU time 24.81 seconds
Started Aug 10 04:51:38 PM PDT 24
Finished Aug 10 04:52:03 PM PDT 24
Peak memory 215264 kb
Host smart-ac79aaf8-24e4-49bd-8cab-5d3df9e3d9d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1133065655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1133065655
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4281270643
Short name T36
Test name
Test status
Simulation time 161531064 ps
CPU time 3.46 seconds
Started Aug 10 04:51:39 PM PDT 24
Finished Aug 10 04:51:43 PM PDT 24
Peak memory 210408 kb
Host smart-6cbc2a88-9299-4598-835c-98710badd332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281270643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4281270643
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3586544961
Short name T192
Test name
Test status
Simulation time 3426276390 ps
CPU time 23.79 seconds
Started Aug 10 04:55:43 PM PDT 24
Finished Aug 10 04:56:07 PM PDT 24
Peak memory 215988 kb
Host smart-15b28ccb-16c1-4227-a045-55fa26e1389b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586544961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3586544961
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.135514356
Short name T442
Test name
Test status
Simulation time 37092204 ps
CPU time 0.76 seconds
Started Aug 10 04:50:36 PM PDT 24
Finished Aug 10 04:50:37 PM PDT 24
Peak memory 205940 kb
Host smart-9aea9a1e-67e8-4636-afac-42c263b5c12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135514356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.135514356
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2259451172
Short name T264
Test name
Test status
Simulation time 1180120242 ps
CPU time 53.51 seconds
Started Aug 10 04:52:22 PM PDT 24
Finished Aug 10 04:53:15 PM PDT 24
Peak memory 214188 kb
Host smart-31d24b7d-441c-4be2-b71c-1a99973f4b16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2259451172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2259451172
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1845174719
Short name T168
Test name
Test status
Simulation time 4487455915 ps
CPU time 8.08 seconds
Started Aug 10 04:42:07 PM PDT 24
Finished Aug 10 04:42:15 PM PDT 24
Peak memory 206288 kb
Host smart-2271f73b-3afe-4eeb-ab6c-2b9ccdf82d85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845174719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1845174719
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3750229736
Short name T258
Test name
Test status
Simulation time 53553335 ps
CPU time 2.29 seconds
Started Aug 10 04:50:19 PM PDT 24
Finished Aug 10 04:50:21 PM PDT 24
Peak memory 214292 kb
Host smart-8590637a-6f71-4cfe-91d0-e8161a49216e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750229736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3750229736
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1224620260
Short name T124
Test name
Test status
Simulation time 3011819407 ps
CPU time 24.57 seconds
Started Aug 10 04:51:29 PM PDT 24
Finished Aug 10 04:51:54 PM PDT 24
Peak memory 222608 kb
Host smart-e5127f5f-0a94-4ecb-adb2-e91792232eaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224620260 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1224620260
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3849073357
Short name T6
Test name
Test status
Simulation time 9261954750 ps
CPU time 30.69 seconds
Started Aug 10 04:50:47 PM PDT 24
Finished Aug 10 04:51:17 PM PDT 24
Peak memory 215696 kb
Host smart-992b457e-ee41-4235-84e6-39927f82a2de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849073357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3849073357
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2687606701
Short name T224
Test name
Test status
Simulation time 1236426667 ps
CPU time 27.16 seconds
Started Aug 10 04:51:37 PM PDT 24
Finished Aug 10 04:52:05 PM PDT 24
Peak memory 215176 kb
Host smart-0c1d40ed-de34-43fe-b0af-c700f96dc04f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687606701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2687606701
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1078365773
Short name T633
Test name
Test status
Simulation time 212474607 ps
CPU time 2.47 seconds
Started Aug 10 04:53:34 PM PDT 24
Finished Aug 10 04:53:36 PM PDT 24
Peak memory 221472 kb
Host smart-aa74ead8-82b8-4555-ad59-959c1df8066b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078365773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1078365773
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3120628121
Short name T191
Test name
Test status
Simulation time 3379815500 ps
CPU time 32.7 seconds
Started Aug 10 04:53:51 PM PDT 24
Finished Aug 10 04:54:24 PM PDT 24
Peak memory 215132 kb
Host smart-0dfe64cd-5dd6-4907-8bb4-61e83bf5a095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120628121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3120628121
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1920240412
Short name T403
Test name
Test status
Simulation time 96532932 ps
CPU time 6.05 seconds
Started Aug 10 04:54:11 PM PDT 24
Finished Aug 10 04:54:17 PM PDT 24
Peak memory 214252 kb
Host smart-b4ebfe4b-d85e-4bb5-bb59-ef96040c5479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1920240412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1920240412
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2342530700
Short name T153
Test name
Test status
Simulation time 532835069 ps
CPU time 8.89 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:42:03 PM PDT 24
Peak memory 214212 kb
Host smart-1ec45402-5be5-4d06-9d1d-4d48e428290b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342530700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2342530700
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1627653649
Short name T163
Test name
Test status
Simulation time 390976711 ps
CPU time 4.28 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:25 PM PDT 24
Peak memory 214264 kb
Host smart-dcd07025-d4f0-4ece-8057-bf45ee847ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627653649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1627653649
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2734011812
Short name T43
Test name
Test status
Simulation time 447077624 ps
CPU time 9.96 seconds
Started Aug 10 04:51:04 PM PDT 24
Finished Aug 10 04:51:14 PM PDT 24
Peak memory 230752 kb
Host smart-bd485a47-9061-46da-94ad-b6e010cc74fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734011812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2734011812
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2898740677
Short name T761
Test name
Test status
Simulation time 1204500474 ps
CPU time 29.68 seconds
Started Aug 10 04:53:33 PM PDT 24
Finished Aug 10 04:54:03 PM PDT 24
Peak memory 214936 kb
Host smart-7747a49a-80a0-4c59-81ab-293781d6f62f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898740677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2898740677
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2520247386
Short name T68
Test name
Test status
Simulation time 510479208 ps
CPU time 3.87 seconds
Started Aug 10 04:53:34 PM PDT 24
Finished Aug 10 04:53:38 PM PDT 24
Peak memory 208628 kb
Host smart-d3000923-e44d-41c1-b04d-b7c9bee47bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520247386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2520247386
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4212553312
Short name T150
Test name
Test status
Simulation time 422575254 ps
CPU time 3.85 seconds
Started Aug 10 04:54:31 PM PDT 24
Finished Aug 10 04:54:35 PM PDT 24
Peak memory 222656 kb
Host smart-a774397a-947c-4e3e-9606-12dad295a336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212553312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4212553312
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3557382282
Short name T346
Test name
Test status
Simulation time 507132625 ps
CPU time 2.43 seconds
Started Aug 10 04:50:55 PM PDT 24
Finished Aug 10 04:50:57 PM PDT 24
Peak memory 209272 kb
Host smart-ab25dec4-8621-4774-be0b-95f429c800ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557382282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3557382282
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2270072447
Short name T302
Test name
Test status
Simulation time 44483903 ps
CPU time 2.18 seconds
Started Aug 10 04:55:43 PM PDT 24
Finished Aug 10 04:55:46 PM PDT 24
Peak memory 214472 kb
Host smart-8a238d5f-5bf4-4668-8db6-15876351489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270072447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2270072447
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1290693378
Short name T1033
Test name
Test status
Simulation time 307952078 ps
CPU time 2.42 seconds
Started Aug 10 04:42:33 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 214480 kb
Host smart-b4918484-b71e-46fa-a945-43bcc724a262
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290693378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1290693378
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2979486274
Short name T158
Test name
Test status
Simulation time 497340222 ps
CPU time 5.74 seconds
Started Aug 10 04:42:31 PM PDT 24
Finished Aug 10 04:42:37 PM PDT 24
Peak memory 214232 kb
Host smart-ac0c6137-a309-4681-b255-d4c17502257a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979486274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2979486274
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2489909468
Short name T155
Test name
Test status
Simulation time 172998046 ps
CPU time 4.2 seconds
Started Aug 10 04:42:22 PM PDT 24
Finished Aug 10 04:42:26 PM PDT 24
Peak memory 214232 kb
Host smart-850f16c4-ea15-4336-9eeb-37b22f9bd518
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489909468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2489909468
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.909573309
Short name T175
Test name
Test status
Simulation time 158632365 ps
CPU time 3.9 seconds
Started Aug 10 04:55:56 PM PDT 24
Finished Aug 10 04:56:00 PM PDT 24
Peak memory 215992 kb
Host smart-ab3ee63b-f10b-4a3c-b4e6-9270227ae7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909573309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.909573309
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.439022265
Short name T147
Test name
Test status
Simulation time 86239177 ps
CPU time 2.62 seconds
Started Aug 10 04:51:21 PM PDT 24
Finished Aug 10 04:51:23 PM PDT 24
Peak memory 222528 kb
Host smart-88d862f2-e17f-4486-8031-045f4ab4aaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439022265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.439022265
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1021684865
Short name T70
Test name
Test status
Simulation time 314382736 ps
CPU time 11.68 seconds
Started Aug 10 04:50:46 PM PDT 24
Finished Aug 10 04:50:57 PM PDT 24
Peak memory 219308 kb
Host smart-7854e7a8-83ec-416c-b24c-0ea5e4117f2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021684865 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1021684865
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.4237636783
Short name T381
Test name
Test status
Simulation time 583134473 ps
CPU time 11.17 seconds
Started Aug 10 04:52:23 PM PDT 24
Finished Aug 10 04:52:34 PM PDT 24
Peak memory 210892 kb
Host smart-9be44314-34e8-42c0-ac97-590899e6dc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237636783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4237636783
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1114217369
Short name T78
Test name
Test status
Simulation time 3805403313 ps
CPU time 45.5 seconds
Started Aug 10 04:52:34 PM PDT 24
Finished Aug 10 04:53:20 PM PDT 24
Peak memory 222540 kb
Host smart-a1e07da8-451e-4a85-ae0c-8c161ea9b561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114217369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1114217369
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.4027493865
Short name T398
Test name
Test status
Simulation time 54396686 ps
CPU time 3.93 seconds
Started Aug 10 04:53:51 PM PDT 24
Finished Aug 10 04:53:55 PM PDT 24
Peak memory 214372 kb
Host smart-18cdaf17-41cf-4a1d-82dd-eaf4f8790c88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027493865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.4027493865
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3113088516
Short name T343
Test name
Test status
Simulation time 161682171 ps
CPU time 2.17 seconds
Started Aug 10 04:51:02 PM PDT 24
Finished Aug 10 04:51:05 PM PDT 24
Peak memory 214140 kb
Host smart-49d7166e-ba58-4b7e-a8ec-b4c74621cecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113088516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3113088516
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.641177806
Short name T324
Test name
Test status
Simulation time 28259552 ps
CPU time 1.96 seconds
Started Aug 10 04:54:41 PM PDT 24
Finished Aug 10 04:54:43 PM PDT 24
Peak memory 208772 kb
Host smart-c967e9fc-408f-4763-8771-e32dd31cf972
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641177806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.641177806
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.291661774
Short name T254
Test name
Test status
Simulation time 130833327 ps
CPU time 2.64 seconds
Started Aug 10 04:54:46 PM PDT 24
Finished Aug 10 04:54:49 PM PDT 24
Peak memory 218252 kb
Host smart-690c4404-392c-44a5-92c7-824d51b07142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291661774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.291661774
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2594184550
Short name T269
Test name
Test status
Simulation time 180740360 ps
CPU time 4.96 seconds
Started Aug 10 04:51:55 PM PDT 24
Finished Aug 10 04:52:00 PM PDT 24
Peak memory 214780 kb
Host smart-ca7ccc0e-56d1-4e96-ac2c-2e14c78764f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594184550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2594184550
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3371943237
Short name T786
Test name
Test status
Simulation time 105356261 ps
CPU time 4.46 seconds
Started Aug 10 04:55:04 PM PDT 24
Finished Aug 10 04:55:09 PM PDT 24
Peak memory 209748 kb
Host smart-991b1c56-cc81-451a-a48e-24c2adfe40c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371943237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3371943237
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.4088353716
Short name T152
Test name
Test status
Simulation time 68695724 ps
CPU time 2.54 seconds
Started Aug 10 04:52:35 PM PDT 24
Finished Aug 10 04:52:38 PM PDT 24
Peak memory 217700 kb
Host smart-aa766ad6-6c31-4a7d-89cf-324844119e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088353716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.4088353716
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3591700154
Short name T149
Test name
Test status
Simulation time 296239205 ps
CPU time 8.74 seconds
Started Aug 10 04:53:23 PM PDT 24
Finished Aug 10 04:53:32 PM PDT 24
Peak memory 222560 kb
Host smart-449aefc1-9960-4e41-91b8-3814017a2b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591700154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3591700154
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.833896910
Short name T151
Test name
Test status
Simulation time 105620451 ps
CPU time 2.51 seconds
Started Aug 10 04:55:14 PM PDT 24
Finished Aug 10 04:55:17 PM PDT 24
Peak memory 217764 kb
Host smart-a7d1b0f3-8f56-4f07-88aa-f55238c49037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833896910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.833896910
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3887581216
Short name T63
Test name
Test status
Simulation time 157926882 ps
CPU time 3.55 seconds
Started Aug 10 04:55:19 PM PDT 24
Finished Aug 10 04:55:23 PM PDT 24
Peak memory 222548 kb
Host smart-97adbca4-d14f-4774-bddf-52191a937ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887581216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3887581216
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3305598636
Short name T148
Test name
Test status
Simulation time 8536768511 ps
CPU time 56.91 seconds
Started Aug 10 04:55:56 PM PDT 24
Finished Aug 10 04:56:53 PM PDT 24
Peak memory 222592 kb
Host smart-9e178ffa-77b7-4720-859a-803a43c5c81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305598636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3305598636
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3471433036
Short name T285
Test name
Test status
Simulation time 123191621 ps
CPU time 4.7 seconds
Started Aug 10 04:52:05 PM PDT 24
Finished Aug 10 04:52:10 PM PDT 24
Peak memory 214336 kb
Host smart-8499b399-83d8-4efe-b972-896a968d78a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471433036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3471433036
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1052506507
Short name T325
Test name
Test status
Simulation time 174358915 ps
CPU time 3.42 seconds
Started Aug 10 04:52:34 PM PDT 24
Finished Aug 10 04:52:37 PM PDT 24
Peak memory 215224 kb
Host smart-74d26439-5e80-452a-aeb9-f21a207b1020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052506507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1052506507
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3675715064
Short name T267
Test name
Test status
Simulation time 3293196326 ps
CPU time 28.05 seconds
Started Aug 10 04:53:21 PM PDT 24
Finished Aug 10 04:53:49 PM PDT 24
Peak memory 215864 kb
Host smart-f4499152-5de2-42f3-a36c-52288df607e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675715064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3675715064
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.4278780971
Short name T237
Test name
Test status
Simulation time 199908015 ps
CPU time 4.02 seconds
Started Aug 10 04:50:53 PM PDT 24
Finished Aug 10 04:50:57 PM PDT 24
Peak memory 214720 kb
Host smart-1b25a916-8466-43ec-b187-e25590eac361
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4278780971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.4278780971
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1302444276
Short name T342
Test name
Test status
Simulation time 666518564 ps
CPU time 3.37 seconds
Started Aug 10 04:53:43 PM PDT 24
Finished Aug 10 04:53:46 PM PDT 24
Peak memory 211548 kb
Host smart-b41c0400-2958-41df-872b-2e87cabae975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302444276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1302444276
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.118126512
Short name T227
Test name
Test status
Simulation time 3311626000 ps
CPU time 33.94 seconds
Started Aug 10 04:53:52 PM PDT 24
Finished Aug 10 04:54:26 PM PDT 24
Peak memory 215884 kb
Host smart-d90e9658-ed31-42f0-a597-17fae3db74ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118126512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.118126512
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1491734321
Short name T289
Test name
Test status
Simulation time 234525384 ps
CPU time 12.47 seconds
Started Aug 10 04:54:36 PM PDT 24
Finished Aug 10 04:54:49 PM PDT 24
Peak memory 214328 kb
Host smart-878e106c-312a-47d0-8463-ba5e06493807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491734321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1491734321
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3100469882
Short name T376
Test name
Test status
Simulation time 97049568 ps
CPU time 4.1 seconds
Started Aug 10 04:55:06 PM PDT 24
Finished Aug 10 04:55:10 PM PDT 24
Peak memory 214192 kb
Host smart-4578930f-7c8d-4ad6-8592-0a90c963a716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100469882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3100469882
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1525696732
Short name T223
Test name
Test status
Simulation time 540749594 ps
CPU time 25.92 seconds
Started Aug 10 04:51:24 PM PDT 24
Finished Aug 10 04:51:50 PM PDT 24
Peak memory 215980 kb
Host smart-7f09b0b3-090e-4224-96a0-632e33430a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525696732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1525696732
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.213968999
Short name T129
Test name
Test status
Simulation time 260422450 ps
CPU time 7.51 seconds
Started Aug 10 04:55:43 PM PDT 24
Finished Aug 10 04:55:51 PM PDT 24
Peak memory 222436 kb
Host smart-b83ae5ed-5736-4254-923a-cc85500f665b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213968999 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.213968999
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.444980759
Short name T251
Test name
Test status
Simulation time 303623681 ps
CPU time 7.32 seconds
Started Aug 10 04:55:45 PM PDT 24
Finished Aug 10 04:55:52 PM PDT 24
Peak memory 214184 kb
Host smart-8022dc86-1c14-4506-8e1d-3397fc70ac73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=444980759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.444980759
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1806309899
Short name T165
Test name
Test status
Simulation time 81999335 ps
CPU time 3.12 seconds
Started Aug 10 04:42:37 PM PDT 24
Finished Aug 10 04:42:41 PM PDT 24
Peak memory 214336 kb
Host smart-ff15e085-4d9f-4f4f-965b-c3363b8db29e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806309899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1806309899
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4129557787
Short name T159
Test name
Test status
Simulation time 215834737 ps
CPU time 4.34 seconds
Started Aug 10 04:42:31 PM PDT 24
Finished Aug 10 04:42:35 PM PDT 24
Peak memory 206028 kb
Host smart-373823f7-b98f-4c53-b3fc-047373a30f3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129557787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.4129557787
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2125128539
Short name T169
Test name
Test status
Simulation time 230667979 ps
CPU time 1.9 seconds
Started Aug 10 04:51:20 PM PDT 24
Finished Aug 10 04:51:22 PM PDT 24
Peak memory 209680 kb
Host smart-08e762b8-2786-477c-9cd4-7984c198baaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125128539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2125128539
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1041166285
Short name T160
Test name
Test status
Simulation time 304133024 ps
CPU time 1.89 seconds
Started Aug 10 04:51:29 PM PDT 24
Finished Aug 10 04:51:31 PM PDT 24
Peak memory 209700 kb
Host smart-415b093e-dc8b-434a-b2f4-7187645d4bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041166285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1041166285
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2715915364
Short name T186
Test name
Test status
Simulation time 82980059 ps
CPU time 3.64 seconds
Started Aug 10 04:51:03 PM PDT 24
Finished Aug 10 04:51:07 PM PDT 24
Peak memory 214304 kb
Host smart-084211b2-1546-4375-877b-2e320c89c343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715915364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2715915364
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1828937550
Short name T107
Test name
Test status
Simulation time 185159618 ps
CPU time 4.7 seconds
Started Aug 10 04:55:16 PM PDT 24
Finished Aug 10 04:55:21 PM PDT 24
Peak memory 217276 kb
Host smart-ae587d57-85de-4e17-ac2b-188cb07fb89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828937550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1828937550
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_random.3078095301
Short name T293
Test name
Test status
Simulation time 655732755 ps
CPU time 5.33 seconds
Started Aug 10 04:50:37 PM PDT 24
Finished Aug 10 04:50:42 PM PDT 24
Peak memory 209064 kb
Host smart-beeb6207-f087-421d-80ce-167e8a6b4a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078095301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3078095301
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.4090286804
Short name T317
Test name
Test status
Simulation time 66296767 ps
CPU time 3.65 seconds
Started Aug 10 04:52:18 PM PDT 24
Finished Aug 10 04:52:21 PM PDT 24
Peak memory 222260 kb
Host smart-f835054c-93bc-4a80-8d0d-42ac258a65c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090286804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.4090286804
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3979914617
Short name T334
Test name
Test status
Simulation time 242926425 ps
CPU time 13.67 seconds
Started Aug 10 04:52:14 PM PDT 24
Finished Aug 10 04:52:28 PM PDT 24
Peak memory 222620 kb
Host smart-db655c9a-84dc-4ff7-a675-54d1c6fc20b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979914617 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3979914617
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.735103683
Short name T40
Test name
Test status
Simulation time 51853750 ps
CPU time 2.94 seconds
Started Aug 10 04:52:15 PM PDT 24
Finished Aug 10 04:52:18 PM PDT 24
Peak memory 209908 kb
Host smart-18a8afa8-007b-4615-8c8e-e78641926db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735103683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.735103683
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.46593308
Short name T206
Test name
Test status
Simulation time 748235400 ps
CPU time 6.16 seconds
Started Aug 10 04:52:16 PM PDT 24
Finished Aug 10 04:52:22 PM PDT 24
Peak memory 208152 kb
Host smart-1fbcd953-8785-4ba2-8941-f75f107d08bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46593308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.46593308
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3396865183
Short name T857
Test name
Test status
Simulation time 809420499 ps
CPU time 9.48 seconds
Started Aug 10 04:52:34 PM PDT 24
Finished Aug 10 04:52:44 PM PDT 24
Peak memory 218732 kb
Host smart-9f061000-9255-426a-a598-2ebef1192300
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396865183 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3396865183
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1791195298
Short name T181
Test name
Test status
Simulation time 674206967 ps
CPU time 19.37 seconds
Started Aug 10 04:52:35 PM PDT 24
Finished Aug 10 04:52:54 PM PDT 24
Peak memory 221136 kb
Host smart-42ac8714-dd11-4105-b119-7715eb1b1a73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791195298 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1791195298
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1752564755
Short name T309
Test name
Test status
Simulation time 190462091 ps
CPU time 4.8 seconds
Started Aug 10 04:52:46 PM PDT 24
Finished Aug 10 04:52:51 PM PDT 24
Peak memory 214168 kb
Host smart-4d211616-89bd-4896-886d-b117a1618376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752564755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1752564755
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3441808539
Short name T229
Test name
Test status
Simulation time 160906409 ps
CPU time 5.03 seconds
Started Aug 10 04:52:54 PM PDT 24
Finished Aug 10 04:53:00 PM PDT 24
Peak memory 214256 kb
Host smart-00efcc41-c60e-4bdd-bee2-1d5ed6e1dece
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3441808539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3441808539
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3035254677
Short name T272
Test name
Test status
Simulation time 282357907 ps
CPU time 7.62 seconds
Started Aug 10 04:50:55 PM PDT 24
Finished Aug 10 04:51:02 PM PDT 24
Peak memory 208636 kb
Host smart-c23b83c3-c163-4173-9f5a-9cf88a7d1f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035254677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3035254677
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.236196349
Short name T374
Test name
Test status
Simulation time 22737677 ps
CPU time 1.51 seconds
Started Aug 10 04:53:43 PM PDT 24
Finished Aug 10 04:53:45 PM PDT 24
Peak memory 214328 kb
Host smart-d5b90b05-d61f-443d-95f1-74dd88046c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236196349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.236196349
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3116046395
Short name T220
Test name
Test status
Simulation time 145822924 ps
CPU time 3.17 seconds
Started Aug 10 04:53:52 PM PDT 24
Finished Aug 10 04:53:55 PM PDT 24
Peak memory 208648 kb
Host smart-b94e1bc8-7bc9-4954-b0ce-976fd17c23bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116046395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3116046395
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1866304014
Short name T360
Test name
Test status
Simulation time 29409056 ps
CPU time 2.46 seconds
Started Aug 10 04:54:13 PM PDT 24
Finished Aug 10 04:54:15 PM PDT 24
Peak memory 214332 kb
Host smart-0b2c3d21-2b6a-4a46-ab17-0e8212f83c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866304014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1866304014
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3748226864
Short name T795
Test name
Test status
Simulation time 107836079 ps
CPU time 3.17 seconds
Started Aug 10 04:54:11 PM PDT 24
Finished Aug 10 04:54:14 PM PDT 24
Peak memory 220820 kb
Host smart-a60c676c-7f82-4221-b120-cc6f6e2939a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748226864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3748226864
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2346164081
Short name T312
Test name
Test status
Simulation time 478912569 ps
CPU time 16.43 seconds
Started Aug 10 04:54:41 PM PDT 24
Finished Aug 10 04:54:58 PM PDT 24
Peak memory 210576 kb
Host smart-18a5f16b-1111-4566-afba-543334b4eba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346164081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2346164081
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_random.2546691669
Short name T354
Test name
Test status
Simulation time 4181690278 ps
CPU time 7.62 seconds
Started Aug 10 04:54:55 PM PDT 24
Finished Aug 10 04:55:03 PM PDT 24
Peak memory 208848 kb
Host smart-727685b0-ac38-44e0-b4c2-1130c25686d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546691669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2546691669
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.828567814
Short name T259
Test name
Test status
Simulation time 166440659 ps
CPU time 3.46 seconds
Started Aug 10 04:55:21 PM PDT 24
Finished Aug 10 04:55:25 PM PDT 24
Peak memory 215668 kb
Host smart-8fd4c300-4325-490f-90b3-13c67c136045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828567814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.828567814
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1598576089
Short name T77
Test name
Test status
Simulation time 37466310525 ps
CPU time 388.28 seconds
Started Aug 10 04:55:34 PM PDT 24
Finished Aug 10 05:02:03 PM PDT 24
Peak memory 222500 kb
Host smart-c4f2c7b5-3d69-4423-b6f9-099eac8db970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598576089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1598576089
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2098257523
Short name T211
Test name
Test status
Simulation time 41030783 ps
CPU time 2.88 seconds
Started Aug 10 04:55:44 PM PDT 24
Finished Aug 10 04:55:47 PM PDT 24
Peak memory 220436 kb
Host smart-81d79032-95bb-4b34-a705-6d852432a79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098257523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2098257523
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3412184659
Short name T1079
Test name
Test status
Simulation time 783991785 ps
CPU time 9.31 seconds
Started Aug 10 04:42:09 PM PDT 24
Finished Aug 10 04:42:18 PM PDT 24
Peak memory 206032 kb
Host smart-953663bf-6a40-4699-9b26-15f377f8c7a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412184659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
412184659
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.972511465
Short name T929
Test name
Test status
Simulation time 645064406 ps
CPU time 15.91 seconds
Started Aug 10 04:42:08 PM PDT 24
Finished Aug 10 04:42:24 PM PDT 24
Peak memory 206160 kb
Host smart-2bb03b82-d51d-4b36-960f-a76046b99cda
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972511465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.972511465
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1443105287
Short name T958
Test name
Test status
Simulation time 58652757 ps
CPU time 1.26 seconds
Started Aug 10 04:42:09 PM PDT 24
Finished Aug 10 04:42:10 PM PDT 24
Peak memory 206120 kb
Host smart-3c1c9217-ef78-4e22-99fa-d5f2505dcd56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443105287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
443105287
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3851521252
Short name T1022
Test name
Test status
Simulation time 28625473 ps
CPU time 1.88 seconds
Started Aug 10 04:42:08 PM PDT 24
Finished Aug 10 04:42:10 PM PDT 24
Peak memory 214288 kb
Host smart-c9155b23-6857-4e49-9681-9e9501cbe21f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851521252 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3851521252
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.187546573
Short name T942
Test name
Test status
Simulation time 35319337 ps
CPU time 1.01 seconds
Started Aug 10 04:42:07 PM PDT 24
Finished Aug 10 04:42:08 PM PDT 24
Peak memory 205880 kb
Host smart-c116dabc-78c8-4cf4-a07a-c129b9292506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187546573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.187546573
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3803357625
Short name T930
Test name
Test status
Simulation time 25320524 ps
CPU time 0.74 seconds
Started Aug 10 04:42:07 PM PDT 24
Finished Aug 10 04:42:08 PM PDT 24
Peak memory 205740 kb
Host smart-cc5d4807-fd26-42b9-8ac0-162ec3a64135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803357625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3803357625
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2924089741
Short name T962
Test name
Test status
Simulation time 22007908 ps
CPU time 1.53 seconds
Started Aug 10 04:42:07 PM PDT 24
Finished Aug 10 04:42:08 PM PDT 24
Peak memory 206100 kb
Host smart-b80ba004-deae-46e7-84a0-862bcccd2147
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924089741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2924089741
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3670892745
Short name T966
Test name
Test status
Simulation time 317016952 ps
CPU time 2.12 seconds
Started Aug 10 04:41:56 PM PDT 24
Finished Aug 10 04:41:58 PM PDT 24
Peak memory 214604 kb
Host smart-102d51d6-c5ad-4e82-b8a8-6254590a78c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670892745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3670892745
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.349211296
Short name T1058
Test name
Test status
Simulation time 3295562050 ps
CPU time 11.55 seconds
Started Aug 10 04:41:57 PM PDT 24
Finished Aug 10 04:42:09 PM PDT 24
Peak memory 214652 kb
Host smart-04aade37-d02b-4919-b95f-7d3c2af47970
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349211296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.349211296
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3594305935
Short name T1064
Test name
Test status
Simulation time 233681194 ps
CPU time 1.64 seconds
Started Aug 10 04:41:56 PM PDT 24
Finished Aug 10 04:41:58 PM PDT 24
Peak memory 214180 kb
Host smart-3e146546-7317-4dc9-a112-3977bede6221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594305935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3594305935
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3584144837
Short name T919
Test name
Test status
Simulation time 665107860 ps
CPU time 5.49 seconds
Started Aug 10 04:42:08 PM PDT 24
Finished Aug 10 04:42:13 PM PDT 24
Peak memory 206104 kb
Host smart-115b38ef-9edd-47f0-9c5a-701b8b335164
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584144837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
584144837
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2945683017
Short name T1036
Test name
Test status
Simulation time 1779323154 ps
CPU time 24.77 seconds
Started Aug 10 04:42:08 PM PDT 24
Finished Aug 10 04:42:33 PM PDT 24
Peak memory 206068 kb
Host smart-fabbc3c0-7a51-431c-936e-62072edc7a6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945683017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
945683017
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3831193935
Short name T1082
Test name
Test status
Simulation time 21734310 ps
CPU time 1.2 seconds
Started Aug 10 04:42:09 PM PDT 24
Finished Aug 10 04:42:10 PM PDT 24
Peak memory 206120 kb
Host smart-ac65a836-f43a-46a2-9ca2-2eb4bd086952
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831193935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
831193935
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1858080764
Short name T1074
Test name
Test status
Simulation time 55273005 ps
CPU time 1.03 seconds
Started Aug 10 04:42:07 PM PDT 24
Finished Aug 10 04:42:08 PM PDT 24
Peak memory 205884 kb
Host smart-91ba570a-f5a6-4185-a4d7-4bd7810e65e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858080764 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1858080764
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.725838549
Short name T999
Test name
Test status
Simulation time 35293159 ps
CPU time 1.2 seconds
Started Aug 10 04:42:08 PM PDT 24
Finished Aug 10 04:42:09 PM PDT 24
Peak memory 205976 kb
Host smart-5b9b1def-368b-42ca-a85c-eee0026d8a71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725838549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.725838549
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3377064255
Short name T957
Test name
Test status
Simulation time 107724739 ps
CPU time 0.84 seconds
Started Aug 10 04:42:08 PM PDT 24
Finished Aug 10 04:42:09 PM PDT 24
Peak memory 205708 kb
Host smart-f173c314-0114-4a45-a0f8-cdff5dff8e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377064255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3377064255
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3255864551
Short name T1038
Test name
Test status
Simulation time 20716480 ps
CPU time 1.36 seconds
Started Aug 10 04:42:07 PM PDT 24
Finished Aug 10 04:42:09 PM PDT 24
Peak memory 206084 kb
Host smart-574b2e6e-396e-4f3d-a946-b26d2f6c023c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255864551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3255864551
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.985037485
Short name T1021
Test name
Test status
Simulation time 413321900 ps
CPU time 3.38 seconds
Started Aug 10 04:42:06 PM PDT 24
Finished Aug 10 04:42:10 PM PDT 24
Peak memory 214840 kb
Host smart-9bec562a-da59-4337-aa4b-3b06795da2fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985037485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.985037485
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1207360645
Short name T946
Test name
Test status
Simulation time 1588081260 ps
CPU time 6.81 seconds
Started Aug 10 04:42:06 PM PDT 24
Finished Aug 10 04:42:13 PM PDT 24
Peak memory 214456 kb
Host smart-815823c4-7a06-432c-91ce-9db8b6e532e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207360645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1207360645
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.157237141
Short name T995
Test name
Test status
Simulation time 24337105 ps
CPU time 1.81 seconds
Started Aug 10 04:42:08 PM PDT 24
Finished Aug 10 04:42:10 PM PDT 24
Peak memory 222472 kb
Host smart-5a6ed6a6-0b6b-4660-b3e0-931ca9905b36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157237141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.157237141
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.706423348
Short name T172
Test name
Test status
Simulation time 178596565 ps
CPU time 2.54 seconds
Started Aug 10 04:42:08 PM PDT 24
Finished Aug 10 04:42:11 PM PDT 24
Peak memory 214104 kb
Host smart-600ab1f2-c044-4cc6-b561-3b299d217764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706423348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
706423348
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3560247241
Short name T156
Test name
Test status
Simulation time 185953394 ps
CPU time 1.7 seconds
Started Aug 10 04:42:22 PM PDT 24
Finished Aug 10 04:42:24 PM PDT 24
Peak memory 214476 kb
Host smart-c5dd97fc-9514-465a-bff1-c9ddf36f633c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560247241 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3560247241
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1902155023
Short name T154
Test name
Test status
Simulation time 17595076 ps
CPU time 0.95 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:22 PM PDT 24
Peak memory 205884 kb
Host smart-4a01729a-4859-49af-92c4-260ab5cfe0cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902155023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1902155023
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.805721288
Short name T1084
Test name
Test status
Simulation time 24668613 ps
CPU time 0.74 seconds
Started Aug 10 04:42:24 PM PDT 24
Finished Aug 10 04:42:25 PM PDT 24
Peak memory 205892 kb
Host smart-5981a7b3-1397-4526-a8fc-b8bc929b2b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805721288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.805721288
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.385216197
Short name T1066
Test name
Test status
Simulation time 293167699 ps
CPU time 1.74 seconds
Started Aug 10 04:42:24 PM PDT 24
Finished Aug 10 04:42:25 PM PDT 24
Peak memory 206048 kb
Host smart-598ea364-5b2a-49e9-8e83-31a4a83d50e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385216197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.385216197
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3229626166
Short name T936
Test name
Test status
Simulation time 51406931 ps
CPU time 1.99 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 214568 kb
Host smart-76a6c14a-5300-43a8-a5d8-3d9094b82d84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229626166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3229626166
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1372365944
Short name T143
Test name
Test status
Simulation time 170749346 ps
CPU time 6.36 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:28 PM PDT 24
Peak memory 214580 kb
Host smart-58e6081e-295e-4041-a5a0-a4e669f67904
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372365944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1372365944
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.4211168219
Short name T1035
Test name
Test status
Simulation time 111664353 ps
CPU time 2.33 seconds
Started Aug 10 04:42:23 PM PDT 24
Finished Aug 10 04:42:26 PM PDT 24
Peak memory 214308 kb
Host smart-82798cb5-a83c-4e78-87a3-2fccd09f4c01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211168219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.4211168219
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.169569684
Short name T944
Test name
Test status
Simulation time 263686610 ps
CPU time 8.28 seconds
Started Aug 10 04:42:22 PM PDT 24
Finished Aug 10 04:42:30 PM PDT 24
Peak memory 214256 kb
Host smart-8fe1cf39-59d3-4421-b5bd-cff127ea12f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169569684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.169569684
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1406715368
Short name T937
Test name
Test status
Simulation time 73049241 ps
CPU time 1.35 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:33 PM PDT 24
Peak memory 214252 kb
Host smart-6e1afb6f-6094-493c-b503-1bc1069bb17b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406715368 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1406715368
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2493761426
Short name T1039
Test name
Test status
Simulation time 27619979 ps
CPU time 1.23 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:37 PM PDT 24
Peak memory 206196 kb
Host smart-c78978d4-18e3-49e9-af61-353265aa0d68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493761426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2493761426
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.939941881
Short name T1020
Test name
Test status
Simulation time 20664909 ps
CPU time 0.73 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 205784 kb
Host smart-9af61ab0-0791-4496-b80e-a64736936675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939941881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.939941881
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2119586425
Short name T984
Test name
Test status
Simulation time 21573892 ps
CPU time 1.49 seconds
Started Aug 10 04:42:31 PM PDT 24
Finished Aug 10 04:42:32 PM PDT 24
Peak memory 206144 kb
Host smart-2e0c058b-e7aa-4135-986d-5e2e327712ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119586425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2119586425
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3054567371
Short name T115
Test name
Test status
Simulation time 230428093 ps
CPU time 1.85 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:35 PM PDT 24
Peak memory 219676 kb
Host smart-bb180e68-77ba-4bf7-876e-231eff94a98d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054567371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3054567371
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3745960621
Short name T1071
Test name
Test status
Simulation time 2039440680 ps
CPU time 12.25 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:44 PM PDT 24
Peak memory 214620 kb
Host smart-a04bf785-94bc-45e0-9f84-1fcec3bec82a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745960621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3745960621
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2872758077
Short name T956
Test name
Test status
Simulation time 38282608 ps
CPU time 2.37 seconds
Started Aug 10 04:42:33 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 214280 kb
Host smart-945a048b-0d6b-4cae-8548-8ed4a546391f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872758077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2872758077
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1185158353
Short name T1042
Test name
Test status
Simulation time 23150043 ps
CPU time 1.56 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 219948 kb
Host smart-48710688-02bf-48f4-b6d0-9d7c6c876897
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185158353 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1185158353
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.683473954
Short name T1018
Test name
Test status
Simulation time 14390212 ps
CPU time 1.45 seconds
Started Aug 10 04:42:33 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 206060 kb
Host smart-94bf1b5f-2d8c-4ec2-86b0-9b3955440cd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683473954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.683473954
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2379400947
Short name T985
Test name
Test status
Simulation time 65686554 ps
CPU time 0.8 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:33 PM PDT 24
Peak memory 205916 kb
Host smart-877463fa-ddf0-4f87-afcc-fc5a277b4aab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379400947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2379400947
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3560034485
Short name T1028
Test name
Test status
Simulation time 631670811 ps
CPU time 1.75 seconds
Started Aug 10 04:42:34 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 205980 kb
Host smart-e48aff35-3d2a-4547-bbb0-a6e5ca3af6d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560034485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3560034485
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.787751230
Short name T982
Test name
Test status
Simulation time 237595637 ps
CPU time 4.81 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:37 PM PDT 24
Peak memory 214584 kb
Host smart-08344c28-479f-4ec7-b768-b003a1a8d299
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787751230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.787751230
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.468215501
Short name T921
Test name
Test status
Simulation time 105424246 ps
CPU time 2.42 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:35 PM PDT 24
Peak memory 215452 kb
Host smart-9ceac55b-c532-4815-848c-d0c51fc8b539
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468215501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.468215501
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4258884955
Short name T1007
Test name
Test status
Simulation time 51629052 ps
CPU time 1.57 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 214328 kb
Host smart-adcb6945-b3f0-487b-aa00-f7bc976ecbe4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258884955 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.4258884955
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3596040987
Short name T990
Test name
Test status
Simulation time 13341606 ps
CPU time 1.07 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:34 PM PDT 24
Peak memory 205948 kb
Host smart-76e2c5e0-2a4c-42b5-ba71-ba7f15d20c47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596040987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3596040987
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1020838446
Short name T918
Test name
Test status
Simulation time 44173119 ps
CPU time 0.85 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 205808 kb
Host smart-4f54a7b3-c58b-47d1-9b07-f0ab1cf59b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020838446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1020838446
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2754273591
Short name T1023
Test name
Test status
Simulation time 1164761272 ps
CPU time 4.88 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:38 PM PDT 24
Peak memory 205968 kb
Host smart-294cf440-06c2-484c-a9a8-7e634dc7fed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754273591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2754273591
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1553836035
Short name T1046
Test name
Test status
Simulation time 2638688031 ps
CPU time 3.9 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:37 PM PDT 24
Peak memory 214708 kb
Host smart-231913a8-16f1-49cb-9a10-c770f078a932
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553836035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1553836035
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3329406561
Short name T1080
Test name
Test status
Simulation time 3917386727 ps
CPU time 11.53 seconds
Started Aug 10 04:42:34 PM PDT 24
Finished Aug 10 04:42:46 PM PDT 24
Peak memory 214668 kb
Host smart-a9a778f7-8921-4033-84e1-31bc44b6acec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329406561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3329406561
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1649836608
Short name T1030
Test name
Test status
Simulation time 255777555 ps
CPU time 3.09 seconds
Started Aug 10 04:42:30 PM PDT 24
Finished Aug 10 04:42:33 PM PDT 24
Peak memory 217492 kb
Host smart-d2fa1b53-74d9-4969-aeab-3121f9ccd10a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649836608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1649836608
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.596240335
Short name T1032
Test name
Test status
Simulation time 153399728 ps
CPU time 2.55 seconds
Started Aug 10 04:42:36 PM PDT 24
Finished Aug 10 04:42:38 PM PDT 24
Peak memory 214304 kb
Host smart-d0176797-5175-40d0-bdd4-674c6b49044b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596240335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.596240335
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1490527932
Short name T977
Test name
Test status
Simulation time 28468451 ps
CPU time 1.51 seconds
Started Aug 10 04:42:31 PM PDT 24
Finished Aug 10 04:42:33 PM PDT 24
Peak memory 206068 kb
Host smart-e8346e6f-27ee-4f21-9968-30d7738e0387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490527932 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1490527932
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1304216366
Short name T983
Test name
Test status
Simulation time 60092776 ps
CPU time 1.7 seconds
Started Aug 10 04:42:34 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 206032 kb
Host smart-d7d0ddab-aba3-428b-b9ce-2634eac2da0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304216366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1304216366
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3637325524
Short name T976
Test name
Test status
Simulation time 12447451 ps
CPU time 0.88 seconds
Started Aug 10 04:42:31 PM PDT 24
Finished Aug 10 04:42:32 PM PDT 24
Peak memory 205848 kb
Host smart-f831d3d3-829c-4c39-ae3c-1fd952368ad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637325524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3637325524
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1579326763
Short name T145
Test name
Test status
Simulation time 173085962 ps
CPU time 1.82 seconds
Started Aug 10 04:42:33 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 205924 kb
Host smart-d74a123a-2264-428b-b7ae-b6a5a8b643d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579326763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1579326763
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.962324324
Short name T119
Test name
Test status
Simulation time 187131877 ps
CPU time 2.65 seconds
Started Aug 10 04:42:33 PM PDT 24
Finished Aug 10 04:42:37 PM PDT 24
Peak memory 214644 kb
Host smart-4f7e5cc1-48be-49ce-9bcf-a6b13cb6cb3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962324324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.962324324
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2424383969
Short name T951
Test name
Test status
Simulation time 176916452 ps
CPU time 4.91 seconds
Started Aug 10 04:42:34 PM PDT 24
Finished Aug 10 04:42:39 PM PDT 24
Peak memory 220372 kb
Host smart-6cab7d08-962b-49be-98df-b5b54aad423c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424383969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2424383969
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.4289689575
Short name T1056
Test name
Test status
Simulation time 89299531 ps
CPU time 3.11 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 214320 kb
Host smart-63a0fddc-6c7f-4638-a9ed-4a1014619482
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289689575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.4289689575
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3317966134
Short name T380
Test name
Test status
Simulation time 936259291 ps
CPU time 7.14 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:42 PM PDT 24
Peak memory 205940 kb
Host smart-75fb4f1c-8ca0-48e1-b320-0c89a838a4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317966134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3317966134
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1749118156
Short name T1012
Test name
Test status
Simulation time 88853405 ps
CPU time 2.22 seconds
Started Aug 10 04:42:30 PM PDT 24
Finished Aug 10 04:42:32 PM PDT 24
Peak memory 214540 kb
Host smart-3d798df3-b82f-49f6-b798-032ec2138568
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749118156 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1749118156
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3702254243
Short name T142
Test name
Test status
Simulation time 12970088 ps
CPU time 1.09 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:34 PM PDT 24
Peak memory 205952 kb
Host smart-05cb25de-0206-4745-857b-6163ddca20ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702254243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3702254243
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1170291214
Short name T1016
Test name
Test status
Simulation time 26583596 ps
CPU time 0.81 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 205880 kb
Host smart-6a2717e6-cd7a-4102-ab26-b1100b9cc973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170291214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1170291214
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3724676823
Short name T981
Test name
Test status
Simulation time 211279151 ps
CPU time 2.72 seconds
Started Aug 10 04:42:38 PM PDT 24
Finished Aug 10 04:42:41 PM PDT 24
Peak memory 206036 kb
Host smart-ff9e2a29-30f4-4c2a-8e3f-9d5876f0e3ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724676823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3724676823
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.715402258
Short name T947
Test name
Test status
Simulation time 311128499 ps
CPU time 2 seconds
Started Aug 10 04:42:33 PM PDT 24
Finished Aug 10 04:42:35 PM PDT 24
Peak memory 214640 kb
Host smart-a9d3639a-c2c0-4eda-9b35-e19f677a4371
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715402258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.715402258
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1835400361
Short name T991
Test name
Test status
Simulation time 2035633748 ps
CPU time 7.61 seconds
Started Aug 10 04:42:30 PM PDT 24
Finished Aug 10 04:42:38 PM PDT 24
Peak memory 214448 kb
Host smart-249dadf6-627b-489d-8e2a-3486346e1a25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835400361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1835400361
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3025982774
Short name T952
Test name
Test status
Simulation time 28831114 ps
CPU time 1.77 seconds
Started Aug 10 04:42:30 PM PDT 24
Finished Aug 10 04:42:32 PM PDT 24
Peak memory 214256 kb
Host smart-98fa35bd-ea6b-40f4-bc14-49f395306a03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025982774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3025982774
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1180017833
Short name T161
Test name
Test status
Simulation time 257955485 ps
CPU time 5.05 seconds
Started Aug 10 04:42:34 PM PDT 24
Finished Aug 10 04:42:39 PM PDT 24
Peak memory 215180 kb
Host smart-88abeb03-0801-4f0f-8f38-d4208639745f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180017833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1180017833
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2059589136
Short name T980
Test name
Test status
Simulation time 65892895 ps
CPU time 2.11 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:37 PM PDT 24
Peak memory 214376 kb
Host smart-67e50207-0967-4a53-89ba-130918b16fc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059589136 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2059589136
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3306400681
Short name T1025
Test name
Test status
Simulation time 31982167 ps
CPU time 1.08 seconds
Started Aug 10 04:42:33 PM PDT 24
Finished Aug 10 04:42:35 PM PDT 24
Peak memory 205996 kb
Host smart-3c3cea66-b444-4c4f-b561-b5cbbc638079
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306400681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3306400681
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1828058546
Short name T1004
Test name
Test status
Simulation time 23345177 ps
CPU time 0.73 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:33 PM PDT 24
Peak memory 205916 kb
Host smart-77a2555f-3273-4a6c-ad48-caffd82a13db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828058546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1828058546
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3406195363
Short name T972
Test name
Test status
Simulation time 181896685 ps
CPU time 2.31 seconds
Started Aug 10 04:42:31 PM PDT 24
Finished Aug 10 04:42:34 PM PDT 24
Peak memory 206252 kb
Host smart-9ca65219-9ba9-4c72-adcf-9dd350c2c5c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406195363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3406195363
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.988719823
Short name T114
Test name
Test status
Simulation time 404282133 ps
CPU time 1.67 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:35 PM PDT 24
Peak memory 214520 kb
Host smart-a23b9a3d-a569-42b7-8143-43e6c229a161
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988719823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.988719823
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1918636839
Short name T993
Test name
Test status
Simulation time 201493092 ps
CPU time 2.06 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:38 PM PDT 24
Peak memory 214448 kb
Host smart-cfe0ccd4-c66c-42bb-be26-f6160dfd1dba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918636839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1918636839
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2901693997
Short name T170
Test name
Test status
Simulation time 112380778 ps
CPU time 3.29 seconds
Started Aug 10 04:42:38 PM PDT 24
Finished Aug 10 04:42:41 PM PDT 24
Peak memory 215456 kb
Host smart-7b6bc40b-943f-4002-9f5f-f3452c75be9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901693997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2901693997
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3611283810
Short name T953
Test name
Test status
Simulation time 115661526 ps
CPU time 1.44 seconds
Started Aug 10 04:42:30 PM PDT 24
Finished Aug 10 04:42:31 PM PDT 24
Peak memory 206040 kb
Host smart-35a00a39-1de6-4f3f-a9ec-5fff76a3cae8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611283810 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3611283810
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4214755327
Short name T924
Test name
Test status
Simulation time 46907816 ps
CPU time 0.88 seconds
Started Aug 10 04:42:36 PM PDT 24
Finished Aug 10 04:42:37 PM PDT 24
Peak memory 205864 kb
Host smart-68723f53-b015-45e2-a553-1a0cb995b821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214755327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.4214755327
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2489509090
Short name T1034
Test name
Test status
Simulation time 27085911 ps
CPU time 0.72 seconds
Started Aug 10 04:42:37 PM PDT 24
Finished Aug 10 04:42:38 PM PDT 24
Peak memory 205812 kb
Host smart-0de0f54b-09f9-4c78-9128-fc5619f6fb82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489509090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2489509090
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3970729392
Short name T1013
Test name
Test status
Simulation time 139218628 ps
CPU time 2.59 seconds
Started Aug 10 04:42:33 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 206028 kb
Host smart-448265da-69f0-4632-89d9-c3a997f5843d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970729392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3970729392
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3151217625
Short name T933
Test name
Test status
Simulation time 194083728 ps
CPU time 3.1 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 214516 kb
Host smart-29c68868-7ffc-4ab6-945d-9eda80e100fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151217625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3151217625
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2423941725
Short name T122
Test name
Test status
Simulation time 165674785 ps
CPU time 4.55 seconds
Started Aug 10 04:42:31 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 214544 kb
Host smart-72b35b0b-916f-48ab-a8af-35cf7e4a0449
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423941725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2423941725
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4283826069
Short name T943
Test name
Test status
Simulation time 45097270 ps
CPU time 3.29 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 214300 kb
Host smart-6faf5cb3-dc2d-4118-b7e9-e543bdae889e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283826069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4283826069
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2254789901
Short name T925
Test name
Test status
Simulation time 102863397 ps
CPU time 1.51 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:37 PM PDT 24
Peak memory 206192 kb
Host smart-80704460-5f13-4f86-94c7-3fffc665d134
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254789901 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2254789901
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.38634854
Short name T923
Test name
Test status
Simulation time 70915960 ps
CPU time 1.21 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:34 PM PDT 24
Peak memory 206148 kb
Host smart-41dfb1b7-fc59-4eae-bc6d-05869df961ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38634854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.38634854
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1844086170
Short name T986
Test name
Test status
Simulation time 44253317 ps
CPU time 0.87 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:33 PM PDT 24
Peak memory 205804 kb
Host smart-77c7b956-f972-4066-b6ca-be949325f72a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844086170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1844086170
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2235973053
Short name T140
Test name
Test status
Simulation time 52665114 ps
CPU time 1.35 seconds
Started Aug 10 04:42:34 PM PDT 24
Finished Aug 10 04:42:36 PM PDT 24
Peak memory 205992 kb
Host smart-ed15cfe0-6d45-4c7a-bbf2-add6ff46eced
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235973053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2235973053
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1707724087
Short name T1055
Test name
Test status
Simulation time 166700373 ps
CPU time 5.06 seconds
Started Aug 10 04:42:37 PM PDT 24
Finished Aug 10 04:42:42 PM PDT 24
Peak memory 214572 kb
Host smart-b4eebdb9-3250-4da9-92a0-8fda261f70ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707724087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1707724087
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3544149586
Short name T1043
Test name
Test status
Simulation time 175290842 ps
CPU time 9.01 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:44 PM PDT 24
Peak memory 214540 kb
Host smart-e2a00a1d-931b-47dd-85e7-fb25e8c7530e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544149586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3544149586
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3787688349
Short name T927
Test name
Test status
Simulation time 26144557 ps
CPU time 1.51 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:37 PM PDT 24
Peak memory 222540 kb
Host smart-738427fb-f7a9-4340-aba4-191b3cca6cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787688349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3787688349
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2503548088
Short name T164
Test name
Test status
Simulation time 233159450 ps
CPU time 3.39 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:39 PM PDT 24
Peak memory 205972 kb
Host smart-41065fa5-8306-4f5d-b820-af92faae33cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503548088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2503548088
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.233856267
Short name T1049
Test name
Test status
Simulation time 925861844 ps
CPU time 2.81 seconds
Started Aug 10 04:42:48 PM PDT 24
Finished Aug 10 04:42:51 PM PDT 24
Peak memory 214296 kb
Host smart-ce157e17-7eaf-405d-9812-a4c6d155f18a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233856267 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.233856267
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1530790007
Short name T1017
Test name
Test status
Simulation time 128662577 ps
CPU time 0.88 seconds
Started Aug 10 04:42:33 PM PDT 24
Finished Aug 10 04:42:35 PM PDT 24
Peak memory 205756 kb
Host smart-0d8b34d2-7b0f-49e7-bc98-30310223aa16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530790007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1530790007
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2699448560
Short name T1060
Test name
Test status
Simulation time 12546189 ps
CPU time 0.8 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:34 PM PDT 24
Peak memory 205832 kb
Host smart-3b6ceaaa-0d0f-4fbc-b90a-6634b2f1c357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699448560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2699448560
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.620777334
Short name T1057
Test name
Test status
Simulation time 813223389 ps
CPU time 1.59 seconds
Started Aug 10 04:42:41 PM PDT 24
Finished Aug 10 04:42:42 PM PDT 24
Peak memory 206148 kb
Host smart-55a6f5bc-f6d6-4b08-a5a1-30063941a60a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620777334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.620777334
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3273444665
Short name T967
Test name
Test status
Simulation time 161645405 ps
CPU time 1.62 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:33 PM PDT 24
Peak memory 214640 kb
Host smart-cf6ed834-90db-4df9-bd86-87bef6a32b96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273444665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3273444665
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3858803755
Short name T975
Test name
Test status
Simulation time 1664031521 ps
CPU time 6.75 seconds
Started Aug 10 04:42:35 PM PDT 24
Finished Aug 10 04:42:42 PM PDT 24
Peak memory 214548 kb
Host smart-7a6909a2-2e20-4c7f-83ca-df70620438fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858803755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3858803755
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1565286731
Short name T973
Test name
Test status
Simulation time 130172889 ps
CPU time 2.29 seconds
Started Aug 10 04:42:32 PM PDT 24
Finished Aug 10 04:42:35 PM PDT 24
Peak memory 214376 kb
Host smart-2be8f02a-5813-4d42-956b-b833d05f5618
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565286731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1565286731
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1579177280
Short name T167
Test name
Test status
Simulation time 168300925 ps
CPU time 2.8 seconds
Started Aug 10 04:42:31 PM PDT 24
Finished Aug 10 04:42:34 PM PDT 24
Peak memory 206036 kb
Host smart-bab71ca4-077d-43a0-8146-665593108b36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579177280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1579177280
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.4188635210
Short name T965
Test name
Test status
Simulation time 3687629866 ps
CPU time 5.13 seconds
Started Aug 10 04:42:23 PM PDT 24
Finished Aug 10 04:42:28 PM PDT 24
Peak memory 206180 kb
Host smart-73369ae1-c142-4977-b9bc-1603155787f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188635210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.4
188635210
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1855087080
Short name T1048
Test name
Test status
Simulation time 439967942 ps
CPU time 13.22 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:33 PM PDT 24
Peak memory 206060 kb
Host smart-06e808f8-6741-4a53-9b7c-bd2114f3127e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855087080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
855087080
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3523185324
Short name T1002
Test name
Test status
Simulation time 62477933 ps
CPU time 0.96 seconds
Started Aug 10 04:42:19 PM PDT 24
Finished Aug 10 04:42:20 PM PDT 24
Peak memory 206016 kb
Host smart-be622ef0-05b2-4e84-a53e-d7b4c4220c28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523185324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
523185324
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1041502970
Short name T1053
Test name
Test status
Simulation time 25712735 ps
CPU time 1.79 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:22 PM PDT 24
Peak memory 214308 kb
Host smart-3d4efd50-7a41-48c5-891d-5ccbf30ccfba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041502970 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1041502970
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1469164486
Short name T961
Test name
Test status
Simulation time 573811887 ps
CPU time 1.8 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:22 PM PDT 24
Peak memory 206048 kb
Host smart-0e6e3c95-d6f8-4656-afad-a4f07d59c354
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469164486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1469164486
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3189882812
Short name T994
Test name
Test status
Simulation time 24383234 ps
CPU time 0.76 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:20 PM PDT 24
Peak memory 205728 kb
Host smart-a66ffdce-3043-40a8-926c-11f6114b7bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189882812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3189882812
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3106942521
Short name T1045
Test name
Test status
Simulation time 173148153 ps
CPU time 2.89 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 206048 kb
Host smart-17a1764f-c570-479e-a575-4501c63a7e35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106942521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3106942521
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3405125685
Short name T117
Test name
Test status
Simulation time 84508615 ps
CPU time 3.01 seconds
Started Aug 10 04:42:08 PM PDT 24
Finished Aug 10 04:42:11 PM PDT 24
Peak memory 214520 kb
Host smart-5a329840-4d84-4a54-bd01-d805d78cea3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405125685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3405125685
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3602624450
Short name T1003
Test name
Test status
Simulation time 332932376 ps
CPU time 4.71 seconds
Started Aug 10 04:42:07 PM PDT 24
Finished Aug 10 04:42:12 PM PDT 24
Peak memory 214628 kb
Host smart-5c95729a-9a91-4484-b576-427af57c082c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602624450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3602624450
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.622986109
Short name T934
Test name
Test status
Simulation time 109764331 ps
CPU time 3.76 seconds
Started Aug 10 04:42:08 PM PDT 24
Finished Aug 10 04:42:12 PM PDT 24
Peak memory 214280 kb
Host smart-a8e1f7e9-e6f1-477d-8c3d-78a0a8888f50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622986109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.622986109
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1164365442
Short name T1014
Test name
Test status
Simulation time 112463758 ps
CPU time 0.82 seconds
Started Aug 10 04:42:44 PM PDT 24
Finished Aug 10 04:42:45 PM PDT 24
Peak memory 205768 kb
Host smart-b3db45a8-2e9d-491a-89df-5d2040ffa389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164365442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1164365442
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1258309655
Short name T1061
Test name
Test status
Simulation time 38118678 ps
CPU time 0.71 seconds
Started Aug 10 04:42:44 PM PDT 24
Finished Aug 10 04:42:44 PM PDT 24
Peak memory 205836 kb
Host smart-4bbeeb50-2f6c-4e8f-a028-c7314ff091d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258309655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1258309655
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.77887932
Short name T935
Test name
Test status
Simulation time 29269897 ps
CPU time 0.71 seconds
Started Aug 10 04:42:41 PM PDT 24
Finished Aug 10 04:42:42 PM PDT 24
Peak memory 205824 kb
Host smart-b73ce48d-1b7f-4fd3-be14-a82d884f2ccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77887932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.77887932
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3134380115
Short name T1067
Test name
Test status
Simulation time 11676753 ps
CPU time 0.73 seconds
Started Aug 10 04:42:40 PM PDT 24
Finished Aug 10 04:42:41 PM PDT 24
Peak memory 205836 kb
Host smart-af86a1c1-6ed5-4e45-b197-5f56ca9bdf20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134380115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3134380115
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2566333067
Short name T970
Test name
Test status
Simulation time 15547545 ps
CPU time 0.93 seconds
Started Aug 10 04:42:42 PM PDT 24
Finished Aug 10 04:42:43 PM PDT 24
Peak memory 205932 kb
Host smart-bee2c655-b8b6-41a6-b6a7-c08a67d98a55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566333067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2566333067
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3515034544
Short name T1070
Test name
Test status
Simulation time 16311089 ps
CPU time 0.74 seconds
Started Aug 10 04:42:43 PM PDT 24
Finished Aug 10 04:42:44 PM PDT 24
Peak memory 205776 kb
Host smart-3dcbf6fe-dcb9-46b2-bb24-71bfa97b1225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515034544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3515034544
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3919664389
Short name T998
Test name
Test status
Simulation time 28531806 ps
CPU time 0.71 seconds
Started Aug 10 04:42:41 PM PDT 24
Finished Aug 10 04:42:41 PM PDT 24
Peak memory 205704 kb
Host smart-c2f94e52-ceb9-4464-a1cc-12084444d0ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919664389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3919664389
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.787604204
Short name T1068
Test name
Test status
Simulation time 52586998 ps
CPU time 0.86 seconds
Started Aug 10 04:42:43 PM PDT 24
Finished Aug 10 04:42:44 PM PDT 24
Peak memory 205900 kb
Host smart-f63a11e5-f0da-4339-98ec-ac4841bc9d97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787604204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.787604204
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3982742966
Short name T1000
Test name
Test status
Simulation time 30654866 ps
CPU time 0.67 seconds
Started Aug 10 04:42:40 PM PDT 24
Finished Aug 10 04:42:41 PM PDT 24
Peak memory 205724 kb
Host smart-1cc615bd-0531-4132-89c8-c12d1fc18f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982742966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3982742966
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1060045408
Short name T1026
Test name
Test status
Simulation time 11504110 ps
CPU time 0.75 seconds
Started Aug 10 04:42:49 PM PDT 24
Finished Aug 10 04:42:50 PM PDT 24
Peak memory 205704 kb
Host smart-65ce6919-f753-4551-828b-872e3ef43ba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060045408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1060045408
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3157065545
Short name T1062
Test name
Test status
Simulation time 133548460 ps
CPU time 9.01 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:29 PM PDT 24
Peak memory 206008 kb
Host smart-621d391a-5773-4693-bb3f-1453370a4944
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157065545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
157065545
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.269956989
Short name T1077
Test name
Test status
Simulation time 138696507 ps
CPU time 6.38 seconds
Started Aug 10 04:42:19 PM PDT 24
Finished Aug 10 04:42:26 PM PDT 24
Peak memory 206328 kb
Host smart-14d66c60-3e2c-4a03-a859-d93dd454e196
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269956989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.269956989
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4136715449
Short name T926
Test name
Test status
Simulation time 108120811 ps
CPU time 1.5 seconds
Started Aug 10 04:42:19 PM PDT 24
Finished Aug 10 04:42:21 PM PDT 24
Peak memory 205972 kb
Host smart-69d3c57a-51b8-4746-ab59-fc0bcb8284b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136715449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
136715449
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2646547127
Short name T1029
Test name
Test status
Simulation time 42857738 ps
CPU time 1.45 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:22 PM PDT 24
Peak memory 214496 kb
Host smart-45dbc880-23b0-4e45-ad04-682f74d22fa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646547127 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2646547127
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2634414063
Short name T1015
Test name
Test status
Simulation time 92284810 ps
CPU time 1.29 seconds
Started Aug 10 04:42:19 PM PDT 24
Finished Aug 10 04:42:20 PM PDT 24
Peak memory 206132 kb
Host smart-590b34f1-be11-45d8-86a9-ab78bd5864ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634414063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2634414063
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.276601470
Short name T1009
Test name
Test status
Simulation time 9677454 ps
CPU time 0.73 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:21 PM PDT 24
Peak memory 205820 kb
Host smart-fd77e820-f3bc-411e-b08a-6fce8e3b9721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276601470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.276601470
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1389302571
Short name T1011
Test name
Test status
Simulation time 84502324 ps
CPU time 3.83 seconds
Started Aug 10 04:42:23 PM PDT 24
Finished Aug 10 04:42:26 PM PDT 24
Peak memory 206192 kb
Host smart-fca87c09-1b9b-4e93-a82b-d5057c7580ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389302571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1389302571
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.585449894
Short name T1073
Test name
Test status
Simulation time 156316956 ps
CPU time 1.38 seconds
Started Aug 10 04:42:22 PM PDT 24
Finished Aug 10 04:42:24 PM PDT 24
Peak memory 214568 kb
Host smart-431ba2f0-5687-491c-b2b5-90a3aa7eade7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585449894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.585449894
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2059087832
Short name T988
Test name
Test status
Simulation time 785370572 ps
CPU time 5.49 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:27 PM PDT 24
Peak memory 220724 kb
Host smart-4b2cb566-2256-4841-b041-b055ce55a26c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059087832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2059087832
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1527132334
Short name T948
Test name
Test status
Simulation time 86994730 ps
CPU time 1.87 seconds
Started Aug 10 04:42:19 PM PDT 24
Finished Aug 10 04:42:21 PM PDT 24
Peak memory 214308 kb
Host smart-ba54d96a-71b3-42ac-8f6f-44a423d58ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527132334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1527132334
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1095325644
Short name T1027
Test name
Test status
Simulation time 80003160 ps
CPU time 0.79 seconds
Started Aug 10 04:42:46 PM PDT 24
Finished Aug 10 04:42:47 PM PDT 24
Peak memory 205800 kb
Host smart-d6fbaeb3-03c0-47b7-95f2-8c59a103ec12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095325644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1095325644
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2094040126
Short name T941
Test name
Test status
Simulation time 12665960 ps
CPU time 0.85 seconds
Started Aug 10 04:42:41 PM PDT 24
Finished Aug 10 04:42:42 PM PDT 24
Peak memory 205816 kb
Host smart-8286e9e4-7328-4200-bb66-d022fd9041ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094040126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2094040126
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.330761394
Short name T922
Test name
Test status
Simulation time 11713442 ps
CPU time 0.84 seconds
Started Aug 10 04:42:43 PM PDT 24
Finished Aug 10 04:42:44 PM PDT 24
Peak memory 205760 kb
Host smart-57f1fe85-574f-4a81-bd68-f6509669d616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330761394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.330761394
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.281235874
Short name T1081
Test name
Test status
Simulation time 28220322 ps
CPU time 0.83 seconds
Started Aug 10 04:42:47 PM PDT 24
Finished Aug 10 04:42:49 PM PDT 24
Peak memory 205788 kb
Host smart-6ae33b52-8182-4366-9cc2-a5ea0ea979d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281235874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.281235874
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3887774811
Short name T959
Test name
Test status
Simulation time 12939856 ps
CPU time 0.88 seconds
Started Aug 10 04:42:41 PM PDT 24
Finished Aug 10 04:42:42 PM PDT 24
Peak memory 205872 kb
Host smart-cea64c39-f798-446d-b9f4-e9a1412edcf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887774811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3887774811
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1214782232
Short name T1019
Test name
Test status
Simulation time 20578622 ps
CPU time 0.81 seconds
Started Aug 10 04:42:42 PM PDT 24
Finished Aug 10 04:42:43 PM PDT 24
Peak memory 205760 kb
Host smart-fffab5eb-7de9-434a-b53b-6ccba77f5471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214782232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1214782232
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4289597571
Short name T1069
Test name
Test status
Simulation time 10024467 ps
CPU time 0.82 seconds
Started Aug 10 04:42:51 PM PDT 24
Finished Aug 10 04:42:52 PM PDT 24
Peak memory 205788 kb
Host smart-8864e098-2221-4201-bc2a-19e0b41e61cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289597571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4289597571
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1001405050
Short name T954
Test name
Test status
Simulation time 11112523 ps
CPU time 0.86 seconds
Started Aug 10 04:42:43 PM PDT 24
Finished Aug 10 04:42:44 PM PDT 24
Peak memory 205828 kb
Host smart-a18a5d05-ab20-4620-94d9-e1702a181dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001405050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1001405050
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1778852343
Short name T955
Test name
Test status
Simulation time 15009892 ps
CPU time 0.95 seconds
Started Aug 10 04:42:46 PM PDT 24
Finished Aug 10 04:42:47 PM PDT 24
Peak memory 205960 kb
Host smart-1a2c3c1c-1243-423b-914f-99940425f6f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778852343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1778852343
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1003622077
Short name T938
Test name
Test status
Simulation time 12550579 ps
CPU time 0.72 seconds
Started Aug 10 04:42:44 PM PDT 24
Finished Aug 10 04:42:45 PM PDT 24
Peak memory 205836 kb
Host smart-d4653e08-1739-4490-a100-c8692d1c2fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003622077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1003622077
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2970813522
Short name T997
Test name
Test status
Simulation time 71020482 ps
CPU time 4.52 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:26 PM PDT 24
Peak memory 206128 kb
Host smart-c01dc215-2946-41b8-9ec1-feeb68ecb569
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970813522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
970813522
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1375158803
Short name T384
Test name
Test status
Simulation time 1003285900 ps
CPU time 14.61 seconds
Started Aug 10 04:42:22 PM PDT 24
Finished Aug 10 04:42:37 PM PDT 24
Peak memory 205956 kb
Host smart-5b06b492-fb76-4b2a-a79d-05887204105f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375158803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
375158803
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3833681986
Short name T932
Test name
Test status
Simulation time 60960580 ps
CPU time 1.22 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:21 PM PDT 24
Peak memory 206076 kb
Host smart-6b91562d-db5c-466f-b71d-a6e977db9588
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833681986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
833681986
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1614284377
Short name T963
Test name
Test status
Simulation time 83646246 ps
CPU time 1.1 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:21 PM PDT 24
Peak memory 206084 kb
Host smart-6e354f80-d73a-4b05-b86f-89a03a16e8e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614284377 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1614284377
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3796603841
Short name T1010
Test name
Test status
Simulation time 82625722 ps
CPU time 1.04 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 205944 kb
Host smart-109bb5eb-a314-4e34-9f8b-b02cbd4bed46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796603841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3796603841
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1013998691
Short name T992
Test name
Test status
Simulation time 53910789 ps
CPU time 0.79 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:21 PM PDT 24
Peak memory 205816 kb
Host smart-fb87f079-0d33-4f2c-b8cb-a88871708125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013998691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1013998691
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4096840899
Short name T139
Test name
Test status
Simulation time 87841839 ps
CPU time 2.47 seconds
Started Aug 10 04:42:17 PM PDT 24
Finished Aug 10 04:42:20 PM PDT 24
Peak memory 206112 kb
Host smart-85919367-0ba4-4a50-87cc-49f8c957fee8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096840899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.4096840899
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2452017467
Short name T1037
Test name
Test status
Simulation time 362936525 ps
CPU time 3.44 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:25 PM PDT 24
Peak memory 214608 kb
Host smart-df2bb898-9dd3-4fff-862d-235f8dd4a712
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452017467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2452017467
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2903587331
Short name T989
Test name
Test status
Simulation time 856168178 ps
CPU time 9.83 seconds
Started Aug 10 04:42:22 PM PDT 24
Finished Aug 10 04:42:32 PM PDT 24
Peak memory 214564 kb
Host smart-bf59c75e-deed-4cb2-b22b-973d40451628
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903587331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2903587331
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.832090353
Short name T969
Test name
Test status
Simulation time 603090882 ps
CPU time 3.84 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:25 PM PDT 24
Peak memory 214376 kb
Host smart-07cfbeb2-1192-4e68-a64e-57c311e661e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832090353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.832090353
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2993227620
Short name T173
Test name
Test status
Simulation time 101489979 ps
CPU time 4.81 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:25 PM PDT 24
Peak memory 214252 kb
Host smart-ceb407f1-35cf-49cb-8d0f-5c5c01ef8939
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993227620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2993227620
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.561082542
Short name T928
Test name
Test status
Simulation time 39969367 ps
CPU time 0.76 seconds
Started Aug 10 04:42:42 PM PDT 24
Finished Aug 10 04:42:43 PM PDT 24
Peak memory 205776 kb
Host smart-fa70dcb3-3f88-456d-acf1-daf362fb16c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561082542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.561082542
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3034959958
Short name T1072
Test name
Test status
Simulation time 14685980 ps
CPU time 0.81 seconds
Started Aug 10 04:42:48 PM PDT 24
Finished Aug 10 04:42:50 PM PDT 24
Peak memory 205788 kb
Host smart-8e56f057-bd42-4069-9dd7-f62a57cf5590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034959958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3034959958
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2325937613
Short name T979
Test name
Test status
Simulation time 70368303 ps
CPU time 0.91 seconds
Started Aug 10 04:42:47 PM PDT 24
Finished Aug 10 04:42:48 PM PDT 24
Peak memory 205788 kb
Host smart-ee58bf92-55f6-4c16-a03e-5352057d6789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325937613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2325937613
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2172383900
Short name T939
Test name
Test status
Simulation time 29746002 ps
CPU time 0.71 seconds
Started Aug 10 04:42:47 PM PDT 24
Finished Aug 10 04:42:48 PM PDT 24
Peak memory 205728 kb
Host smart-dd66b9b8-dc56-4677-b1e5-f27fd5ec9f75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172383900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2172383900
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2466679989
Short name T1047
Test name
Test status
Simulation time 19247073 ps
CPU time 0.71 seconds
Started Aug 10 04:42:46 PM PDT 24
Finished Aug 10 04:42:46 PM PDT 24
Peak memory 205728 kb
Host smart-de21439c-4be5-431d-a5b4-3897b190a438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466679989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2466679989
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3697253069
Short name T1040
Test name
Test status
Simulation time 42555985 ps
CPU time 0.75 seconds
Started Aug 10 04:42:44 PM PDT 24
Finished Aug 10 04:42:45 PM PDT 24
Peak memory 205760 kb
Host smart-4db07165-0aa0-4038-82f6-0b9c72879a4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697253069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3697253069
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1959964633
Short name T964
Test name
Test status
Simulation time 49095968 ps
CPU time 0.73 seconds
Started Aug 10 04:42:43 PM PDT 24
Finished Aug 10 04:42:44 PM PDT 24
Peak memory 205776 kb
Host smart-6e6f756e-ff09-4159-a7b1-d2478e905b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959964633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1959964633
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1145415941
Short name T1024
Test name
Test status
Simulation time 39950589 ps
CPU time 0.84 seconds
Started Aug 10 04:42:43 PM PDT 24
Finished Aug 10 04:42:43 PM PDT 24
Peak memory 205900 kb
Host smart-7d4ed154-9fe0-4ef9-8f86-b0037c38a511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145415941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1145415941
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2489958632
Short name T949
Test name
Test status
Simulation time 9654322 ps
CPU time 0.73 seconds
Started Aug 10 04:42:40 PM PDT 24
Finished Aug 10 04:42:41 PM PDT 24
Peak memory 205752 kb
Host smart-814a8b1f-cd35-4d54-9920-ae2fda67ae62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489958632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2489958632
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1938511155
Short name T950
Test name
Test status
Simulation time 104496159 ps
CPU time 0.86 seconds
Started Aug 10 04:42:43 PM PDT 24
Finished Aug 10 04:42:44 PM PDT 24
Peak memory 205828 kb
Host smart-20d67fbb-4153-49c0-80c2-19029b16388d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938511155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1938511155
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3073180960
Short name T1075
Test name
Test status
Simulation time 47078121 ps
CPU time 2.17 seconds
Started Aug 10 04:42:19 PM PDT 24
Finished Aug 10 04:42:21 PM PDT 24
Peak memory 214392 kb
Host smart-a98ad9e4-8182-44f4-9c5e-7690843fe761
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073180960 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3073180960
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2572954144
Short name T182
Test name
Test status
Simulation time 22953913 ps
CPU time 1.14 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 206020 kb
Host smart-b687eeda-930e-4ec0-afda-eb1324d09dd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572954144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2572954144
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1015348166
Short name T917
Test name
Test status
Simulation time 14717504 ps
CPU time 0.76 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:20 PM PDT 24
Peak memory 205776 kb
Host smart-a0c371b2-6be2-427f-86eb-431332e9f9fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015348166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1015348166
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.504141033
Short name T1006
Test name
Test status
Simulation time 182856888 ps
CPU time 2.38 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 206160 kb
Host smart-ba429074-c7cf-495d-9a10-bfd9c48816c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504141033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.504141033
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3916432651
Short name T121
Test name
Test status
Simulation time 297188845 ps
CPU time 1.98 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:22 PM PDT 24
Peak memory 214572 kb
Host smart-0bb9e432-90bf-4f34-8a12-51b6bd281393
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916432651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3916432651
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2429163226
Short name T1076
Test name
Test status
Simulation time 210612332 ps
CPU time 4.86 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:25 PM PDT 24
Peak memory 220688 kb
Host smart-8ea41aeb-98d8-4c05-bc1c-47488b95a9a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429163226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2429163226
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2970593762
Short name T940
Test name
Test status
Simulation time 159659630 ps
CPU time 3.72 seconds
Started Aug 10 04:42:19 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 214300 kb
Host smart-761350ba-9b9d-4605-abe2-a25e2134b128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970593762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2970593762
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3283308137
Short name T162
Test name
Test status
Simulation time 94426898 ps
CPU time 3.38 seconds
Started Aug 10 04:42:19 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 214180 kb
Host smart-9a0c3eee-2bec-451a-b5fe-2918dc7cc927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283308137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3283308137
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1047288604
Short name T1044
Test name
Test status
Simulation time 138866598 ps
CPU time 1.54 seconds
Started Aug 10 04:42:24 PM PDT 24
Finished Aug 10 04:42:25 PM PDT 24
Peak memory 218140 kb
Host smart-8f580098-cb0a-4495-b375-3973a533c5a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047288604 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1047288604
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.233487058
Short name T920
Test name
Test status
Simulation time 23359843 ps
CPU time 1.17 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 206040 kb
Host smart-a07a9c14-7cb1-4ce9-9715-e93f3c2ee518
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233487058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.233487058
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.677449913
Short name T1054
Test name
Test status
Simulation time 41109114 ps
CPU time 0.74 seconds
Started Aug 10 04:42:22 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 205776 kb
Host smart-d03c3779-3cde-4162-b1fa-3352b33d2322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677449913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.677449913
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1446115366
Short name T974
Test name
Test status
Simulation time 337883193 ps
CPU time 2.82 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:24 PM PDT 24
Peak memory 205956 kb
Host smart-8b97fdad-6c09-4aaf-9e57-050d4199a04a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446115366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1446115366
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3146386684
Short name T1052
Test name
Test status
Simulation time 677539411 ps
CPU time 5.81 seconds
Started Aug 10 04:42:22 PM PDT 24
Finished Aug 10 04:42:28 PM PDT 24
Peak memory 214576 kb
Host smart-9d972a2b-8c9b-4ef1-a53f-9f6bab6c67e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146386684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3146386684
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2714217778
Short name T1051
Test name
Test status
Simulation time 366089545 ps
CPU time 4.67 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:24 PM PDT 24
Peak memory 220384 kb
Host smart-64e2e775-d33e-4ca8-b7a8-f5d4d5551528
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714217778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2714217778
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3117437493
Short name T1078
Test name
Test status
Simulation time 143102769 ps
CPU time 5.14 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:26 PM PDT 24
Peak memory 214164 kb
Host smart-4bb0d1bd-579e-48b3-9ed8-73c561adddaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117437493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3117437493
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1339295665
Short name T1008
Test name
Test status
Simulation time 53640884 ps
CPU time 1.07 seconds
Started Aug 10 04:42:18 PM PDT 24
Finished Aug 10 04:42:19 PM PDT 24
Peak memory 205980 kb
Host smart-7391ce1e-45fb-4c84-8014-21da6fb777e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339295665 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1339295665
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.315566839
Short name T1065
Test name
Test status
Simulation time 33348547 ps
CPU time 1.6 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 206076 kb
Host smart-81b3434e-f6e7-43e7-9fcc-b237ce72cb53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315566839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.315566839
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.328184601
Short name T1001
Test name
Test status
Simulation time 24952801 ps
CPU time 0.75 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:21 PM PDT 24
Peak memory 205752 kb
Host smart-02916a7c-c265-43a8-b9e8-3f0d2c25787a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328184601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.328184601
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3981830114
Short name T971
Test name
Test status
Simulation time 326527817 ps
CPU time 3.67 seconds
Started Aug 10 04:42:19 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 205928 kb
Host smart-5e9252d1-7d02-4533-96c8-322bc5bfcc78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981830114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3981830114
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1774492379
Short name T931
Test name
Test status
Simulation time 174991865 ps
CPU time 3.92 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:25 PM PDT 24
Peak memory 214512 kb
Host smart-d298364b-a40a-48a2-b756-e1cf414d8b37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774492379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1774492379
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2276466141
Short name T945
Test name
Test status
Simulation time 91446659 ps
CPU time 1.66 seconds
Started Aug 10 04:42:25 PM PDT 24
Finished Aug 10 04:42:26 PM PDT 24
Peak memory 216444 kb
Host smart-d37b4a16-11c4-41f5-a6ab-80a2ae1cf8fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276466141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2276466141
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2994147639
Short name T978
Test name
Test status
Simulation time 499718319 ps
CPU time 3.75 seconds
Started Aug 10 04:42:20 PM PDT 24
Finished Aug 10 04:42:24 PM PDT 24
Peak memory 206052 kb
Host smart-5fb22cd7-e4ca-413c-9538-6592496ac5ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994147639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2994147639
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3718317606
Short name T1083
Test name
Test status
Simulation time 70202115 ps
CPU time 2.26 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 214288 kb
Host smart-a7107e6d-81cc-4ec0-a599-5d04170babc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718317606 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3718317606
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2350450249
Short name T1031
Test name
Test status
Simulation time 46276991 ps
CPU time 1.29 seconds
Started Aug 10 04:42:22 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 206000 kb
Host smart-b0f1b5f0-6827-4920-b194-397cf2cd9005
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350450249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2350450249
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3452280801
Short name T1041
Test name
Test status
Simulation time 13398032 ps
CPU time 0.86 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:22 PM PDT 24
Peak memory 205740 kb
Host smart-07174cc2-7c9c-4a1d-aaee-278e486c18da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452280801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3452280801
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.726325482
Short name T141
Test name
Test status
Simulation time 518506402 ps
CPU time 4.96 seconds
Started Aug 10 04:42:24 PM PDT 24
Finished Aug 10 04:42:29 PM PDT 24
Peak memory 206048 kb
Host smart-da9fe689-6820-4c29-b5f4-db59a5cb7620
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726325482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.726325482
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1010787094
Short name T1059
Test name
Test status
Simulation time 82427189 ps
CPU time 2.92 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:24 PM PDT 24
Peak memory 214568 kb
Host smart-fa997fb1-733b-43ce-a0c8-89e64355fb54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010787094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1010787094
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3176934323
Short name T120
Test name
Test status
Simulation time 1036931083 ps
CPU time 8.23 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:29 PM PDT 24
Peak memory 214484 kb
Host smart-3a4cd492-8274-4097-91db-dacc40342d94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176934323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3176934323
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.731211612
Short name T1063
Test name
Test status
Simulation time 68965805 ps
CPU time 1.92 seconds
Started Aug 10 04:42:25 PM PDT 24
Finished Aug 10 04:42:27 PM PDT 24
Peak memory 214236 kb
Host smart-535c2094-7b5f-4c00-9661-f4abf013406e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731211612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.731211612
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3077681780
Short name T171
Test name
Test status
Simulation time 179814409 ps
CPU time 2.68 seconds
Started Aug 10 04:42:25 PM PDT 24
Finished Aug 10 04:42:28 PM PDT 24
Peak memory 214356 kb
Host smart-034f9ba7-442f-4e00-9306-1b199fcbf45b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077681780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3077681780
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4250756487
Short name T960
Test name
Test status
Simulation time 47790086 ps
CPU time 1.68 seconds
Started Aug 10 04:42:24 PM PDT 24
Finished Aug 10 04:42:26 PM PDT 24
Peak memory 214396 kb
Host smart-8a9066af-5433-4f92-ba93-f4540e687df8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250756487 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.4250756487
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.901762695
Short name T1005
Test name
Test status
Simulation time 27568942 ps
CPU time 1.46 seconds
Started Aug 10 04:42:24 PM PDT 24
Finished Aug 10 04:42:26 PM PDT 24
Peak memory 206060 kb
Host smart-5d2e5919-3cdd-4bc9-a32f-f76bf3c56ea4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901762695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.901762695
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3203586414
Short name T987
Test name
Test status
Simulation time 17378151 ps
CPU time 0.92 seconds
Started Aug 10 04:42:25 PM PDT 24
Finished Aug 10 04:42:26 PM PDT 24
Peak memory 205908 kb
Host smart-9fbc4b45-e625-4379-9ea5-c62866f9e3f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203586414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3203586414
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1379625384
Short name T968
Test name
Test status
Simulation time 90834209 ps
CPU time 2.72 seconds
Started Aug 10 04:42:23 PM PDT 24
Finished Aug 10 04:42:25 PM PDT 24
Peak memory 206076 kb
Host smart-5dc38b22-cdff-466b-a51f-582e35e27f53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379625384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1379625384
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1279852755
Short name T118
Test name
Test status
Simulation time 433212780 ps
CPU time 2.68 seconds
Started Aug 10 04:42:24 PM PDT 24
Finished Aug 10 04:42:26 PM PDT 24
Peak memory 214632 kb
Host smart-eddd9a1e-b52a-4c5d-aa95-661e6836088b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279852755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1279852755
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3351558430
Short name T1050
Test name
Test status
Simulation time 304921442 ps
CPU time 6.5 seconds
Started Aug 10 04:42:24 PM PDT 24
Finished Aug 10 04:42:30 PM PDT 24
Peak memory 214548 kb
Host smart-03253d89-c284-46a1-a1ba-2643ec7c188b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351558430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3351558430
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3945317081
Short name T996
Test name
Test status
Simulation time 244779286 ps
CPU time 1.97 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:23 PM PDT 24
Peak memory 215392 kb
Host smart-96baba85-e3f1-4ee7-9520-5b5cca097fd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945317081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3945317081
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2597823759
Short name T166
Test name
Test status
Simulation time 121742546 ps
CPU time 5.6 seconds
Started Aug 10 04:42:21 PM PDT 24
Finished Aug 10 04:42:27 PM PDT 24
Peak memory 214244 kb
Host smart-09de9217-6f60-4668-9d11-4ad85e52a877
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597823759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2597823759
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3626504738
Short name T1
Test name
Test status
Simulation time 355895306 ps
CPU time 4.37 seconds
Started Aug 10 04:50:21 PM PDT 24
Finished Aug 10 04:50:25 PM PDT 24
Peak memory 215392 kb
Host smart-85bf6b44-8f03-414c-bbc7-f313c3dfc7d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3626504738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3626504738
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1076503117
Short name T44
Test name
Test status
Simulation time 159609287 ps
CPU time 3.11 seconds
Started Aug 10 04:50:21 PM PDT 24
Finished Aug 10 04:50:24 PM PDT 24
Peak memory 209552 kb
Host smart-632848c2-d362-45f1-a5a1-340a020f0627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076503117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1076503117
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.834293425
Short name T340
Test name
Test status
Simulation time 281195749 ps
CPU time 2.68 seconds
Started Aug 10 04:50:20 PM PDT 24
Finished Aug 10 04:50:23 PM PDT 24
Peak memory 214088 kb
Host smart-7801ce07-1f18-472e-8024-11f76857f9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834293425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.834293425
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3802524367
Short name T901
Test name
Test status
Simulation time 308232283 ps
CPU time 2.15 seconds
Started Aug 10 04:50:21 PM PDT 24
Finished Aug 10 04:50:23 PM PDT 24
Peak memory 215268 kb
Host smart-12166c45-3775-4d74-976a-d54bea62dbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802524367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3802524367
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.4181021869
Short name T455
Test name
Test status
Simulation time 102604939 ps
CPU time 3.47 seconds
Started Aug 10 04:50:21 PM PDT 24
Finished Aug 10 04:50:25 PM PDT 24
Peak memory 208064 kb
Host smart-05b3d058-5db1-4824-bcf7-97e8eb2b52d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181021869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.4181021869
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2815872596
Short name T42
Test name
Test status
Simulation time 733803817 ps
CPU time 20.95 seconds
Started Aug 10 04:50:28 PM PDT 24
Finished Aug 10 04:50:49 PM PDT 24
Peak memory 230720 kb
Host smart-ec22d6ad-7422-40be-a2c9-ecf9dd3fb0d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815872596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2815872596
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1260170788
Short name T464
Test name
Test status
Simulation time 673863538 ps
CPU time 3.36 seconds
Started Aug 10 04:50:12 PM PDT 24
Finished Aug 10 04:50:15 PM PDT 24
Peak memory 208560 kb
Host smart-5351db86-76cd-4545-9301-e21433863132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260170788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1260170788
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.4234791059
Short name T466
Test name
Test status
Simulation time 522058196 ps
CPU time 19.34 seconds
Started Aug 10 04:50:20 PM PDT 24
Finished Aug 10 04:50:39 PM PDT 24
Peak memory 208824 kb
Host smart-14bb8acf-b1ee-41aa-a05b-0c8573fe64d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234791059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.4234791059
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3284838585
Short name T613
Test name
Test status
Simulation time 129075870 ps
CPU time 4.03 seconds
Started Aug 10 04:50:12 PM PDT 24
Finished Aug 10 04:50:16 PM PDT 24
Peak memory 207984 kb
Host smart-7d8bb5e5-23d0-4bf4-99b7-98e9ca8d2d3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284838585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3284838585
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1927643795
Short name T777
Test name
Test status
Simulation time 468044004 ps
CPU time 11.7 seconds
Started Aug 10 04:50:19 PM PDT 24
Finished Aug 10 04:50:31 PM PDT 24
Peak memory 208144 kb
Host smart-e46de50b-d76e-4b3e-9899-be081020cc08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927643795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1927643795
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.388228060
Short name T630
Test name
Test status
Simulation time 93103982 ps
CPU time 2.2 seconds
Started Aug 10 04:50:26 PM PDT 24
Finished Aug 10 04:50:29 PM PDT 24
Peak memory 209228 kb
Host smart-904d350a-96db-46f0-b2a1-27d9a960917c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388228060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.388228060
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2636924101
Short name T387
Test name
Test status
Simulation time 28299967 ps
CPU time 1.9 seconds
Started Aug 10 04:50:12 PM PDT 24
Finished Aug 10 04:50:14 PM PDT 24
Peak memory 208116 kb
Host smart-a0812b88-361d-4e87-ac8c-3b388415c9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636924101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2636924101
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3200737976
Short name T472
Test name
Test status
Simulation time 115986458 ps
CPU time 4.79 seconds
Started Aug 10 04:50:19 PM PDT 24
Finished Aug 10 04:50:24 PM PDT 24
Peak memory 208464 kb
Host smart-3a0c1290-643e-45d0-8047-fdcfa29b4945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200737976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3200737976
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2071192175
Short name T710
Test name
Test status
Simulation time 62384326 ps
CPU time 2.83 seconds
Started Aug 10 04:50:27 PM PDT 24
Finished Aug 10 04:50:30 PM PDT 24
Peak memory 209728 kb
Host smart-96f79bfd-2c9e-46f7-a6d4-a2b66f0d0a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071192175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2071192175
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.4129098513
Short name T762
Test name
Test status
Simulation time 57959574 ps
CPU time 0.81 seconds
Started Aug 10 04:50:46 PM PDT 24
Finished Aug 10 04:50:47 PM PDT 24
Peak memory 205864 kb
Host smart-89fd9352-fb92-43be-b7fc-63d80c5f5d52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129098513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4129098513
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2403165783
Short name T402
Test name
Test status
Simulation time 57882040 ps
CPU time 2.51 seconds
Started Aug 10 04:50:36 PM PDT 24
Finished Aug 10 04:50:38 PM PDT 24
Peak memory 214292 kb
Host smart-5b875810-ddc3-4988-ac37-359ec151a550
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403165783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2403165783
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.49817622
Short name T66
Test name
Test status
Simulation time 360922358 ps
CPU time 4.27 seconds
Started Aug 10 04:50:46 PM PDT 24
Finished Aug 10 04:50:50 PM PDT 24
Peak memory 208588 kb
Host smart-88d56407-9856-4306-95f8-52996f7b0187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49817622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.49817622
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1527998084
Short name T297
Test name
Test status
Simulation time 163373139 ps
CPU time 1.81 seconds
Started Aug 10 04:50:36 PM PDT 24
Finished Aug 10 04:50:37 PM PDT 24
Peak memory 209304 kb
Host smart-97a945e4-6ada-425c-8462-07938271dc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527998084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1527998084
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.697561970
Short name T91
Test name
Test status
Simulation time 2192560654 ps
CPU time 5.6 seconds
Started Aug 10 04:50:45 PM PDT 24
Finished Aug 10 04:50:51 PM PDT 24
Peak memory 209176 kb
Host smart-9cc0806e-b61c-4c2e-be3f-25a3f44497f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697561970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.697561970
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3600789678
Short name T323
Test name
Test status
Simulation time 75421638 ps
CPU time 3.46 seconds
Started Aug 10 04:50:45 PM PDT 24
Finished Aug 10 04:50:49 PM PDT 24
Peak memory 214168 kb
Host smart-5746bbca-5896-4c24-89f0-6c6009054d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600789678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3600789678
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.819425400
Short name T618
Test name
Test status
Simulation time 290940668 ps
CPU time 4.07 seconds
Started Aug 10 04:50:37 PM PDT 24
Finished Aug 10 04:50:41 PM PDT 24
Peak memory 208728 kb
Host smart-b0d56e41-733f-4d2e-b92d-ce52612c0ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819425400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.819425400
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2465086199
Short name T12
Test name
Test status
Simulation time 418701089 ps
CPU time 5.1 seconds
Started Aug 10 04:50:44 PM PDT 24
Finished Aug 10 04:50:50 PM PDT 24
Peak memory 236968 kb
Host smart-378f6b8f-dcc6-4f62-b7bc-624262d4303e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465086199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2465086199
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1405638273
Short name T714
Test name
Test status
Simulation time 49830871 ps
CPU time 1.66 seconds
Started Aug 10 04:50:36 PM PDT 24
Finished Aug 10 04:50:37 PM PDT 24
Peak memory 206724 kb
Host smart-2379e236-cc30-4879-befe-80afccd4257e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405638273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1405638273
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3941382878
Short name T440
Test name
Test status
Simulation time 18248925 ps
CPU time 1.77 seconds
Started Aug 10 04:50:37 PM PDT 24
Finished Aug 10 04:50:39 PM PDT 24
Peak memory 206816 kb
Host smart-aac7a857-f729-4e0e-9d36-6d3d5070a53a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941382878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3941382878
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.886170795
Short name T449
Test name
Test status
Simulation time 195080892 ps
CPU time 2.81 seconds
Started Aug 10 04:50:34 PM PDT 24
Finished Aug 10 04:50:37 PM PDT 24
Peak memory 206972 kb
Host smart-12b0a3c0-3ff4-418b-8858-177a949497c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886170795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.886170795
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3102918942
Short name T263
Test name
Test status
Simulation time 4903630572 ps
CPU time 40.15 seconds
Started Aug 10 04:50:35 PM PDT 24
Finished Aug 10 04:51:16 PM PDT 24
Peak memory 208680 kb
Host smart-65d314fa-c2b1-4fb2-aa6c-ff7e3b940a40
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102918942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3102918942
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1985781983
Short name T756
Test name
Test status
Simulation time 35266509 ps
CPU time 2.28 seconds
Started Aug 10 04:50:44 PM PDT 24
Finished Aug 10 04:50:46 PM PDT 24
Peak memory 215976 kb
Host smart-de4cfe91-c5c1-4bd1-bfb9-38f53258bcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985781983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1985781983
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2444799365
Short name T422
Test name
Test status
Simulation time 321366778 ps
CPU time 4.06 seconds
Started Aug 10 04:50:35 PM PDT 24
Finished Aug 10 04:50:39 PM PDT 24
Peak memory 208520 kb
Host smart-22f24828-7a22-46ba-96fb-f2dd7fc3e044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444799365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2444799365
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.322276353
Short name T860
Test name
Test status
Simulation time 217009116 ps
CPU time 4.35 seconds
Started Aug 10 04:50:46 PM PDT 24
Finished Aug 10 04:50:50 PM PDT 24
Peak memory 207872 kb
Host smart-1df3c406-a785-4f6c-929b-caa9c86acf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322276353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.322276353
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1375082634
Short name T383
Test name
Test status
Simulation time 763928943 ps
CPU time 5.73 seconds
Started Aug 10 04:50:44 PM PDT 24
Finished Aug 10 04:50:50 PM PDT 24
Peak memory 210056 kb
Host smart-378a1265-4370-4254-a034-8e1f5b42469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375082634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1375082634
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3669756663
Short name T589
Test name
Test status
Simulation time 10648171 ps
CPU time 0.9 seconds
Started Aug 10 04:52:17 PM PDT 24
Finished Aug 10 04:52:18 PM PDT 24
Peak memory 205804 kb
Host smart-6b1545a4-daf2-4ca7-882f-36876b55bdbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669756663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3669756663
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.358890328
Short name T614
Test name
Test status
Simulation time 978737021 ps
CPU time 4.66 seconds
Started Aug 10 04:52:13 PM PDT 24
Finished Aug 10 04:52:18 PM PDT 24
Peak memory 210388 kb
Host smart-3e74e1ed-c2e6-4b82-aabf-40801bd5688b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358890328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.358890328
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1275077317
Short name T255
Test name
Test status
Simulation time 564446661 ps
CPU time 19.39 seconds
Started Aug 10 04:52:06 PM PDT 24
Finished Aug 10 04:52:25 PM PDT 24
Peak memory 209892 kb
Host smart-da8645cd-eed5-4b64-89f1-dab31df139b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275077317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1275077317
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2955840206
Short name T187
Test name
Test status
Simulation time 224601281 ps
CPU time 2.39 seconds
Started Aug 10 04:52:08 PM PDT 24
Finished Aug 10 04:52:11 PM PDT 24
Peak memory 222432 kb
Host smart-8c41a6c6-9644-4cb6-9311-cd980023a2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955840206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2955840206
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2308581474
Short name T184
Test name
Test status
Simulation time 94763565 ps
CPU time 1.49 seconds
Started Aug 10 04:52:08 PM PDT 24
Finished Aug 10 04:52:10 PM PDT 24
Peak memory 214268 kb
Host smart-9960a966-7dcd-40b5-b02c-b1b0fcaf75fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308581474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2308581474
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.27508721
Short name T666
Test name
Test status
Simulation time 64871265 ps
CPU time 2.47 seconds
Started Aug 10 04:52:06 PM PDT 24
Finished Aug 10 04:52:09 PM PDT 24
Peak memory 207884 kb
Host smart-cf1a43e7-e98c-4396-b90e-1f32114428f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27508721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.27508721
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1037312339
Short name T189
Test name
Test status
Simulation time 79817894 ps
CPU time 2.51 seconds
Started Aug 10 04:52:05 PM PDT 24
Finished Aug 10 04:52:07 PM PDT 24
Peak memory 206728 kb
Host smart-d5f19f81-e5ed-4985-abde-50deb5f4ab0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037312339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1037312339
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3734112501
Short name T585
Test name
Test status
Simulation time 47975386 ps
CPU time 2.67 seconds
Started Aug 10 04:52:06 PM PDT 24
Finished Aug 10 04:52:09 PM PDT 24
Peak memory 207012 kb
Host smart-ddada46c-55f1-4332-b7c9-5325bbc78c12
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734112501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3734112501
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.474641137
Short name T456
Test name
Test status
Simulation time 81448088 ps
CPU time 2.56 seconds
Started Aug 10 04:52:06 PM PDT 24
Finished Aug 10 04:52:08 PM PDT 24
Peak memory 206896 kb
Host smart-e1a4709d-9036-49f3-9d3a-069e2c569055
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474641137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.474641137
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3831062178
Short name T657
Test name
Test status
Simulation time 2767117492 ps
CPU time 39.75 seconds
Started Aug 10 04:52:05 PM PDT 24
Finished Aug 10 04:52:45 PM PDT 24
Peak memory 208376 kb
Host smart-83a4bd14-6653-44cd-acec-3d8c472f3ef5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831062178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3831062178
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.4147909426
Short name T791
Test name
Test status
Simulation time 115369932 ps
CPU time 2.9 seconds
Started Aug 10 04:52:13 PM PDT 24
Finished Aug 10 04:52:16 PM PDT 24
Peak memory 208980 kb
Host smart-16e52683-70db-4cd8-b54b-e232c19a2ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147909426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.4147909426
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3102716442
Short name T535
Test name
Test status
Simulation time 101178574 ps
CPU time 2.4 seconds
Started Aug 10 04:52:06 PM PDT 24
Finished Aug 10 04:52:08 PM PDT 24
Peak memory 208452 kb
Host smart-e039328d-0d41-4302-ada8-2b107528075f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102716442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3102716442
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1554522339
Short name T315
Test name
Test status
Simulation time 902256669 ps
CPU time 11.49 seconds
Started Aug 10 04:52:15 PM PDT 24
Finished Aug 10 04:52:26 PM PDT 24
Peak memory 214700 kb
Host smart-f97d069b-b750-421a-a80e-6e8038b15b1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554522339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1554522339
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2490921107
Short name T583
Test name
Test status
Simulation time 1582927756 ps
CPU time 24.69 seconds
Started Aug 10 04:52:05 PM PDT 24
Finished Aug 10 04:52:30 PM PDT 24
Peak memory 208920 kb
Host smart-d32197ac-4ba7-48ff-993e-254df8c75523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490921107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2490921107
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3217241315
Short name T680
Test name
Test status
Simulation time 12379116 ps
CPU time 0.84 seconds
Started Aug 10 04:52:25 PM PDT 24
Finished Aug 10 04:52:26 PM PDT 24
Peak memory 205848 kb
Host smart-e32bfdb4-b15c-42f0-a494-b59fc27e55ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217241315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3217241315
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1844310123
Short name T821
Test name
Test status
Simulation time 119531812 ps
CPU time 2.7 seconds
Started Aug 10 04:52:14 PM PDT 24
Finished Aug 10 04:52:17 PM PDT 24
Peak memory 215004 kb
Host smart-088d3ba3-43c9-4b64-a8db-fe3215adcfb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844310123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1844310123
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2410314669
Short name T32
Test name
Test status
Simulation time 60630739 ps
CPU time 4.28 seconds
Started Aug 10 04:52:14 PM PDT 24
Finished Aug 10 04:52:18 PM PDT 24
Peak memory 209876 kb
Host smart-d7744f15-1d6b-4e01-b8fe-eeb3661e810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410314669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2410314669
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.142090578
Short name T79
Test name
Test status
Simulation time 95934314 ps
CPU time 2.1 seconds
Started Aug 10 04:52:14 PM PDT 24
Finished Aug 10 04:52:16 PM PDT 24
Peak memory 214320 kb
Host smart-16a788f6-ec64-4f4b-b35d-54d0201d4261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142090578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.142090578
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2094756720
Short name T97
Test name
Test status
Simulation time 510966226 ps
CPU time 7.41 seconds
Started Aug 10 04:52:14 PM PDT 24
Finished Aug 10 04:52:22 PM PDT 24
Peak memory 222488 kb
Host smart-35361746-96d7-4769-bc76-43c1e3f49d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094756720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2094756720
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3445637122
Short name T319
Test name
Test status
Simulation time 34842517 ps
CPU time 2.14 seconds
Started Aug 10 04:52:18 PM PDT 24
Finished Aug 10 04:52:20 PM PDT 24
Peak memory 214160 kb
Host smart-8da6fd47-1b6a-4d03-aa6c-4e3741b30e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445637122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3445637122
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3962809887
Short name T530
Test name
Test status
Simulation time 72774449 ps
CPU time 3.53 seconds
Started Aug 10 04:52:14 PM PDT 24
Finished Aug 10 04:52:18 PM PDT 24
Peak memory 214236 kb
Host smart-f30b1e86-4353-44b5-9e23-9f5745c16a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962809887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3962809887
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2249211400
Short name T203
Test name
Test status
Simulation time 490462886 ps
CPU time 4.48 seconds
Started Aug 10 04:52:14 PM PDT 24
Finished Aug 10 04:52:18 PM PDT 24
Peak memory 207148 kb
Host smart-b34b2c92-ea40-42e2-8052-6f7d214fe433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249211400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2249211400
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2491138391
Short name T566
Test name
Test status
Simulation time 22063505 ps
CPU time 1.81 seconds
Started Aug 10 04:52:17 PM PDT 24
Finished Aug 10 04:52:19 PM PDT 24
Peak memory 207080 kb
Host smart-d03784a0-47ad-4727-acec-450ff51c3d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491138391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2491138391
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2297988630
Short name T744
Test name
Test status
Simulation time 166217580 ps
CPU time 4.53 seconds
Started Aug 10 04:52:14 PM PDT 24
Finished Aug 10 04:52:19 PM PDT 24
Peak memory 207908 kb
Host smart-9b64cb58-ad5b-4e35-a53d-fece1edbc5ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297988630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2297988630
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1932112586
Short name T806
Test name
Test status
Simulation time 1077041526 ps
CPU time 15.05 seconds
Started Aug 10 04:52:15 PM PDT 24
Finished Aug 10 04:52:30 PM PDT 24
Peak memory 208764 kb
Host smart-f65d9175-204f-4521-a2fc-24e770830e9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932112586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1932112586
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.4095548873
Short name T533
Test name
Test status
Simulation time 457085678 ps
CPU time 4.23 seconds
Started Aug 10 04:52:25 PM PDT 24
Finished Aug 10 04:52:29 PM PDT 24
Peak memory 215760 kb
Host smart-70112719-c182-4660-8fa2-c19533e62f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095548873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.4095548873
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3473644812
Short name T462
Test name
Test status
Simulation time 147036989 ps
CPU time 4.15 seconds
Started Aug 10 04:52:14 PM PDT 24
Finished Aug 10 04:52:18 PM PDT 24
Peak memory 206868 kb
Host smart-b013bcc1-638c-4b83-afa5-296dbf6c7d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473644812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3473644812
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.827039252
Short name T305
Test name
Test status
Simulation time 7468358798 ps
CPU time 44.75 seconds
Started Aug 10 04:52:24 PM PDT 24
Finished Aug 10 04:53:09 PM PDT 24
Peak memory 217312 kb
Host smart-b126f955-f3ae-4974-ae57-7ed627e53368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827039252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.827039252
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2322206668
Short name T882
Test name
Test status
Simulation time 879124670 ps
CPU time 13.04 seconds
Started Aug 10 04:52:24 PM PDT 24
Finished Aug 10 04:52:38 PM PDT 24
Peak memory 222488 kb
Host smart-674ea457-e413-46a7-be89-cd786c070671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322206668 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2322206668
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.208583826
Short name T111
Test name
Test status
Simulation time 1686648090 ps
CPU time 48.67 seconds
Started Aug 10 04:52:15 PM PDT 24
Finished Aug 10 04:53:04 PM PDT 24
Peak memory 210264 kb
Host smart-4760238c-5f3d-4c65-a223-d58890dbb907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208583826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.208583826
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1809213474
Short name T102
Test name
Test status
Simulation time 49252828 ps
CPU time 0.74 seconds
Started Aug 10 04:52:33 PM PDT 24
Finished Aug 10 04:52:34 PM PDT 24
Peak memory 205888 kb
Host smart-5c0cf51d-a57e-4ebf-818c-d66346c39946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809213474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1809213474
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1149515432
Short name T858
Test name
Test status
Simulation time 84457559 ps
CPU time 2.32 seconds
Started Aug 10 04:52:33 PM PDT 24
Finished Aug 10 04:52:36 PM PDT 24
Peak memory 214656 kb
Host smart-ff44e66a-a6ac-4cd0-ab29-5e19c6a610e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149515432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1149515432
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1229323574
Short name T555
Test name
Test status
Simulation time 1193464041 ps
CPU time 4.31 seconds
Started Aug 10 04:52:24 PM PDT 24
Finished Aug 10 04:52:28 PM PDT 24
Peak memory 219716 kb
Host smart-145a32dd-be91-4125-aed8-b964b9348012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229323574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1229323574
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.4063513907
Short name T256
Test name
Test status
Simulation time 44071934 ps
CPU time 1.95 seconds
Started Aug 10 04:52:25 PM PDT 24
Finished Aug 10 04:52:27 PM PDT 24
Peak memory 214212 kb
Host smart-1520fd9e-65b0-4043-befd-9d413bea5f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063513907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.4063513907
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3740984479
Short name T213
Test name
Test status
Simulation time 317528473 ps
CPU time 4.43 seconds
Started Aug 10 04:52:24 PM PDT 24
Finished Aug 10 04:52:29 PM PDT 24
Peak memory 214148 kb
Host smart-300d2d19-f069-4af0-b60d-0911b1116fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740984479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3740984479
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3898451338
Short name T445
Test name
Test status
Simulation time 151631918 ps
CPU time 6.27 seconds
Started Aug 10 04:52:24 PM PDT 24
Finished Aug 10 04:52:30 PM PDT 24
Peak memory 222344 kb
Host smart-f04590d9-fdc5-4d5e-af8b-7ef85287f9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898451338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3898451338
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1317661097
Short name T625
Test name
Test status
Simulation time 96946674 ps
CPU time 4.33 seconds
Started Aug 10 04:52:24 PM PDT 24
Finished Aug 10 04:52:28 PM PDT 24
Peak memory 208752 kb
Host smart-c5f1a073-41b6-4c18-917a-54d490ad929a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317661097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1317661097
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2740265771
Short name T712
Test name
Test status
Simulation time 504312755 ps
CPU time 15.63 seconds
Started Aug 10 04:52:26 PM PDT 24
Finished Aug 10 04:52:41 PM PDT 24
Peak memory 208080 kb
Host smart-18e33abf-8f02-42ac-96d0-b8cfd98cb4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740265771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2740265771
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2451718313
Short name T500
Test name
Test status
Simulation time 36837073 ps
CPU time 2.46 seconds
Started Aug 10 04:52:23 PM PDT 24
Finished Aug 10 04:52:26 PM PDT 24
Peak memory 206868 kb
Host smart-1657455a-0879-439c-89c2-d6a2eb8775fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451718313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2451718313
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.20176401
Short name T414
Test name
Test status
Simulation time 128898949 ps
CPU time 2.5 seconds
Started Aug 10 04:52:25 PM PDT 24
Finished Aug 10 04:52:28 PM PDT 24
Peak memory 207368 kb
Host smart-246567cb-0939-4d67-afec-835b5e14cf77
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20176401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.20176401
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3158137235
Short name T698
Test name
Test status
Simulation time 227328929 ps
CPU time 2.84 seconds
Started Aug 10 04:52:25 PM PDT 24
Finished Aug 10 04:52:28 PM PDT 24
Peak memory 207528 kb
Host smart-76d43178-4cad-45b4-b75f-910b8ea14014
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158137235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3158137235
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2148605389
Short name T705
Test name
Test status
Simulation time 287833090 ps
CPU time 3.2 seconds
Started Aug 10 04:52:34 PM PDT 24
Finished Aug 10 04:52:38 PM PDT 24
Peak memory 214256 kb
Host smart-c0cd9506-39da-4419-a7e9-1404ecda7183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148605389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2148605389
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3558865305
Short name T634
Test name
Test status
Simulation time 768073694 ps
CPU time 3.79 seconds
Started Aug 10 04:52:23 PM PDT 24
Finished Aug 10 04:52:27 PM PDT 24
Peak memory 206700 kb
Host smart-0b09065d-7c29-4b8b-9794-b78e1f98b24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558865305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3558865305
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3837402325
Short name T216
Test name
Test status
Simulation time 4106126616 ps
CPU time 39.13 seconds
Started Aug 10 04:52:39 PM PDT 24
Finished Aug 10 04:53:19 PM PDT 24
Peak memory 216180 kb
Host smart-2cfef568-16e7-4c52-8904-d766abbc0ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837402325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3837402325
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2895910203
Short name T201
Test name
Test status
Simulation time 153233359 ps
CPU time 4.73 seconds
Started Aug 10 04:52:25 PM PDT 24
Finished Aug 10 04:52:30 PM PDT 24
Peak memory 208920 kb
Host smart-7f9faddb-797e-457d-851b-1764f41a2f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895910203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2895910203
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.277259630
Short name T739
Test name
Test status
Simulation time 414919426 ps
CPU time 6.62 seconds
Started Aug 10 04:52:34 PM PDT 24
Finished Aug 10 04:52:40 PM PDT 24
Peak memory 210928 kb
Host smart-25f89609-488d-480f-9fad-448f12492f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277259630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.277259630
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2110750101
Short name T570
Test name
Test status
Simulation time 30404330 ps
CPU time 0.79 seconds
Started Aug 10 04:52:36 PM PDT 24
Finished Aug 10 04:52:36 PM PDT 24
Peak memory 205988 kb
Host smart-a356cd65-f30b-43ee-8287-8a21255283a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110750101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2110750101
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.4113952122
Short name T859
Test name
Test status
Simulation time 879784954 ps
CPU time 13.05 seconds
Started Aug 10 04:52:39 PM PDT 24
Finished Aug 10 04:52:52 PM PDT 24
Peak memory 222436 kb
Host smart-709bd824-fe48-45f2-94c3-356bd70f8b09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113952122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.4113952122
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2675847481
Short name T831
Test name
Test status
Simulation time 103164203 ps
CPU time 2.79 seconds
Started Aug 10 04:52:33 PM PDT 24
Finished Aug 10 04:52:36 PM PDT 24
Peak memory 207800 kb
Host smart-1db15949-3b87-4555-b53d-06e0d85775f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675847481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2675847481
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3451391277
Short name T23
Test name
Test status
Simulation time 2822052415 ps
CPU time 17.63 seconds
Started Aug 10 04:52:35 PM PDT 24
Finished Aug 10 04:52:53 PM PDT 24
Peak memory 214380 kb
Host smart-46fd4c3a-30ab-44db-a558-f06f8e8f3aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451391277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3451391277
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2163288638
Short name T869
Test name
Test status
Simulation time 537401228 ps
CPU time 11.14 seconds
Started Aug 10 04:52:33 PM PDT 24
Finished Aug 10 04:52:44 PM PDT 24
Peak memory 222280 kb
Host smart-4a68ccf4-bf86-480a-ae0d-b5c05ee5be7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163288638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2163288638
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3202918974
Short name T588
Test name
Test status
Simulation time 122243036 ps
CPU time 5.9 seconds
Started Aug 10 04:52:35 PM PDT 24
Finished Aug 10 04:52:41 PM PDT 24
Peak memory 220168 kb
Host smart-693f06bc-985d-40bc-95c6-352d310075a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202918974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3202918974
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2269672031
Short name T661
Test name
Test status
Simulation time 213733067 ps
CPU time 4.85 seconds
Started Aug 10 04:52:34 PM PDT 24
Finished Aug 10 04:52:39 PM PDT 24
Peak memory 208816 kb
Host smart-08e85039-b9e1-4c9b-9558-eda6e621923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269672031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2269672031
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.616981868
Short name T432
Test name
Test status
Simulation time 115271854 ps
CPU time 3.01 seconds
Started Aug 10 04:52:35 PM PDT 24
Finished Aug 10 04:52:38 PM PDT 24
Peak memory 207056 kb
Host smart-723c0068-9eef-4a5a-8fc3-21054cb44bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616981868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.616981868
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2454574027
Short name T80
Test name
Test status
Simulation time 226557368 ps
CPU time 2.98 seconds
Started Aug 10 04:52:35 PM PDT 24
Finished Aug 10 04:52:38 PM PDT 24
Peak memory 208828 kb
Host smart-1528cdb4-150f-4ebd-ad72-1e2c9e657d31
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454574027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2454574027
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3910380446
Short name T912
Test name
Test status
Simulation time 162008793 ps
CPU time 4.85 seconds
Started Aug 10 04:52:34 PM PDT 24
Finished Aug 10 04:52:39 PM PDT 24
Peak memory 209012 kb
Host smart-13fcb5ce-efb0-4d64-8c0e-a7039184b5c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910380446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3910380446
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.881637908
Short name T601
Test name
Test status
Simulation time 105381553 ps
CPU time 2.82 seconds
Started Aug 10 04:52:34 PM PDT 24
Finished Aug 10 04:52:37 PM PDT 24
Peak memory 206864 kb
Host smart-1c47ac97-6409-4baa-bcd6-c08ed21e3aa5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881637908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.881637908
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2242237439
Short name T242
Test name
Test status
Simulation time 116120197 ps
CPU time 2.62 seconds
Started Aug 10 04:52:36 PM PDT 24
Finished Aug 10 04:52:38 PM PDT 24
Peak memory 218312 kb
Host smart-4caa90ee-2fc6-4f7d-a554-d393a429cb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242237439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2242237439
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2567240222
Short name T14
Test name
Test status
Simulation time 38962939 ps
CPU time 1.63 seconds
Started Aug 10 04:52:35 PM PDT 24
Finished Aug 10 04:52:37 PM PDT 24
Peak memory 206028 kb
Host smart-8c28f00d-d8ef-48cf-bfd9-e491d89d8c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567240222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2567240222
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3045710027
Short name T667
Test name
Test status
Simulation time 381663379 ps
CPU time 5.62 seconds
Started Aug 10 04:52:35 PM PDT 24
Finished Aug 10 04:52:41 PM PDT 24
Peak memory 219864 kb
Host smart-059fcde8-0c9f-4fcf-abe9-070a04defb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045710027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3045710027
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2209849062
Short name T133
Test name
Test status
Simulation time 160737715 ps
CPU time 1.87 seconds
Started Aug 10 04:52:39 PM PDT 24
Finished Aug 10 04:52:41 PM PDT 24
Peak memory 209476 kb
Host smart-028b829e-e491-4605-bd95-d8c6f490a707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209849062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2209849062
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.4004662385
Short name T443
Test name
Test status
Simulation time 11459113 ps
CPU time 0.75 seconds
Started Aug 10 04:52:45 PM PDT 24
Finished Aug 10 04:52:46 PM PDT 24
Peak memory 205884 kb
Host smart-6e1b4611-6d7b-4041-abe5-b0b8a8501988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004662385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4004662385
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.770553782
Short name T27
Test name
Test status
Simulation time 174349605 ps
CPU time 2.88 seconds
Started Aug 10 04:52:45 PM PDT 24
Finished Aug 10 04:52:48 PM PDT 24
Peak memory 209680 kb
Host smart-05747c88-e76d-4d75-a046-e5e0766d26cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770553782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.770553782
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.4244888237
Short name T491
Test name
Test status
Simulation time 26106267 ps
CPU time 2.03 seconds
Started Aug 10 04:52:44 PM PDT 24
Finished Aug 10 04:52:47 PM PDT 24
Peak memory 207580 kb
Host smart-a12ba031-5047-4587-a3c3-45d86ce86491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244888237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.4244888237
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3293105288
Short name T318
Test name
Test status
Simulation time 272456766 ps
CPU time 3.28 seconds
Started Aug 10 04:52:44 PM PDT 24
Finished Aug 10 04:52:47 PM PDT 24
Peak memory 222412 kb
Host smart-bf0c7096-df33-4884-a3f4-1c92c9d55fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293105288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3293105288
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.611404047
Short name T825
Test name
Test status
Simulation time 48044758 ps
CPU time 2.19 seconds
Started Aug 10 04:52:45 PM PDT 24
Finished Aug 10 04:52:47 PM PDT 24
Peak memory 206052 kb
Host smart-882fc63a-72ab-4855-8fa3-751c806f2c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611404047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.611404047
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2259123076
Short name T847
Test name
Test status
Simulation time 206850837 ps
CPU time 4.07 seconds
Started Aug 10 04:52:32 PM PDT 24
Finished Aug 10 04:52:36 PM PDT 24
Peak memory 207380 kb
Host smart-a244b922-3779-4e17-9b87-1b466a2b0329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259123076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2259123076
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.4272396983
Short name T709
Test name
Test status
Simulation time 422467232 ps
CPU time 5.23 seconds
Started Aug 10 04:52:35 PM PDT 24
Finished Aug 10 04:52:41 PM PDT 24
Peak memory 208600 kb
Host smart-aab62070-1ee4-4ad4-8d4b-b5562b2dc7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272396983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.4272396983
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3962681646
Short name T734
Test name
Test status
Simulation time 266303729 ps
CPU time 4.33 seconds
Started Aug 10 04:52:39 PM PDT 24
Finished Aug 10 04:52:43 PM PDT 24
Peak memory 208632 kb
Host smart-0cdb1fd8-e6e1-4003-a14c-bcd1fb6cc2c0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962681646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3962681646
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3194859669
Short name T386
Test name
Test status
Simulation time 296567713 ps
CPU time 4.2 seconds
Started Aug 10 04:52:34 PM PDT 24
Finished Aug 10 04:52:39 PM PDT 24
Peak memory 207000 kb
Host smart-28a683d6-7b7b-4264-87e1-a2d30c84eaee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194859669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3194859669
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1616766445
Short name T770
Test name
Test status
Simulation time 195223788 ps
CPU time 3.36 seconds
Started Aug 10 04:52:36 PM PDT 24
Finished Aug 10 04:52:39 PM PDT 24
Peak memory 206864 kb
Host smart-01dde0f6-c4db-4b81-8533-3ffe83e9af51
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616766445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1616766445
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1187630353
Short name T240
Test name
Test status
Simulation time 92620168 ps
CPU time 2.06 seconds
Started Aug 10 04:52:44 PM PDT 24
Finished Aug 10 04:52:46 PM PDT 24
Peak memory 218268 kb
Host smart-71c5efd7-ff5b-4c81-8d24-990353ee26aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187630353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1187630353
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2162263821
Short name T394
Test name
Test status
Simulation time 250775072 ps
CPU time 3.67 seconds
Started Aug 10 04:52:34 PM PDT 24
Finished Aug 10 04:52:38 PM PDT 24
Peak memory 208060 kb
Host smart-2c1fbd04-473c-4d57-9487-a9369d4f68dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162263821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2162263821
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3759389412
Short name T271
Test name
Test status
Simulation time 122340848 ps
CPU time 2.76 seconds
Started Aug 10 04:52:44 PM PDT 24
Finished Aug 10 04:52:47 PM PDT 24
Peak memory 207644 kb
Host smart-707c8483-bb99-4879-a1f5-0490c013c419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759389412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3759389412
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.424791566
Short name T453
Test name
Test status
Simulation time 770165171 ps
CPU time 6 seconds
Started Aug 10 04:52:44 PM PDT 24
Finished Aug 10 04:52:51 PM PDT 24
Peak memory 210816 kb
Host smart-6b163cd6-e861-4d99-9ded-e4b69b9a0a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424791566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.424791566
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1805183289
Short name T565
Test name
Test status
Simulation time 25519540 ps
CPU time 0.88 seconds
Started Aug 10 04:52:54 PM PDT 24
Finished Aug 10 04:52:55 PM PDT 24
Peak memory 205852 kb
Host smart-d9816875-37b3-4407-beb6-2fadcf1c03c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805183289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1805183289
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1651379397
Short name T288
Test name
Test status
Simulation time 56481997 ps
CPU time 4.19 seconds
Started Aug 10 04:52:44 PM PDT 24
Finished Aug 10 04:52:49 PM PDT 24
Peak memory 215448 kb
Host smart-dd496c40-c294-44f8-8e47-51da21b8af35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651379397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1651379397
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.164857280
Short name T752
Test name
Test status
Simulation time 274336948 ps
CPU time 3.25 seconds
Started Aug 10 04:52:44 PM PDT 24
Finished Aug 10 04:52:48 PM PDT 24
Peak memory 208156 kb
Host smart-6e3d23a9-48f8-4651-98c8-6db0fead78e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164857280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.164857280
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1899299510
Short name T575
Test name
Test status
Simulation time 943115022 ps
CPU time 2.85 seconds
Started Aug 10 04:52:43 PM PDT 24
Finished Aug 10 04:52:46 PM PDT 24
Peak memory 209072 kb
Host smart-f209545e-5c81-4b66-81ba-fb024defa36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899299510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1899299510
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3155372437
Short name T92
Test name
Test status
Simulation time 125575372 ps
CPU time 4.52 seconds
Started Aug 10 04:52:46 PM PDT 24
Finished Aug 10 04:52:50 PM PDT 24
Peak memory 209096 kb
Host smart-70252419-f2ca-4173-9e7f-53fcdca13ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155372437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3155372437
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3002356594
Short name T341
Test name
Test status
Simulation time 36747858 ps
CPU time 2.6 seconds
Started Aug 10 04:52:46 PM PDT 24
Finished Aug 10 04:52:48 PM PDT 24
Peak memory 220704 kb
Host smart-9389a348-413b-4501-b863-b4090ff504d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002356594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3002356594
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2609243418
Short name T2
Test name
Test status
Simulation time 43400948 ps
CPU time 3.09 seconds
Started Aug 10 04:52:46 PM PDT 24
Finished Aug 10 04:52:49 PM PDT 24
Peak memory 208536 kb
Host smart-529cbecb-f053-4813-a896-8d8b619c7a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609243418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2609243418
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.712293188
Short name T902
Test name
Test status
Simulation time 128529134 ps
CPU time 3.65 seconds
Started Aug 10 04:52:43 PM PDT 24
Finished Aug 10 04:52:47 PM PDT 24
Peak memory 207964 kb
Host smart-7f48cfc9-e939-4ddd-9217-1ac56098e3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712293188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.712293188
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.418891058
Short name T314
Test name
Test status
Simulation time 92339246 ps
CPU time 2.05 seconds
Started Aug 10 04:52:44 PM PDT 24
Finished Aug 10 04:52:47 PM PDT 24
Peak memory 208540 kb
Host smart-763884cc-9da1-4737-9969-67969abaf04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418891058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.418891058
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2958708994
Short name T363
Test name
Test status
Simulation time 115854568 ps
CPU time 3.27 seconds
Started Aug 10 04:52:44 PM PDT 24
Finished Aug 10 04:52:47 PM PDT 24
Peak memory 206872 kb
Host smart-56984a6a-8610-4e0c-a9d3-23680e62b4b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958708994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2958708994
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2132415055
Short name T421
Test name
Test status
Simulation time 126507742 ps
CPU time 4.11 seconds
Started Aug 10 04:52:46 PM PDT 24
Finished Aug 10 04:52:50 PM PDT 24
Peak memory 207088 kb
Host smart-957a9c77-8ea1-4e3e-a2f8-addce1589d8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132415055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2132415055
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.4270655491
Short name T485
Test name
Test status
Simulation time 193739302 ps
CPU time 2.57 seconds
Started Aug 10 04:52:47 PM PDT 24
Finished Aug 10 04:52:49 PM PDT 24
Peak memory 208632 kb
Host smart-3550e86e-fae9-4fa8-a835-d008573ad974
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270655491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.4270655491
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1618351293
Short name T397
Test name
Test status
Simulation time 117562422 ps
CPU time 2.29 seconds
Started Aug 10 04:52:45 PM PDT 24
Finished Aug 10 04:52:47 PM PDT 24
Peak memory 207448 kb
Host smart-29ff2e46-424b-4140-a08f-db8d9d6b1c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618351293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1618351293
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1210614655
Short name T468
Test name
Test status
Simulation time 232432475 ps
CPU time 2.34 seconds
Started Aug 10 04:52:47 PM PDT 24
Finished Aug 10 04:52:49 PM PDT 24
Peak memory 206692 kb
Host smart-d2045814-f47d-4bd9-8e49-dde920935da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210614655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1210614655
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.570853526
Short name T193
Test name
Test status
Simulation time 448730457 ps
CPU time 12.31 seconds
Started Aug 10 04:52:45 PM PDT 24
Finished Aug 10 04:52:57 PM PDT 24
Peak memory 222448 kb
Host smart-ff745b98-e8fb-43ac-b980-77dce522666c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570853526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.570853526
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1920193412
Short name T72
Test name
Test status
Simulation time 755241700 ps
CPU time 11.68 seconds
Started Aug 10 04:52:46 PM PDT 24
Finished Aug 10 04:52:58 PM PDT 24
Peak memory 222508 kb
Host smart-37114c11-8e0a-4064-85e2-e8543a13ab7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920193412 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1920193412
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1921424890
Short name T801
Test name
Test status
Simulation time 532369046 ps
CPU time 5.81 seconds
Started Aug 10 04:52:44 PM PDT 24
Finished Aug 10 04:52:50 PM PDT 24
Peak memory 208036 kb
Host smart-6113c9f9-4552-4388-b8c8-3bf8ea105847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921424890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1921424890
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1301825609
Short name T454
Test name
Test status
Simulation time 77413231 ps
CPU time 2.96 seconds
Started Aug 10 04:52:43 PM PDT 24
Finished Aug 10 04:52:47 PM PDT 24
Peak memory 209632 kb
Host smart-554d69a6-7f8b-4c41-8b94-4d42d574a677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301825609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1301825609
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.759946494
Short name T713
Test name
Test status
Simulation time 35831587 ps
CPU time 0.73 seconds
Started Aug 10 04:52:56 PM PDT 24
Finished Aug 10 04:52:57 PM PDT 24
Peak memory 205864 kb
Host smart-c311cbbc-ef56-4fad-b4d3-64deac86ad65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759946494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.759946494
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.309852604
Short name T25
Test name
Test status
Simulation time 43293329 ps
CPU time 2.2 seconds
Started Aug 10 04:52:54 PM PDT 24
Finished Aug 10 04:52:56 PM PDT 24
Peak memory 209168 kb
Host smart-de034164-6583-4c12-b3f1-217f7ade719b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309852604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.309852604
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1936214648
Short name T872
Test name
Test status
Simulation time 604526063 ps
CPU time 13.81 seconds
Started Aug 10 04:52:54 PM PDT 24
Finished Aug 10 04:53:08 PM PDT 24
Peak memory 214292 kb
Host smart-997a5476-5c7f-4956-8e4a-57a2e1c05a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936214648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1936214648
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2345285567
Short name T96
Test name
Test status
Simulation time 366967040 ps
CPU time 4.92 seconds
Started Aug 10 04:52:54 PM PDT 24
Finished Aug 10 04:52:59 PM PDT 24
Peak memory 219156 kb
Host smart-5559586b-21a2-4613-b6af-f81dd611f547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345285567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2345285567
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1168941776
Short name T320
Test name
Test status
Simulation time 79691422 ps
CPU time 3.45 seconds
Started Aug 10 04:52:55 PM PDT 24
Finished Aug 10 04:52:59 PM PDT 24
Peak memory 214192 kb
Host smart-40001d4d-2b91-4256-ae6c-7a44483f3a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168941776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1168941776
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2247020272
Short name T880
Test name
Test status
Simulation time 308552011 ps
CPU time 3.66 seconds
Started Aug 10 04:52:54 PM PDT 24
Finished Aug 10 04:52:58 PM PDT 24
Peak memory 207984 kb
Host smart-ffd408c4-9722-4857-b870-d03a6b6e5eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247020272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2247020272
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1214498138
Short name T194
Test name
Test status
Simulation time 330284206 ps
CPU time 4.06 seconds
Started Aug 10 04:52:56 PM PDT 24
Finished Aug 10 04:53:00 PM PDT 24
Peak memory 209904 kb
Host smart-3cc3f5fb-cf19-4db3-8560-4c9ab1cde8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214498138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1214498138
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.976333228
Short name T474
Test name
Test status
Simulation time 302442218 ps
CPU time 2.06 seconds
Started Aug 10 04:52:54 PM PDT 24
Finished Aug 10 04:52:56 PM PDT 24
Peak memory 208744 kb
Host smart-43bc2909-788d-46fb-bef0-89dd017bb624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976333228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.976333228
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.14611761
Short name T447
Test name
Test status
Simulation time 357586240 ps
CPU time 2.66 seconds
Started Aug 10 04:52:56 PM PDT 24
Finished Aug 10 04:52:59 PM PDT 24
Peak memory 206860 kb
Host smart-fd914df4-8f1c-4d6d-a4c9-7988c626bdc9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14611761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.14611761
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2643404185
Short name T788
Test name
Test status
Simulation time 248549182 ps
CPU time 3.96 seconds
Started Aug 10 04:52:54 PM PDT 24
Finished Aug 10 04:52:58 PM PDT 24
Peak memory 208044 kb
Host smart-6026402d-3f5c-44b7-812a-5ea8665032fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643404185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2643404185
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3782041753
Short name T573
Test name
Test status
Simulation time 133793320 ps
CPU time 4.32 seconds
Started Aug 10 04:52:53 PM PDT 24
Finished Aug 10 04:52:58 PM PDT 24
Peak memory 207960 kb
Host smart-385fd716-a715-429f-bb5f-64ace03f266c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782041753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3782041753
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.845268591
Short name T329
Test name
Test status
Simulation time 102633373 ps
CPU time 3.15 seconds
Started Aug 10 04:52:55 PM PDT 24
Finished Aug 10 04:52:59 PM PDT 24
Peak memory 209784 kb
Host smart-99d7988e-ab17-40b3-9efa-3739ad7ac900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845268591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.845268591
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2121444975
Short name T704
Test name
Test status
Simulation time 143217731 ps
CPU time 3.85 seconds
Started Aug 10 04:52:54 PM PDT 24
Finished Aug 10 04:52:58 PM PDT 24
Peak memory 208284 kb
Host smart-0aeb3d01-eb11-49b0-b943-154cee9ef55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121444975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2121444975
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2483366102
Short name T653
Test name
Test status
Simulation time 1388693949 ps
CPU time 20.83 seconds
Started Aug 10 04:52:55 PM PDT 24
Finished Aug 10 04:53:16 PM PDT 24
Peak memory 215216 kb
Host smart-cab44a9e-f36d-4938-9761-a438975632c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483366102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2483366102
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.474573112
Short name T180
Test name
Test status
Simulation time 495030188 ps
CPU time 10.37 seconds
Started Aug 10 04:52:56 PM PDT 24
Finished Aug 10 04:53:07 PM PDT 24
Peak memory 222448 kb
Host smart-c5de7410-0f52-4a7e-97f0-0509935b2acc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474573112 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.474573112
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4073455269
Short name T408
Test name
Test status
Simulation time 3283567749 ps
CPU time 31.28 seconds
Started Aug 10 04:52:56 PM PDT 24
Finished Aug 10 04:53:27 PM PDT 24
Peak memory 208732 kb
Host smart-42fbee06-89d9-40e8-8797-c3438e4211f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073455269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4073455269
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3113175908
Short name T717
Test name
Test status
Simulation time 118070927 ps
CPU time 3.59 seconds
Started Aug 10 04:52:54 PM PDT 24
Finished Aug 10 04:52:58 PM PDT 24
Peak memory 210356 kb
Host smart-076662fd-b0a0-480a-99b9-49d348685b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113175908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3113175908
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3826329169
Short name T687
Test name
Test status
Simulation time 28368746 ps
CPU time 0.77 seconds
Started Aug 10 04:53:06 PM PDT 24
Finished Aug 10 04:53:07 PM PDT 24
Peak memory 205852 kb
Host smart-8238a1aa-134e-4334-b2d2-c1acaceb8a44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826329169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3826329169
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.4294796071
Short name T399
Test name
Test status
Simulation time 163973569 ps
CPU time 7.85 seconds
Started Aug 10 04:53:05 PM PDT 24
Finished Aug 10 04:53:13 PM PDT 24
Peak memory 214308 kb
Host smart-8cbabf49-c26a-4e43-b8ea-00c2a9d689dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294796071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.4294796071
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2648320377
Short name T728
Test name
Test status
Simulation time 125323900 ps
CPU time 6.58 seconds
Started Aug 10 04:53:07 PM PDT 24
Finished Aug 10 04:53:14 PM PDT 24
Peak memory 210308 kb
Host smart-06543508-5995-4858-8aa0-4e8e1ca47a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648320377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2648320377
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.75242402
Short name T836
Test name
Test status
Simulation time 153737749 ps
CPU time 3.04 seconds
Started Aug 10 04:53:04 PM PDT 24
Finished Aug 10 04:53:08 PM PDT 24
Peak memory 206816 kb
Host smart-d4671152-c360-4910-bb25-11ace6aedeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75242402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.75242402
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1197171101
Short name T534
Test name
Test status
Simulation time 82543413 ps
CPU time 3.95 seconds
Started Aug 10 04:53:03 PM PDT 24
Finished Aug 10 04:53:07 PM PDT 24
Peak memory 214248 kb
Host smart-cdbf7179-ef0c-4779-ab8f-598488c08a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197171101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1197171101
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.681304072
Short name T811
Test name
Test status
Simulation time 115991446 ps
CPU time 5.56 seconds
Started Aug 10 04:53:05 PM PDT 24
Finished Aug 10 04:53:11 PM PDT 24
Peak memory 222352 kb
Host smart-9803f649-364d-4ebf-bbae-0da661b61ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681304072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.681304072
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3703525039
Short name T676
Test name
Test status
Simulation time 68108039 ps
CPU time 3.55 seconds
Started Aug 10 04:53:05 PM PDT 24
Finished Aug 10 04:53:09 PM PDT 24
Peak memory 219440 kb
Host smart-df5145a5-e9c3-4867-b0b4-8f2ec30da932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703525039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3703525039
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3008773340
Short name T517
Test name
Test status
Simulation time 397811511 ps
CPU time 3.22 seconds
Started Aug 10 04:52:55 PM PDT 24
Finished Aug 10 04:52:59 PM PDT 24
Peak memory 208848 kb
Host smart-b79c1a7c-e456-4efc-8102-5c070d5c5cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008773340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3008773340
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.723616912
Short name T427
Test name
Test status
Simulation time 61326206 ps
CPU time 3.13 seconds
Started Aug 10 04:53:07 PM PDT 24
Finished Aug 10 04:53:10 PM PDT 24
Peak memory 206988 kb
Host smart-64798cf3-43d1-49ed-b9a0-98da21ce6f2d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723616912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.723616912
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3279278488
Short name T779
Test name
Test status
Simulation time 770006956 ps
CPU time 5.02 seconds
Started Aug 10 04:52:54 PM PDT 24
Finished Aug 10 04:53:00 PM PDT 24
Peak memory 208280 kb
Host smart-b97b6579-9c77-4bb4-9925-0ecbe7bd6621
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279278488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3279278488
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3727377365
Short name T388
Test name
Test status
Simulation time 140352156 ps
CPU time 2.61 seconds
Started Aug 10 04:53:05 PM PDT 24
Finished Aug 10 04:53:08 PM PDT 24
Peak memory 206640 kb
Host smart-ffa9b115-1e54-4cd1-89e4-9e52b3248408
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727377365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3727377365
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.786831617
Short name T624
Test name
Test status
Simulation time 105247773 ps
CPU time 3.81 seconds
Started Aug 10 04:53:09 PM PDT 24
Finished Aug 10 04:53:12 PM PDT 24
Peak memory 208200 kb
Host smart-ea146a3f-ffcb-4705-9148-668677eec016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786831617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.786831617
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.558769861
Short name T647
Test name
Test status
Simulation time 123017129 ps
CPU time 3.18 seconds
Started Aug 10 04:52:56 PM PDT 24
Finished Aug 10 04:52:59 PM PDT 24
Peak memory 208432 kb
Host smart-fb7d0eef-50bc-476c-879a-5aa0e49f13ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558769861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.558769861
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1129215987
Short name T336
Test name
Test status
Simulation time 250083988 ps
CPU time 13.15 seconds
Started Aug 10 04:53:05 PM PDT 24
Finished Aug 10 04:53:19 PM PDT 24
Peak memory 215572 kb
Host smart-4bcdd469-0e48-400f-a3ed-aca7eb1ec296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129215987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1129215987
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1814030209
Short name T669
Test name
Test status
Simulation time 43255052 ps
CPU time 2.89 seconds
Started Aug 10 04:53:07 PM PDT 24
Finished Aug 10 04:53:10 PM PDT 24
Peak memory 214236 kb
Host smart-6d9a2e2b-9c30-4b4a-9408-eb4ee1a5d349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814030209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1814030209
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3501553179
Short name T494
Test name
Test status
Simulation time 329774505 ps
CPU time 3.38 seconds
Started Aug 10 04:53:05 PM PDT 24
Finished Aug 10 04:53:09 PM PDT 24
Peak memory 209656 kb
Host smart-3f6af0dc-f905-401f-937e-26975a0e7ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501553179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3501553179
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1878857181
Short name T558
Test name
Test status
Simulation time 14572576 ps
CPU time 0.8 seconds
Started Aug 10 04:53:21 PM PDT 24
Finished Aug 10 04:53:22 PM PDT 24
Peak memory 205896 kb
Host smart-f025abbe-787a-436d-9529-2c8b527e609b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878857181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1878857181
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1557929057
Short name T253
Test name
Test status
Simulation time 319506976 ps
CPU time 5.04 seconds
Started Aug 10 04:53:05 PM PDT 24
Finished Aug 10 04:53:10 PM PDT 24
Peak memory 214212 kb
Host smart-9d6beed4-efa4-4b4d-939f-9f86eb80bb50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557929057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1557929057
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.507667324
Short name T577
Test name
Test status
Simulation time 33833585 ps
CPU time 1.67 seconds
Started Aug 10 04:53:06 PM PDT 24
Finished Aug 10 04:53:08 PM PDT 24
Peak memory 207492 kb
Host smart-ec09871b-3c84-48c7-8435-f19f0f59262a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507667324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.507667324
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1322356041
Short name T90
Test name
Test status
Simulation time 821797370 ps
CPU time 8.61 seconds
Started Aug 10 04:53:22 PM PDT 24
Finished Aug 10 04:53:31 PM PDT 24
Peak memory 214312 kb
Host smart-ecd5792a-3e25-4252-aa69-970b1794c730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322356041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1322356041
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2077192880
Short name T234
Test name
Test status
Simulation time 441396938 ps
CPU time 2.16 seconds
Started Aug 10 04:53:23 PM PDT 24
Finished Aug 10 04:53:25 PM PDT 24
Peak memory 214152 kb
Host smart-27976e00-1452-4e76-b991-54e9eb59181f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077192880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2077192880
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1612003141
Short name T746
Test name
Test status
Simulation time 120107788 ps
CPU time 5.29 seconds
Started Aug 10 04:53:07 PM PDT 24
Finished Aug 10 04:53:12 PM PDT 24
Peak memory 210548 kb
Host smart-ac936050-912d-4804-96dc-107289cf4718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612003141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1612003141
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3690346137
Short name T369
Test name
Test status
Simulation time 40195734 ps
CPU time 2.83 seconds
Started Aug 10 04:53:06 PM PDT 24
Finished Aug 10 04:53:09 PM PDT 24
Peak memory 208440 kb
Host smart-5e821b21-4d4a-4453-a626-83525544e6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690346137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3690346137
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1890810956
Short name T355
Test name
Test status
Simulation time 21599493 ps
CPU time 1.95 seconds
Started Aug 10 04:53:07 PM PDT 24
Finished Aug 10 04:53:09 PM PDT 24
Peak memory 207092 kb
Host smart-27aee12c-a55f-49b2-9d7f-2417c3ff00f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890810956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1890810956
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.140526100
Short name T546
Test name
Test status
Simulation time 219772133 ps
CPU time 3.18 seconds
Started Aug 10 04:53:07 PM PDT 24
Finished Aug 10 04:53:11 PM PDT 24
Peak memory 208748 kb
Host smart-5c5cee5a-967f-4778-a269-c8d04ba2c570
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140526100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.140526100
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.321339375
Short name T896
Test name
Test status
Simulation time 60100974 ps
CPU time 3.14 seconds
Started Aug 10 04:53:06 PM PDT 24
Finished Aug 10 04:53:09 PM PDT 24
Peak memory 208836 kb
Host smart-3f7a8080-242d-41ee-a2b4-5e6e91d922dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321339375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.321339375
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.316110473
Short name T210
Test name
Test status
Simulation time 752467848 ps
CPU time 3.43 seconds
Started Aug 10 04:53:06 PM PDT 24
Finished Aug 10 04:53:09 PM PDT 24
Peak memory 208840 kb
Host smart-2a463c1b-7161-4e3c-9808-17141507a8fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316110473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.316110473
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.504673691
Short name T755
Test name
Test status
Simulation time 69510713 ps
CPU time 3.42 seconds
Started Aug 10 04:53:21 PM PDT 24
Finished Aug 10 04:53:25 PM PDT 24
Peak memory 214196 kb
Host smart-5c431152-a4f0-4d38-8f22-04bb4c8efdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504673691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.504673691
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.265177085
Short name T887
Test name
Test status
Simulation time 50538329 ps
CPU time 2.41 seconds
Started Aug 10 04:53:05 PM PDT 24
Finished Aug 10 04:53:08 PM PDT 24
Peak memory 206704 kb
Host smart-3c15e624-dbed-4490-a8cf-1558fba93668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265177085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.265177085
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.112404424
Short name T839
Test name
Test status
Simulation time 340124464 ps
CPU time 11.73 seconds
Started Aug 10 04:53:21 PM PDT 24
Finished Aug 10 04:53:33 PM PDT 24
Peak memory 220364 kb
Host smart-d2b19295-f028-4048-81ec-dded70c8b61a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112404424 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.112404424
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.198609515
Short name T582
Test name
Test status
Simulation time 254683276 ps
CPU time 3.35 seconds
Started Aug 10 04:53:22 PM PDT 24
Finished Aug 10 04:53:26 PM PDT 24
Peak memory 209172 kb
Host smart-c2a5a30c-b15c-4882-8168-00e0d3bd0177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198609515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.198609515
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2014823742
Short name T604
Test name
Test status
Simulation time 320219013 ps
CPU time 1.85 seconds
Started Aug 10 04:53:22 PM PDT 24
Finished Aug 10 04:53:24 PM PDT 24
Peak memory 210064 kb
Host smart-11c40251-8e5e-4711-b3cb-8538ceef53c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014823742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2014823742
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2912365190
Short name T590
Test name
Test status
Simulation time 39874866 ps
CPU time 0.81 seconds
Started Aug 10 04:53:23 PM PDT 24
Finished Aug 10 04:53:24 PM PDT 24
Peak memory 205864 kb
Host smart-3364e7a7-666e-4d2f-85de-7aa2d1347cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912365190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2912365190
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1690916213
Short name T37
Test name
Test status
Simulation time 279359885 ps
CPU time 2.97 seconds
Started Aug 10 04:53:24 PM PDT 24
Finished Aug 10 04:53:27 PM PDT 24
Peak memory 208616 kb
Host smart-1b10fa06-8c08-4bc1-a3c8-f4176e2ad767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690916213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1690916213
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.302649133
Short name T758
Test name
Test status
Simulation time 39366102 ps
CPU time 2.36 seconds
Started Aug 10 04:53:22 PM PDT 24
Finished Aug 10 04:53:24 PM PDT 24
Peak memory 207584 kb
Host smart-f463f60b-6ecf-412c-97e0-5d2562d5404f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302649133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.302649133
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.4145844647
Short name T599
Test name
Test status
Simulation time 81284499 ps
CPU time 3.83 seconds
Started Aug 10 04:53:21 PM PDT 24
Finished Aug 10 04:53:25 PM PDT 24
Peak memory 222420 kb
Host smart-26474c56-866a-433c-845a-4f78497352bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145844647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.4145844647
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1987404188
Short name T479
Test name
Test status
Simulation time 202907016 ps
CPU time 3.54 seconds
Started Aug 10 04:53:23 PM PDT 24
Finished Aug 10 04:53:26 PM PDT 24
Peak memory 214220 kb
Host smart-f7fc152e-5c35-4e6f-971e-033c15fbc7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987404188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1987404188
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1199464591
Short name T691
Test name
Test status
Simulation time 87820349 ps
CPU time 2.69 seconds
Started Aug 10 04:53:22 PM PDT 24
Finished Aug 10 04:53:25 PM PDT 24
Peak memory 208144 kb
Host smart-cca6ed6b-0716-4483-b564-adcabd0abf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199464591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1199464591
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2929167854
Short name T743
Test name
Test status
Simulation time 287607220 ps
CPU time 2.31 seconds
Started Aug 10 04:53:23 PM PDT 24
Finished Aug 10 04:53:25 PM PDT 24
Peak memory 206756 kb
Host smart-174dd1d4-7f41-4940-9216-2b1f87d3c8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929167854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2929167854
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.315807757
Short name T245
Test name
Test status
Simulation time 50248989 ps
CPU time 2.79 seconds
Started Aug 10 04:53:25 PM PDT 24
Finished Aug 10 04:53:28 PM PDT 24
Peak memory 208492 kb
Host smart-5fe2b930-28fb-4e81-9345-f85edad64005
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315807757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.315807757
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.959935534
Short name T308
Test name
Test status
Simulation time 2459668629 ps
CPU time 18.46 seconds
Started Aug 10 04:53:22 PM PDT 24
Finished Aug 10 04:53:41 PM PDT 24
Peak memory 208980 kb
Host smart-f7916066-72ca-43d8-a908-48b197a5ab91
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959935534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.959935534
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3886808342
Short name T544
Test name
Test status
Simulation time 90989391 ps
CPU time 3.93 seconds
Started Aug 10 04:53:23 PM PDT 24
Finished Aug 10 04:53:27 PM PDT 24
Peak memory 208872 kb
Host smart-7881a58f-ad59-45b5-a252-8c18acef375a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886808342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3886808342
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.395375263
Short name T727
Test name
Test status
Simulation time 35735308 ps
CPU time 1.85 seconds
Started Aug 10 04:53:23 PM PDT 24
Finished Aug 10 04:53:25 PM PDT 24
Peak memory 208348 kb
Host smart-8ca31c8c-c22c-4d36-87d3-40bb4a9e65bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395375263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.395375263
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.309000919
Short name T396
Test name
Test status
Simulation time 1912422946 ps
CPU time 3.66 seconds
Started Aug 10 04:53:22 PM PDT 24
Finished Aug 10 04:53:25 PM PDT 24
Peak memory 208400 kb
Host smart-bea0c920-231c-4fc3-bf85-dfcf87ddac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309000919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.309000919
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2139262800
Short name T372
Test name
Test status
Simulation time 7493586916 ps
CPU time 215.55 seconds
Started Aug 10 04:53:21 PM PDT 24
Finished Aug 10 04:56:57 PM PDT 24
Peak memory 216012 kb
Host smart-71ca1cbe-f880-451e-8eab-46f9caf12338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139262800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2139262800
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.451391084
Short name T274
Test name
Test status
Simulation time 1124073796 ps
CPU time 16.33 seconds
Started Aug 10 04:53:21 PM PDT 24
Finished Aug 10 04:53:38 PM PDT 24
Peak memory 214248 kb
Host smart-db633560-7b2e-4182-a9a6-038293be9e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451391084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.451391084
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3055986112
Short name T131
Test name
Test status
Simulation time 147247336 ps
CPU time 1.89 seconds
Started Aug 10 04:53:21 PM PDT 24
Finished Aug 10 04:53:23 PM PDT 24
Peak memory 209684 kb
Host smart-e8b29780-99d3-480f-bd8f-6afe0cb6d7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055986112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3055986112
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2399131178
Short name T637
Test name
Test status
Simulation time 12825574 ps
CPU time 0.76 seconds
Started Aug 10 04:51:03 PM PDT 24
Finished Aug 10 04:51:04 PM PDT 24
Peak memory 205848 kb
Host smart-6add2826-fd52-451c-9482-2ebd1899e9d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399131178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2399131178
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3193170649
Short name T828
Test name
Test status
Simulation time 246707946 ps
CPU time 7.75 seconds
Started Aug 10 04:50:54 PM PDT 24
Finished Aug 10 04:51:02 PM PDT 24
Peak memory 222568 kb
Host smart-73ecd45e-3799-44a3-b126-dde437d30e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193170649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3193170649
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.881774792
Short name T73
Test name
Test status
Simulation time 316460555 ps
CPU time 2.66 seconds
Started Aug 10 04:50:53 PM PDT 24
Finished Aug 10 04:50:56 PM PDT 24
Peak memory 209280 kb
Host smart-365d2a99-d1f8-4742-b84e-94f7869fa22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881774792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.881774792
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.4018824051
Short name T911
Test name
Test status
Simulation time 34128545 ps
CPU time 1.8 seconds
Started Aug 10 04:50:54 PM PDT 24
Finished Aug 10 04:50:55 PM PDT 24
Peak memory 214296 kb
Host smart-099d7f0f-809c-4983-84d0-5d9e34f8d390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018824051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.4018824051
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1585742573
Short name T649
Test name
Test status
Simulation time 150776448 ps
CPU time 3.35 seconds
Started Aug 10 04:50:53 PM PDT 24
Finished Aug 10 04:50:56 PM PDT 24
Peak memory 209384 kb
Host smart-823ba487-4077-4bfb-910b-1af2efc69601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585742573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1585742573
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2972363273
Short name T428
Test name
Test status
Simulation time 41453768 ps
CPU time 2.84 seconds
Started Aug 10 04:50:53 PM PDT 24
Finished Aug 10 04:50:55 PM PDT 24
Peak memory 210176 kb
Host smart-f6b79f8e-cc07-40a0-b3e6-7db23ed76108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972363273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2972363273
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1807278914
Short name T11
Test name
Test status
Simulation time 3891292857 ps
CPU time 9.58 seconds
Started Aug 10 04:51:03 PM PDT 24
Finished Aug 10 04:51:13 PM PDT 24
Peak memory 237908 kb
Host smart-c5d5b4f1-6480-4a04-b524-026eae5b5f7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807278914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1807278914
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.4263473399
Short name T662
Test name
Test status
Simulation time 751119326 ps
CPU time 3.13 seconds
Started Aug 10 04:50:46 PM PDT 24
Finished Aug 10 04:50:49 PM PDT 24
Peak memory 208540 kb
Host smart-65877094-2bde-4ad4-80bc-86462a48b866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263473399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.4263473399
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1024740386
Short name T783
Test name
Test status
Simulation time 1013301636 ps
CPU time 3.05 seconds
Started Aug 10 04:50:53 PM PDT 24
Finished Aug 10 04:50:56 PM PDT 24
Peak memory 206932 kb
Host smart-da2c8629-9591-402d-9b9a-9d52d8e2004d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024740386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1024740386
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2138867135
Short name T609
Test name
Test status
Simulation time 9641680352 ps
CPU time 40.48 seconds
Started Aug 10 04:50:46 PM PDT 24
Finished Aug 10 04:51:26 PM PDT 24
Peak memory 208432 kb
Host smart-9011f636-e93c-4cec-bb82-8dcbac183b4d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138867135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2138867135
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3778109137
Short name T516
Test name
Test status
Simulation time 316444709 ps
CPU time 5.52 seconds
Started Aug 10 04:50:52 PM PDT 24
Finished Aug 10 04:50:58 PM PDT 24
Peak memory 208712 kb
Host smart-d6d9fce6-7d9e-4b64-abb2-93db0fa3525f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778109137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3778109137
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2117289625
Short name T663
Test name
Test status
Simulation time 1651055718 ps
CPU time 18.5 seconds
Started Aug 10 04:50:54 PM PDT 24
Finished Aug 10 04:51:12 PM PDT 24
Peak memory 218480 kb
Host smart-2df27d2d-e6ad-433d-b13b-6541435f4eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117289625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2117289625
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1590684823
Short name T130
Test name
Test status
Simulation time 405507260 ps
CPU time 2.55 seconds
Started Aug 10 04:50:44 PM PDT 24
Finished Aug 10 04:50:47 PM PDT 24
Peak memory 206636 kb
Host smart-5afbb796-e485-4eed-b6cf-cf1c24b7626d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590684823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1590684823
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.859431544
Short name T75
Test name
Test status
Simulation time 97549645 ps
CPU time 4.24 seconds
Started Aug 10 04:50:53 PM PDT 24
Finished Aug 10 04:50:57 PM PDT 24
Peak memory 209860 kb
Host smart-c1a28156-2a2a-4b42-9863-47963532ed92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859431544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.859431544
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2925398624
Short name T128
Test name
Test status
Simulation time 56773230 ps
CPU time 1.28 seconds
Started Aug 10 04:50:55 PM PDT 24
Finished Aug 10 04:50:56 PM PDT 24
Peak memory 209540 kb
Host smart-4f3f4fcd-3d62-4a52-b7cc-22467e6c8c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925398624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2925398624
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.641696029
Short name T678
Test name
Test status
Simulation time 16398318 ps
CPU time 0.8 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:37 PM PDT 24
Peak memory 205876 kb
Host smart-e898aa37-420e-4463-8381-11970ef4ce4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641696029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.641696029
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3201101286
Short name T21
Test name
Test status
Simulation time 276015769 ps
CPU time 5.91 seconds
Started Aug 10 04:53:38 PM PDT 24
Finished Aug 10 04:53:44 PM PDT 24
Peak memory 222592 kb
Host smart-f06d8dcb-2ccc-4877-903f-876181c68ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201101286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3201101286
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3199382614
Short name T769
Test name
Test status
Simulation time 2005655080 ps
CPU time 15.93 seconds
Started Aug 10 04:53:33 PM PDT 24
Finished Aug 10 04:53:49 PM PDT 24
Peak memory 209388 kb
Host smart-a0c6bbdf-6293-4ee9-a4e1-37b39bda8084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199382614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3199382614
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3796343011
Short name T104
Test name
Test status
Simulation time 43330948 ps
CPU time 2.76 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:38 PM PDT 24
Peak memory 214572 kb
Host smart-6e3c6675-0a9f-409b-a08a-282fc3d13748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796343011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3796343011
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2369299569
Short name T463
Test name
Test status
Simulation time 293596449 ps
CPU time 2.44 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:38 PM PDT 24
Peak memory 218632 kb
Host smart-561248cf-974d-465b-b8aa-a34e97fa1ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369299569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2369299569
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2367748927
Short name T339
Test name
Test status
Simulation time 260574127 ps
CPU time 4.44 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:41 PM PDT 24
Peak memory 214224 kb
Host smart-11be0204-9dd9-4f03-aeae-bf46f3179162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367748927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2367748927
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1757075961
Short name T250
Test name
Test status
Simulation time 378338287 ps
CPU time 2.19 seconds
Started Aug 10 04:53:22 PM PDT 24
Finished Aug 10 04:53:24 PM PDT 24
Peak memory 208740 kb
Host smart-021fdb96-930c-4190-9332-874dabde44b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757075961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1757075961
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3805642951
Short name T521
Test name
Test status
Simulation time 208348509 ps
CPU time 2.73 seconds
Started Aug 10 04:53:23 PM PDT 24
Finished Aug 10 04:53:26 PM PDT 24
Peak memory 206900 kb
Host smart-9b720cfc-3c49-4f72-82ec-d8f5369c538c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805642951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3805642951
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.447393554
Short name T772
Test name
Test status
Simulation time 40367956 ps
CPU time 1.91 seconds
Started Aug 10 04:53:23 PM PDT 24
Finished Aug 10 04:53:25 PM PDT 24
Peak memory 207108 kb
Host smart-5003c126-0e18-4355-a7cd-af44559cb296
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447393554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.447393554
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3019834489
Short name T489
Test name
Test status
Simulation time 43781046 ps
CPU time 2.64 seconds
Started Aug 10 04:53:25 PM PDT 24
Finished Aug 10 04:53:28 PM PDT 24
Peak memory 208500 kb
Host smart-2229f187-100f-485b-9917-4df43c91fe97
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019834489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3019834489
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1413502086
Short name T718
Test name
Test status
Simulation time 206504353 ps
CPU time 2.62 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:39 PM PDT 24
Peak memory 207384 kb
Host smart-56831f19-41c7-42b4-b797-3b483e5bf2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413502086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1413502086
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2325299770
Short name T915
Test name
Test status
Simulation time 181524045 ps
CPU time 2.29 seconds
Started Aug 10 04:53:22 PM PDT 24
Finished Aug 10 04:53:25 PM PDT 24
Peak memory 207900 kb
Host smart-142e6946-0d86-4cf1-a1b9-05c3ca6b81b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325299770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2325299770
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2442775541
Short name T126
Test name
Test status
Simulation time 562742688 ps
CPU time 21.78 seconds
Started Aug 10 04:53:33 PM PDT 24
Finished Aug 10 04:53:55 PM PDT 24
Peak memory 222484 kb
Host smart-42f54d74-035f-4565-b0bc-104f6dfd7cd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442775541 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2442775541
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2768277156
Short name T559
Test name
Test status
Simulation time 642640931 ps
CPU time 15.74 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:52 PM PDT 24
Peak memory 208632 kb
Host smart-2e415d05-a591-450d-bd33-f140f6d384dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768277156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2768277156
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.281831547
Short name T531
Test name
Test status
Simulation time 150666052 ps
CPU time 3.38 seconds
Started Aug 10 04:53:33 PM PDT 24
Finished Aug 10 04:53:36 PM PDT 24
Peak memory 210260 kb
Host smart-d01f74b6-b4e8-440b-91db-31d6f875b4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281831547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.281831547
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3636769230
Short name T423
Test name
Test status
Simulation time 15674345 ps
CPU time 0.77 seconds
Started Aug 10 04:53:33 PM PDT 24
Finished Aug 10 04:53:34 PM PDT 24
Peak memory 205956 kb
Host smart-4313b9d0-916d-4a10-8d44-c1c99345ce32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636769230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3636769230
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2538765791
Short name T205
Test name
Test status
Simulation time 64463629 ps
CPU time 4.61 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:40 PM PDT 24
Peak memory 214344 kb
Host smart-5ce3be8c-406d-4e66-aeaf-4b6a4f448129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2538765791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2538765791
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1329162977
Short name T587
Test name
Test status
Simulation time 155266242 ps
CPU time 2.56 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:39 PM PDT 24
Peak memory 207516 kb
Host smart-655b58bd-5bec-4348-9897-f9567a22277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329162977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1329162977
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.483215957
Short name T526
Test name
Test status
Simulation time 47809642 ps
CPU time 1.85 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:38 PM PDT 24
Peak memory 214208 kb
Host smart-12f1cb97-dd40-4f1c-8521-4198b09ef8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483215957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.483215957
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.309870544
Short name T212
Test name
Test status
Simulation time 106876376 ps
CPU time 3.96 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:40 PM PDT 24
Peak memory 209052 kb
Host smart-827f15ac-b4bf-478f-aa26-828593a8c2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309870544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.309870544
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3783456465
Short name T204
Test name
Test status
Simulation time 1094265178 ps
CPU time 11.73 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:47 PM PDT 24
Peak memory 214308 kb
Host smart-4c66f9fc-ed52-4330-929f-4247ce37c7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783456465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3783456465
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2889547474
Short name T416
Test name
Test status
Simulation time 1389707083 ps
CPU time 6.4 seconds
Started Aug 10 04:53:38 PM PDT 24
Finished Aug 10 04:53:44 PM PDT 24
Peak memory 207780 kb
Host smart-6237064c-0d49-4e4a-a6ff-74bd6708f08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889547474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2889547474
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.4206646592
Short name T874
Test name
Test status
Simulation time 521791067 ps
CPU time 12.82 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:48 PM PDT 24
Peak memory 208052 kb
Host smart-edc13d5f-6860-4b42-b02b-2185ef26c498
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206646592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4206646592
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.673499861
Short name T333
Test name
Test status
Simulation time 119125846 ps
CPU time 2.51 seconds
Started Aug 10 04:53:34 PM PDT 24
Finished Aug 10 04:53:36 PM PDT 24
Peak memory 206860 kb
Host smart-078e0811-0446-4ff1-8fd2-01d5e8028aea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673499861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.673499861
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3298859901
Short name T448
Test name
Test status
Simulation time 1379715070 ps
CPU time 5.77 seconds
Started Aug 10 04:53:34 PM PDT 24
Finished Aug 10 04:53:40 PM PDT 24
Peak memory 208144 kb
Host smart-a15497ce-617f-4985-8132-5a4583ab3eeb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298859901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3298859901
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2491853773
Short name T841
Test name
Test status
Simulation time 352466671 ps
CPU time 4.33 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:40 PM PDT 24
Peak memory 208948 kb
Host smart-ba10e344-e810-4bb6-a98e-45a3dcbeae5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491853773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2491853773
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3871372537
Short name T665
Test name
Test status
Simulation time 154312590 ps
CPU time 3.47 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:39 PM PDT 24
Peak memory 206688 kb
Host smart-bdfc098c-90c9-4b8e-8006-bc94605c9216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871372537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3871372537
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3063892183
Short name T328
Test name
Test status
Simulation time 222746191 ps
CPU time 8.52 seconds
Started Aug 10 04:53:34 PM PDT 24
Finished Aug 10 04:53:42 PM PDT 24
Peak memory 222420 kb
Host smart-f3cde420-306b-4e35-8030-78e1c5da034f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063892183 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3063892183
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3281449923
Short name T720
Test name
Test status
Simulation time 111235166 ps
CPU time 2.48 seconds
Started Aug 10 04:53:34 PM PDT 24
Finished Aug 10 04:53:36 PM PDT 24
Peak memory 207712 kb
Host smart-dfa9ed1b-a872-41ed-8fd6-9e8b90e5265c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281449923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3281449923
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2498603914
Short name T134
Test name
Test status
Simulation time 134912072 ps
CPU time 2.8 seconds
Started Aug 10 04:53:37 PM PDT 24
Finished Aug 10 04:53:40 PM PDT 24
Peak memory 209584 kb
Host smart-822c8610-7a1c-4f6b-8408-3cc64236be68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498603914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2498603914
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3789601394
Short name T109
Test name
Test status
Simulation time 18323590 ps
CPU time 1.02 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:37 PM PDT 24
Peak memory 206036 kb
Host smart-6c4acf17-f91f-4ea2-bd4d-a3c95471844d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789601394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3789601394
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2011026206
Short name T295
Test name
Test status
Simulation time 124588027 ps
CPU time 5.34 seconds
Started Aug 10 04:53:40 PM PDT 24
Finished Aug 10 04:53:45 PM PDT 24
Peak memory 214228 kb
Host smart-8eff79de-ef8c-4c3e-8097-8b4d09a098d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2011026206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2011026206
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.259333999
Short name T29
Test name
Test status
Simulation time 328812751 ps
CPU time 4.8 seconds
Started Aug 10 04:53:33 PM PDT 24
Finished Aug 10 04:53:38 PM PDT 24
Peak memory 222632 kb
Host smart-cb55fc44-f54b-43d6-87af-8844a0672915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259333999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.259333999
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.760589231
Short name T76
Test name
Test status
Simulation time 23880538 ps
CPU time 1.75 seconds
Started Aug 10 04:53:37 PM PDT 24
Finished Aug 10 04:53:39 PM PDT 24
Peak memory 209512 kb
Host smart-8805abbe-9461-4ea1-86b1-cedcd7e20f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760589231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.760589231
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3977451446
Short name T792
Test name
Test status
Simulation time 83999241 ps
CPU time 2.11 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:38 PM PDT 24
Peak memory 214356 kb
Host smart-dda48ad4-3da6-4d76-b293-12844261fae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977451446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3977451446
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2564671360
Short name T304
Test name
Test status
Simulation time 207893595 ps
CPU time 5.13 seconds
Started Aug 10 04:53:32 PM PDT 24
Finished Aug 10 04:53:37 PM PDT 24
Peak memory 222380 kb
Host smart-5a78ccdb-6879-4b56-991c-57a7247b0219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564671360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2564671360
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3498334489
Short name T685
Test name
Test status
Simulation time 72432429 ps
CPU time 2.63 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:38 PM PDT 24
Peak memory 214196 kb
Host smart-2d5aa4dd-4988-4fa4-ad8b-9b8786c106e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498334489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3498334489
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2203356540
Short name T503
Test name
Test status
Simulation time 379944039 ps
CPU time 9.92 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:45 PM PDT 24
Peak memory 210132 kb
Host smart-b44146a2-f7d7-4165-b9a1-c74b04854022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203356540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2203356540
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.827528588
Short name T548
Test name
Test status
Simulation time 213359584 ps
CPU time 2.88 seconds
Started Aug 10 04:53:37 PM PDT 24
Finished Aug 10 04:53:40 PM PDT 24
Peak memory 208492 kb
Host smart-f9f4ecb2-a8fe-4d01-ad99-ded6a95226ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827528588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.827528588
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1450087287
Short name T742
Test name
Test status
Simulation time 708551877 ps
CPU time 5.77 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:41 PM PDT 24
Peak memory 207876 kb
Host smart-866677da-18ae-4d94-845f-27555e9902b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450087287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1450087287
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3306618708
Short name T711
Test name
Test status
Simulation time 28654280 ps
CPU time 2.25 seconds
Started Aug 10 04:53:33 PM PDT 24
Finished Aug 10 04:53:36 PM PDT 24
Peak memory 208928 kb
Host smart-3515bf90-1d94-4e7c-9bcc-42058af7e3c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306618708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3306618708
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1460499399
Short name T689
Test name
Test status
Simulation time 257748110 ps
CPU time 3.45 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:40 PM PDT 24
Peak memory 206928 kb
Host smart-8c66d00d-b39e-4640-aede-1dd37ec8bf73
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460499399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1460499399
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3941124969
Short name T632
Test name
Test status
Simulation time 71796960 ps
CPU time 3.27 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:38 PM PDT 24
Peak memory 208516 kb
Host smart-476ef748-4ce2-442e-b114-cf367f689e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941124969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3941124969
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.245701053
Short name T885
Test name
Test status
Simulation time 117356202 ps
CPU time 2.48 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:39 PM PDT 24
Peak memory 208628 kb
Host smart-93566989-ed6d-457b-a16a-6bbd07f0d52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245701053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.245701053
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.991806995
Short name T361
Test name
Test status
Simulation time 685009602 ps
CPU time 4.99 seconds
Started Aug 10 04:53:34 PM PDT 24
Finished Aug 10 04:53:39 PM PDT 24
Peak memory 218344 kb
Host smart-e319aee2-2c5f-420f-aaa8-da7ef7b29faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991806995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.991806995
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1921436454
Short name T132
Test name
Test status
Simulation time 89449342 ps
CPU time 2.05 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:38 PM PDT 24
Peak memory 209964 kb
Host smart-deabfcd4-2c83-4a37-9ed9-38a824b597b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921436454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1921436454
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3564009949
Short name T891
Test name
Test status
Simulation time 40992071 ps
CPU time 0.84 seconds
Started Aug 10 04:53:44 PM PDT 24
Finished Aug 10 04:53:45 PM PDT 24
Peak memory 205944 kb
Host smart-7cc4314f-6731-4fb5-9694-41540e028f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564009949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3564009949
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2570389220
Short name T799
Test name
Test status
Simulation time 101643919 ps
CPU time 5.73 seconds
Started Aug 10 04:53:44 PM PDT 24
Finished Aug 10 04:53:49 PM PDT 24
Peak memory 214608 kb
Host smart-ae2a93dc-8d41-4e41-8990-141ad1837fd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2570389220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2570389220
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2006027116
Short name T815
Test name
Test status
Simulation time 272766285 ps
CPU time 3.38 seconds
Started Aug 10 04:53:47 PM PDT 24
Finished Aug 10 04:53:50 PM PDT 24
Peak memory 208988 kb
Host smart-3ce229f8-68c5-4099-86ee-b285ef8ac61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006027116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2006027116
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3032248264
Short name T316
Test name
Test status
Simulation time 113560855 ps
CPU time 2.25 seconds
Started Aug 10 04:53:43 PM PDT 24
Finished Aug 10 04:53:45 PM PDT 24
Peak memory 214568 kb
Host smart-4de3b263-b7de-4ed4-a7b5-f49de9af0b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032248264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3032248264
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3584908618
Short name T99
Test name
Test status
Simulation time 368106713 ps
CPU time 9.51 seconds
Started Aug 10 04:53:48 PM PDT 24
Finished Aug 10 04:53:58 PM PDT 24
Peak memory 222336 kb
Host smart-a39be002-bdd2-4434-ad71-8744bb372a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584908618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3584908618
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2016100213
Short name T236
Test name
Test status
Simulation time 124030275 ps
CPU time 2.74 seconds
Started Aug 10 04:53:47 PM PDT 24
Finished Aug 10 04:53:50 PM PDT 24
Peak memory 220156 kb
Host smart-21f35269-6e36-4e7c-8743-b0237c26729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016100213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2016100213
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_random.1542284511
Short name T826
Test name
Test status
Simulation time 931358009 ps
CPU time 16.16 seconds
Started Aug 10 04:53:44 PM PDT 24
Finished Aug 10 04:54:01 PM PDT 24
Peak memory 209404 kb
Host smart-34c79b3d-5596-4b47-af67-26df8823a8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542284511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1542284511
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.448763255
Short name T871
Test name
Test status
Simulation time 1670671665 ps
CPU time 23.31 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:58 PM PDT 24
Peak memory 208768 kb
Host smart-96046c1b-5d71-43aa-8e11-ec8849ae9535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448763255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.448763255
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1938764732
Short name T389
Test name
Test status
Simulation time 175247513 ps
CPU time 3.83 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:39 PM PDT 24
Peak memory 206852 kb
Host smart-78ecef24-4d93-4ab4-9c23-97dae29c2b77
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938764732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1938764732
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3324843762
Short name T789
Test name
Test status
Simulation time 475425828 ps
CPU time 4.52 seconds
Started Aug 10 04:53:35 PM PDT 24
Finished Aug 10 04:53:40 PM PDT 24
Peak memory 206744 kb
Host smart-c5eaae3a-2526-45c1-9b92-00d4c85277fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324843762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3324843762
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1556576952
Short name T499
Test name
Test status
Simulation time 179191431 ps
CPU time 2.81 seconds
Started Aug 10 04:53:43 PM PDT 24
Finished Aug 10 04:53:46 PM PDT 24
Peak memory 206948 kb
Host smart-e2a5d8b3-29ef-4d3e-8358-731b905740c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556576952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1556576952
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1870787920
Short name T112
Test name
Test status
Simulation time 57564912 ps
CPU time 1.39 seconds
Started Aug 10 04:53:48 PM PDT 24
Finished Aug 10 04:53:50 PM PDT 24
Peak memory 214284 kb
Host smart-bf083156-1738-479d-8c8a-02a7e2c68c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870787920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1870787920
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.123348003
Short name T420
Test name
Test status
Simulation time 159500682 ps
CPU time 3.77 seconds
Started Aug 10 04:53:36 PM PDT 24
Finished Aug 10 04:53:40 PM PDT 24
Peak memory 207012 kb
Host smart-72c64a21-b9fe-4011-a232-f7850b8107c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123348003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.123348003
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1308435959
Short name T248
Test name
Test status
Simulation time 1466073937 ps
CPU time 48.52 seconds
Started Aug 10 04:53:43 PM PDT 24
Finished Aug 10 04:54:32 PM PDT 24
Peak memory 217044 kb
Host smart-41ab229e-fdd4-409e-9a55-7c03b1e94b54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308435959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1308435959
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3720847091
Short name T179
Test name
Test status
Simulation time 3809807367 ps
CPU time 10.76 seconds
Started Aug 10 04:53:44 PM PDT 24
Finished Aug 10 04:53:55 PM PDT 24
Peak memory 222520 kb
Host smart-1a147353-ad70-41db-94fc-be123b616b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720847091 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3720847091
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3309887045
Short name T660
Test name
Test status
Simulation time 257060127 ps
CPU time 5.61 seconds
Started Aug 10 04:53:47 PM PDT 24
Finished Aug 10 04:53:53 PM PDT 24
Peak memory 209932 kb
Host smart-ce6e5a8c-03ee-492a-8064-8e6f169cb80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309887045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3309887045
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3914448141
Short name T488
Test name
Test status
Simulation time 244836047 ps
CPU time 3.16 seconds
Started Aug 10 04:53:44 PM PDT 24
Finished Aug 10 04:53:47 PM PDT 24
Peak memory 210280 kb
Host smart-b2e98946-3662-4364-afc5-b353d01292ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914448141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3914448141
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.205218074
Short name T774
Test name
Test status
Simulation time 12360844 ps
CPU time 0.86 seconds
Started Aug 10 04:53:52 PM PDT 24
Finished Aug 10 04:53:53 PM PDT 24
Peak memory 205892 kb
Host smart-c4637567-0cce-4033-bc64-e50f7542d730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205218074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.205218074
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2229622282
Short name T834
Test name
Test status
Simulation time 141432013 ps
CPU time 6.64 seconds
Started Aug 10 04:53:48 PM PDT 24
Finished Aug 10 04:53:55 PM PDT 24
Peak memory 221612 kb
Host smart-e9be690c-75d7-4d2e-8982-1b2d7563bc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229622282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2229622282
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3304747884
Short name T848
Test name
Test status
Simulation time 51496584 ps
CPU time 2.66 seconds
Started Aug 10 04:53:43 PM PDT 24
Finished Aug 10 04:53:46 PM PDT 24
Peak memory 208804 kb
Host smart-34c4751b-e0fb-4ef9-9225-db221457d6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304747884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3304747884
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1683009050
Short name T45
Test name
Test status
Simulation time 64514338 ps
CPU time 2.9 seconds
Started Aug 10 04:53:43 PM PDT 24
Finished Aug 10 04:53:46 PM PDT 24
Peak memory 214420 kb
Host smart-4ddb3521-c820-4312-87fc-47f8ede4cc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683009050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1683009050
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.469733527
Short name T352
Test name
Test status
Simulation time 245186046 ps
CPU time 8.66 seconds
Started Aug 10 04:53:47 PM PDT 24
Finished Aug 10 04:53:56 PM PDT 24
Peak memory 209316 kb
Host smart-8deb6f90-b883-4a41-bd7e-11530fa7653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469733527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.469733527
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2387301555
Short name T615
Test name
Test status
Simulation time 107224898 ps
CPU time 2.87 seconds
Started Aug 10 04:53:48 PM PDT 24
Finished Aug 10 04:53:51 PM PDT 24
Peak memory 208020 kb
Host smart-5f64bb51-1d21-41ea-b870-9975201b3976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387301555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2387301555
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.4270235478
Short name T866
Test name
Test status
Simulation time 533556290 ps
CPU time 3.05 seconds
Started Aug 10 04:53:48 PM PDT 24
Finished Aug 10 04:53:51 PM PDT 24
Peak memory 208912 kb
Host smart-e39f2a8f-ba03-4022-b6ad-a1dbbdd027d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270235478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.4270235478
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.809662455
Short name T446
Test name
Test status
Simulation time 79189432 ps
CPU time 2.57 seconds
Started Aug 10 04:53:42 PM PDT 24
Finished Aug 10 04:53:45 PM PDT 24
Peak memory 206884 kb
Host smart-b18b1354-907c-4541-9988-56bd234e2c9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809662455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.809662455
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3762078094
Short name T619
Test name
Test status
Simulation time 3702139294 ps
CPU time 18.62 seconds
Started Aug 10 04:53:42 PM PDT 24
Finished Aug 10 04:54:00 PM PDT 24
Peak memory 208964 kb
Host smart-e67c2dca-d74a-41f2-b040-21d69a4042f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762078094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3762078094
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2187559183
Short name T287
Test name
Test status
Simulation time 595144429 ps
CPU time 7.79 seconds
Started Aug 10 04:53:54 PM PDT 24
Finished Aug 10 04:54:02 PM PDT 24
Peak memory 218524 kb
Host smart-3d8023ec-c2a7-40ea-ae0f-e777eaf8e222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187559183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2187559183
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.801383245
Short name T699
Test name
Test status
Simulation time 177158935 ps
CPU time 3.13 seconds
Started Aug 10 04:53:47 PM PDT 24
Finished Aug 10 04:53:50 PM PDT 24
Peak memory 206620 kb
Host smart-584b4609-9c59-4af5-9fbb-26d0e4b70ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801383245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.801383245
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.536346190
Short name T553
Test name
Test status
Simulation time 779443543 ps
CPU time 10.18 seconds
Started Aug 10 04:54:02 PM PDT 24
Finished Aug 10 04:54:12 PM PDT 24
Peak memory 222516 kb
Host smart-229f8bb2-45fa-4780-941c-0c84754e1289
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536346190 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.536346190
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2902896470
Short name T617
Test name
Test status
Simulation time 331576670 ps
CPU time 8.1 seconds
Started Aug 10 04:53:47 PM PDT 24
Finished Aug 10 04:53:55 PM PDT 24
Peak memory 218376 kb
Host smart-1c780847-ef5b-40b4-aaab-395e16f58ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902896470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2902896470
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1357035921
Short name T890
Test name
Test status
Simulation time 351189451 ps
CPU time 2.86 seconds
Started Aug 10 04:53:53 PM PDT 24
Finished Aug 10 04:53:56 PM PDT 24
Peak memory 209636 kb
Host smart-c576f69d-c0e7-4ccf-8461-c1b0fab3ffae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357035921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1357035921
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2806276783
Short name T436
Test name
Test status
Simulation time 14125426 ps
CPU time 0.72 seconds
Started Aug 10 04:53:52 PM PDT 24
Finished Aug 10 04:53:53 PM PDT 24
Peak memory 205912 kb
Host smart-0ea9140a-c732-4505-9bf9-c6a039527583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806276783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2806276783
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.53243242
Short name T895
Test name
Test status
Simulation time 141871300 ps
CPU time 5.19 seconds
Started Aug 10 04:53:51 PM PDT 24
Finished Aug 10 04:53:56 PM PDT 24
Peak memory 220460 kb
Host smart-a66e8b03-877c-47cf-bc75-900d78abcd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53243242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.53243242
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1622403161
Short name T571
Test name
Test status
Simulation time 119645983 ps
CPU time 2.03 seconds
Started Aug 10 04:53:52 PM PDT 24
Finished Aug 10 04:53:54 PM PDT 24
Peak memory 207412 kb
Host smart-f2d79507-e3ed-4764-aa4b-c2a87051b19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622403161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1622403161
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1386232873
Short name T731
Test name
Test status
Simulation time 278668985 ps
CPU time 6.38 seconds
Started Aug 10 04:53:51 PM PDT 24
Finished Aug 10 04:53:57 PM PDT 24
Peak memory 209280 kb
Host smart-ae71c555-e2a4-49b2-ada0-4093075a417c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386232873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1386232873
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_random.2000901863
Short name T813
Test name
Test status
Simulation time 387045206 ps
CPU time 5.16 seconds
Started Aug 10 04:53:51 PM PDT 24
Finished Aug 10 04:53:57 PM PDT 24
Peak memory 214288 kb
Host smart-755674fe-fd98-4827-8070-9b96e30df045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000901863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2000901863
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.754111824
Short name T594
Test name
Test status
Simulation time 324905703 ps
CPU time 3.06 seconds
Started Aug 10 04:53:58 PM PDT 24
Finished Aug 10 04:54:01 PM PDT 24
Peak memory 207332 kb
Host smart-23d7b4ff-79ae-4969-a68a-28da1c82f166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754111824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.754111824
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.900146431
Short name T481
Test name
Test status
Simulation time 155653022 ps
CPU time 4.8 seconds
Started Aug 10 04:53:52 PM PDT 24
Finished Aug 10 04:53:57 PM PDT 24
Peak memory 207980 kb
Host smart-69b2de9f-8f6a-4adf-a59d-258d9d698b59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900146431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.900146431
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.455527529
Short name T636
Test name
Test status
Simulation time 105221411 ps
CPU time 2.78 seconds
Started Aug 10 04:53:54 PM PDT 24
Finished Aug 10 04:53:57 PM PDT 24
Peak memory 207880 kb
Host smart-1354304f-7289-45e5-be09-89f1c744f3a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455527529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.455527529
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.778551804
Short name T208
Test name
Test status
Simulation time 274991059 ps
CPU time 3.67 seconds
Started Aug 10 04:53:57 PM PDT 24
Finished Aug 10 04:54:01 PM PDT 24
Peak memory 208556 kb
Host smart-d4498b4b-cf55-495b-a5d4-560270dc5b69
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778551804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.778551804
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1964655340
Short name T515
Test name
Test status
Simulation time 139965054 ps
CPU time 2.08 seconds
Started Aug 10 04:53:56 PM PDT 24
Finished Aug 10 04:53:58 PM PDT 24
Peak memory 209324 kb
Host smart-d9ea48ea-6934-47ad-874e-f4a29000571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964655340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1964655340
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.873599485
Short name T824
Test name
Test status
Simulation time 179452571 ps
CPU time 4.32 seconds
Started Aug 10 04:53:52 PM PDT 24
Finished Aug 10 04:53:57 PM PDT 24
Peak memory 208452 kb
Host smart-ae5e63a3-b667-4733-9684-7bd3dc3a15fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873599485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.873599485
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.377414831
Short name T434
Test name
Test status
Simulation time 102748801 ps
CPU time 4.33 seconds
Started Aug 10 04:53:57 PM PDT 24
Finished Aug 10 04:54:01 PM PDT 24
Peak memory 209324 kb
Host smart-8e6cdd65-c49b-45b4-84ac-e746a3100b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377414831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.377414831
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.106893137
Short name T35
Test name
Test status
Simulation time 62776015 ps
CPU time 2.87 seconds
Started Aug 10 04:53:52 PM PDT 24
Finished Aug 10 04:53:55 PM PDT 24
Peak memory 210412 kb
Host smart-fb998a87-3595-4f9c-96f6-e342d74d0ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106893137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.106893137
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2746592238
Short name T766
Test name
Test status
Simulation time 13095511 ps
CPU time 0.88 seconds
Started Aug 10 04:54:10 PM PDT 24
Finished Aug 10 04:54:11 PM PDT 24
Peak memory 205824 kb
Host smart-da683298-2868-4983-8100-db0d348e1021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746592238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2746592238
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3425366141
Short name T366
Test name
Test status
Simulation time 988494740 ps
CPU time 10.86 seconds
Started Aug 10 04:53:52 PM PDT 24
Finished Aug 10 04:54:03 PM PDT 24
Peak memory 214340 kb
Host smart-4a136f39-d8fc-4268-b665-5c71abb374df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425366141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3425366141
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3799945029
Short name T523
Test name
Test status
Simulation time 191856944 ps
CPU time 2.41 seconds
Started Aug 10 04:53:59 PM PDT 24
Finished Aug 10 04:54:02 PM PDT 24
Peak memory 207796 kb
Host smart-5040da88-9e24-4d52-ac14-3ac91b5ac36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799945029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3799945029
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2951508635
Short name T395
Test name
Test status
Simulation time 8644897799 ps
CPU time 12.07 seconds
Started Aug 10 04:54:01 PM PDT 24
Finished Aug 10 04:54:13 PM PDT 24
Peak memory 208772 kb
Host smart-aa404a8e-8ad4-4756-b668-ba2c2aa9fd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951508635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2951508635
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1818356639
Short name T84
Test name
Test status
Simulation time 67820752 ps
CPU time 2.47 seconds
Started Aug 10 04:53:59 PM PDT 24
Finished Aug 10 04:54:01 PM PDT 24
Peak memory 214468 kb
Host smart-e00a957d-a8cf-4cb9-8a62-2ab670cf6d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818356639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1818356639
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.225286941
Short name T803
Test name
Test status
Simulation time 215399795 ps
CPU time 1.92 seconds
Started Aug 10 04:53:59 PM PDT 24
Finished Aug 10 04:54:01 PM PDT 24
Peak memory 217124 kb
Host smart-865171f8-add4-4825-aeaa-4b774853aa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225286941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.225286941
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.644531793
Short name T914
Test name
Test status
Simulation time 178162091 ps
CPU time 4.61 seconds
Started Aug 10 04:54:00 PM PDT 24
Finished Aug 10 04:54:05 PM PDT 24
Peak memory 210372 kb
Host smart-0e29a1bc-6458-4a97-ad6b-202623486c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644531793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.644531793
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.517145199
Short name T763
Test name
Test status
Simulation time 1750300178 ps
CPU time 9.5 seconds
Started Aug 10 04:53:58 PM PDT 24
Finished Aug 10 04:54:07 PM PDT 24
Peak memory 209404 kb
Host smart-db134f01-1363-4be3-8d3b-35414e88a1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517145199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.517145199
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.130265928
Short name T642
Test name
Test status
Simulation time 48394301 ps
CPU time 2.64 seconds
Started Aug 10 04:53:55 PM PDT 24
Finished Aug 10 04:53:57 PM PDT 24
Peak memory 206832 kb
Host smart-cf6979ce-8c18-4741-badc-178ad60b870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130265928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.130265928
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3530930045
Short name T337
Test name
Test status
Simulation time 570436630 ps
CPU time 5.12 seconds
Started Aug 10 04:53:51 PM PDT 24
Finished Aug 10 04:53:56 PM PDT 24
Peak memory 207884 kb
Host smart-2464b03b-73e0-47be-85f5-41c3f80c50f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530930045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3530930045
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2808470053
Short name T390
Test name
Test status
Simulation time 469960057 ps
CPU time 6.44 seconds
Started Aug 10 04:53:54 PM PDT 24
Finished Aug 10 04:54:00 PM PDT 24
Peak memory 208876 kb
Host smart-5237c34b-e8c1-4f2f-9caf-1189d886d367
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808470053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2808470053
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.4027245332
Short name T861
Test name
Test status
Simulation time 34731572 ps
CPU time 2.28 seconds
Started Aug 10 04:53:53 PM PDT 24
Finished Aug 10 04:53:55 PM PDT 24
Peak memory 206752 kb
Host smart-0ab7cb60-527e-4221-b22f-58625595dc51
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027245332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.4027245332
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2069843967
Short name T697
Test name
Test status
Simulation time 638477247 ps
CPU time 3.8 seconds
Started Aug 10 04:54:01 PM PDT 24
Finished Aug 10 04:54:05 PM PDT 24
Peak memory 218128 kb
Host smart-69deed7f-6af3-4d7a-ad35-340f86650f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069843967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2069843967
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.268876194
Short name T591
Test name
Test status
Simulation time 64947230 ps
CPU time 2.95 seconds
Started Aug 10 04:53:51 PM PDT 24
Finished Aug 10 04:53:54 PM PDT 24
Peak memory 208852 kb
Host smart-32dfb46e-e4e0-4bbf-9a40-8d539e84ca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268876194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.268876194
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.89361258
Short name T543
Test name
Test status
Simulation time 220882804 ps
CPU time 9.85 seconds
Started Aug 10 04:53:59 PM PDT 24
Finished Aug 10 04:54:09 PM PDT 24
Peak memory 218876 kb
Host smart-370a0624-6413-478e-849d-0810b7c341c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89361258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.89361258
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3564385558
Short name T750
Test name
Test status
Simulation time 1696126789 ps
CPU time 6.72 seconds
Started Aug 10 04:53:59 PM PDT 24
Finished Aug 10 04:54:06 PM PDT 24
Peak memory 214220 kb
Host smart-3d342a0a-f0b7-4086-bf97-57b657efc4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564385558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3564385558
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2102917814
Short name T457
Test name
Test status
Simulation time 94325593 ps
CPU time 3.3 seconds
Started Aug 10 04:53:59 PM PDT 24
Finished Aug 10 04:54:03 PM PDT 24
Peak memory 210148 kb
Host smart-5ea55265-a0a7-4322-843d-4646f23898c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102917814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2102917814
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.257167642
Short name T664
Test name
Test status
Simulation time 57590283 ps
CPU time 0.76 seconds
Started Aug 10 04:54:12 PM PDT 24
Finished Aug 10 04:54:13 PM PDT 24
Peak memory 205876 kb
Host smart-d4c5a940-7128-4b9d-ab73-1042119044ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257167642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.257167642
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2977632928
Short name T406
Test name
Test status
Simulation time 45794561 ps
CPU time 3.55 seconds
Started Aug 10 04:54:09 PM PDT 24
Finished Aug 10 04:54:13 PM PDT 24
Peak memory 215312 kb
Host smart-bbf58de5-72aa-4154-96ea-95b4f9b932a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977632928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2977632928
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2026729543
Short name T796
Test name
Test status
Simulation time 538300061 ps
CPU time 5.82 seconds
Started Aug 10 04:54:10 PM PDT 24
Finished Aug 10 04:54:16 PM PDT 24
Peak memory 209188 kb
Host smart-75250081-7519-4525-b6d8-b2a166ae949f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026729543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2026729543
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1876328899
Short name T335
Test name
Test status
Simulation time 205405455 ps
CPU time 3.73 seconds
Started Aug 10 04:54:13 PM PDT 24
Finished Aug 10 04:54:17 PM PDT 24
Peak memory 210164 kb
Host smart-55ab78de-8e3f-499b-b366-a1c1e402515d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876328899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1876328899
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2027092252
Short name T349
Test name
Test status
Simulation time 861981558 ps
CPU time 7.07 seconds
Started Aug 10 04:54:14 PM PDT 24
Finished Aug 10 04:54:21 PM PDT 24
Peak memory 214312 kb
Host smart-75e9c0f7-0869-4b32-b288-4fe6b2111e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027092252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2027092252
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3345567154
Short name T741
Test name
Test status
Simulation time 162018886 ps
CPU time 4.28 seconds
Started Aug 10 04:54:10 PM PDT 24
Finished Aug 10 04:54:14 PM PDT 24
Peak memory 222336 kb
Host smart-07cdad15-d503-4148-ad24-67469ae839ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345567154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3345567154
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2813422029
Short name T760
Test name
Test status
Simulation time 46354505 ps
CPU time 2.21 seconds
Started Aug 10 04:54:11 PM PDT 24
Finished Aug 10 04:54:13 PM PDT 24
Peak memory 214216 kb
Host smart-a358d74f-7953-441e-a6da-336345dc73e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813422029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2813422029
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.716425396
Short name T527
Test name
Test status
Simulation time 367855800 ps
CPU time 5.31 seconds
Started Aug 10 04:54:10 PM PDT 24
Finished Aug 10 04:54:15 PM PDT 24
Peak memory 214212 kb
Host smart-94dde498-5eb0-4146-90d6-2ed5b744c725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716425396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.716425396
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3141034431
Short name T520
Test name
Test status
Simulation time 887049200 ps
CPU time 6.06 seconds
Started Aug 10 04:54:14 PM PDT 24
Finished Aug 10 04:54:20 PM PDT 24
Peak memory 208460 kb
Host smart-37d43302-7409-4f64-a912-79f654cd8bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141034431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3141034431
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2967554298
Short name T702
Test name
Test status
Simulation time 37997579 ps
CPU time 2.32 seconds
Started Aug 10 04:54:11 PM PDT 24
Finished Aug 10 04:54:13 PM PDT 24
Peak memory 206868 kb
Host smart-fee1de63-12d8-4adf-9362-559fa4496e48
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967554298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2967554298
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3444208268
Short name T708
Test name
Test status
Simulation time 127361978 ps
CPU time 3.58 seconds
Started Aug 10 04:54:10 PM PDT 24
Finished Aug 10 04:54:14 PM PDT 24
Peak memory 208868 kb
Host smart-216097a4-02f7-406c-9dae-891e29c3b2f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444208268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3444208268
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2310455687
Short name T510
Test name
Test status
Simulation time 50760011 ps
CPU time 2.81 seconds
Started Aug 10 04:54:13 PM PDT 24
Finished Aug 10 04:54:16 PM PDT 24
Peak memory 206948 kb
Host smart-f986ba96-9f8f-420c-861d-8c8af896df3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310455687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2310455687
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3422317960
Short name T852
Test name
Test status
Simulation time 322311661 ps
CPU time 4.03 seconds
Started Aug 10 04:54:11 PM PDT 24
Finished Aug 10 04:54:15 PM PDT 24
Peak memory 215600 kb
Host smart-ceba9058-e81a-4445-ba12-14d26f1c62c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422317960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3422317960
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1597378087
Short name T545
Test name
Test status
Simulation time 175534109 ps
CPU time 2.51 seconds
Started Aug 10 04:54:14 PM PDT 24
Finished Aug 10 04:54:17 PM PDT 24
Peak memory 206936 kb
Host smart-31e87324-6384-4be1-b5a0-5c8356c0b12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597378087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1597378087
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2172468426
Short name T567
Test name
Test status
Simulation time 1877034950 ps
CPU time 13.34 seconds
Started Aug 10 04:54:08 PM PDT 24
Finished Aug 10 04:54:22 PM PDT 24
Peak memory 219496 kb
Host smart-7a6d83d5-edd3-48e0-b1a6-85826b6f6245
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172468426 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2172468426
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3624484604
Short name T429
Test name
Test status
Simulation time 59909478 ps
CPU time 4 seconds
Started Aug 10 04:54:10 PM PDT 24
Finished Aug 10 04:54:14 PM PDT 24
Peak memory 214336 kb
Host smart-fea2d6ee-11dd-4643-a6d4-691e6ee2ea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624484604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3624484604
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2700728755
Short name T863
Test name
Test status
Simulation time 57417163 ps
CPU time 2.3 seconds
Started Aug 10 04:54:11 PM PDT 24
Finished Aug 10 04:54:13 PM PDT 24
Peak memory 209956 kb
Host smart-a30bb9dd-c0fa-4fc0-8fa2-3d12b8afef36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700728755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2700728755
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.745349703
Short name T814
Test name
Test status
Simulation time 11574909 ps
CPU time 0.76 seconds
Started Aug 10 04:54:21 PM PDT 24
Finished Aug 10 04:54:22 PM PDT 24
Peak memory 205840 kb
Host smart-2eb163ac-2074-4a1e-a719-83fc8e3581bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745349703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.745349703
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1990670946
Short name T759
Test name
Test status
Simulation time 1007859288 ps
CPU time 27.12 seconds
Started Aug 10 04:54:20 PM PDT 24
Finished Aug 10 04:54:48 PM PDT 24
Peak memory 214492 kb
Host smart-3b2d978e-f971-4f82-8ed6-a6115c56603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990670946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1990670946
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2092768992
Short name T602
Test name
Test status
Simulation time 174368611 ps
CPU time 2.97 seconds
Started Aug 10 04:54:13 PM PDT 24
Finished Aug 10 04:54:16 PM PDT 24
Peak memory 209160 kb
Host smart-cf7515ff-9d1f-440b-8c6d-b53349264f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092768992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2092768992
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2399818699
Short name T502
Test name
Test status
Simulation time 283169534 ps
CPU time 5.98 seconds
Started Aug 10 04:54:13 PM PDT 24
Finished Aug 10 04:54:19 PM PDT 24
Peak memory 222472 kb
Host smart-a4ce96b0-8fd2-413d-8fa7-34554d17f18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399818699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2399818699
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1198254922
Short name T658
Test name
Test status
Simulation time 1067860083 ps
CPU time 6.35 seconds
Started Aug 10 04:54:10 PM PDT 24
Finished Aug 10 04:54:16 PM PDT 24
Peak memory 209596 kb
Host smart-f885e182-0acd-47f6-a5c9-011ee37a4c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198254922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1198254922
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3700147058
Short name T820
Test name
Test status
Simulation time 21198283 ps
CPU time 1.78 seconds
Started Aug 10 04:54:10 PM PDT 24
Finished Aug 10 04:54:12 PM PDT 24
Peak memory 206876 kb
Host smart-1f0bdf1d-6f12-40d4-b93d-879687775e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700147058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3700147058
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2892103860
Short name T584
Test name
Test status
Simulation time 29246904 ps
CPU time 2.14 seconds
Started Aug 10 04:54:11 PM PDT 24
Finished Aug 10 04:54:13 PM PDT 24
Peak memory 207428 kb
Host smart-536ddc2d-3be7-45ac-8d1b-58bc07bc2fe4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892103860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2892103860
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2748241896
Short name T564
Test name
Test status
Simulation time 514463788 ps
CPU time 13.82 seconds
Started Aug 10 04:54:13 PM PDT 24
Finished Aug 10 04:54:27 PM PDT 24
Peak memory 207900 kb
Host smart-87541c7d-d7cc-4862-a0b7-cc8f59cf5577
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748241896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2748241896
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2526057378
Short name T330
Test name
Test status
Simulation time 338994155 ps
CPU time 5.47 seconds
Started Aug 10 04:54:10 PM PDT 24
Finished Aug 10 04:54:16 PM PDT 24
Peak memory 207868 kb
Host smart-0e528449-87e3-4459-bd89-7b27680b0d31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526057378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2526057378
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.108596854
Short name T541
Test name
Test status
Simulation time 95062892 ps
CPU time 2.9 seconds
Started Aug 10 04:54:17 PM PDT 24
Finished Aug 10 04:54:20 PM PDT 24
Peak memory 209016 kb
Host smart-5f03be40-01ec-4417-80cb-c9c8792f3e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108596854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.108596854
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1657041568
Short name T603
Test name
Test status
Simulation time 52391128 ps
CPU time 2.13 seconds
Started Aug 10 04:54:10 PM PDT 24
Finished Aug 10 04:54:12 PM PDT 24
Peak memory 208740 kb
Host smart-b8793e35-37d4-4ee6-8142-1e55ceb6e219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657041568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1657041568
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1131381333
Short name T596
Test name
Test status
Simulation time 984250092 ps
CPU time 36.26 seconds
Started Aug 10 04:54:20 PM PDT 24
Finished Aug 10 04:54:56 PM PDT 24
Peak memory 220512 kb
Host smart-5b7d0b5c-1ee2-4ac2-90f0-a4e7102a0d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131381333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1131381333
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.887899591
Short name T176
Test name
Test status
Simulation time 1360225397 ps
CPU time 12.77 seconds
Started Aug 10 04:54:25 PM PDT 24
Finished Aug 10 04:54:38 PM PDT 24
Peak memory 218852 kb
Host smart-39ddf322-cb3e-47c0-b012-844d55e12812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887899591 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.887899591
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.4052894838
Short name T635
Test name
Test status
Simulation time 1304586239 ps
CPU time 12.16 seconds
Started Aug 10 04:54:14 PM PDT 24
Finished Aug 10 04:54:26 PM PDT 24
Peak memory 214292 kb
Host smart-21e6cce8-4de5-4cd4-bdea-e8c3d2b99400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052894838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.4052894838
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3703110086
Short name T444
Test name
Test status
Simulation time 86403521 ps
CPU time 2.68 seconds
Started Aug 10 04:54:21 PM PDT 24
Finished Aug 10 04:54:24 PM PDT 24
Peak memory 209764 kb
Host smart-c05f15b6-04d8-47a2-b853-96c266b4d052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703110086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3703110086
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.593315025
Short name T875
Test name
Test status
Simulation time 19266111 ps
CPU time 0.82 seconds
Started Aug 10 04:54:20 PM PDT 24
Finished Aug 10 04:54:21 PM PDT 24
Peak memory 205836 kb
Host smart-4784f571-a24b-42f5-a6e1-60186257fad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593315025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.593315025
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.479631905
Short name T332
Test name
Test status
Simulation time 424764545 ps
CPU time 4.72 seconds
Started Aug 10 04:54:22 PM PDT 24
Finished Aug 10 04:54:27 PM PDT 24
Peak memory 215328 kb
Host smart-ce6b6c73-5a5c-4d8c-b33f-6c3d1e066f08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479631905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.479631905
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1880584449
Short name T807
Test name
Test status
Simulation time 656525183 ps
CPU time 3.06 seconds
Started Aug 10 04:54:19 PM PDT 24
Finished Aug 10 04:54:22 PM PDT 24
Peak memory 214292 kb
Host smart-cf9ada58-9acb-4762-8a69-f79a690f9cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880584449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1880584449
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1156959326
Short name T881
Test name
Test status
Simulation time 724765960 ps
CPU time 18.22 seconds
Started Aug 10 04:54:22 PM PDT 24
Finished Aug 10 04:54:41 PM PDT 24
Peak memory 208324 kb
Host smart-d01ea4f7-5e11-4f0b-b051-f1229d818d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156959326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1156959326
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2923614982
Short name T24
Test name
Test status
Simulation time 1381713934 ps
CPU time 4.96 seconds
Started Aug 10 04:54:20 PM PDT 24
Finished Aug 10 04:54:25 PM PDT 24
Peak memory 214212 kb
Host smart-0aaee254-d111-4b5b-8c2e-afdf631ecd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923614982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2923614982
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2854642815
Short name T359
Test name
Test status
Simulation time 95723368 ps
CPU time 1.91 seconds
Started Aug 10 04:54:19 PM PDT 24
Finished Aug 10 04:54:21 PM PDT 24
Peak memory 222360 kb
Host smart-d36860bc-47d1-42ef-9f8f-424f70feb620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854642815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2854642815
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.881477518
Short name T137
Test name
Test status
Simulation time 89664614 ps
CPU time 3.96 seconds
Started Aug 10 04:54:21 PM PDT 24
Finished Aug 10 04:54:25 PM PDT 24
Peak memory 208884 kb
Host smart-441e2163-7009-4648-b503-35ee2f071495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881477518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.881477518
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2899843703
Short name T370
Test name
Test status
Simulation time 354508350 ps
CPU time 5.56 seconds
Started Aug 10 04:54:22 PM PDT 24
Finished Aug 10 04:54:27 PM PDT 24
Peak memory 209552 kb
Host smart-c8dd50f9-83cd-47cd-950b-8175801899bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899843703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2899843703
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.735479408
Short name T347
Test name
Test status
Simulation time 42925420 ps
CPU time 2.77 seconds
Started Aug 10 04:54:21 PM PDT 24
Finished Aug 10 04:54:24 PM PDT 24
Peak memory 208672 kb
Host smart-5d76038f-30b8-47ea-9ea9-caccbce7b824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735479408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.735479408
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3846389654
Short name T519
Test name
Test status
Simulation time 97170093 ps
CPU time 2.85 seconds
Started Aug 10 04:54:25 PM PDT 24
Finished Aug 10 04:54:27 PM PDT 24
Peak memory 206888 kb
Host smart-1845486b-a339-4f81-bdfb-2a3943f84dcd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846389654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3846389654
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4218004190
Short name T867
Test name
Test status
Simulation time 162923706 ps
CPU time 3.41 seconds
Started Aug 10 04:54:17 PM PDT 24
Finished Aug 10 04:54:20 PM PDT 24
Peak memory 206696 kb
Host smart-e02aeabc-b18e-4aeb-8019-5ae503598e9d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218004190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4218004190
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4069688887
Short name T296
Test name
Test status
Simulation time 92202842 ps
CPU time 1.95 seconds
Started Aug 10 04:54:19 PM PDT 24
Finished Aug 10 04:54:21 PM PDT 24
Peak memory 208456 kb
Host smart-0124d1dc-c1c2-41b9-baca-2cac21797b46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069688887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4069688887
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2101820706
Short name T294
Test name
Test status
Simulation time 753625259 ps
CPU time 6.3 seconds
Started Aug 10 04:54:18 PM PDT 24
Finished Aug 10 04:54:25 PM PDT 24
Peak memory 210380 kb
Host smart-b052420a-44df-44d4-a812-0f0ce7b0bd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101820706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2101820706
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.781329093
Short name T574
Test name
Test status
Simulation time 718072774 ps
CPU time 7.2 seconds
Started Aug 10 04:54:22 PM PDT 24
Finished Aug 10 04:54:29 PM PDT 24
Peak memory 208008 kb
Host smart-fccad661-2933-42fc-9fa5-50322570b0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781329093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.781329093
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.327049124
Short name T749
Test name
Test status
Simulation time 153767929 ps
CPU time 4.53 seconds
Started Aug 10 04:54:25 PM PDT 24
Finished Aug 10 04:54:29 PM PDT 24
Peak memory 219396 kb
Host smart-eaef7ce2-145c-41b0-a20d-cdeb694d5195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327049124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.327049124
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2107946018
Short name T909
Test name
Test status
Simulation time 1068742330 ps
CPU time 23.16 seconds
Started Aug 10 04:54:18 PM PDT 24
Finished Aug 10 04:54:42 PM PDT 24
Peak memory 220324 kb
Host smart-64f425a9-ed9f-4744-a07c-2fe0aebfa94d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107946018 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2107946018
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.430251144
Short name T490
Test name
Test status
Simulation time 359396531 ps
CPU time 3.64 seconds
Started Aug 10 04:54:22 PM PDT 24
Finished Aug 10 04:54:25 PM PDT 24
Peak memory 209812 kb
Host smart-2a3739cc-c84b-4ddb-92d7-354464b926fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430251144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.430251144
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1215881321
Short name T798
Test name
Test status
Simulation time 656850146 ps
CPU time 2.52 seconds
Started Aug 10 04:54:20 PM PDT 24
Finished Aug 10 04:54:23 PM PDT 24
Peak memory 209828 kb
Host smart-a683e991-6731-48a8-b4e5-72b0279130eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215881321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1215881321
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1149914649
Short name T701
Test name
Test status
Simulation time 14438402 ps
CPU time 0.8 seconds
Started Aug 10 04:51:05 PM PDT 24
Finished Aug 10 04:51:06 PM PDT 24
Peak memory 205880 kb
Host smart-5b722c8a-a238-4529-8dc9-1382f308f37a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149914649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1149914649
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3414864329
Short name T855
Test name
Test status
Simulation time 568177239 ps
CPU time 3.49 seconds
Started Aug 10 04:51:04 PM PDT 24
Finished Aug 10 04:51:08 PM PDT 24
Peak memory 214308 kb
Host smart-b97b94a3-f682-4f75-b243-f6246b907653
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3414864329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3414864329
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1138063578
Short name T9
Test name
Test status
Simulation time 318905207 ps
CPU time 2.98 seconds
Started Aug 10 04:51:04 PM PDT 24
Finished Aug 10 04:51:07 PM PDT 24
Peak memory 211444 kb
Host smart-6e7a531e-ef28-4d97-b1cc-b9b5081498a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138063578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1138063578
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.4126383488
Short name T13
Test name
Test status
Simulation time 165974320 ps
CPU time 1.71 seconds
Started Aug 10 04:51:03 PM PDT 24
Finished Aug 10 04:51:05 PM PDT 24
Peak memory 207152 kb
Host smart-3001b6b7-4a18-4844-aa60-f5e61eb03fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126383488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.4126383488
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2228287266
Short name T174
Test name
Test status
Simulation time 1436924760 ps
CPU time 4.21 seconds
Started Aug 10 04:51:05 PM PDT 24
Finished Aug 10 04:51:09 PM PDT 24
Peak memory 214296 kb
Host smart-4a53746c-1895-426d-9133-c012a860fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228287266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2228287266
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3135802086
Short name T757
Test name
Test status
Simulation time 420104452 ps
CPU time 5.01 seconds
Started Aug 10 04:51:03 PM PDT 24
Finished Aug 10 04:51:09 PM PDT 24
Peak memory 207392 kb
Host smart-0333d59d-2f05-4679-a07b-ea2feb9a5c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135802086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3135802086
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4109989485
Short name T898
Test name
Test status
Simulation time 169095147 ps
CPU time 2.75 seconds
Started Aug 10 04:51:05 PM PDT 24
Finished Aug 10 04:51:08 PM PDT 24
Peak memory 208372 kb
Host smart-2f609f99-f6a4-4715-8aad-0435bee4e4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109989485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4109989485
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.856802339
Short name T268
Test name
Test status
Simulation time 35863534 ps
CPU time 2.6 seconds
Started Aug 10 04:51:04 PM PDT 24
Finished Aug 10 04:51:07 PM PDT 24
Peak memory 208628 kb
Host smart-172a2010-646c-495b-b9dd-d985815a64c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856802339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.856802339
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2194616352
Short name T864
Test name
Test status
Simulation time 254359322 ps
CPU time 3.42 seconds
Started Aug 10 04:51:03 PM PDT 24
Finished Aug 10 04:51:06 PM PDT 24
Peak memory 208888 kb
Host smart-8fe530c4-d06f-4623-86ff-3ca2f08f452c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194616352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2194616352
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3133648447
Short name T556
Test name
Test status
Simulation time 53157567 ps
CPU time 2.46 seconds
Started Aug 10 04:51:03 PM PDT 24
Finished Aug 10 04:51:06 PM PDT 24
Peak memory 206820 kb
Host smart-97df5143-ccc8-4dda-ad79-eabe1258df7b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133648447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3133648447
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2279403134
Short name T532
Test name
Test status
Simulation time 152440499 ps
CPU time 3.6 seconds
Started Aug 10 04:51:04 PM PDT 24
Finished Aug 10 04:51:08 PM PDT 24
Peak memory 208768 kb
Host smart-6830238a-a674-4ac2-96c1-6bf66895a3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279403134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2279403134
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1867646796
Short name T650
Test name
Test status
Simulation time 557684740 ps
CPU time 3.85 seconds
Started Aug 10 04:51:04 PM PDT 24
Finished Aug 10 04:51:08 PM PDT 24
Peak memory 206568 kb
Host smart-162151f5-f761-4d7c-88d7-a719c516e15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867646796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1867646796
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.4032141543
Short name T539
Test name
Test status
Simulation time 199885945 ps
CPU time 2.91 seconds
Started Aug 10 04:51:04 PM PDT 24
Finished Aug 10 04:51:07 PM PDT 24
Peak memory 206832 kb
Host smart-91964273-e07d-41a4-9f60-651978ff57ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032141543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.4032141543
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.604154741
Short name T306
Test name
Test status
Simulation time 1086248119 ps
CPU time 12.09 seconds
Started Aug 10 04:51:03 PM PDT 24
Finished Aug 10 04:51:15 PM PDT 24
Peak memory 218136 kb
Host smart-7e85a3b0-ccc5-42bf-ace9-2fb9ea083ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604154741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.604154741
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3412214307
Short name T379
Test name
Test status
Simulation time 493358549 ps
CPU time 13.12 seconds
Started Aug 10 04:51:02 PM PDT 24
Finished Aug 10 04:51:15 PM PDT 24
Peak memory 210400 kb
Host smart-3147fdee-1ec0-42c9-bd72-7af1ef701e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412214307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3412214307
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1158124275
Short name T450
Test name
Test status
Simulation time 43616119 ps
CPU time 0.72 seconds
Started Aug 10 04:54:21 PM PDT 24
Finished Aug 10 04:54:22 PM PDT 24
Peak memory 205848 kb
Host smart-d39312e9-f1ff-4123-9d31-a578799390e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158124275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1158124275
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.419482282
Short name T307
Test name
Test status
Simulation time 365199202 ps
CPU time 3.81 seconds
Started Aug 10 04:54:19 PM PDT 24
Finished Aug 10 04:54:22 PM PDT 24
Peak memory 215276 kb
Host smart-0375e8d1-570a-4ce9-aac9-a78779bd0156
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419482282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.419482282
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.971100048
Short name T644
Test name
Test status
Simulation time 437285370 ps
CPU time 2.71 seconds
Started Aug 10 04:54:20 PM PDT 24
Finished Aug 10 04:54:22 PM PDT 24
Peak memory 214436 kb
Host smart-2f7e1aa6-09df-4fd2-a739-b22d881c5ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971100048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.971100048
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.4205159931
Short name T651
Test name
Test status
Simulation time 153093989 ps
CPU time 3.87 seconds
Started Aug 10 04:54:20 PM PDT 24
Finished Aug 10 04:54:24 PM PDT 24
Peak memory 218224 kb
Host smart-867e0c1c-6338-4a96-9066-d3cd34b52025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205159931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.4205159931
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.484586185
Short name T86
Test name
Test status
Simulation time 152226141 ps
CPU time 4.32 seconds
Started Aug 10 04:54:19 PM PDT 24
Finished Aug 10 04:54:23 PM PDT 24
Peak memory 209596 kb
Host smart-161926ed-fceb-495e-a393-ade50967c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484586185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.484586185
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3332855108
Short name T373
Test name
Test status
Simulation time 86045693 ps
CPU time 4.2 seconds
Started Aug 10 04:54:20 PM PDT 24
Finished Aug 10 04:54:25 PM PDT 24
Peak memory 221064 kb
Host smart-68b63677-3efc-47a9-aacc-fc17d7584ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332855108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3332855108
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3321592298
Short name T832
Test name
Test status
Simulation time 368211652 ps
CPU time 4.13 seconds
Started Aug 10 04:54:20 PM PDT 24
Finished Aug 10 04:54:25 PM PDT 24
Peak memory 209800 kb
Host smart-5b0eb197-692d-4738-8ddc-da503183b949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321592298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3321592298
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3243463055
Short name T536
Test name
Test status
Simulation time 394173079 ps
CPU time 4.58 seconds
Started Aug 10 04:54:21 PM PDT 24
Finished Aug 10 04:54:26 PM PDT 24
Peak memory 208620 kb
Host smart-7b2b5ae6-727a-4899-ab06-a76ae5f8ad04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243463055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3243463055
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2691516144
Short name T776
Test name
Test status
Simulation time 475040153 ps
CPU time 5.41 seconds
Started Aug 10 04:54:19 PM PDT 24
Finished Aug 10 04:54:24 PM PDT 24
Peak memory 208860 kb
Host smart-265c0637-e335-4028-a5e8-a45bac17c5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691516144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2691516144
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3285336055
Short name T844
Test name
Test status
Simulation time 209212058 ps
CPU time 4.27 seconds
Started Aug 10 04:54:18 PM PDT 24
Finished Aug 10 04:54:23 PM PDT 24
Peak memory 208892 kb
Host smart-3f06556c-099a-48ea-9863-b8b3962f9110
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285336055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3285336055
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.70011428
Short name T620
Test name
Test status
Simulation time 150540821 ps
CPU time 3.67 seconds
Started Aug 10 04:54:20 PM PDT 24
Finished Aug 10 04:54:24 PM PDT 24
Peak memory 209096 kb
Host smart-f0ae12a1-7ffc-4453-9469-4954571dbf71
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70011428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.70011428
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3971657849
Short name T207
Test name
Test status
Simulation time 41837399 ps
CPU time 1.86 seconds
Started Aug 10 04:54:22 PM PDT 24
Finished Aug 10 04:54:24 PM PDT 24
Peak memory 206892 kb
Host smart-d499cfe5-fe49-481e-8d7d-f7fb2e1fae46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971657849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3971657849
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2336442337
Short name T326
Test name
Test status
Simulation time 105472684 ps
CPU time 2.19 seconds
Started Aug 10 04:54:20 PM PDT 24
Finished Aug 10 04:54:22 PM PDT 24
Peak memory 214336 kb
Host smart-6f5f0f85-8340-4ee9-b795-e9985688e646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336442337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2336442337
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2521939208
Short name T626
Test name
Test status
Simulation time 2581424106 ps
CPU time 17.41 seconds
Started Aug 10 04:54:18 PM PDT 24
Finished Aug 10 04:54:36 PM PDT 24
Peak memory 208060 kb
Host smart-f6868284-13b5-4962-9dca-677f24c919db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521939208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2521939208
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.977380320
Short name T542
Test name
Test status
Simulation time 1359398448 ps
CPU time 20.96 seconds
Started Aug 10 04:54:25 PM PDT 24
Finished Aug 10 04:54:46 PM PDT 24
Peak memory 222464 kb
Host smart-788e4037-cbf1-4bdb-88fc-d2a5b24d966b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977380320 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.977380320
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3640985745
Short name T835
Test name
Test status
Simulation time 342554008 ps
CPU time 7.74 seconds
Started Aug 10 04:54:19 PM PDT 24
Finished Aug 10 04:54:27 PM PDT 24
Peak memory 208592 kb
Host smart-b9129b4d-610b-4193-a9ae-ccb844d16367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640985745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3640985745
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2808683677
Short name T554
Test name
Test status
Simulation time 224071208 ps
CPU time 2.6 seconds
Started Aug 10 04:54:19 PM PDT 24
Finished Aug 10 04:54:22 PM PDT 24
Peak memory 210204 kb
Host smart-1f7778bc-439f-42bb-8753-97f5a9848251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808683677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2808683677
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3456432897
Short name T906
Test name
Test status
Simulation time 39822537 ps
CPU time 0.92 seconds
Started Aug 10 04:54:30 PM PDT 24
Finished Aug 10 04:54:31 PM PDT 24
Peak memory 205884 kb
Host smart-02ffe785-f243-47cb-bb28-991418d20ec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456432897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3456432897
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3072643157
Short name T327
Test name
Test status
Simulation time 391109758 ps
CPU time 6 seconds
Started Aug 10 04:54:27 PM PDT 24
Finished Aug 10 04:54:33 PM PDT 24
Peak memory 214380 kb
Host smart-e137ea29-b931-49c2-93b5-61e210f73c83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072643157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3072643157
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1193611182
Short name T7
Test name
Test status
Simulation time 288040263 ps
CPU time 7.57 seconds
Started Aug 10 04:54:33 PM PDT 24
Finished Aug 10 04:54:41 PM PDT 24
Peak memory 222672 kb
Host smart-678044dd-ec86-4bc8-9b7c-77022676ceee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193611182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1193611182
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1410203267
Short name T71
Test name
Test status
Simulation time 310292543 ps
CPU time 1.89 seconds
Started Aug 10 04:54:31 PM PDT 24
Finished Aug 10 04:54:33 PM PDT 24
Peak memory 210372 kb
Host smart-ac972f22-289f-4388-aedc-faf3106caec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410203267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1410203267
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3054820222
Short name T300
Test name
Test status
Simulation time 203034478 ps
CPU time 5.13 seconds
Started Aug 10 04:54:27 PM PDT 24
Finished Aug 10 04:54:32 PM PDT 24
Peak memory 214272 kb
Host smart-1d9dc19a-fbe2-4bd9-a661-663312764010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054820222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3054820222
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3228590084
Short name T511
Test name
Test status
Simulation time 117807495 ps
CPU time 1.98 seconds
Started Aug 10 04:54:27 PM PDT 24
Finished Aug 10 04:54:29 PM PDT 24
Peak memory 206100 kb
Host smart-ee30936b-8b82-4e32-94bb-699e8671dd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228590084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3228590084
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2807727159
Short name T812
Test name
Test status
Simulation time 295246095 ps
CPU time 3.36 seconds
Started Aug 10 04:54:27 PM PDT 24
Finished Aug 10 04:54:30 PM PDT 24
Peak memory 207376 kb
Host smart-7b83685d-31f4-4272-88ca-5474b0254248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807727159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2807727159
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4020321285
Short name T195
Test name
Test status
Simulation time 91273655 ps
CPU time 2.04 seconds
Started Aug 10 04:54:17 PM PDT 24
Finished Aug 10 04:54:19 PM PDT 24
Peak memory 208688 kb
Host smart-9b5eb459-86e7-481c-b0b9-83d5b1c5ee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020321285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4020321285
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3127862251
Short name T671
Test name
Test status
Simulation time 183678030 ps
CPU time 4.22 seconds
Started Aug 10 04:54:31 PM PDT 24
Finished Aug 10 04:54:36 PM PDT 24
Peak memory 208960 kb
Host smart-4e760f70-aa07-45b2-9d1a-4aa5d49260b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127862251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3127862251
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2648980431
Short name T754
Test name
Test status
Simulation time 169890893 ps
CPU time 1.88 seconds
Started Aug 10 04:54:30 PM PDT 24
Finished Aug 10 04:54:32 PM PDT 24
Peak memory 206780 kb
Host smart-3cfa54f5-0660-433d-be3d-8e24b6bec478
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648980431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2648980431
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.4022816152
Short name T496
Test name
Test status
Simulation time 7679795155 ps
CPU time 57.89 seconds
Started Aug 10 04:54:30 PM PDT 24
Finished Aug 10 04:55:28 PM PDT 24
Peak memory 207988 kb
Host smart-767d01d7-3593-4a61-b673-f6f2e32d8ce9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022816152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4022816152
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2850499314
Short name T393
Test name
Test status
Simulation time 25686208 ps
CPU time 1.87 seconds
Started Aug 10 04:54:29 PM PDT 24
Finished Aug 10 04:54:31 PM PDT 24
Peak memory 214188 kb
Host smart-debf51ee-fa63-4ae4-b2eb-29d86da68ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850499314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2850499314
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3940739017
Short name T853
Test name
Test status
Simulation time 61758957 ps
CPU time 2.95 seconds
Started Aug 10 04:54:20 PM PDT 24
Finished Aug 10 04:54:23 PM PDT 24
Peak memory 208480 kb
Host smart-ef0d915c-9722-479f-9dd4-b2520155dda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940739017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3940739017
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2354573807
Short name T239
Test name
Test status
Simulation time 448912080 ps
CPU time 7.42 seconds
Started Aug 10 04:54:33 PM PDT 24
Finished Aug 10 04:54:41 PM PDT 24
Peak memory 220040 kb
Host smart-f9e4e5df-fb37-4ea6-961f-b83e2a863ef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354573807 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2354573807
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1554809012
Short name T695
Test name
Test status
Simulation time 361277459 ps
CPU time 5.01 seconds
Started Aug 10 04:54:31 PM PDT 24
Finished Aug 10 04:54:37 PM PDT 24
Peak memory 214312 kb
Host smart-94a6a5fb-0518-4279-b7d4-3aa5a124dff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554809012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1554809012
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1924528269
Short name T879
Test name
Test status
Simulation time 53307765 ps
CPU time 2.45 seconds
Started Aug 10 04:54:32 PM PDT 24
Finished Aug 10 04:54:34 PM PDT 24
Peak memory 209700 kb
Host smart-c2499442-61d7-4d76-b620-95e4f18b137b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924528269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1924528269
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3669940136
Short name T623
Test name
Test status
Simulation time 39782361 ps
CPU time 0.76 seconds
Started Aug 10 04:54:36 PM PDT 24
Finished Aug 10 04:54:37 PM PDT 24
Peak memory 205916 kb
Host smart-57efe55d-b4a2-4773-9002-1db55c112b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669940136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3669940136
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.428925048
Short name T345
Test name
Test status
Simulation time 204120658 ps
CPU time 6.36 seconds
Started Aug 10 04:54:28 PM PDT 24
Finished Aug 10 04:54:34 PM PDT 24
Peak memory 222400 kb
Host smart-5d082976-2686-4985-8565-f6df1abacb3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428925048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.428925048
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.4062482576
Short name T514
Test name
Test status
Simulation time 395258809 ps
CPU time 3.24 seconds
Started Aug 10 04:54:28 PM PDT 24
Finished Aug 10 04:54:32 PM PDT 24
Peak memory 207868 kb
Host smart-ce198d2f-5d48-4d70-b340-0bfea0657b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062482576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.4062482576
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1545744205
Short name T476
Test name
Test status
Simulation time 228536856 ps
CPU time 3.32 seconds
Started Aug 10 04:54:31 PM PDT 24
Finished Aug 10 04:54:35 PM PDT 24
Peak memory 207936 kb
Host smart-da0bb21a-d88e-45cf-ab73-6b461ea9a17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545744205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1545744205
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1978144040
Short name T261
Test name
Test status
Simulation time 318604221 ps
CPU time 4.18 seconds
Started Aug 10 04:54:26 PM PDT 24
Finished Aug 10 04:54:31 PM PDT 24
Peak memory 222280 kb
Host smart-8581251a-dab8-4e21-b5b5-970fd18b9f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978144040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1978144040
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2849533502
Short name T47
Test name
Test status
Simulation time 373527363 ps
CPU time 3.4 seconds
Started Aug 10 04:54:27 PM PDT 24
Finished Aug 10 04:54:30 PM PDT 24
Peak memory 209764 kb
Host smart-7ff2cc50-4034-4ca5-a4df-4b4acd23f97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849533502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2849533502
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2756475796
Short name T438
Test name
Test status
Simulation time 19322512144 ps
CPU time 28.33 seconds
Started Aug 10 04:54:27 PM PDT 24
Finished Aug 10 04:54:55 PM PDT 24
Peak memory 208724 kb
Host smart-3d1c2fbf-f36f-48de-bf90-fb515bbac004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756475796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2756475796
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1590068409
Short name T249
Test name
Test status
Simulation time 167788075 ps
CPU time 6.28 seconds
Started Aug 10 04:54:31 PM PDT 24
Finished Aug 10 04:54:37 PM PDT 24
Peak memory 208548 kb
Host smart-49941f88-d0ef-4eb2-98a4-76f94bfbe1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590068409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1590068409
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1780210893
Short name T473
Test name
Test status
Simulation time 69905146 ps
CPU time 1.83 seconds
Started Aug 10 04:54:26 PM PDT 24
Finished Aug 10 04:54:28 PM PDT 24
Peak memory 206964 kb
Host smart-8e8fb020-19d9-4d08-80fa-eb93b4324c0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780210893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1780210893
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3625302126
Short name T413
Test name
Test status
Simulation time 159103556 ps
CPU time 2.33 seconds
Started Aug 10 04:54:31 PM PDT 24
Finished Aug 10 04:54:33 PM PDT 24
Peak memory 208000 kb
Host smart-88cefac3-16cb-41dc-a7bb-d2b713c9a23f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625302126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3625302126
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3023555088
Short name T467
Test name
Test status
Simulation time 198898993 ps
CPU time 2.91 seconds
Started Aug 10 04:54:33 PM PDT 24
Finished Aug 10 04:54:36 PM PDT 24
Peak memory 206920 kb
Host smart-72a28ff6-3260-4838-8e54-de5f2e29d7db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023555088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3023555088
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3928760962
Short name T198
Test name
Test status
Simulation time 38124914 ps
CPU time 2.77 seconds
Started Aug 10 04:54:28 PM PDT 24
Finished Aug 10 04:54:31 PM PDT 24
Peak memory 218164 kb
Host smart-19cf4439-72b0-4964-ada0-8e62f3dc0d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928760962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3928760962
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.4244233065
Short name T506
Test name
Test status
Simulation time 5365547142 ps
CPU time 40.84 seconds
Started Aug 10 04:54:25 PM PDT 24
Finished Aug 10 04:55:06 PM PDT 24
Peak memory 208532 kb
Host smart-deb5a78b-5299-41d3-9a14-c70e1bcd9612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244233065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4244233065
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.791898727
Short name T222
Test name
Test status
Simulation time 2240409337 ps
CPU time 38.65 seconds
Started Aug 10 04:54:31 PM PDT 24
Finished Aug 10 04:55:10 PM PDT 24
Peak memory 222484 kb
Host smart-ce33ff3c-38e3-4e32-9428-06f39fc42a4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791898727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.791898727
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1432780568
Short name T477
Test name
Test status
Simulation time 68967508 ps
CPU time 3.67 seconds
Started Aug 10 04:54:30 PM PDT 24
Finished Aug 10 04:54:34 PM PDT 24
Peak memory 218372 kb
Host smart-12f3e8b8-0284-43b4-aecb-504c09cc11bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432780568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1432780568
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3347635624
Short name T775
Test name
Test status
Simulation time 31249570 ps
CPU time 1.86 seconds
Started Aug 10 04:54:26 PM PDT 24
Finished Aug 10 04:54:28 PM PDT 24
Peak memory 210252 kb
Host smart-64f28af0-c7aa-4b5e-acc1-53a7f9ff404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347635624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3347635624
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2596982647
Short name T876
Test name
Test status
Simulation time 48205325 ps
CPU time 0.76 seconds
Started Aug 10 04:54:36 PM PDT 24
Finished Aug 10 04:54:36 PM PDT 24
Peak memory 205836 kb
Host smart-6354cf9c-2042-497f-94a3-45a4862b3edc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596982647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2596982647
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2399427707
Short name T243
Test name
Test status
Simulation time 210068896 ps
CPU time 6.16 seconds
Started Aug 10 04:54:36 PM PDT 24
Finished Aug 10 04:54:42 PM PDT 24
Peak memory 214328 kb
Host smart-13e3cdcf-6126-46a5-91cb-8ac7d7b77ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399427707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2399427707
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1892541462
Short name T595
Test name
Test status
Simulation time 131601130 ps
CPU time 2.02 seconds
Started Aug 10 04:54:35 PM PDT 24
Finished Aug 10 04:54:37 PM PDT 24
Peak memory 218096 kb
Host smart-e85c9b9d-be59-485d-8403-37718ecd2fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892541462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1892541462
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2463435065
Short name T375
Test name
Test status
Simulation time 845446393 ps
CPU time 4.65 seconds
Started Aug 10 04:54:38 PM PDT 24
Finished Aug 10 04:54:42 PM PDT 24
Peak memory 214228 kb
Host smart-261bf7e2-596b-422b-a205-7e85312bb847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463435065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2463435065
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3377918826
Short name T283
Test name
Test status
Simulation time 44801970 ps
CPU time 2.8 seconds
Started Aug 10 04:54:36 PM PDT 24
Finished Aug 10 04:54:39 PM PDT 24
Peak memory 222432 kb
Host smart-b5f703d5-e935-45da-ae7c-64067a5c8419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377918826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3377918826
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.695011744
Short name T475
Test name
Test status
Simulation time 759454968 ps
CPU time 2.2 seconds
Started Aug 10 04:54:38 PM PDT 24
Finished Aug 10 04:54:40 PM PDT 24
Peak memory 214236 kb
Host smart-8d19b70e-e648-4e79-baa1-e823cbe90640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695011744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.695011744
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.864871544
Short name T478
Test name
Test status
Simulation time 453728178 ps
CPU time 4.49 seconds
Started Aug 10 04:54:36 PM PDT 24
Finished Aug 10 04:54:41 PM PDT 24
Peak memory 207024 kb
Host smart-fbad73c7-74d1-4852-a676-605a6916b81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864871544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.864871544
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.919953211
Short name T840
Test name
Test status
Simulation time 51218728 ps
CPU time 2.98 seconds
Started Aug 10 04:54:37 PM PDT 24
Finished Aug 10 04:54:40 PM PDT 24
Peak memory 208416 kb
Host smart-6e39a581-1eb8-468e-a55c-15d09209ec66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919953211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.919953211
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.4077935739
Short name T703
Test name
Test status
Simulation time 1986114548 ps
CPU time 6.97 seconds
Started Aug 10 04:54:36 PM PDT 24
Finished Aug 10 04:54:43 PM PDT 24
Peak memory 207116 kb
Host smart-039f4c56-1e65-4a96-8c3c-498976a73504
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077935739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4077935739
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2561930847
Short name T412
Test name
Test status
Simulation time 2049951773 ps
CPU time 45.02 seconds
Started Aug 10 04:54:37 PM PDT 24
Finished Aug 10 04:55:22 PM PDT 24
Peak memory 207896 kb
Host smart-60b42431-621f-474f-91c0-e8ab49e1452e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561930847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2561930847
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2897184577
Short name T483
Test name
Test status
Simulation time 175311326 ps
CPU time 2.27 seconds
Started Aug 10 04:54:41 PM PDT 24
Finished Aug 10 04:54:44 PM PDT 24
Peak memory 207684 kb
Host smart-4201ab12-3e58-4476-ba46-4741588bdd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897184577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2897184577
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3643593610
Short name T784
Test name
Test status
Simulation time 1331091552 ps
CPU time 12.76 seconds
Started Aug 10 04:54:35 PM PDT 24
Finished Aug 10 04:54:48 PM PDT 24
Peak memory 208532 kb
Host smart-dfae6325-82e7-461a-b38e-c2ad1d22be49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643593610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3643593610
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.216711938
Short name T889
Test name
Test status
Simulation time 1995718418 ps
CPU time 21.86 seconds
Started Aug 10 04:54:37 PM PDT 24
Finished Aug 10 04:54:59 PM PDT 24
Peak memory 215380 kb
Host smart-abfaa4bd-8191-4e72-9cf8-ed91dc80351a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216711938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.216711938
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1629539235
Short name T219
Test name
Test status
Simulation time 803038801 ps
CPU time 19.06 seconds
Started Aug 10 04:54:39 PM PDT 24
Finished Aug 10 04:54:58 PM PDT 24
Peak memory 222408 kb
Host smart-a92c337b-ae02-4aa4-b064-8ed06830181e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629539235 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1629539235
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.736574206
Short name T113
Test name
Test status
Simulation time 54323722 ps
CPU time 1.51 seconds
Started Aug 10 04:54:39 PM PDT 24
Finished Aug 10 04:54:40 PM PDT 24
Peak memory 209804 kb
Host smart-1191b5b3-b528-464f-a0ce-13b0f3e655f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736574206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.736574206
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.769104958
Short name T562
Test name
Test status
Simulation time 8946087 ps
CPU time 0.69 seconds
Started Aug 10 04:54:51 PM PDT 24
Finished Aug 10 04:54:52 PM PDT 24
Peak memory 205852 kb
Host smart-aa253b2c-0c97-4271-a631-1fe70005c7cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769104958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.769104958
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1077561749
Short name T458
Test name
Test status
Simulation time 520041715 ps
CPU time 13.11 seconds
Started Aug 10 04:54:37 PM PDT 24
Finished Aug 10 04:54:50 PM PDT 24
Peak memory 208940 kb
Host smart-99642df8-ecd4-4385-9cf1-256842370dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077561749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1077561749
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.356425095
Short name T298
Test name
Test status
Simulation time 42775822 ps
CPU time 2.65 seconds
Started Aug 10 04:54:37 PM PDT 24
Finished Aug 10 04:54:40 PM PDT 24
Peak memory 221568 kb
Host smart-5a1ff165-a3ad-4f96-84fd-3d6b70ad58b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356425095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.356425095
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3013756638
Short name T62
Test name
Test status
Simulation time 701848856 ps
CPU time 4.61 seconds
Started Aug 10 04:54:40 PM PDT 24
Finished Aug 10 04:54:44 PM PDT 24
Peak memory 214256 kb
Host smart-4284a066-3b00-483b-a5a7-11655f323cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013756638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3013756638
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.189381401
Short name T230
Test name
Test status
Simulation time 844672536 ps
CPU time 12.4 seconds
Started Aug 10 04:54:36 PM PDT 24
Finished Aug 10 04:54:49 PM PDT 24
Peak memory 209092 kb
Host smart-6915de78-344a-422a-9fe4-8d838f0836b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189381401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.189381401
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.202890991
Short name T655
Test name
Test status
Simulation time 170168981 ps
CPU time 3.76 seconds
Started Aug 10 04:54:36 PM PDT 24
Finished Aug 10 04:54:40 PM PDT 24
Peak memory 208844 kb
Host smart-2862e1f6-ce22-49c2-b6e1-391cc63ced98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202890991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.202890991
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2499174940
Short name T549
Test name
Test status
Simulation time 129249365 ps
CPU time 3.23 seconds
Started Aug 10 04:54:40 PM PDT 24
Finished Aug 10 04:54:44 PM PDT 24
Peak memory 208548 kb
Host smart-d1b3e154-d52a-4435-840c-ced961d7d7ee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499174940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2499174940
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1919539099
Short name T905
Test name
Test status
Simulation time 50979958 ps
CPU time 2.6 seconds
Started Aug 10 04:54:39 PM PDT 24
Finished Aug 10 04:54:41 PM PDT 24
Peak memory 206808 kb
Host smart-88187c01-df1d-4a4b-951a-2b9c76e21332
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919539099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1919539099
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1320285905
Short name T241
Test name
Test status
Simulation time 234935793 ps
CPU time 2.97 seconds
Started Aug 10 04:54:36 PM PDT 24
Finished Aug 10 04:54:39 PM PDT 24
Peak memory 208876 kb
Host smart-60750b7c-960d-433e-96c8-b5fe991b6efe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320285905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1320285905
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1254579136
Short name T209
Test name
Test status
Simulation time 675693461 ps
CPU time 3.1 seconds
Started Aug 10 04:54:45 PM PDT 24
Finished Aug 10 04:54:48 PM PDT 24
Peak memory 209936 kb
Host smart-2c096e7e-9241-495d-9369-658a17b3c1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254579136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1254579136
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.4192607243
Short name T197
Test name
Test status
Simulation time 1713062407 ps
CPU time 14.76 seconds
Started Aug 10 04:54:39 PM PDT 24
Finished Aug 10 04:54:54 PM PDT 24
Peak memory 208628 kb
Host smart-fb7e3253-56c4-4aea-ac90-677ab0a6e6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192607243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.4192607243
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1526143204
Short name T244
Test name
Test status
Simulation time 1953078124 ps
CPU time 20.71 seconds
Started Aug 10 04:54:45 PM PDT 24
Finished Aug 10 04:55:06 PM PDT 24
Peak memory 215980 kb
Host smart-a95d8077-2e28-4a84-bdb4-2b10b9e75bc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526143204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1526143204
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.948143431
Short name T497
Test name
Test status
Simulation time 104924652 ps
CPU time 4.43 seconds
Started Aug 10 04:54:37 PM PDT 24
Finished Aug 10 04:54:41 PM PDT 24
Peak memory 209192 kb
Host smart-de31661e-db0f-47be-9306-fa86b4748abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948143431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.948143431
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1031464833
Short name T382
Test name
Test status
Simulation time 268937107 ps
CPU time 1.37 seconds
Started Aug 10 04:54:46 PM PDT 24
Finished Aug 10 04:54:47 PM PDT 24
Peak memory 210068 kb
Host smart-fe68a30f-017d-4482-b0d5-bac7cc81bdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031464833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1031464833
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2983515010
Short name T748
Test name
Test status
Simulation time 25118488 ps
CPU time 0.85 seconds
Started Aug 10 04:54:46 PM PDT 24
Finished Aug 10 04:54:47 PM PDT 24
Peak memory 205888 kb
Host smart-ca319c7d-dfcd-444d-88c7-ac5ad93bbd33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983515010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2983515010
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2765335479
Short name T292
Test name
Test status
Simulation time 126605443 ps
CPU time 4.62 seconds
Started Aug 10 04:54:47 PM PDT 24
Finished Aug 10 04:54:51 PM PDT 24
Peak memory 213524 kb
Host smart-f2381769-7659-409a-99a2-6cab0136c0c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765335479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2765335479
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.398482189
Short name T683
Test name
Test status
Simulation time 267612880 ps
CPU time 3.68 seconds
Started Aug 10 04:54:45 PM PDT 24
Finished Aug 10 04:54:48 PM PDT 24
Peak memory 221804 kb
Host smart-aad060f2-3c47-4759-9b82-afe683ef3c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398482189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.398482189
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1287857669
Short name T85
Test name
Test status
Simulation time 64423195 ps
CPU time 3.61 seconds
Started Aug 10 04:54:45 PM PDT 24
Finished Aug 10 04:54:49 PM PDT 24
Peak memory 222284 kb
Host smart-6be49d38-aae4-4687-9691-faea9bb32a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287857669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1287857669
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2923941971
Short name T819
Test name
Test status
Simulation time 38782636 ps
CPU time 2.34 seconds
Started Aug 10 04:54:51 PM PDT 24
Finished Aug 10 04:54:53 PM PDT 24
Peak memory 222224 kb
Host smart-85fc0360-e3c6-4b1a-9d4f-87b127a9aaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923941971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2923941971
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2456647359
Short name T878
Test name
Test status
Simulation time 71655792 ps
CPU time 3.88 seconds
Started Aug 10 04:54:46 PM PDT 24
Finished Aug 10 04:54:50 PM PDT 24
Peak memory 219780 kb
Host smart-0c955810-e735-4ac5-a78a-f9f69bfad66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456647359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2456647359
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3810577020
Short name T83
Test name
Test status
Simulation time 509820035 ps
CPU time 16.28 seconds
Started Aug 10 04:54:51 PM PDT 24
Finished Aug 10 04:55:08 PM PDT 24
Peak memory 218080 kb
Host smart-dee4dfe2-8a7e-48b7-962e-e59451cf9c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810577020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3810577020
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.26237681
Short name T606
Test name
Test status
Simulation time 243839796 ps
CPU time 7.57 seconds
Started Aug 10 04:54:45 PM PDT 24
Finished Aug 10 04:54:53 PM PDT 24
Peak memory 208308 kb
Host smart-c328421f-1a20-4054-b5bb-b667578b7c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26237681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.26237681
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1702163458
Short name T622
Test name
Test status
Simulation time 329642672 ps
CPU time 5.15 seconds
Started Aug 10 04:54:46 PM PDT 24
Finished Aug 10 04:54:51 PM PDT 24
Peak memory 208860 kb
Host smart-9b2f8503-5093-404c-bed6-f892b1debcf0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702163458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1702163458
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.166650537
Short name T648
Test name
Test status
Simulation time 101866908 ps
CPU time 4.16 seconds
Started Aug 10 04:54:46 PM PDT 24
Finished Aug 10 04:54:50 PM PDT 24
Peak memory 206940 kb
Host smart-5a3ff3ef-6afc-481a-94b7-f76f88fb514d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166650537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.166650537
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2686137372
Short name T512
Test name
Test status
Simulation time 184890208 ps
CPU time 6.82 seconds
Started Aug 10 04:54:51 PM PDT 24
Finished Aug 10 04:54:58 PM PDT 24
Peak memory 208640 kb
Host smart-207367eb-2e12-4e78-92e4-0afb1e1d0bc6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686137372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2686137372
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1983526392
Short name T817
Test name
Test status
Simulation time 234358878 ps
CPU time 3.63 seconds
Started Aug 10 04:54:50 PM PDT 24
Finished Aug 10 04:54:54 PM PDT 24
Peak memory 209760 kb
Host smart-31a6d983-85bb-4fcb-9f5d-80883ce99fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983526392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1983526392
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1002669266
Short name T580
Test name
Test status
Simulation time 186198497 ps
CPU time 3.78 seconds
Started Aug 10 04:54:46 PM PDT 24
Finished Aug 10 04:54:49 PM PDT 24
Peak memory 207096 kb
Host smart-e2fb214e-19e8-4881-8095-6407d257104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002669266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1002669266
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.602659265
Short name T190
Test name
Test status
Simulation time 3216448396 ps
CPU time 39.76 seconds
Started Aug 10 04:54:47 PM PDT 24
Finished Aug 10 04:55:26 PM PDT 24
Peak memory 216464 kb
Host smart-58611765-8e79-40df-830f-a99491a1fd9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602659265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.602659265
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3019717011
Short name T157
Test name
Test status
Simulation time 522986129 ps
CPU time 10.26 seconds
Started Aug 10 04:54:46 PM PDT 24
Finished Aug 10 04:54:57 PM PDT 24
Peak memory 222808 kb
Host smart-cae5ca13-0919-487a-ac9f-2112bf9b8758
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019717011 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3019717011
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3887055867
Short name T673
Test name
Test status
Simulation time 5961497673 ps
CPU time 40.59 seconds
Started Aug 10 04:54:46 PM PDT 24
Finished Aug 10 04:55:27 PM PDT 24
Peak memory 208552 kb
Host smart-a1b607be-bf45-4f38-a378-b4856da6305a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887055867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3887055867
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3809390919
Short name T64
Test name
Test status
Simulation time 46090325 ps
CPU time 2.52 seconds
Started Aug 10 04:54:48 PM PDT 24
Finished Aug 10 04:54:51 PM PDT 24
Peak memory 210220 kb
Host smart-32fa318c-234b-4448-a3df-61aa12107890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809390919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3809390919
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2299934670
Short name T572
Test name
Test status
Simulation time 25043839 ps
CPU time 0.92 seconds
Started Aug 10 04:54:54 PM PDT 24
Finished Aug 10 04:54:55 PM PDT 24
Peak memory 206100 kb
Host smart-df4f5eb0-ba2f-499b-be67-3f81ffafa8d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299934670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2299934670
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3660261362
Short name T400
Test name
Test status
Simulation time 103760904 ps
CPU time 5.66 seconds
Started Aug 10 04:54:53 PM PDT 24
Finished Aug 10 04:54:59 PM PDT 24
Peak memory 214236 kb
Host smart-bf9af8cb-11bd-4289-9371-f396d14bd32f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660261362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3660261362
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1389430368
Short name T108
Test name
Test status
Simulation time 151636925 ps
CPU time 2.25 seconds
Started Aug 10 04:54:56 PM PDT 24
Finished Aug 10 04:54:58 PM PDT 24
Peak memory 208240 kb
Host smart-a799d0c5-719d-435b-9892-3e74ac62fe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389430368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1389430368
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3845372949
Short name T892
Test name
Test status
Simulation time 567675769 ps
CPU time 3.85 seconds
Started Aug 10 04:54:55 PM PDT 24
Finished Aug 10 04:54:59 PM PDT 24
Peak memory 214432 kb
Host smart-695d7ea7-98cf-4046-a8f4-7d194c5420fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845372949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3845372949
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1472200015
Short name T607
Test name
Test status
Simulation time 162077315 ps
CPU time 4.7 seconds
Started Aug 10 04:54:53 PM PDT 24
Finished Aug 10 04:54:58 PM PDT 24
Peak memory 220956 kb
Host smart-f5e03f9b-849c-41ac-8da2-be224a70e147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472200015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1472200015
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.712270656
Short name T65
Test name
Test status
Simulation time 326660189 ps
CPU time 4.05 seconds
Started Aug 10 04:54:53 PM PDT 24
Finished Aug 10 04:54:58 PM PDT 24
Peak memory 216236 kb
Host smart-3a758eff-dabe-4bb1-a0f9-83d793f6bf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712270656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.712270656
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2700395968
Short name T884
Test name
Test status
Simulation time 864951412 ps
CPU time 7.14 seconds
Started Aug 10 04:54:54 PM PDT 24
Finished Aug 10 04:55:01 PM PDT 24
Peak memory 218084 kb
Host smart-dfe163a7-b333-4163-8630-84e9b5762037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700395968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2700395968
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.4064565985
Short name T612
Test name
Test status
Simulation time 115692733 ps
CPU time 2.68 seconds
Started Aug 10 04:54:55 PM PDT 24
Finished Aug 10 04:54:58 PM PDT 24
Peak memory 207084 kb
Host smart-d7d14e5a-c36c-4e1c-bbd6-bfc3253e0281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064565985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.4064565985
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.515166213
Short name T616
Test name
Test status
Simulation time 194740906 ps
CPU time 2.7 seconds
Started Aug 10 04:54:53 PM PDT 24
Finished Aug 10 04:54:56 PM PDT 24
Peak memory 206812 kb
Host smart-2a57a4ac-dbb4-4cc5-abef-1420017bd495
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515166213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.515166213
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2674585517
Short name T608
Test name
Test status
Simulation time 50557474 ps
CPU time 2.82 seconds
Started Aug 10 04:54:56 PM PDT 24
Finished Aug 10 04:54:59 PM PDT 24
Peak memory 206912 kb
Host smart-2429f7c1-92ee-4566-a69e-c67313ea1126
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674585517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2674585517
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1662437790
Short name T773
Test name
Test status
Simulation time 285736877 ps
CPU time 3.42 seconds
Started Aug 10 04:54:55 PM PDT 24
Finished Aug 10 04:54:59 PM PDT 24
Peak memory 208668 kb
Host smart-3ea0be4f-8f1b-4402-8503-5de65d936840
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662437790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1662437790
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2248706687
Short name T286
Test name
Test status
Simulation time 135245956 ps
CPU time 2.21 seconds
Started Aug 10 04:54:55 PM PDT 24
Finished Aug 10 04:54:57 PM PDT 24
Peak memory 210260 kb
Host smart-f95234e0-885a-4c3a-b40f-cf76218d1bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248706687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2248706687
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1342717071
Short name T17
Test name
Test status
Simulation time 52289326 ps
CPU time 2.17 seconds
Started Aug 10 04:54:53 PM PDT 24
Finished Aug 10 04:54:55 PM PDT 24
Peak memory 206624 kb
Host smart-3c176f37-b6ad-4f58-9642-2ae5800357fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342717071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1342717071
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2365839038
Short name T270
Test name
Test status
Simulation time 664393688 ps
CPU time 5.82 seconds
Started Aug 10 04:54:53 PM PDT 24
Finished Aug 10 04:54:59 PM PDT 24
Peak memory 210288 kb
Host smart-d1226d43-e6a8-4897-94d6-2fcb98c50d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365839038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2365839038
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1020416768
Short name T868
Test name
Test status
Simulation time 625269090 ps
CPU time 6.83 seconds
Started Aug 10 04:54:52 PM PDT 24
Finished Aug 10 04:54:59 PM PDT 24
Peak memory 210396 kb
Host smart-47ae98d1-cfaa-45a3-b562-da9d4efdb4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020416768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1020416768
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.271730965
Short name T557
Test name
Test status
Simulation time 22658432 ps
CPU time 0.9 seconds
Started Aug 10 04:55:04 PM PDT 24
Finished Aug 10 04:55:05 PM PDT 24
Peak memory 205960 kb
Host smart-aae61535-4114-4bd3-86f4-a6ece34c00b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271730965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.271730965
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.61881326
Short name T913
Test name
Test status
Simulation time 2628506997 ps
CPU time 17 seconds
Started Aug 10 04:54:57 PM PDT 24
Finished Aug 10 04:55:15 PM PDT 24
Peak memory 210164 kb
Host smart-1e8763af-7b79-4458-b58e-38def2a588ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61881326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.61881326
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3911246630
Short name T49
Test name
Test status
Simulation time 25311273 ps
CPU time 1.8 seconds
Started Aug 10 04:55:03 PM PDT 24
Finished Aug 10 04:55:05 PM PDT 24
Peak memory 214352 kb
Host smart-a3d93d87-072a-4811-b744-505fcea095c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911246630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3911246630
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.267656443
Short name T816
Test name
Test status
Simulation time 424575474 ps
CPU time 3.7 seconds
Started Aug 10 04:55:04 PM PDT 24
Finished Aug 10 04:55:08 PM PDT 24
Peak memory 214160 kb
Host smart-4272b277-e804-4922-a775-e3f6123c7b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267656443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.267656443
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4025842711
Short name T729
Test name
Test status
Simulation time 66456067 ps
CPU time 1.96 seconds
Started Aug 10 04:54:53 PM PDT 24
Finished Aug 10 04:54:55 PM PDT 24
Peak memory 219724 kb
Host smart-3039a0b5-659b-47c7-8975-d30fa7459df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025842711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4025842711
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_sideload.658451771
Short name T451
Test name
Test status
Simulation time 559933513 ps
CPU time 2.73 seconds
Started Aug 10 04:54:58 PM PDT 24
Finished Aug 10 04:55:01 PM PDT 24
Peak memory 208756 kb
Host smart-810d9b60-2f24-41d2-930d-bb1d342cdc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658451771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.658451771
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.40349314
Short name T581
Test name
Test status
Simulation time 143332589 ps
CPU time 4.54 seconds
Started Aug 10 04:54:55 PM PDT 24
Finished Aug 10 04:55:00 PM PDT 24
Peak memory 206884 kb
Host smart-7b6bac39-35ef-40fe-b590-a5c5eb3def11
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40349314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.40349314
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2776665469
Short name T800
Test name
Test status
Simulation time 290619799 ps
CPU time 3.1 seconds
Started Aug 10 04:54:54 PM PDT 24
Finished Aug 10 04:54:57 PM PDT 24
Peak memory 206856 kb
Host smart-d0142deb-0d85-4ab2-b1e1-7cd0928aeba6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776665469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2776665469
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2954571755
Short name T353
Test name
Test status
Simulation time 425513344 ps
CPU time 4.54 seconds
Started Aug 10 04:54:54 PM PDT 24
Finished Aug 10 04:54:59 PM PDT 24
Peak memory 206848 kb
Host smart-feb582b8-4e22-45a4-8a9d-5d80a5125da7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954571755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2954571755
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1008785025
Short name T266
Test name
Test status
Simulation time 466806723 ps
CPU time 4.59 seconds
Started Aug 10 04:55:07 PM PDT 24
Finished Aug 10 04:55:12 PM PDT 24
Peak memory 214200 kb
Host smart-0b1dfa62-9cfa-423d-97fc-8b2d87f380b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008785025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1008785025
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.32774432
Short name T81
Test name
Test status
Simulation time 76426375 ps
CPU time 2.45 seconds
Started Aug 10 04:54:54 PM PDT 24
Finished Aug 10 04:54:56 PM PDT 24
Peak memory 206744 kb
Host smart-4ca43997-c319-43cd-8275-016101db5e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32774432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.32774432
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3385723003
Short name T652
Test name
Test status
Simulation time 255939003 ps
CPU time 5.85 seconds
Started Aug 10 04:55:03 PM PDT 24
Finished Aug 10 04:55:09 PM PDT 24
Peak memory 215000 kb
Host smart-08502271-832e-4492-908e-eb235baf5fa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385723003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3385723003
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.4194427279
Short name T715
Test name
Test status
Simulation time 62500986 ps
CPU time 3.76 seconds
Started Aug 10 04:54:54 PM PDT 24
Finished Aug 10 04:54:58 PM PDT 24
Peak memory 207592 kb
Host smart-5020bc3e-6bf7-4196-8d94-3d8700340881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194427279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.4194427279
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.434204515
Short name T629
Test name
Test status
Simulation time 52669230 ps
CPU time 2.58 seconds
Started Aug 10 04:55:05 PM PDT 24
Finished Aug 10 04:55:08 PM PDT 24
Peak memory 210264 kb
Host smart-315f0feb-7b8e-49bd-82bf-e31fb4bf54af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434204515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.434204515
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3384136210
Short name T560
Test name
Test status
Simulation time 15396977 ps
CPU time 0.81 seconds
Started Aug 10 04:55:08 PM PDT 24
Finished Aug 10 04:55:09 PM PDT 24
Peak memory 205892 kb
Host smart-efff21a7-b4da-4421-bc3d-1d3f7719a7e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384136210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3384136210
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.567353970
Short name T280
Test name
Test status
Simulation time 119205186 ps
CPU time 4.62 seconds
Started Aug 10 04:55:06 PM PDT 24
Finished Aug 10 04:55:11 PM PDT 24
Peak memory 222388 kb
Host smart-d345f0e4-1ddf-4224-8462-0a2ecd1a460b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567353970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.567353970
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.284260701
Short name T19
Test name
Test status
Simulation time 232713434 ps
CPU time 3.65 seconds
Started Aug 10 04:55:05 PM PDT 24
Finished Aug 10 04:55:08 PM PDT 24
Peak memory 222548 kb
Host smart-a932500d-be17-4bf9-a363-cb5c75425e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284260701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.284260701
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3494763126
Short name T690
Test name
Test status
Simulation time 22471270 ps
CPU time 1.61 seconds
Started Aug 10 04:55:06 PM PDT 24
Finished Aug 10 04:55:07 PM PDT 24
Peak memory 207368 kb
Host smart-2dc3f62b-f029-4dd6-9d51-4765a54d20b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494763126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3494763126
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.4094103964
Short name T850
Test name
Test status
Simulation time 133587547 ps
CPU time 3.9 seconds
Started Aug 10 04:55:06 PM PDT 24
Finished Aug 10 04:55:10 PM PDT 24
Peak memory 220240 kb
Host smart-c089368f-ffef-41a1-a9d8-55ef270728d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094103964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.4094103964
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2999362328
Short name T903
Test name
Test status
Simulation time 302406107 ps
CPU time 3.91 seconds
Started Aug 10 04:55:06 PM PDT 24
Finished Aug 10 04:55:10 PM PDT 24
Peak memory 209272 kb
Host smart-3b4153c1-f86c-42aa-9981-9f8524437809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999362328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2999362328
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.4083479400
Short name T231
Test name
Test status
Simulation time 135760496 ps
CPU time 5.25 seconds
Started Aug 10 04:55:05 PM PDT 24
Finished Aug 10 04:55:10 PM PDT 24
Peak memory 209148 kb
Host smart-7642b983-c64a-48ed-8d12-15273aecb864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083479400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.4083479400
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.428384364
Short name T441
Test name
Test status
Simulation time 308923139 ps
CPU time 4.03 seconds
Started Aug 10 04:55:04 PM PDT 24
Finished Aug 10 04:55:08 PM PDT 24
Peak memory 208492 kb
Host smart-1ef6d8d2-7dab-48d0-9cdf-b4584273b183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428384364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.428384364
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3474900692
Short name T679
Test name
Test status
Simulation time 134783302 ps
CPU time 4.38 seconds
Started Aug 10 04:55:06 PM PDT 24
Finished Aug 10 04:55:10 PM PDT 24
Peak memory 208660 kb
Host smart-3031bd24-1bc0-474b-865a-d6354731c133
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474900692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3474900692
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2384355291
Short name T790
Test name
Test status
Simulation time 196674110 ps
CPU time 2.66 seconds
Started Aug 10 04:55:06 PM PDT 24
Finished Aug 10 04:55:09 PM PDT 24
Peak memory 207048 kb
Host smart-99e28fe0-cff8-4c7e-b658-c63c55398ba3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384355291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2384355291
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3373107748
Short name T461
Test name
Test status
Simulation time 67798140 ps
CPU time 1.73 seconds
Started Aug 10 04:55:06 PM PDT 24
Finished Aug 10 04:55:08 PM PDT 24
Peak memory 206840 kb
Host smart-7beca6ac-c4b3-4e75-adea-623625f142a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373107748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3373107748
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3521261068
Short name T486
Test name
Test status
Simulation time 68368751 ps
CPU time 2.48 seconds
Started Aug 10 04:55:07 PM PDT 24
Finished Aug 10 04:55:09 PM PDT 24
Peak memory 209392 kb
Host smart-56e3e2a5-7eda-4dcf-8dc4-87ff408e3e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521261068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3521261068
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1552199882
Short name T425
Test name
Test status
Simulation time 142927154 ps
CPU time 2.08 seconds
Started Aug 10 04:55:05 PM PDT 24
Finished Aug 10 04:55:07 PM PDT 24
Peak memory 207888 kb
Host smart-bba702ea-0bbc-45d9-b06e-401e223df307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552199882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1552199882
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3023505889
Short name T899
Test name
Test status
Simulation time 1911355377 ps
CPU time 25.69 seconds
Started Aug 10 04:55:07 PM PDT 24
Finished Aug 10 04:55:33 PM PDT 24
Peak memory 215512 kb
Host smart-858f3879-dad5-4bca-963a-f06ee39918a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023505889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3023505889
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.461364243
Short name T873
Test name
Test status
Simulation time 1302233351 ps
CPU time 18.52 seconds
Started Aug 10 04:55:04 PM PDT 24
Finished Aug 10 04:55:23 PM PDT 24
Peak memory 222436 kb
Host smart-15bbe4e0-0be1-48c5-89f0-3b1593ccfc0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461364243 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.461364243
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2792836338
Short name T26
Test name
Test status
Simulation time 167024430 ps
CPU time 2.95 seconds
Started Aug 10 04:55:04 PM PDT 24
Finished Aug 10 04:55:07 PM PDT 24
Peak memory 218228 kb
Host smart-bcd4900f-fdcb-4d82-845a-79b64fdc8794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792836338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2792836338
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3181388032
Short name T34
Test name
Test status
Simulation time 71544017 ps
CPU time 2.09 seconds
Started Aug 10 04:55:05 PM PDT 24
Finished Aug 10 04:55:07 PM PDT 24
Peak memory 209868 kb
Host smart-154de11f-a5c0-4aa8-b7ce-7c575d81cb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181388032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3181388032
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1020821499
Short name T415
Test name
Test status
Simulation time 133907316 ps
CPU time 0.9 seconds
Started Aug 10 04:55:14 PM PDT 24
Finished Aug 10 04:55:15 PM PDT 24
Peak memory 205836 kb
Host smart-2e2dfb67-9aa4-4cbc-8a29-b50ce0af9c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020821499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1020821499
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3187140802
Short name T405
Test name
Test status
Simulation time 328707712 ps
CPU time 16.1 seconds
Started Aug 10 04:55:06 PM PDT 24
Finished Aug 10 04:55:22 PM PDT 24
Peak memory 214640 kb
Host smart-d93466fc-0d8c-43ca-b473-1e102a880735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3187140802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3187140802
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.899764083
Short name T505
Test name
Test status
Simulation time 1074895817 ps
CPU time 5.77 seconds
Started Aug 10 04:55:04 PM PDT 24
Finished Aug 10 04:55:10 PM PDT 24
Peak memory 221624 kb
Host smart-1222a561-10f6-4739-bc2c-e6ffacfd126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899764083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.899764083
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2840713233
Short name T780
Test name
Test status
Simulation time 64327830 ps
CPU time 2.57 seconds
Started Aug 10 04:55:05 PM PDT 24
Finished Aug 10 04:55:08 PM PDT 24
Peak memory 207512 kb
Host smart-632c9b28-55b4-40f4-ac63-60fa37bdf2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840713233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2840713233
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4165128310
Short name T621
Test name
Test status
Simulation time 138752230 ps
CPU time 1.96 seconds
Started Aug 10 04:55:06 PM PDT 24
Finished Aug 10 04:55:08 PM PDT 24
Peak memory 222344 kb
Host smart-838b5b20-21ea-4eee-8aaa-962529bddf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165128310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4165128310
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3836115617
Short name T218
Test name
Test status
Simulation time 257921949 ps
CPU time 3.51 seconds
Started Aug 10 04:55:05 PM PDT 24
Finished Aug 10 04:55:09 PM PDT 24
Peak memory 214348 kb
Host smart-fccffef1-0107-41f2-b306-16b0cff23d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836115617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3836115617
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3999861617
Short name T344
Test name
Test status
Simulation time 1044224932 ps
CPU time 9.28 seconds
Started Aug 10 04:55:05 PM PDT 24
Finished Aug 10 04:55:14 PM PDT 24
Peak memory 214300 kb
Host smart-45018632-4771-4dc2-b99b-d6b1f16b9736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999861617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3999861617
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.66762597
Short name T724
Test name
Test status
Simulation time 5404264339 ps
CPU time 34.07 seconds
Started Aug 10 04:55:03 PM PDT 24
Finished Aug 10 04:55:37 PM PDT 24
Peak memory 208132 kb
Host smart-5eaac415-d3bb-4e69-8636-fe0b5ba97931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66762597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.66762597
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.485641724
Short name T311
Test name
Test status
Simulation time 1017828540 ps
CPU time 3.67 seconds
Started Aug 10 04:55:07 PM PDT 24
Finished Aug 10 04:55:10 PM PDT 24
Peak memory 208628 kb
Host smart-6da3d7a1-086f-4ca9-8caa-8f1339bd8420
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485641724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.485641724
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1743591810
Short name T810
Test name
Test status
Simulation time 171669236 ps
CPU time 4.25 seconds
Started Aug 10 04:55:06 PM PDT 24
Finished Aug 10 04:55:10 PM PDT 24
Peak memory 208836 kb
Host smart-eb97b7fa-05e8-4660-8ec7-e6bcd9df5015
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743591810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1743591810
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3232542562
Short name T646
Test name
Test status
Simulation time 26905825 ps
CPU time 1.87 seconds
Started Aug 10 04:55:04 PM PDT 24
Finished Aug 10 04:55:06 PM PDT 24
Peak memory 206800 kb
Host smart-22fc89cc-7033-49a4-aebf-90479b1f2879
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232542562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3232542562
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2781112595
Short name T568
Test name
Test status
Simulation time 127584949 ps
CPU time 1.95 seconds
Started Aug 10 04:55:04 PM PDT 24
Finished Aug 10 04:55:07 PM PDT 24
Peak memory 207188 kb
Host smart-f7ed142a-1245-45cc-bea9-dad9dc4ff197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781112595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2781112595
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.808422464
Short name T435
Test name
Test status
Simulation time 217691266 ps
CPU time 4.08 seconds
Started Aug 10 04:55:06 PM PDT 24
Finished Aug 10 04:55:10 PM PDT 24
Peak memory 206724 kb
Host smart-9e569edd-3986-4ae8-b7e0-3f49c4a64ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808422464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.808422464
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2791721112
Short name T52
Test name
Test status
Simulation time 1554794827 ps
CPU time 13.47 seconds
Started Aug 10 04:55:14 PM PDT 24
Finished Aug 10 04:55:28 PM PDT 24
Peak memory 222580 kb
Host smart-9b18e780-66f6-462e-884d-be5e6514f864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791721112 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2791721112
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.516807041
Short name T364
Test name
Test status
Simulation time 135647706 ps
CPU time 3.45 seconds
Started Aug 10 04:55:03 PM PDT 24
Finished Aug 10 04:55:07 PM PDT 24
Peak memory 209400 kb
Host smart-44f424c5-44d3-4fdb-9137-d1ce508f7848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516807041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.516807041
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2275278274
Short name T378
Test name
Test status
Simulation time 29057421 ps
CPU time 1.74 seconds
Started Aug 10 04:55:16 PM PDT 24
Finished Aug 10 04:55:18 PM PDT 24
Peak memory 208328 kb
Host smart-8a2b30b7-a69a-4028-9ce7-17cf42e0f23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275278274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2275278274
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2700158049
Short name T849
Test name
Test status
Simulation time 12095649 ps
CPU time 0.78 seconds
Started Aug 10 04:51:24 PM PDT 24
Finished Aug 10 04:51:25 PM PDT 24
Peak memory 205900 kb
Host smart-e1bee245-5dd9-4b35-8c6e-568f85a21784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700158049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2700158049
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3605823263
Short name T782
Test name
Test status
Simulation time 217489765 ps
CPU time 3.01 seconds
Started Aug 10 04:51:13 PM PDT 24
Finished Aug 10 04:51:16 PM PDT 24
Peak memory 215172 kb
Host smart-28bd4ecc-32ae-44e5-ab19-36d32a6ebcea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605823263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3605823263
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2027027010
Short name T787
Test name
Test status
Simulation time 41837096 ps
CPU time 2.75 seconds
Started Aug 10 04:51:14 PM PDT 24
Finished Aug 10 04:51:17 PM PDT 24
Peak memory 210392 kb
Host smart-cf72b739-9763-4bbd-874b-531c5ff43bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027027010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2027027010
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3969588775
Short name T282
Test name
Test status
Simulation time 30941316 ps
CPU time 2.26 seconds
Started Aug 10 04:51:20 PM PDT 24
Finished Aug 10 04:51:23 PM PDT 24
Peak memory 214332 kb
Host smart-14907ed0-c299-4b2b-a51c-d3d7be1e80ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969588775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3969588775
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2990041028
Short name T659
Test name
Test status
Simulation time 273643569 ps
CPU time 2.72 seconds
Started Aug 10 04:51:24 PM PDT 24
Finished Aug 10 04:51:26 PM PDT 24
Peak memory 214892 kb
Host smart-696e2b95-9a7a-4f9b-beef-f81dd50a8302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990041028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2990041028
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.958301604
Short name T310
Test name
Test status
Simulation time 146041274 ps
CPU time 3.07 seconds
Started Aug 10 04:51:11 PM PDT 24
Finished Aug 10 04:51:14 PM PDT 24
Peak memory 214380 kb
Host smart-5afbef41-909d-4fb1-adcf-65b102f3c5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958301604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.958301604
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3120432785
Short name T482
Test name
Test status
Simulation time 57350841 ps
CPU time 3.36 seconds
Started Aug 10 04:51:11 PM PDT 24
Finished Aug 10 04:51:15 PM PDT 24
Peak memory 209116 kb
Host smart-d16130d9-5000-4408-b9db-025a53ee3e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120432785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3120432785
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.456675111
Short name T656
Test name
Test status
Simulation time 103935921 ps
CPU time 1.94 seconds
Started Aug 10 04:51:11 PM PDT 24
Finished Aug 10 04:51:13 PM PDT 24
Peak memory 208480 kb
Host smart-5dddf389-b8c1-4a17-8109-965be37536f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456675111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.456675111
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1905492418
Short name T645
Test name
Test status
Simulation time 47455397 ps
CPU time 2.84 seconds
Started Aug 10 04:51:11 PM PDT 24
Finished Aug 10 04:51:14 PM PDT 24
Peak memory 208652 kb
Host smart-c741a274-085a-444b-bd5a-b418d605e8f4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905492418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1905492418
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1741024958
Short name T823
Test name
Test status
Simulation time 27464951 ps
CPU time 1.77 seconds
Started Aug 10 04:51:12 PM PDT 24
Finished Aug 10 04:51:13 PM PDT 24
Peak memory 206808 kb
Host smart-7d9398e5-9b1d-4a5e-b66d-1f86359518f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741024958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1741024958
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2894693147
Short name T563
Test name
Test status
Simulation time 140244219 ps
CPU time 5.64 seconds
Started Aug 10 04:51:12 PM PDT 24
Finished Aug 10 04:51:17 PM PDT 24
Peak memory 208924 kb
Host smart-156c67ec-3420-4982-b757-cce59bb26171
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894693147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2894693147
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4043160561
Short name T586
Test name
Test status
Simulation time 147243535 ps
CPU time 3.18 seconds
Started Aug 10 04:51:20 PM PDT 24
Finished Aug 10 04:51:23 PM PDT 24
Peak memory 209936 kb
Host smart-20870e82-949a-4684-91ed-1b09bc5e8af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043160561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4043160561
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.971871147
Short name T818
Test name
Test status
Simulation time 135510545 ps
CPU time 4.83 seconds
Started Aug 10 04:51:03 PM PDT 24
Finished Aug 10 04:51:08 PM PDT 24
Peak memory 208552 kb
Host smart-da1d5bde-8725-40a6-8018-dee2b3de68a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971871147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.971871147
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1446167260
Short name T498
Test name
Test status
Simulation time 6882292296 ps
CPU time 82.53 seconds
Started Aug 10 04:51:12 PM PDT 24
Finished Aug 10 04:52:34 PM PDT 24
Peak memory 221500 kb
Host smart-8cd8c5ac-fe83-4d26-80cd-576e5dc41330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446167260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1446167260
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1473705455
Short name T480
Test name
Test status
Simulation time 36986753 ps
CPU time 0.84 seconds
Started Aug 10 04:55:15 PM PDT 24
Finished Aug 10 04:55:16 PM PDT 24
Peak memory 206004 kb
Host smart-f8629915-4303-49af-9658-449f57033187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473705455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1473705455
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3921546599
Short name T391
Test name
Test status
Simulation time 53690946 ps
CPU time 2.86 seconds
Started Aug 10 04:55:15 PM PDT 24
Finished Aug 10 04:55:18 PM PDT 24
Peak memory 208028 kb
Host smart-ae70b63b-b9e7-47a7-b618-abc001acff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921546599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3921546599
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2170887388
Short name T322
Test name
Test status
Simulation time 98764274 ps
CPU time 2.75 seconds
Started Aug 10 04:55:14 PM PDT 24
Finished Aug 10 04:55:17 PM PDT 24
Peak memory 214228 kb
Host smart-5205bc44-744e-4f7b-a4b1-9be12d4e21f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170887388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2170887388
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.604067245
Short name T55
Test name
Test status
Simulation time 212789866 ps
CPU time 4.12 seconds
Started Aug 10 04:55:16 PM PDT 24
Finished Aug 10 04:55:20 PM PDT 24
Peak memory 220432 kb
Host smart-066c93df-1cbe-483b-aa9b-b76d7f493668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604067245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.604067245
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3252568968
Short name T46
Test name
Test status
Simulation time 245707811 ps
CPU time 2.42 seconds
Started Aug 10 04:55:16 PM PDT 24
Finished Aug 10 04:55:19 PM PDT 24
Peak memory 215900 kb
Host smart-c4023785-8ccd-4241-a507-fa292210b0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252568968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3252568968
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1841484794
Short name T730
Test name
Test status
Simulation time 251012208 ps
CPU time 3.14 seconds
Started Aug 10 04:55:16 PM PDT 24
Finished Aug 10 04:55:19 PM PDT 24
Peak memory 218248 kb
Host smart-2fe737fb-1d46-4a46-9252-5c390de417bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841484794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1841484794
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.4180887832
Short name T654
Test name
Test status
Simulation time 140826124 ps
CPU time 2.91 seconds
Started Aug 10 04:55:19 PM PDT 24
Finished Aug 10 04:55:22 PM PDT 24
Peak memory 206824 kb
Host smart-0b45bcd9-c3bf-48f3-9320-e9da74b46f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180887832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.4180887832
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.366185247
Short name T745
Test name
Test status
Simulation time 923296246 ps
CPU time 6.54 seconds
Started Aug 10 04:55:19 PM PDT 24
Finished Aug 10 04:55:25 PM PDT 24
Peak memory 207964 kb
Host smart-19abda2f-b5df-4187-a6a1-2eb7fe831c73
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366185247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.366185247
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3640172627
Short name T627
Test name
Test status
Simulation time 4058203944 ps
CPU time 45.03 seconds
Started Aug 10 04:55:14 PM PDT 24
Finished Aug 10 04:55:59 PM PDT 24
Peak memory 207932 kb
Host smart-aaba2030-a391-4efc-b373-144989431b6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640172627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3640172627
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.36157406
Short name T569
Test name
Test status
Simulation time 250568434 ps
CPU time 2.76 seconds
Started Aug 10 04:55:14 PM PDT 24
Finished Aug 10 04:55:17 PM PDT 24
Peak memory 206944 kb
Host smart-c4570549-e615-46b9-b4ef-d4c128b0b6b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36157406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.36157406
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1580375474
Short name T910
Test name
Test status
Simulation time 1627762830 ps
CPU time 16.02 seconds
Started Aug 10 04:55:13 PM PDT 24
Finished Aug 10 04:55:29 PM PDT 24
Peak memory 214180 kb
Host smart-827c6d56-4990-4d5f-9aae-b2c9ff64776b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580375474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1580375474
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1294538113
Short name T495
Test name
Test status
Simulation time 166577610 ps
CPU time 2.27 seconds
Started Aug 10 04:55:14 PM PDT 24
Finished Aug 10 04:55:16 PM PDT 24
Peak memory 208184 kb
Host smart-bd035447-acab-4000-b5e6-a5aacdd43c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294538113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1294538113
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2000305236
Short name T675
Test name
Test status
Simulation time 113061088 ps
CPU time 3.64 seconds
Started Aug 10 04:55:16 PM PDT 24
Finished Aug 10 04:55:19 PM PDT 24
Peak memory 214300 kb
Host smart-4da4bb46-1dd8-4831-9e7a-818b3390ff82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000305236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2000305236
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1277528291
Short name T437
Test name
Test status
Simulation time 363664815 ps
CPU time 4.27 seconds
Started Aug 10 04:55:17 PM PDT 24
Finished Aug 10 04:55:21 PM PDT 24
Peak memory 210260 kb
Host smart-2ccd1d71-8619-449a-acf4-fbb34d6fcbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277528291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1277528291
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3044385050
Short name T736
Test name
Test status
Simulation time 9845696 ps
CPU time 0.71 seconds
Started Aug 10 04:55:27 PM PDT 24
Finished Aug 10 04:55:28 PM PDT 24
Peak memory 205912 kb
Host smart-c86ceef4-3423-4330-83b1-a05d57f7398c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044385050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3044385050
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.4013968365
Short name T247
Test name
Test status
Simulation time 225053720 ps
CPU time 4.51 seconds
Started Aug 10 04:55:15 PM PDT 24
Finished Aug 10 04:55:20 PM PDT 24
Peak memory 222388 kb
Host smart-73c1cd48-6ff6-4eba-b253-044e101a9ab2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013968365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.4013968365
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1758343224
Short name T829
Test name
Test status
Simulation time 404353964 ps
CPU time 6.56 seconds
Started Aug 10 04:55:17 PM PDT 24
Finished Aug 10 04:55:24 PM PDT 24
Peak memory 209212 kb
Host smart-0806f6aa-7a82-49f9-9f60-851b83092582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758343224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1758343224
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.4061420502
Short name T98
Test name
Test status
Simulation time 293738977 ps
CPU time 7.62 seconds
Started Aug 10 04:55:15 PM PDT 24
Finished Aug 10 04:55:22 PM PDT 24
Peak memory 222132 kb
Host smart-93ebca99-c24b-4fe3-8456-f368e263dca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061420502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.4061420502
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3470055053
Short name T321
Test name
Test status
Simulation time 111042327 ps
CPU time 5.03 seconds
Started Aug 10 04:55:13 PM PDT 24
Finished Aug 10 04:55:19 PM PDT 24
Peak memory 222372 kb
Host smart-d2e160a2-3647-4daa-8208-aee4681b3664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470055053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3470055053
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.4237007212
Short name T51
Test name
Test status
Simulation time 242688144 ps
CPU time 1.9 seconds
Started Aug 10 04:55:17 PM PDT 24
Finished Aug 10 04:55:19 PM PDT 24
Peak memory 214240 kb
Host smart-c65e8ab5-6a32-4e22-8637-ff3ab4090d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237007212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.4237007212
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.35479353
Short name T528
Test name
Test status
Simulation time 187722308 ps
CPU time 5.9 seconds
Started Aug 10 04:55:16 PM PDT 24
Finished Aug 10 04:55:22 PM PDT 24
Peak memory 207344 kb
Host smart-13567f73-b046-4e5a-af49-ef93dc3c3149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35479353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.35479353
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1266974664
Short name T809
Test name
Test status
Simulation time 249908283 ps
CPU time 3.22 seconds
Started Aug 10 04:55:14 PM PDT 24
Finished Aug 10 04:55:18 PM PDT 24
Peak memory 208692 kb
Host smart-11613d58-cf7f-4909-a753-7414cc05a3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266974664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1266974664
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3585925455
Short name T262
Test name
Test status
Simulation time 48941297 ps
CPU time 2.19 seconds
Started Aug 10 04:55:17 PM PDT 24
Finished Aug 10 04:55:19 PM PDT 24
Peak memory 208432 kb
Host smart-2808c16c-8165-4efb-9ec9-f143e44fccde
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585925455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3585925455
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3507846458
Short name T82
Test name
Test status
Simulation time 219636937 ps
CPU time 2.38 seconds
Started Aug 10 04:55:17 PM PDT 24
Finished Aug 10 04:55:19 PM PDT 24
Peak memory 207000 kb
Host smart-5cbc5c5a-1d94-4a9b-87d6-1b7a934619cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507846458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3507846458
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1659893076
Short name T550
Test name
Test status
Simulation time 82440235 ps
CPU time 3.27 seconds
Started Aug 10 04:55:15 PM PDT 24
Finished Aug 10 04:55:19 PM PDT 24
Peak memory 208192 kb
Host smart-e495e3eb-b0c6-4979-93c5-ba7f0a9780ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659893076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1659893076
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.155992470
Short name T348
Test name
Test status
Simulation time 61232139 ps
CPU time 2.8 seconds
Started Aug 10 04:55:16 PM PDT 24
Finished Aug 10 04:55:19 PM PDT 24
Peak memory 207488 kb
Host smart-50b30e32-d3c3-4d37-a93d-21c24cc3b6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155992470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.155992470
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2935486309
Short name T409
Test name
Test status
Simulation time 329911878 ps
CPU time 8.18 seconds
Started Aug 10 04:55:14 PM PDT 24
Finished Aug 10 04:55:23 PM PDT 24
Peak memory 208064 kb
Host smart-4ee065cf-fa90-4d6f-906b-e1d07bef093c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935486309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2935486309
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2930299597
Short name T228
Test name
Test status
Simulation time 815134638 ps
CPU time 34.85 seconds
Started Aug 10 04:55:17 PM PDT 24
Finished Aug 10 04:55:52 PM PDT 24
Peak memory 222384 kb
Host smart-386ff38e-e01f-41a2-b239-02999ea84087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930299597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2930299597
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2794958649
Short name T178
Test name
Test status
Simulation time 2928513541 ps
CPU time 25.21 seconds
Started Aug 10 04:55:23 PM PDT 24
Finished Aug 10 04:55:48 PM PDT 24
Peak memory 222540 kb
Host smart-5547cb76-7814-4730-9416-946a9f46ecb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794958649 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2794958649
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1054558911
Short name T202
Test name
Test status
Simulation time 942671403 ps
CPU time 6.6 seconds
Started Aug 10 04:55:14 PM PDT 24
Finished Aug 10 04:55:21 PM PDT 24
Peak memory 218100 kb
Host smart-de9e1fc7-ebe2-4c99-87d9-d121b1970d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054558911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1054558911
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.544638914
Short name T60
Test name
Test status
Simulation time 215117168 ps
CPU time 3.23 seconds
Started Aug 10 04:55:16 PM PDT 24
Finished Aug 10 04:55:19 PM PDT 24
Peak memory 209856 kb
Host smart-c949de83-15bb-49af-8e71-b8e58e5dfb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544638914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.544638914
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2716163564
Short name T723
Test name
Test status
Simulation time 12355105 ps
CPU time 0.71 seconds
Started Aug 10 04:55:26 PM PDT 24
Finished Aug 10 04:55:27 PM PDT 24
Peak memory 205896 kb
Host smart-58311ceb-c3e7-46d8-886a-e5ce3de95115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716163564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2716163564
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2819830475
Short name T706
Test name
Test status
Simulation time 510521578 ps
CPU time 10.63 seconds
Started Aug 10 04:55:21 PM PDT 24
Finished Aug 10 04:55:32 PM PDT 24
Peak memory 209024 kb
Host smart-e3bc8a16-e77e-42e7-8748-ff4ea0526d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819830475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2819830475
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3583141059
Short name T694
Test name
Test status
Simulation time 22917837 ps
CPU time 1.66 seconds
Started Aug 10 04:55:23 PM PDT 24
Finished Aug 10 04:55:25 PM PDT 24
Peak memory 207664 kb
Host smart-f17c33cb-f205-4cc9-8f14-f98a702225f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583141059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3583141059
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3508782154
Short name T89
Test name
Test status
Simulation time 109904546 ps
CPU time 4.49 seconds
Started Aug 10 04:55:21 PM PDT 24
Finished Aug 10 04:55:26 PM PDT 24
Peak memory 209956 kb
Host smart-7e960a1a-9f7f-45c6-b13d-3a377d3ff640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508782154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3508782154
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1458855145
Short name T908
Test name
Test status
Simulation time 109836461 ps
CPU time 3.85 seconds
Started Aug 10 04:55:23 PM PDT 24
Finished Aug 10 04:55:27 PM PDT 24
Peak memory 222312 kb
Host smart-da8b936c-737a-40e1-80b2-01836ea4a9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458855145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1458855145
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.447703845
Short name T469
Test name
Test status
Simulation time 80011418 ps
CPU time 3.88 seconds
Started Aug 10 04:55:22 PM PDT 24
Finished Aug 10 04:55:26 PM PDT 24
Peak memory 217980 kb
Host smart-378efb0c-a2c3-4e3d-a9ac-b25c73a8b5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447703845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.447703845
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1551275855
Short name T233
Test name
Test status
Simulation time 283071593 ps
CPU time 3.6 seconds
Started Aug 10 04:55:24 PM PDT 24
Finished Aug 10 04:55:28 PM PDT 24
Peak memory 207272 kb
Host smart-03e3516b-c248-40da-8551-005750b562e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551275855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1551275855
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.584640606
Short name T631
Test name
Test status
Simulation time 487153858 ps
CPU time 3.62 seconds
Started Aug 10 04:55:23 PM PDT 24
Finished Aug 10 04:55:26 PM PDT 24
Peak memory 208372 kb
Host smart-a2ce82c7-aa8d-42ad-b49e-decd16c36d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584640606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.584640606
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.391072410
Short name T693
Test name
Test status
Simulation time 34186322 ps
CPU time 2.17 seconds
Started Aug 10 04:55:21 PM PDT 24
Finished Aug 10 04:55:23 PM PDT 24
Peak memory 206888 kb
Host smart-12d60767-1a25-45c5-a694-d626ec6a5e7a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391072410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.391072410
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1120125283
Short name T684
Test name
Test status
Simulation time 917317704 ps
CPU time 10.73 seconds
Started Aug 10 04:55:20 PM PDT 24
Finished Aug 10 04:55:31 PM PDT 24
Peak memory 206948 kb
Host smart-c08a2c4e-dd6c-48ff-861e-cfedb25c73aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120125283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1120125283
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1445024850
Short name T740
Test name
Test status
Simulation time 67827699 ps
CPU time 3.47 seconds
Started Aug 10 04:55:23 PM PDT 24
Finished Aug 10 04:55:27 PM PDT 24
Peak memory 206864 kb
Host smart-91980dd2-44a2-40d8-8e7d-81cdc7aeab22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445024850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1445024850
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3697844362
Short name T200
Test name
Test status
Simulation time 658466770 ps
CPU time 3.26 seconds
Started Aug 10 04:55:22 PM PDT 24
Finished Aug 10 04:55:25 PM PDT 24
Peak memory 209220 kb
Host smart-2b1bea8e-0b90-4262-808e-633c8a078337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697844362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3697844362
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2509642989
Short name T525
Test name
Test status
Simulation time 57100384 ps
CPU time 2.78 seconds
Started Aug 10 04:55:22 PM PDT 24
Finished Aug 10 04:55:25 PM PDT 24
Peak memory 208532 kb
Host smart-d9a2ba1d-c46f-4b0c-9ee2-dc1113186837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509642989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2509642989
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1688072203
Short name T217
Test name
Test status
Simulation time 46818798491 ps
CPU time 105.87 seconds
Started Aug 10 04:55:24 PM PDT 24
Finished Aug 10 04:57:10 PM PDT 24
Peak memory 217152 kb
Host smart-46f64b82-5f78-4056-af81-fa2626b7811d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688072203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1688072203
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3703209161
Short name T18
Test name
Test status
Simulation time 237050420 ps
CPU time 3.68 seconds
Started Aug 10 04:55:27 PM PDT 24
Finished Aug 10 04:55:31 PM PDT 24
Peak memory 208316 kb
Host smart-2190a132-284f-4988-a099-ec6933b869eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703209161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3703209161
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2847138243
Short name T537
Test name
Test status
Simulation time 4240672776 ps
CPU time 30.68 seconds
Started Aug 10 04:55:22 PM PDT 24
Finished Aug 10 04:55:53 PM PDT 24
Peak memory 211336 kb
Host smart-89cc77d4-71b5-43c3-8927-91cc2f127167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847138243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2847138243
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3043219826
Short name T721
Test name
Test status
Simulation time 13027549 ps
CPU time 0.91 seconds
Started Aug 10 04:55:36 PM PDT 24
Finished Aug 10 04:55:37 PM PDT 24
Peak memory 205944 kb
Host smart-f6eb885c-2c33-4d19-ae48-babbaf0505cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043219826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3043219826
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.846586046
Short name T674
Test name
Test status
Simulation time 35023670 ps
CPU time 2.26 seconds
Started Aug 10 04:55:22 PM PDT 24
Finished Aug 10 04:55:25 PM PDT 24
Peak memory 208184 kb
Host smart-0b76f4ee-3f3b-4cf3-9e49-f714824eecf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846586046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.846586046
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1791254934
Short name T88
Test name
Test status
Simulation time 945319756 ps
CPU time 26.85 seconds
Started Aug 10 04:55:23 PM PDT 24
Finished Aug 10 04:55:50 PM PDT 24
Peak memory 214416 kb
Host smart-55ca33d0-e418-4f25-89ca-29bfa74f37c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791254934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1791254934
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.258066343
Short name T281
Test name
Test status
Simulation time 264972247 ps
CPU time 2.82 seconds
Started Aug 10 04:55:25 PM PDT 24
Finished Aug 10 04:55:28 PM PDT 24
Peak memory 214168 kb
Host smart-9f000f2c-07f9-456e-9932-4f6ea7ca7e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258066343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.258066343
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.993408498
Short name T916
Test name
Test status
Simulation time 433109286 ps
CPU time 3.28 seconds
Started Aug 10 04:55:24 PM PDT 24
Finished Aug 10 04:55:27 PM PDT 24
Peak memory 206744 kb
Host smart-83748a6d-d48f-4e46-b94d-ba05cae2a477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993408498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.993408498
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3882744811
Short name T808
Test name
Test status
Simulation time 8967243746 ps
CPU time 54.03 seconds
Started Aug 10 04:55:26 PM PDT 24
Finished Aug 10 04:56:20 PM PDT 24
Peak memory 210192 kb
Host smart-bf1bc1dc-2e91-4272-b881-ac04be941f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882744811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3882744811
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3837329671
Short name T610
Test name
Test status
Simulation time 182807935 ps
CPU time 4.15 seconds
Started Aug 10 04:55:23 PM PDT 24
Finished Aug 10 04:55:27 PM PDT 24
Peak memory 206840 kb
Host smart-574e48bf-55ae-4af8-bc6b-27e099647ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837329671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3837329671
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.439479119
Short name T362
Test name
Test status
Simulation time 38608530 ps
CPU time 2.44 seconds
Started Aug 10 04:55:24 PM PDT 24
Finished Aug 10 04:55:27 PM PDT 24
Peak memory 207564 kb
Host smart-abe299ca-23c7-4944-9ee6-c24d266f4ac8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439479119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.439479119
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3414396683
Short name T870
Test name
Test status
Simulation time 24272292 ps
CPU time 1.84 seconds
Started Aug 10 04:55:24 PM PDT 24
Finished Aug 10 04:55:26 PM PDT 24
Peak memory 206868 kb
Host smart-89429e1e-e6d9-48af-883a-1dfb428e5cd5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414396683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3414396683
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.603683298
Short name T460
Test name
Test status
Simulation time 4345006136 ps
CPU time 57.03 seconds
Started Aug 10 04:55:22 PM PDT 24
Finished Aug 10 04:56:19 PM PDT 24
Peak memory 208528 kb
Host smart-417684c1-1857-4656-9052-8d9be17b43f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603683298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.603683298
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1146375296
Short name T522
Test name
Test status
Simulation time 86028747 ps
CPU time 3.38 seconds
Started Aug 10 04:55:26 PM PDT 24
Finished Aug 10 04:55:29 PM PDT 24
Peak memory 209380 kb
Host smart-4d31c804-9e11-4369-8f65-d5a498828b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146375296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1146375296
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1099685211
Short name T551
Test name
Test status
Simulation time 46925852 ps
CPU time 2.4 seconds
Started Aug 10 04:55:23 PM PDT 24
Finished Aug 10 04:55:26 PM PDT 24
Peak memory 206104 kb
Host smart-0a2f85de-d227-4b88-8387-ea4551bd2617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099685211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1099685211
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1183353507
Short name T628
Test name
Test status
Simulation time 7841006488 ps
CPU time 38.63 seconds
Started Aug 10 04:55:26 PM PDT 24
Finished Aug 10 04:56:04 PM PDT 24
Peak memory 218240 kb
Host smart-0080c87e-016b-4c81-85a1-fefb9d969cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183353507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1183353507
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.39914639
Short name T851
Test name
Test status
Simulation time 266721803 ps
CPU time 1.58 seconds
Started Aug 10 04:55:33 PM PDT 24
Finished Aug 10 04:55:35 PM PDT 24
Peak memory 209704 kb
Host smart-2cb4df3f-cf40-4dcc-9a0c-cae12c6c3490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39914639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.39914639
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3630543835
Short name T101
Test name
Test status
Simulation time 39105636 ps
CPU time 0.84 seconds
Started Aug 10 04:55:36 PM PDT 24
Finished Aug 10 04:55:37 PM PDT 24
Peak memory 205952 kb
Host smart-f1b2b8bf-950d-412e-b53c-9b060368e15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630543835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3630543835
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3106236847
Short name T183
Test name
Test status
Simulation time 114693406 ps
CPU time 6.22 seconds
Started Aug 10 04:55:33 PM PDT 24
Finished Aug 10 04:55:40 PM PDT 24
Peak memory 215612 kb
Host smart-f8172506-829f-4131-863c-4d99a1d8c17b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106236847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3106236847
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.764535980
Short name T31
Test name
Test status
Simulation time 226304703 ps
CPU time 3.08 seconds
Started Aug 10 04:55:34 PM PDT 24
Finished Aug 10 04:55:37 PM PDT 24
Peak memory 210072 kb
Host smart-42a51aa5-4293-42d9-8b22-66bd324f392c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764535980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.764535980
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1313892011
Short name T430
Test name
Test status
Simulation time 484501614 ps
CPU time 2.77 seconds
Started Aug 10 04:55:35 PM PDT 24
Finished Aug 10 04:55:38 PM PDT 24
Peak memory 206912 kb
Host smart-4b4ab5c0-9ea3-45c2-86b0-830c0d7d7f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313892011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1313892011
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2428355072
Short name T93
Test name
Test status
Simulation time 95643144 ps
CPU time 4.02 seconds
Started Aug 10 04:55:34 PM PDT 24
Finished Aug 10 04:55:38 PM PDT 24
Peak memory 214424 kb
Host smart-c6904857-6cd8-4706-8360-3230d945a6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428355072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2428355072
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2089438125
Short name T719
Test name
Test status
Simulation time 662984030 ps
CPU time 6.09 seconds
Started Aug 10 04:55:34 PM PDT 24
Finished Aug 10 04:55:41 PM PDT 24
Peak memory 214332 kb
Host smart-0014e52b-fbd5-41e2-9795-fe9a5a0aabd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089438125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2089438125
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1442608363
Short name T552
Test name
Test status
Simulation time 82968521 ps
CPU time 2.81 seconds
Started Aug 10 04:55:36 PM PDT 24
Finished Aug 10 04:55:39 PM PDT 24
Peak memory 220476 kb
Host smart-5b84ba8e-25f6-42fb-8b7b-98dd43f331a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442608363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1442608363
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2489690420
Short name T725
Test name
Test status
Simulation time 203027296 ps
CPU time 7.69 seconds
Started Aug 10 04:55:35 PM PDT 24
Finished Aug 10 04:55:43 PM PDT 24
Peak memory 214244 kb
Host smart-731c16fe-c111-4bb7-adef-22385c38b4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489690420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2489690420
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1216743038
Short name T805
Test name
Test status
Simulation time 41471803 ps
CPU time 1.75 seconds
Started Aug 10 04:55:36 PM PDT 24
Finished Aug 10 04:55:38 PM PDT 24
Peak memory 206800 kb
Host smart-616ba0b1-a157-4221-b69b-9ef8d3a25ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216743038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1216743038
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2359598764
Short name T726
Test name
Test status
Simulation time 136622607 ps
CPU time 2.68 seconds
Started Aug 10 04:55:34 PM PDT 24
Finished Aug 10 04:55:37 PM PDT 24
Peak memory 206884 kb
Host smart-1cba3f74-6c26-4032-9c2e-ac5f6a1fadc2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359598764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2359598764
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1291775711
Short name T411
Test name
Test status
Simulation time 347604942 ps
CPU time 4.2 seconds
Started Aug 10 04:55:35 PM PDT 24
Finished Aug 10 04:55:39 PM PDT 24
Peak memory 208440 kb
Host smart-5cb076fc-9378-44b2-a583-f1e4e374f65a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291775711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1291775711
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2659832400
Short name T507
Test name
Test status
Simulation time 61295510 ps
CPU time 3.23 seconds
Started Aug 10 04:55:35 PM PDT 24
Finished Aug 10 04:55:38 PM PDT 24
Peak memory 206808 kb
Host smart-f44bfffc-34a1-41cc-92f1-98c431df8714
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659832400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2659832400
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1398817794
Short name T639
Test name
Test status
Simulation time 35611205 ps
CPU time 1.96 seconds
Started Aug 10 04:55:34 PM PDT 24
Finished Aug 10 04:55:36 PM PDT 24
Peak memory 208448 kb
Host smart-fa3f9fd1-fe4e-441d-8c6a-0e95541aa360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398817794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1398817794
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3665153624
Short name T696
Test name
Test status
Simulation time 896694223 ps
CPU time 14.8 seconds
Started Aug 10 04:55:35 PM PDT 24
Finished Aug 10 04:55:50 PM PDT 24
Peak memory 208736 kb
Host smart-4c5fd3dc-f0aa-496e-b649-a7fb50577f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665153624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3665153624
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1980602828
Short name T894
Test name
Test status
Simulation time 3672920858 ps
CPU time 83.29 seconds
Started Aug 10 04:55:34 PM PDT 24
Finished Aug 10 04:56:58 PM PDT 24
Peak memory 222564 kb
Host smart-8d68534a-032a-46fc-a830-91ffa0a1d434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980602828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1980602828
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.599086118
Short name T886
Test name
Test status
Simulation time 270073453 ps
CPU time 5.56 seconds
Started Aug 10 04:55:35 PM PDT 24
Finished Aug 10 04:55:41 PM PDT 24
Peak memory 218020 kb
Host smart-4cf2ba60-64a1-4f6a-b076-76e832240a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599086118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.599086118
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2538223944
Short name T125
Test name
Test status
Simulation time 2208141121 ps
CPU time 9.2 seconds
Started Aug 10 04:55:34 PM PDT 24
Finished Aug 10 04:55:43 PM PDT 24
Peak memory 210852 kb
Host smart-3635e83a-c580-4c09-9c4b-283fe7912c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538223944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2538223944
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2496122158
Short name T605
Test name
Test status
Simulation time 44936844 ps
CPU time 0.76 seconds
Started Aug 10 04:55:48 PM PDT 24
Finished Aug 10 04:55:49 PM PDT 24
Peak memory 205880 kb
Host smart-0d983898-8222-4db3-a63b-1e00c5296dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496122158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2496122158
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3586198893
Short name T407
Test name
Test status
Simulation time 925484193 ps
CPU time 46.65 seconds
Started Aug 10 04:55:34 PM PDT 24
Finished Aug 10 04:56:21 PM PDT 24
Peak memory 214180 kb
Host smart-7bbf8000-f685-4949-ae08-8cd4d849fbe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586198893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3586198893
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4267121900
Short name T38
Test name
Test status
Simulation time 180779297 ps
CPU time 5.56 seconds
Started Aug 10 04:55:47 PM PDT 24
Finished Aug 10 04:55:53 PM PDT 24
Peak memory 220576 kb
Host smart-e2a6008b-0eae-4d74-a849-84bfbca79485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267121900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4267121900
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2961239731
Short name T54
Test name
Test status
Simulation time 583899398 ps
CPU time 3.24 seconds
Started Aug 10 04:55:34 PM PDT 24
Finished Aug 10 04:55:38 PM PDT 24
Peak memory 207580 kb
Host smart-c99afa02-d33b-4e8d-9569-8697f8494949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961239731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2961239731
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.881444033
Short name T377
Test name
Test status
Simulation time 1762868364 ps
CPU time 41.15 seconds
Started Aug 10 04:55:44 PM PDT 24
Finished Aug 10 04:56:25 PM PDT 24
Peak memory 218544 kb
Host smart-4f8e1642-1eaa-4c42-b686-68d0b48f4436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881444033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.881444033
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.218715277
Short name T257
Test name
Test status
Simulation time 175637241 ps
CPU time 4.26 seconds
Started Aug 10 04:55:47 PM PDT 24
Finished Aug 10 04:55:51 PM PDT 24
Peak memory 214268 kb
Host smart-203ba197-8fcb-4274-84b1-7995148d68e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218715277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.218715277
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_random.164199413
Short name T471
Test name
Test status
Simulation time 294464825 ps
CPU time 6.83 seconds
Started Aug 10 04:55:35 PM PDT 24
Finished Aug 10 04:55:42 PM PDT 24
Peak memory 208428 kb
Host smart-8c940452-2550-4aa2-9e06-13d9fdef3194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164199413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.164199413
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1711844752
Short name T265
Test name
Test status
Simulation time 58311391 ps
CPU time 3.09 seconds
Started Aug 10 04:55:35 PM PDT 24
Finished Aug 10 04:55:38 PM PDT 24
Peak memory 208512 kb
Host smart-4923cf9b-eec8-4e3e-abc2-bf5a138f2fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711844752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1711844752
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.773707389
Short name T465
Test name
Test status
Simulation time 55134710 ps
CPU time 2.71 seconds
Started Aug 10 04:55:35 PM PDT 24
Finished Aug 10 04:55:38 PM PDT 24
Peak memory 206932 kb
Host smart-06b46fb0-a599-4c54-aa6e-d66040da631b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773707389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.773707389
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3351117647
Short name T15
Test name
Test status
Simulation time 403197607 ps
CPU time 8.7 seconds
Started Aug 10 04:55:34 PM PDT 24
Finished Aug 10 04:55:43 PM PDT 24
Peak memory 206936 kb
Host smart-9d1e5a6e-74be-4820-898c-8de657fdfd95
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351117647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3351117647
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.334219875
Short name T103
Test name
Test status
Simulation time 547208530 ps
CPU time 13.33 seconds
Started Aug 10 04:55:34 PM PDT 24
Finished Aug 10 04:55:47 PM PDT 24
Peak memory 208620 kb
Host smart-7227498a-6428-46ea-97a1-7a51c0ab402d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334219875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.334219875
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1041217309
Short name T452
Test name
Test status
Simulation time 153606124 ps
CPU time 2.46 seconds
Started Aug 10 04:55:45 PM PDT 24
Finished Aug 10 04:55:47 PM PDT 24
Peak memory 209268 kb
Host smart-3c9cbb4b-3b9e-4fef-81fd-3c7c985724d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041217309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1041217309
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.5647650
Short name T578
Test name
Test status
Simulation time 20723410 ps
CPU time 1.69 seconds
Started Aug 10 04:55:35 PM PDT 24
Finished Aug 10 04:55:37 PM PDT 24
Peak memory 206912 kb
Host smart-1be208f2-46f3-4c98-8ff0-be032a99c81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5647650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.5647650
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.93766953
Short name T371
Test name
Test status
Simulation time 2401012176 ps
CPU time 59.39 seconds
Started Aug 10 04:55:42 PM PDT 24
Finished Aug 10 04:56:42 PM PDT 24
Peak memory 221804 kb
Host smart-f4551d01-8783-48ee-bed6-554f8412854f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93766953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.93766953
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.339538790
Short name T598
Test name
Test status
Simulation time 101806446 ps
CPU time 5.15 seconds
Started Aug 10 04:55:48 PM PDT 24
Finished Aug 10 04:55:54 PM PDT 24
Peak memory 208788 kb
Host smart-0799582e-ed3c-43f6-ab3f-b865ceab064c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339538790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.339538790
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1896766268
Short name T417
Test name
Test status
Simulation time 92758643 ps
CPU time 1.29 seconds
Started Aug 10 04:55:45 PM PDT 24
Finished Aug 10 04:55:47 PM PDT 24
Peak memory 209792 kb
Host smart-ff3dcb1e-ae2d-4dc0-b4b2-4cf56c4b0296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896766268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1896766268
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2044026707
Short name T470
Test name
Test status
Simulation time 29061936 ps
CPU time 0.88 seconds
Started Aug 10 04:55:45 PM PDT 24
Finished Aug 10 04:55:46 PM PDT 24
Peak memory 205944 kb
Host smart-1b2468d2-8143-45f8-ba7a-546a593332ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044026707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2044026707
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3930693531
Short name T69
Test name
Test status
Simulation time 175438529 ps
CPU time 4.8 seconds
Started Aug 10 04:55:49 PM PDT 24
Finished Aug 10 04:55:54 PM PDT 24
Peak memory 214408 kb
Host smart-a84a6e9d-8e9f-49e3-8669-eb42c1d3f554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930693531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3930693531
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2396512532
Short name T893
Test name
Test status
Simulation time 94184097 ps
CPU time 1.55 seconds
Started Aug 10 04:55:46 PM PDT 24
Finished Aug 10 04:55:47 PM PDT 24
Peak memory 207668 kb
Host smart-5000097c-61be-4c14-8437-342b70d509c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396512532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2396512532
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.367538131
Short name T737
Test name
Test status
Simulation time 116279896 ps
CPU time 5.13 seconds
Started Aug 10 04:55:45 PM PDT 24
Finished Aug 10 04:55:50 PM PDT 24
Peak memory 214344 kb
Host smart-7f6a7281-ca52-4283-a74c-95ef4aba7d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367538131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.367538131
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.731731229
Short name T303
Test name
Test status
Simulation time 52373773 ps
CPU time 1.84 seconds
Started Aug 10 04:55:43 PM PDT 24
Finished Aug 10 04:55:45 PM PDT 24
Peak memory 214260 kb
Host smart-b7f64d25-8983-4a3c-b93a-215c1ac89f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731731229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.731731229
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2500495344
Short name T838
Test name
Test status
Simulation time 406259099 ps
CPU time 4.79 seconds
Started Aug 10 04:55:50 PM PDT 24
Finished Aug 10 04:55:55 PM PDT 24
Peak memory 209780 kb
Host smart-a108a8f1-bf3c-4404-b3dd-1be177002ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500495344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2500495344
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1284082618
Short name T459
Test name
Test status
Simulation time 232575910 ps
CPU time 2.63 seconds
Started Aug 10 04:55:44 PM PDT 24
Finished Aug 10 04:55:47 PM PDT 24
Peak memory 208364 kb
Host smart-7629dad4-de1a-4cee-9e78-17b926b0eb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284082618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1284082618
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1642785121
Short name T418
Test name
Test status
Simulation time 131440153 ps
CPU time 5.2 seconds
Started Aug 10 04:55:43 PM PDT 24
Finished Aug 10 04:55:49 PM PDT 24
Peak memory 208112 kb
Host smart-8eeed2bb-349a-4bf0-8fa1-0926bafb4018
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642785121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1642785121
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1773803569
Short name T735
Test name
Test status
Simulation time 368778991 ps
CPU time 3.36 seconds
Started Aug 10 04:55:44 PM PDT 24
Finished Aug 10 04:55:48 PM PDT 24
Peak memory 208684 kb
Host smart-f12a55f8-09da-4bf1-93ca-a9722b8aca7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773803569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1773803569
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.775390559
Short name T501
Test name
Test status
Simulation time 2930341297 ps
CPU time 20.3 seconds
Started Aug 10 04:55:47 PM PDT 24
Finished Aug 10 04:56:07 PM PDT 24
Peak memory 208640 kb
Host smart-95a5cd8a-4e0b-418e-aa4c-14f8a2ed7db4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775390559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.775390559
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2483924288
Short name T793
Test name
Test status
Simulation time 26303079 ps
CPU time 1.96 seconds
Started Aug 10 04:55:50 PM PDT 24
Finished Aug 10 04:55:52 PM PDT 24
Peak memory 208020 kb
Host smart-e9641b08-e9e0-4305-bc40-762f37752ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483924288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2483924288
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3594716403
Short name T785
Test name
Test status
Simulation time 535012209 ps
CPU time 2.46 seconds
Started Aug 10 04:55:50 PM PDT 24
Finished Aug 10 04:55:52 PM PDT 24
Peak memory 206728 kb
Host smart-e178814d-dd7b-4ad9-9750-07e49ffe41d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594716403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3594716403
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3980318621
Short name T640
Test name
Test status
Simulation time 645432439 ps
CPU time 7.59 seconds
Started Aug 10 04:55:44 PM PDT 24
Finished Aug 10 04:55:51 PM PDT 24
Peak memory 210232 kb
Host smart-15b6bd0d-c551-4d04-9ab7-c797251b1b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980318621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3980318621
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1004709682
Short name T487
Test name
Test status
Simulation time 217503227 ps
CPU time 1.83 seconds
Started Aug 10 04:55:44 PM PDT 24
Finished Aug 10 04:55:46 PM PDT 24
Peak memory 210160 kb
Host smart-07656b34-28b6-40a5-9ef2-8de7faeb8dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004709682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1004709682
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.4288302534
Short name T862
Test name
Test status
Simulation time 24796032 ps
CPU time 0.82 seconds
Started Aug 10 04:55:56 PM PDT 24
Finished Aug 10 04:55:57 PM PDT 24
Peak memory 205908 kb
Host smart-d6e0013f-6300-43cd-862c-34324e05ce4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288302534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.4288302534
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1262073207
Short name T404
Test name
Test status
Simulation time 80020314 ps
CPU time 4.73 seconds
Started Aug 10 04:55:45 PM PDT 24
Finished Aug 10 04:55:50 PM PDT 24
Peak memory 214252 kb
Host smart-0092eb6e-edf4-4c82-9638-ab45e471ef9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1262073207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1262073207
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1867803128
Short name T822
Test name
Test status
Simulation time 147333123 ps
CPU time 2.99 seconds
Started Aug 10 04:55:50 PM PDT 24
Finished Aug 10 04:55:53 PM PDT 24
Peak memory 209136 kb
Host smart-2efd01ff-fa71-4318-a13b-3859c40ba42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867803128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1867803128
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.337929789
Short name T827
Test name
Test status
Simulation time 134391428 ps
CPU time 2.25 seconds
Started Aug 10 04:55:44 PM PDT 24
Finished Aug 10 04:55:46 PM PDT 24
Peak memory 208208 kb
Host smart-645ecb94-2f67-41a0-b693-5a99eaa577b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337929789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.337929789
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2019391797
Short name T677
Test name
Test status
Simulation time 114684196 ps
CPU time 2.03 seconds
Started Aug 10 04:55:44 PM PDT 24
Finished Aug 10 04:55:46 PM PDT 24
Peak memory 214260 kb
Host smart-2c2b7a20-48e5-4a2c-a4ee-0735c3d89ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019391797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2019391797
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1208203584
Short name T235
Test name
Test status
Simulation time 48194567 ps
CPU time 2.55 seconds
Started Aug 10 04:55:46 PM PDT 24
Finished Aug 10 04:55:48 PM PDT 24
Peak memory 206068 kb
Host smart-3c466e4a-225f-4ff2-8770-4c9bd5c5879c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208203584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1208203584
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.72726120
Short name T226
Test name
Test status
Simulation time 584592119 ps
CPU time 5.5 seconds
Started Aug 10 04:55:43 PM PDT 24
Finished Aug 10 04:55:49 PM PDT 24
Peak memory 208752 kb
Host smart-7c524c94-dd85-4dec-87d3-76405f7dd841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72726120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.72726120
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.995727841
Short name T368
Test name
Test status
Simulation time 1704368053 ps
CPU time 16.44 seconds
Started Aug 10 04:55:46 PM PDT 24
Finished Aug 10 04:56:03 PM PDT 24
Peak memory 208064 kb
Host smart-a07640f2-3015-48a3-81f7-73aafdba9cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995727841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.995727841
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1750979584
Short name T900
Test name
Test status
Simulation time 1210621901 ps
CPU time 3.8 seconds
Started Aug 10 04:55:50 PM PDT 24
Finished Aug 10 04:55:54 PM PDT 24
Peak memory 206836 kb
Host smart-0e04652b-1a07-4275-8288-1535dc267be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750979584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1750979584
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.505241080
Short name T561
Test name
Test status
Simulation time 90740644 ps
CPU time 3.58 seconds
Started Aug 10 04:55:47 PM PDT 24
Finished Aug 10 04:55:50 PM PDT 24
Peak memory 208412 kb
Host smart-28cb09d7-12bc-45b0-94ab-7c5ef7ca248e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505241080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.505241080
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1628103780
Short name T331
Test name
Test status
Simulation time 129967599 ps
CPU time 1.79 seconds
Started Aug 10 04:55:45 PM PDT 24
Finished Aug 10 04:55:47 PM PDT 24
Peak memory 206804 kb
Host smart-fbda44c5-5126-4f16-90e2-3413a43d9a58
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628103780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1628103780
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2807009166
Short name T600
Test name
Test status
Simulation time 439854398 ps
CPU time 3.18 seconds
Started Aug 10 04:55:55 PM PDT 24
Finished Aug 10 04:55:58 PM PDT 24
Peak memory 208752 kb
Host smart-1020ab17-f7dd-4e4f-83cd-07bd0024ba48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807009166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2807009166
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1033529370
Short name T682
Test name
Test status
Simulation time 69271416 ps
CPU time 3.37 seconds
Started Aug 10 04:55:45 PM PDT 24
Finished Aug 10 04:55:48 PM PDT 24
Peak memory 208788 kb
Host smart-86acc972-fca0-46d7-b5a4-f0fd7a1725cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033529370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1033529370
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2141611776
Short name T722
Test name
Test status
Simulation time 33420735 ps
CPU time 2.26 seconds
Started Aug 10 04:55:51 PM PDT 24
Finished Aug 10 04:55:54 PM PDT 24
Peak memory 206800 kb
Host smart-9c2fc510-edaf-44a7-8fe2-c11d65f06fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141611776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2141611776
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2381858075
Short name T277
Test name
Test status
Simulation time 73335410 ps
CPU time 2.46 seconds
Started Aug 10 04:55:56 PM PDT 24
Finished Aug 10 04:55:58 PM PDT 24
Peak memory 206760 kb
Host smart-689539f8-84c5-4196-bc20-b67f183e8fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381858075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2381858075
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1951993071
Short name T668
Test name
Test status
Simulation time 1130757219 ps
CPU time 3.97 seconds
Started Aug 10 04:55:44 PM PDT 24
Finished Aug 10 04:55:49 PM PDT 24
Peak memory 209168 kb
Host smart-d485d2ec-b917-4c8b-b898-e12710ec3b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951993071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1951993071
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.445520910
Short name T802
Test name
Test status
Simulation time 46199031 ps
CPU time 1.4 seconds
Started Aug 10 04:55:46 PM PDT 24
Finished Aug 10 04:55:48 PM PDT 24
Peak memory 209448 kb
Host smart-3276b013-afa6-4074-99cd-01253eeed3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445520910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.445520910
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.581521450
Short name T100
Test name
Test status
Simulation time 46944301 ps
CPU time 0.9 seconds
Started Aug 10 04:55:52 PM PDT 24
Finished Aug 10 04:55:53 PM PDT 24
Peak memory 205908 kb
Host smart-609175b4-acb4-45ff-99b8-02ab381eebca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581521450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.581521450
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.534108271
Short name T356
Test name
Test status
Simulation time 32912850 ps
CPU time 2.69 seconds
Started Aug 10 04:55:55 PM PDT 24
Finished Aug 10 04:55:58 PM PDT 24
Peak memory 214320 kb
Host smart-194e6a30-eb73-4693-97bf-3595c5705d86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=534108271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.534108271
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1007632144
Short name T59
Test name
Test status
Simulation time 60491244 ps
CPU time 2.85 seconds
Started Aug 10 04:55:51 PM PDT 24
Finished Aug 10 04:55:54 PM PDT 24
Peak memory 208004 kb
Host smart-901b9a2d-6e44-40fa-a9aa-c768a283ebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007632144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1007632144
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2242384729
Short name T837
Test name
Test status
Simulation time 112338007 ps
CPU time 3.66 seconds
Started Aug 10 04:55:51 PM PDT 24
Finished Aug 10 04:55:55 PM PDT 24
Peak memory 209664 kb
Host smart-f5371b2f-28ee-4688-a828-ba56ff965a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242384729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2242384729
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2219921322
Short name T358
Test name
Test status
Simulation time 1886312241 ps
CPU time 4.06 seconds
Started Aug 10 04:55:52 PM PDT 24
Finished Aug 10 04:55:56 PM PDT 24
Peak memory 214192 kb
Host smart-d5bebde4-6e80-48e4-99ce-873e662d3893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219921322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2219921322
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.358024654
Short name T291
Test name
Test status
Simulation time 318535113 ps
CPU time 3.14 seconds
Started Aug 10 04:55:52 PM PDT 24
Finished Aug 10 04:55:56 PM PDT 24
Peak memory 218532 kb
Host smart-39d4543b-a81b-4a4b-b8aa-6bc7bd73571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358024654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.358024654
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2089541006
Short name T504
Test name
Test status
Simulation time 662156196 ps
CPU time 4.58 seconds
Started Aug 10 04:55:56 PM PDT 24
Finished Aug 10 04:56:01 PM PDT 24
Peak memory 207192 kb
Host smart-cd6b9972-ef8a-4020-bd89-c9e9f03a5f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089541006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2089541006
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.4025723484
Short name T877
Test name
Test status
Simulation time 337586977 ps
CPU time 6.6 seconds
Started Aug 10 04:55:53 PM PDT 24
Finished Aug 10 04:55:59 PM PDT 24
Peak memory 206844 kb
Host smart-6dfa3825-b34b-44b3-af44-7efcd5a2859e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025723484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4025723484
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1410209066
Short name T778
Test name
Test status
Simulation time 37686478 ps
CPU time 2.36 seconds
Started Aug 10 04:55:54 PM PDT 24
Finished Aug 10 04:55:56 PM PDT 24
Peak memory 206956 kb
Host smart-3fb34227-424f-437a-9230-aef7ef603579
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410209066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1410209066
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1569782057
Short name T597
Test name
Test status
Simulation time 30934325 ps
CPU time 2.3 seconds
Started Aug 10 04:55:56 PM PDT 24
Finished Aug 10 04:55:58 PM PDT 24
Peak memory 206708 kb
Host smart-b836f555-6d80-4eee-9659-226aa438ef7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569782057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1569782057
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3044610631
Short name T524
Test name
Test status
Simulation time 620802004 ps
CPU time 4.91 seconds
Started Aug 10 04:55:56 PM PDT 24
Finished Aug 10 04:56:01 PM PDT 24
Peak memory 208000 kb
Host smart-af7c52d9-ef9a-4fc7-be98-52213977f04d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044610631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3044610631
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1487869446
Short name T904
Test name
Test status
Simulation time 94174238 ps
CPU time 2.72 seconds
Started Aug 10 04:55:52 PM PDT 24
Finished Aug 10 04:55:55 PM PDT 24
Peak memory 209300 kb
Host smart-42466796-19f2-4682-91e2-dbb9a0408285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487869446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1487869446
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3928499091
Short name T768
Test name
Test status
Simulation time 253453386 ps
CPU time 4.52 seconds
Started Aug 10 04:55:54 PM PDT 24
Finished Aug 10 04:55:58 PM PDT 24
Peak memory 208096 kb
Host smart-1c887438-886a-473c-be83-5e31225bba18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928499091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3928499091
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2247644252
Short name T518
Test name
Test status
Simulation time 1362708648 ps
CPU time 23.32 seconds
Started Aug 10 04:55:54 PM PDT 24
Finished Aug 10 04:56:17 PM PDT 24
Peak memory 216552 kb
Host smart-c783a8da-a3f7-4e39-80ad-45ef3fe2920b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247644252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2247644252
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3051977167
Short name T177
Test name
Test status
Simulation time 329989656 ps
CPU time 10.89 seconds
Started Aug 10 04:55:50 PM PDT 24
Finished Aug 10 04:56:01 PM PDT 24
Peak memory 219900 kb
Host smart-a0af133f-44f9-4ed6-984c-8a3540bbd97a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051977167 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3051977167
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.4155428070
Short name T424
Test name
Test status
Simulation time 231213302 ps
CPU time 5.21 seconds
Started Aug 10 04:55:51 PM PDT 24
Finished Aug 10 04:55:56 PM PDT 24
Peak memory 209384 kb
Host smart-7ad3dd8d-6d75-4fb1-94b4-1343112b3d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155428070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.4155428070
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1791154973
Short name T700
Test name
Test status
Simulation time 35602469 ps
CPU time 2.18 seconds
Started Aug 10 04:55:55 PM PDT 24
Finished Aug 10 04:55:58 PM PDT 24
Peak memory 209900 kb
Host smart-108b84f7-c76f-472d-8290-7224a80b107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791154973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1791154973
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2395357710
Short name T883
Test name
Test status
Simulation time 42125184 ps
CPU time 0.78 seconds
Started Aug 10 04:55:53 PM PDT 24
Finished Aug 10 04:55:54 PM PDT 24
Peak memory 205840 kb
Host smart-5262a60c-5917-474a-9bee-ca288d83b8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395357710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2395357710
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1100449853
Short name T279
Test name
Test status
Simulation time 441807282 ps
CPU time 6.58 seconds
Started Aug 10 04:55:51 PM PDT 24
Finished Aug 10 04:55:57 PM PDT 24
Peak memory 215456 kb
Host smart-c495e38f-dae7-4d80-965a-19c24073b72b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1100449853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1100449853
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1026501343
Short name T681
Test name
Test status
Simulation time 159570203 ps
CPU time 4.28 seconds
Started Aug 10 04:55:53 PM PDT 24
Finished Aug 10 04:55:58 PM PDT 24
Peak memory 214260 kb
Host smart-ee492460-2e9b-45d9-93af-8e45f14cb8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026501343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1026501343
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1449978233
Short name T897
Test name
Test status
Simulation time 243115046 ps
CPU time 4.4 seconds
Started Aug 10 04:55:55 PM PDT 24
Finished Aug 10 04:55:59 PM PDT 24
Peak memory 214396 kb
Host smart-1abb5aa4-c497-48a3-99e4-9c46e6436685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449978233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1449978233
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.4195122265
Short name T301
Test name
Test status
Simulation time 243908353 ps
CPU time 3.38 seconds
Started Aug 10 04:55:52 PM PDT 24
Finished Aug 10 04:55:56 PM PDT 24
Peak memory 219788 kb
Host smart-7ca32ef5-7380-4ccf-a3e8-4fbc66d1121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195122265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.4195122265
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3936225979
Short name T484
Test name
Test status
Simulation time 86899649 ps
CPU time 2.67 seconds
Started Aug 10 04:55:53 PM PDT 24
Finished Aug 10 04:55:56 PM PDT 24
Peak memory 219628 kb
Host smart-6b621513-ebe7-48ec-8e58-c7e3aff94dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936225979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3936225979
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.180462394
Short name T592
Test name
Test status
Simulation time 390597358 ps
CPU time 3.62 seconds
Started Aug 10 04:55:54 PM PDT 24
Finished Aug 10 04:55:58 PM PDT 24
Peak memory 209344 kb
Host smart-905cd344-a8ff-40c8-82ec-ceee98ea51f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180462394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.180462394
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1533864225
Short name T276
Test name
Test status
Simulation time 59105578 ps
CPU time 2.37 seconds
Started Aug 10 04:55:55 PM PDT 24
Finished Aug 10 04:55:57 PM PDT 24
Peak memory 206780 kb
Host smart-7bd7ffba-fdc3-4209-85b1-a5c62cc7febf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533864225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1533864225
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1335120051
Short name T692
Test name
Test status
Simulation time 61195454 ps
CPU time 3.07 seconds
Started Aug 10 04:55:53 PM PDT 24
Finished Aug 10 04:55:56 PM PDT 24
Peak memory 208840 kb
Host smart-351a01bc-d87a-4061-aae1-2a10662eecb3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335120051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1335120051
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2688316004
Short name T716
Test name
Test status
Simulation time 264865382 ps
CPU time 3.23 seconds
Started Aug 10 04:55:53 PM PDT 24
Finished Aug 10 04:55:57 PM PDT 24
Peak memory 209228 kb
Host smart-43c7f8f9-3b99-4a81-a972-21e82656a97a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688316004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2688316004
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3377107185
Short name T579
Test name
Test status
Simulation time 786946335 ps
CPU time 5.95 seconds
Started Aug 10 04:55:52 PM PDT 24
Finished Aug 10 04:55:58 PM PDT 24
Peak memory 208428 kb
Host smart-0ebff285-8bd9-4074-bd98-195f64512971
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377107185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3377107185
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.65563440
Short name T804
Test name
Test status
Simulation time 256998429 ps
CPU time 1.91 seconds
Started Aug 10 04:55:56 PM PDT 24
Finished Aug 10 04:55:58 PM PDT 24
Peak memory 208200 kb
Host smart-78838013-ac98-4c13-a877-f666656eb8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65563440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.65563440
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.24397047
Short name T185
Test name
Test status
Simulation time 443245211 ps
CPU time 5.01 seconds
Started Aug 10 04:56:00 PM PDT 24
Finished Aug 10 04:56:05 PM PDT 24
Peak memory 206644 kb
Host smart-3e32e538-af16-4c64-986b-806a41c1d96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24397047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.24397047
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1559716061
Short name T830
Test name
Test status
Simulation time 8042564517 ps
CPU time 56.1 seconds
Started Aug 10 04:55:53 PM PDT 24
Finished Aug 10 04:56:50 PM PDT 24
Peak memory 222452 kb
Host smart-fc288ede-dc4e-4d7e-96cc-2c75980586cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559716061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1559716061
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1045129961
Short name T747
Test name
Test status
Simulation time 446647428 ps
CPU time 19.03 seconds
Started Aug 10 04:55:53 PM PDT 24
Finished Aug 10 04:56:12 PM PDT 24
Peak memory 222564 kb
Host smart-ad9d2328-2430-45cc-bfd8-a5cb2cd3e4d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045129961 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1045129961
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.4236131188
Short name T290
Test name
Test status
Simulation time 289946711 ps
CPU time 5.5 seconds
Started Aug 10 04:55:54 PM PDT 24
Finished Aug 10 04:55:59 PM PDT 24
Peak memory 210544 kb
Host smart-355dc1a7-414d-4440-92c8-fa5902add7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236131188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.4236131188
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.629552285
Short name T419
Test name
Test status
Simulation time 61896275 ps
CPU time 2.89 seconds
Started Aug 10 04:55:59 PM PDT 24
Finished Aug 10 04:56:02 PM PDT 24
Peak memory 209856 kb
Host smart-e8562dc0-d957-4335-a91d-47a4fc429c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629552285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.629552285
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3925513660
Short name T529
Test name
Test status
Simulation time 18187534 ps
CPU time 0.84 seconds
Started Aug 10 04:51:29 PM PDT 24
Finished Aug 10 04:51:30 PM PDT 24
Peak memory 205944 kb
Host smart-fb32b7d5-92e9-4d0b-b8a4-f886683576eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925513660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3925513660
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.950965507
Short name T232
Test name
Test status
Simulation time 126174101 ps
CPU time 2.7 seconds
Started Aug 10 04:51:34 PM PDT 24
Finished Aug 10 04:51:37 PM PDT 24
Peak memory 214240 kb
Host smart-8fbf13e6-7c3b-4d67-b1b6-72b4416362a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950965507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.950965507
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.807810540
Short name T221
Test name
Test status
Simulation time 134925289 ps
CPU time 2.01 seconds
Started Aug 10 04:51:33 PM PDT 24
Finished Aug 10 04:51:35 PM PDT 24
Peak memory 208644 kb
Host smart-17f1dbe8-d297-4154-a77f-046e8bc04ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807810540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.807810540
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.991716494
Short name T357
Test name
Test status
Simulation time 377207996 ps
CPU time 2.94 seconds
Started Aug 10 04:51:29 PM PDT 24
Finished Aug 10 04:51:32 PM PDT 24
Peak memory 218380 kb
Host smart-aa3d0643-6849-477d-8f9e-784049c7bc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991716494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.991716494
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.140900396
Short name T94
Test name
Test status
Simulation time 363521099 ps
CPU time 2.82 seconds
Started Aug 10 04:51:32 PM PDT 24
Finished Aug 10 04:51:35 PM PDT 24
Peak memory 210048 kb
Host smart-2a6ae719-9a1f-4e1d-9c37-b3cee917650b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140900396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.140900396
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3756150509
Short name T833
Test name
Test status
Simulation time 82775745 ps
CPU time 3.05 seconds
Started Aug 10 04:51:28 PM PDT 24
Finished Aug 10 04:51:32 PM PDT 24
Peak memory 214348 kb
Host smart-fb92bf27-f416-422b-ab66-794e44bfe24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756150509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3756150509
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.21217660
Short name T753
Test name
Test status
Simulation time 399026864 ps
CPU time 3.4 seconds
Started Aug 10 04:51:30 PM PDT 24
Finished Aug 10 04:51:33 PM PDT 24
Peak memory 209360 kb
Host smart-18889825-ed35-49dd-9138-53e3b08f476b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21217660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.21217660
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3919105174
Short name T199
Test name
Test status
Simulation time 425276380 ps
CPU time 4.66 seconds
Started Aug 10 04:51:28 PM PDT 24
Finished Aug 10 04:51:33 PM PDT 24
Peak memory 207500 kb
Host smart-c3e3be27-ed38-46b2-8cb9-ef1eeba1658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919105174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3919105174
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3572320703
Short name T123
Test name
Test status
Simulation time 176930549 ps
CPU time 4.92 seconds
Started Aug 10 04:51:19 PM PDT 24
Finished Aug 10 04:51:24 PM PDT 24
Peak memory 207980 kb
Host smart-126a6bd7-a503-4870-b5da-2881e76a21bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572320703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3572320703
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3155150674
Short name T426
Test name
Test status
Simulation time 1373688925 ps
CPU time 18.86 seconds
Started Aug 10 04:51:20 PM PDT 24
Finished Aug 10 04:51:39 PM PDT 24
Peak memory 207824 kb
Host smart-701bdef3-706d-428d-a130-d8e3c7aa4866
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155150674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3155150674
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2970868736
Short name T492
Test name
Test status
Simulation time 120194247 ps
CPU time 1.92 seconds
Started Aug 10 04:51:20 PM PDT 24
Finished Aug 10 04:51:22 PM PDT 24
Peak memory 206804 kb
Host smart-04b242d2-2f5a-4e3e-b050-be283a2843dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970868736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2970868736
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3319100514
Short name T238
Test name
Test status
Simulation time 405693442 ps
CPU time 5.88 seconds
Started Aug 10 04:51:34 PM PDT 24
Finished Aug 10 04:51:39 PM PDT 24
Peak memory 208768 kb
Host smart-7ed18db0-cd68-409f-a810-bc74488e10c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319100514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3319100514
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2729629419
Short name T433
Test name
Test status
Simulation time 81309083 ps
CPU time 1.87 seconds
Started Aug 10 04:51:29 PM PDT 24
Finished Aug 10 04:51:31 PM PDT 24
Peak memory 207588 kb
Host smart-62c0c238-21e4-4266-b6ce-d1b2c7d47008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729629419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2729629419
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.588229743
Short name T794
Test name
Test status
Simulation time 789710348 ps
CPU time 4.55 seconds
Started Aug 10 04:51:19 PM PDT 24
Finished Aug 10 04:51:24 PM PDT 24
Peak memory 207488 kb
Host smart-eaf63e3f-d922-487f-81a9-41c4583f758a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588229743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.588229743
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.4107228281
Short name T110
Test name
Test status
Simulation time 25592051466 ps
CPU time 193.52 seconds
Started Aug 10 04:51:34 PM PDT 24
Finished Aug 10 04:54:47 PM PDT 24
Peak memory 217324 kb
Host smart-f00ed5d6-2ba4-4eac-a609-59c568e01976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107228281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.4107228281
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1668386831
Short name T707
Test name
Test status
Simulation time 174054533 ps
CPU time 3.42 seconds
Started Aug 10 04:51:29 PM PDT 24
Finished Aug 10 04:51:33 PM PDT 24
Peak memory 207588 kb
Host smart-45a97a9d-e995-4663-bdc1-c3303c2cb355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668386831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1668386831
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3038298794
Short name T513
Test name
Test status
Simulation time 50783840 ps
CPU time 0.81 seconds
Started Aug 10 04:51:41 PM PDT 24
Finished Aug 10 04:51:42 PM PDT 24
Peak memory 205960 kb
Host smart-356fe782-db73-4cfa-8ad7-d638462daeef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038298794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3038298794
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2620926087
Short name T854
Test name
Test status
Simulation time 275134859 ps
CPU time 2.86 seconds
Started Aug 10 04:51:42 PM PDT 24
Finished Aug 10 04:51:45 PM PDT 24
Peak memory 214204 kb
Host smart-f85c808e-b902-4342-ac45-cc2e9f6242db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620926087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2620926087
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.466858380
Short name T273
Test name
Test status
Simulation time 89443161 ps
CPU time 2.04 seconds
Started Aug 10 04:51:38 PM PDT 24
Finished Aug 10 04:51:40 PM PDT 24
Peak memory 207268 kb
Host smart-7eb752e4-1673-49cf-a011-fa91fdd6d26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466858380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.466858380
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.637725501
Short name T842
Test name
Test status
Simulation time 84086359 ps
CPU time 4.04 seconds
Started Aug 10 04:51:37 PM PDT 24
Finished Aug 10 04:51:41 PM PDT 24
Peak memory 214248 kb
Host smart-29c3345f-94d7-460d-8f7d-3edf69288da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637725501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.637725501
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2050607080
Short name T106
Test name
Test status
Simulation time 262290340 ps
CPU time 2.82 seconds
Started Aug 10 04:51:41 PM PDT 24
Finished Aug 10 04:51:44 PM PDT 24
Peak memory 221036 kb
Host smart-9f61b537-2ab9-42ec-8f32-d3e27690eb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050607080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2050607080
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.206705904
Short name T686
Test name
Test status
Simulation time 123451902 ps
CPU time 3.24 seconds
Started Aug 10 04:51:36 PM PDT 24
Finished Aug 10 04:51:39 PM PDT 24
Peak memory 219752 kb
Host smart-0ddf6fab-d497-4138-8b72-f6a891c0949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206705904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.206705904
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.729051549
Short name T365
Test name
Test status
Simulation time 738321949 ps
CPU time 6.16 seconds
Started Aug 10 04:51:41 PM PDT 24
Finished Aug 10 04:51:48 PM PDT 24
Peak memory 207204 kb
Host smart-d866303a-0e5e-4602-8de4-96b56a151e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729051549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.729051549
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1311633358
Short name T313
Test name
Test status
Simulation time 2657695031 ps
CPU time 30.39 seconds
Started Aug 10 04:51:28 PM PDT 24
Finished Aug 10 04:51:59 PM PDT 24
Peak memory 208636 kb
Host smart-030eae83-13f3-438b-aafd-e7a6b1bc55e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311633358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1311633358
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4032453293
Short name T781
Test name
Test status
Simulation time 89878143 ps
CPU time 4.13 seconds
Started Aug 10 04:51:41 PM PDT 24
Finished Aug 10 04:51:45 PM PDT 24
Peak memory 208572 kb
Host smart-559fc0be-a61d-4ee1-925b-e430f7bdba0d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032453293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4032453293
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1859941266
Short name T843
Test name
Test status
Simulation time 472457915 ps
CPU time 4.57 seconds
Started Aug 10 04:51:32 PM PDT 24
Finished Aug 10 04:51:37 PM PDT 24
Peak memory 208628 kb
Host smart-dc5619f6-4ca1-494b-8e7f-47668f9228d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859941266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1859941266
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3761694840
Short name T278
Test name
Test status
Simulation time 11065453457 ps
CPU time 40.45 seconds
Started Aug 10 04:51:37 PM PDT 24
Finished Aug 10 04:52:18 PM PDT 24
Peak memory 209060 kb
Host smart-9cc3f7e6-7a57-405a-b2bb-d60b73198fc0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761694840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3761694840
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3442289172
Short name T196
Test name
Test status
Simulation time 431907078 ps
CPU time 4.25 seconds
Started Aug 10 04:51:38 PM PDT 24
Finished Aug 10 04:51:43 PM PDT 24
Peak memory 209264 kb
Host smart-afc099aa-e01b-4c92-8fcd-2b8cf45059d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442289172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3442289172
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1834729330
Short name T672
Test name
Test status
Simulation time 22580986 ps
CPU time 2.16 seconds
Started Aug 10 04:51:33 PM PDT 24
Finished Aug 10 04:51:35 PM PDT 24
Peak memory 208532 kb
Host smart-19911687-d04d-4b3b-9d3f-4fc4880b8668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834729330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1834729330
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3671883970
Short name T338
Test name
Test status
Simulation time 551271689 ps
CPU time 8.86 seconds
Started Aug 10 04:51:39 PM PDT 24
Finished Aug 10 04:51:48 PM PDT 24
Peak memory 218092 kb
Host smart-17b5e743-da58-44f1-ae9f-f0cad4a08ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671883970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3671883970
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3857237120
Short name T771
Test name
Test status
Simulation time 33461265 ps
CPU time 0.86 seconds
Started Aug 10 04:51:54 PM PDT 24
Finished Aug 10 04:51:55 PM PDT 24
Peak memory 205956 kb
Host smart-563873c1-bb0e-4962-83e1-00e6fbac231f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857237120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3857237120
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2367763885
Short name T350
Test name
Test status
Simulation time 128033131 ps
CPU time 2.84 seconds
Started Aug 10 04:51:46 PM PDT 24
Finished Aug 10 04:51:49 PM PDT 24
Peak memory 215312 kb
Host smart-e8e7b84f-bba6-4b77-b092-4c34f3f40903
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2367763885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2367763885
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1433034741
Short name T28
Test name
Test status
Simulation time 395734164 ps
CPU time 5.11 seconds
Started Aug 10 04:51:46 PM PDT 24
Finished Aug 10 04:51:51 PM PDT 24
Peak memory 222744 kb
Host smart-ea300fe5-1988-47dc-82bb-d889ae440df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433034741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1433034741
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3782471754
Short name T431
Test name
Test status
Simulation time 593982593 ps
CPU time 2.93 seconds
Started Aug 10 04:52:20 PM PDT 24
Finished Aug 10 04:52:23 PM PDT 24
Peak memory 218120 kb
Host smart-66249601-5036-454c-b230-79273ec7550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782471754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3782471754
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.652101796
Short name T50
Test name
Test status
Simulation time 357842957 ps
CPU time 3.07 seconds
Started Aug 10 04:51:46 PM PDT 24
Finished Aug 10 04:51:49 PM PDT 24
Peak memory 214260 kb
Host smart-36b0a686-9cbc-4069-88c6-49cb3ec0220d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652101796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.652101796
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.941950539
Short name T299
Test name
Test status
Simulation time 117659879 ps
CPU time 3.52 seconds
Started Aug 10 04:51:47 PM PDT 24
Finished Aug 10 04:51:50 PM PDT 24
Peak memory 220224 kb
Host smart-3e9c4968-bb70-48be-9a76-d8079f87f1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941950539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.941950539
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3095440127
Short name T439
Test name
Test status
Simulation time 241235317 ps
CPU time 3.5 seconds
Started Aug 10 04:51:48 PM PDT 24
Finished Aug 10 04:51:52 PM PDT 24
Peak memory 219460 kb
Host smart-411ee795-0062-4a12-9d3b-924e7e26d9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095440127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3095440127
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.26875803
Short name T732
Test name
Test status
Simulation time 1974456575 ps
CPU time 4.97 seconds
Started Aug 10 04:51:46 PM PDT 24
Finished Aug 10 04:51:51 PM PDT 24
Peak memory 214416 kb
Host smart-f87d19e9-0b94-4561-a7da-a4d57e10db2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26875803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.26875803
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2685871931
Short name T540
Test name
Test status
Simulation time 370414427 ps
CPU time 5.82 seconds
Started Aug 10 04:51:37 PM PDT 24
Finished Aug 10 04:51:43 PM PDT 24
Peak memory 206936 kb
Host smart-af15c6cc-8063-4d11-9b00-e711cdb5da8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685871931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2685871931
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3609064825
Short name T767
Test name
Test status
Simulation time 35361292 ps
CPU time 2.42 seconds
Started Aug 10 04:51:39 PM PDT 24
Finished Aug 10 04:51:41 PM PDT 24
Peak memory 207076 kb
Host smart-3e7d5b9a-9815-47d2-b195-1e632415711a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609064825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3609064825
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1297899045
Short name T641
Test name
Test status
Simulation time 174279474 ps
CPU time 5.89 seconds
Started Aug 10 04:51:41 PM PDT 24
Finished Aug 10 04:51:47 PM PDT 24
Peak memory 208488 kb
Host smart-9047690a-5708-4afd-8924-4f6c26c4152c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297899045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1297899045
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3260491125
Short name T751
Test name
Test status
Simulation time 136852574 ps
CPU time 3.38 seconds
Started Aug 10 04:51:47 PM PDT 24
Finished Aug 10 04:51:51 PM PDT 24
Peak memory 206892 kb
Host smart-2b689370-4e9f-400c-b2a9-9e258f60d9d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260491125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3260491125
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2476662977
Short name T733
Test name
Test status
Simulation time 373650360 ps
CPU time 4.35 seconds
Started Aug 10 04:51:46 PM PDT 24
Finished Aug 10 04:51:50 PM PDT 24
Peak memory 209872 kb
Host smart-3d89c5c9-42ae-46c3-9859-c3d05f2d8751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476662977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2476662977
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2173288631
Short name T410
Test name
Test status
Simulation time 77845719 ps
CPU time 3.2 seconds
Started Aug 10 04:51:39 PM PDT 24
Finished Aug 10 04:51:43 PM PDT 24
Peak memory 208820 kb
Host smart-927c6da1-581d-41e4-9b25-15681d38c8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173288631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2173288631
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1772610681
Short name T5
Test name
Test status
Simulation time 3798575759 ps
CPU time 25.96 seconds
Started Aug 10 04:51:46 PM PDT 24
Finished Aug 10 04:52:12 PM PDT 24
Peak memory 216728 kb
Host smart-4226b7d8-eb0a-4c1f-b0b4-e5ad0b1e058d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772610681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1772610681
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1249293262
Short name T765
Test name
Test status
Simulation time 586875253 ps
CPU time 5.41 seconds
Started Aug 10 04:51:46 PM PDT 24
Finished Aug 10 04:51:51 PM PDT 24
Peak memory 207972 kb
Host smart-fb12559b-843c-4133-ba11-dc9d8ff0bd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249293262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1249293262
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.4276211431
Short name T638
Test name
Test status
Simulation time 67910282 ps
CPU time 2.22 seconds
Started Aug 10 04:51:45 PM PDT 24
Finished Aug 10 04:51:48 PM PDT 24
Peak memory 209820 kb
Host smart-092969b2-226f-41c6-a4c7-88304207f66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276211431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.4276211431
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1633241009
Short name T797
Test name
Test status
Simulation time 37796181 ps
CPU time 0.89 seconds
Started Aug 10 04:51:57 PM PDT 24
Finished Aug 10 04:51:58 PM PDT 24
Peak memory 205872 kb
Host smart-d5874b1b-215e-49b0-abca-adce41a7ce80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633241009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1633241009
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2024857620
Short name T33
Test name
Test status
Simulation time 136224967 ps
CPU time 2.08 seconds
Started Aug 10 04:51:56 PM PDT 24
Finished Aug 10 04:51:58 PM PDT 24
Peak memory 214584 kb
Host smart-94e5c8f1-3705-43c1-8685-9fb9d19371f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024857620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2024857620
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2939533069
Short name T48
Test name
Test status
Simulation time 985585964 ps
CPU time 20.33 seconds
Started Aug 10 04:51:46 PM PDT 24
Finished Aug 10 04:52:06 PM PDT 24
Peak memory 209672 kb
Host smart-2ff2d846-53b8-423b-9cbb-2c16c19401ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939533069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2939533069
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.951747126
Short name T95
Test name
Test status
Simulation time 185536737 ps
CPU time 7.68 seconds
Started Aug 10 04:51:57 PM PDT 24
Finished Aug 10 04:52:05 PM PDT 24
Peak memory 214204 kb
Host smart-a632ed93-dae2-4593-a546-bbc42bf29574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951747126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.951747126
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1437994258
Short name T888
Test name
Test status
Simulation time 124881403 ps
CPU time 5.9 seconds
Started Aug 10 04:51:57 PM PDT 24
Finished Aug 10 04:52:03 PM PDT 24
Peak memory 214176 kb
Host smart-ea78e7ca-2dbe-4018-a565-b48469f02817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437994258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1437994258
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.383540349
Short name T215
Test name
Test status
Simulation time 222601283 ps
CPU time 4.48 seconds
Started Aug 10 04:51:57 PM PDT 24
Finished Aug 10 04:52:02 PM PDT 24
Peak memory 220460 kb
Host smart-e07254eb-cc8f-454c-9d6b-1d888e63ec3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383540349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.383540349
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3096678848
Short name T275
Test name
Test status
Simulation time 135245957 ps
CPU time 5.67 seconds
Started Aug 10 04:51:45 PM PDT 24
Finished Aug 10 04:51:51 PM PDT 24
Peak memory 222380 kb
Host smart-6f88d143-f5a2-4dc8-9742-120b44aaedb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096678848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3096678848
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4286488110
Short name T845
Test name
Test status
Simulation time 104059088 ps
CPU time 2.21 seconds
Started Aug 10 04:51:46 PM PDT 24
Finished Aug 10 04:51:49 PM PDT 24
Peak memory 208536 kb
Host smart-7b8680ec-2062-44e5-85fc-472c10e46a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286488110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4286488110
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2702410618
Short name T611
Test name
Test status
Simulation time 210554605 ps
CPU time 2.88 seconds
Started Aug 10 04:51:46 PM PDT 24
Finished Aug 10 04:51:49 PM PDT 24
Peak memory 208652 kb
Host smart-89a2b411-6883-4868-83ae-b73d5358d902
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702410618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2702410618
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.878011378
Short name T367
Test name
Test status
Simulation time 92815847 ps
CPU time 2.62 seconds
Started Aug 10 04:51:45 PM PDT 24
Finished Aug 10 04:51:48 PM PDT 24
Peak memory 206812 kb
Host smart-0eca950b-1a6c-4235-af36-f992ca9b67db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878011378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.878011378
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2548212806
Short name T643
Test name
Test status
Simulation time 165231157 ps
CPU time 2.98 seconds
Started Aug 10 04:51:47 PM PDT 24
Finished Aug 10 04:51:50 PM PDT 24
Peak memory 208740 kb
Host smart-b3d54284-b8a4-4842-b9cb-be68bc790ee3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548212806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2548212806
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3885719822
Short name T188
Test name
Test status
Simulation time 317798564 ps
CPU time 2.55 seconds
Started Aug 10 04:51:55 PM PDT 24
Finished Aug 10 04:51:58 PM PDT 24
Peak memory 214228 kb
Host smart-0b3e5897-c006-49ed-9c18-d5aa8de2ca53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885719822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3885719822
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2534631802
Short name T392
Test name
Test status
Simulation time 473351602 ps
CPU time 3.34 seconds
Started Aug 10 04:52:20 PM PDT 24
Finished Aug 10 04:52:24 PM PDT 24
Peak memory 208576 kb
Host smart-bb036840-9a20-451c-b0aa-18b987116c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534631802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2534631802
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3137276029
Short name T865
Test name
Test status
Simulation time 829019341 ps
CPU time 9.99 seconds
Started Aug 10 04:51:56 PM PDT 24
Finished Aug 10 04:52:06 PM PDT 24
Peak memory 222128 kb
Host smart-4b2dcd72-57d5-4f75-8815-32f83eaac2a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137276029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3137276029
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3849864553
Short name T576
Test name
Test status
Simulation time 902809417 ps
CPU time 6.91 seconds
Started Aug 10 04:51:56 PM PDT 24
Finished Aug 10 04:52:03 PM PDT 24
Peak memory 218092 kb
Host smart-39f6ccec-ca59-41ae-84d3-dbf5051ec21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849864553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3849864553
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2474480630
Short name T738
Test name
Test status
Simulation time 440333797 ps
CPU time 3.45 seconds
Started Aug 10 04:51:56 PM PDT 24
Finished Aug 10 04:52:00 PM PDT 24
Peak memory 209856 kb
Host smart-17428673-6765-4805-9a5d-2a55cd5714c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474480630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2474480630
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.429746950
Short name T670
Test name
Test status
Simulation time 46303749 ps
CPU time 0.85 seconds
Started Aug 10 04:52:06 PM PDT 24
Finished Aug 10 04:52:07 PM PDT 24
Peak memory 205900 kb
Host smart-9e7fe3eb-ea6a-41f9-8c96-e027458f2647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429746950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.429746950
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3286983024
Short name T385
Test name
Test status
Simulation time 174122649 ps
CPU time 3.6 seconds
Started Aug 10 04:51:56 PM PDT 24
Finished Aug 10 04:52:00 PM PDT 24
Peak memory 214248 kb
Host smart-fc25675a-56c2-462a-a1a5-62efff7d8a37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286983024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3286983024
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.4212365831
Short name T225
Test name
Test status
Simulation time 347213789 ps
CPU time 4.49 seconds
Started Aug 10 04:52:07 PM PDT 24
Finished Aug 10 04:52:12 PM PDT 24
Peak memory 210108 kb
Host smart-0fe4fcf4-0430-41f7-ab9a-7276e4b3d33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212365831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.4212365831
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1327653812
Short name T538
Test name
Test status
Simulation time 93740139 ps
CPU time 3.61 seconds
Started Aug 10 04:51:58 PM PDT 24
Finished Aug 10 04:52:01 PM PDT 24
Peak memory 207492 kb
Host smart-0410a149-17ad-402a-b472-4be4b7a88122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327653812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1327653812
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.63606375
Short name T105
Test name
Test status
Simulation time 158131769 ps
CPU time 3.67 seconds
Started Aug 10 04:52:05 PM PDT 24
Finished Aug 10 04:52:09 PM PDT 24
Peak memory 222356 kb
Host smart-6100f0f0-1ddd-492e-94b3-f171834ee1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63606375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.63606375
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_random.768509284
Short name T856
Test name
Test status
Simulation time 54210944 ps
CPU time 2.57 seconds
Started Aug 10 04:51:55 PM PDT 24
Finished Aug 10 04:51:57 PM PDT 24
Peak memory 214304 kb
Host smart-a5377af3-0894-4cd7-afd2-00e335af19c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768509284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.768509284
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.509392656
Short name T547
Test name
Test status
Simulation time 106230765 ps
CPU time 2.17 seconds
Started Aug 10 04:51:56 PM PDT 24
Finished Aug 10 04:51:58 PM PDT 24
Peak memory 209080 kb
Host smart-e4a90517-1333-4eca-9002-ee3f53182b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509392656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.509392656
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3949471190
Short name T509
Test name
Test status
Simulation time 26394575 ps
CPU time 2.11 seconds
Started Aug 10 04:51:58 PM PDT 24
Finished Aug 10 04:52:00 PM PDT 24
Peak memory 208500 kb
Host smart-2d0a45a1-2ab3-41ed-b4c5-a5d9530175dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949471190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3949471190
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.436928498
Short name T593
Test name
Test status
Simulation time 11589123726 ps
CPU time 38.22 seconds
Started Aug 10 04:51:57 PM PDT 24
Finished Aug 10 04:52:35 PM PDT 24
Peak memory 208692 kb
Host smart-cc31a9fc-6c20-4588-aa57-5ac7e879481b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436928498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.436928498
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.119803761
Short name T846
Test name
Test status
Simulation time 166407022 ps
CPU time 4.4 seconds
Started Aug 10 04:51:56 PM PDT 24
Finished Aug 10 04:52:00 PM PDT 24
Peak memory 207864 kb
Host smart-58ab0d66-3631-4f85-b48e-9f1ec49bd77a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119803761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.119803761
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.902994085
Short name T764
Test name
Test status
Simulation time 33324093 ps
CPU time 1.98 seconds
Started Aug 10 04:52:05 PM PDT 24
Finished Aug 10 04:52:07 PM PDT 24
Peak memory 207368 kb
Host smart-05adfd76-c225-4b22-a459-a5d14593c5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902994085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.902994085
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2896531735
Short name T508
Test name
Test status
Simulation time 110385948 ps
CPU time 2.56 seconds
Started Aug 10 04:51:57 PM PDT 24
Finished Aug 10 04:52:00 PM PDT 24
Peak memory 206696 kb
Host smart-1474b3e6-34f9-4554-9754-c4543eab147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896531735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2896531735
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.456064213
Short name T907
Test name
Test status
Simulation time 1966705136 ps
CPU time 38.14 seconds
Started Aug 10 04:52:06 PM PDT 24
Finished Aug 10 04:52:44 PM PDT 24
Peak memory 220780 kb
Host smart-cd6bf1ba-3544-4a2b-ab72-cddd57691028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456064213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.456064213
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2633626328
Short name T74
Test name
Test status
Simulation time 2163531777 ps
CPU time 26.2 seconds
Started Aug 10 04:52:05 PM PDT 24
Finished Aug 10 04:52:32 PM PDT 24
Peak memory 222620 kb
Host smart-6e963b71-f177-459d-b8a0-adc8e594deb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633626328 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2633626328
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2994706606
Short name T688
Test name
Test status
Simulation time 262752949 ps
CPU time 8.31 seconds
Started Aug 10 04:51:55 PM PDT 24
Finished Aug 10 04:52:04 PM PDT 24
Peak memory 214236 kb
Host smart-4ee79b56-1530-4102-aed5-28e7b9d9c8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994706606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2994706606
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.4245877796
Short name T493
Test name
Test status
Simulation time 143018654 ps
CPU time 3.29 seconds
Started Aug 10 04:52:05 PM PDT 24
Finished Aug 10 04:52:09 PM PDT 24
Peak memory 210164 kb
Host smart-9cb697bb-41ab-456d-afa6-044a9a48a086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245877796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4245877796
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%