Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	41	1			T40	1		T41	1		T6	1
auto[OpGenId]	17	1			T14	1		T48	1		T36	1
auto[OpGenSwOut]	23	1			T50	1		T40	1		T51	1
auto[OpGenHwOut]	19	1			T5	1		T6	1		T25	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1726	1			T5	2		T48	1		T40	2
auto[StInit]	85	1			T1	1		T14	1		T48	1
auto[StCreatorRootKey]	60	1			T5	1		T34	1		T35	1
auto[StOwnerIntKey]	56	1			T5	1		T40	2		T108	1
auto[StOwnerKey]	32	1			T66	2		T135	1		T59	1
auto[StDisabled]	470	1			T5	6		T48	3		T40	6
auto[StInvalid]	50	1			T42	1		T43	1		T110	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3464

1

T1

2

T2

1

T3

1

auto[1]

100

1

T5

1

T14

1

T48

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1720	1			T5	2		T48	1		T40	2
auto[StReset]	auto[1]	6	1			T45	1		T46	1		T47	1
auto[StInit]	auto[0]	51	1			T1	1		T33	1		T216	1
auto[StInit]	auto[1]	34	1			T14	1		T48	1		T50	1
auto[StCreatorRootKey]	auto[0]	41	1			T5	1		T34	1		T35	1
auto[StCreatorRootKey]	auto[1]	19	1			T41	1		T53	1		T54	1
auto[StOwnerIntKey]	auto[0]	35	1			T108	1		T57	2		T66	2
auto[StOwnerIntKey]	auto[1]	21	1			T5	1		T40	2		T6	1
auto[StOwnerKey]	auto[0]	26	1			T66	2		T135	1		T59	1
auto[StOwnerKey]	auto[1]	6	1			T31	1		T217	1		T218	1
auto[StDisabled]	auto[0]	456	1			T5	6		T48	3		T40	6
auto[StDisabled]	auto[1]	14	1			T36	1		T25	1		T58	1
auto[StInvalid]	auto[0]	50	1			T42	1		T43	1		T110	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	5

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	6	1			T45	1		T46	1		T47	1
auto[StInit]	auto[OpAdvance]	11	1			T6	1		T37	1		T219	1
auto[StInit]	auto[OpGenId]	8	1			T14	1		T48	1		T220	1
auto[StInit]	auto[OpGenSwOut]	5	1			T50	1		T51	1		T221	1
auto[StInit]	auto[OpGenHwOut]	10	1			T7	1		T222	1		T74	1
auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T41	1		T53	1		T74	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T54	1		T223	1		T224	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T74	2		T225	1		T226	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	1	1			T227	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T40	1		T223	1		T190	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T228	1		T227	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T40	1		T145	1		T229	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	5	1			T5	1		T6	1		T230	1
auto[StOwnerKey]	auto[OpAdvance]	3	1			T31	1		T218	1		T231	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T217	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T232	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T233	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	6	1			T234	1		T107	1		T235	1
auto[StDisabled]	auto[OpGenId]	3	1			T36	1		T236	1		T237	1
auto[StDisabled]	auto[OpGenSwOut]	3	1			T58	1		T238	1		T239	1
auto[StDisabled]	auto[OpGenHwOut]	2	1			T25	1		T231	1		-	-