Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4887

1

T1

2

T2

2

T3

3

auto[1]

582

1

T12

3

T15

1

T84

3

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4887

1

T1

2

T2

2

T3

3

auto[1]

582

1

T12

3

T15

1

T84

3

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4940

1

T1

2

T2

2

T3

3

auto[1]

529

1

T4

2

T86

3

T48

7

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4940

1

T1

2

T2

2

T3

3

auto[1]

529

1

T4

2

T86

3

T48

7

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	439	1			T5	2		T15	3		T48	1
auto[OpGenId]	1189	1			T1	1		T3	1		T5	5
auto[OpGenSwOut]	1182	1			T2	1		T3	1		T5	5
auto[OpGenHwOut]	2583	1			T1	1		T2	1		T3	1
auto[OpDisable]	76	1			T5	1		T13	1		T49	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	439	1			T5	2		T15	3		T48	1
auto[OpGenId]	1189	1			T1	1		T3	1		T5	5
auto[OpGenSwOut]	1182	1			T2	1		T3	1		T5	5
auto[OpGenHwOut]	2583	1			T1	1		T2	1		T3	1
auto[OpDisable]	76	1			T5	1		T13	1		T49	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4892

1

T1

2

T2

2

T3

2

auto[1]

577

1

T3

1

T5

1

T48

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4892

1

T1

2

T2

2

T3

2

auto[1]

577

1

T3

1

T5

1

T48

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5208

1

T1

2

T2

2

T3

3

auto[1]

261

1

T15

4

T139

7

T140

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1875	1			T1	1		T2	1		T3	1
auto[1]	703	1			T2	1		T4	2		T5	3
auto[2]	731	1			T4	2		T5	2		T12	1
auto[3]	716	1			T4	2		T12	2		T13	1
auto[4]	360	1			T4	1		T84	1		T194	1
auto[5]	382	1			T3	1		T4	1		T5	2
auto[6]	341	1			T1	1		T3	1		T4	1
auto[7]	361	1			T5	1		T84	1		T86	3

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1444	1			T1	1		T3	2		T4	3
clear_one[1]	703	1			T2	1		T4	2		T5	3
clear_one[2]	731	1			T4	2		T5	2		T12	1
clear_one[3]	716	1			T4	2		T12	2		T13	1
clear_none	1875	1			T1	1		T2	1		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	977	1			T1	1		T2	1		T4	2
auto[StInit]	681	1			T1	1		T4	1		T5	1
auto[StCreatorRootKey]	562	1			T3	1		T4	1		T5	2
auto[StOwnerIntKey]	553	1			T4	1		T5	1		T15	1
auto[StOwnerKey]	487	1			T4	1		T5	2		T12	1
auto[StDisabled]	1906	1			T2	1		T3	2		T4	4
auto[StInvalid]	303	1			T42	5		T43	4		T110	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	977	1			T1	1		T2	1		T4	2
auto[StInit]	681	1			T1	1		T4	1		T5	1
auto[StCreatorRootKey]	562	1			T3	1		T4	1		T5	2
auto[StOwnerIntKey]	553	1			T4	1		T5	1		T15	1
auto[StOwnerKey]	487	1			T4	1		T5	2		T12	1
auto[StDisabled]	1906	1			T2	1		T3	2		T4	4
auto[StInvalid]	303	1			T42	5		T43	4		T110	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T243	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	169	1			T1	1		T5	1		T87	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	167	1			T87	1		T42	2		T40	2
auto[0]	auto[StReset]	auto[OpGenHwOut]	255	1			T2	1		T4	1		T5	3
auto[0]	auto[StInit]	auto[OpAdvance]	45	1			T48	1		T139	1		T140	1
auto[0]	auto[StInit]	auto[OpGenId]	94	1			T15	1		T16	1		T39	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	100	1			T5	1		T12	1		T48	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	187	1			T13	1		T84	1		T86	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	20	1			T6	1		T244	1		T245	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	42	1			T5	1		T57	1		T146	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	45	1			T94	1		T108	1		T6	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	87	1			T3	1		T194	1		T210	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T40	1		T246	1		T247	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	36	1			T40	1		T57	1		T248	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	31	1			T40	1		T144	2		T197	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	58	1			T210	1		T142	1		T143	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T5	1		T36	1		T249	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	21	1			T53	1		T250	1		T58	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	22	1			T23	1		T40	1		T7	2
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T205	1		T207	1		T251	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	28	1			T6	1		T193	1		T148	1
auto[0]	auto[StDisabled]	auto[OpGenId]	78	1			T5	1		T48	1		T144	2
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T5	1		T16	1		T48	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	155	1			T84	1		T86	2		T48	1
auto[0]	auto[StDisabled]	auto[OpDisable]	16	1			T57	1		T53	1		T246	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	11	1			T252	1		T253	1		T254	1
auto[0]	auto[StInvalid]	auto[OpGenId]	29	1			T110	2		T109	1		T255	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	25	1			T42	1		T91	1		T255	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T111	1		T96	2		T256	1
auto[1]	auto[StReset]	auto[OpGenId]	19	1			T49	1		T111	1		T89	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	19	1			T44	1		T108	2		T30	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	44	1			T4	1		T213	1		T207	1
auto[1]	auto[StInit]	auto[OpAdvance]	11	1			T6	1		T243	1		T103	1
auto[1]	auto[StInit]	auto[OpGenId]	9	1			T23	1		T36	1		T244	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	14	1			T57	1		T64	1		T74	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	24	1			T4	1		T20	1		T257	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T258	1		T259	1		T237	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T246	1		T135	1		T260	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T7	1		T202	1		T45	2
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T207	1		T142	1		T261	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T135	1		T262	1		T263	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T48	1		T53	1		T201	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T57	1		T264	1		T265	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T213	1		T206	1		T204	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T101	1		T266	1		T231	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	16	1			T246	1		T267	1		T268	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T64	1		T53	1		T269	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T5	1		T84	1		T48	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	21	1			T23	1		T53	1		T148	1
auto[1]	auto[StDisabled]	auto[OpGenId]	65	1			T23	1		T94	1		T244	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T2	1		T5	1		T198	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	151	1			T203	1		T212	1		T210	1
auto[1]	auto[StDisabled]	auto[OpDisable]	13	1			T5	1		T49	1		T270	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	4	1			T110	1		T271	2		T272	1
auto[1]	auto[StInvalid]	auto[OpGenId]	12	1			T111	1		T97	1		T89	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T255	1		T89	1		T273	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T252	1		T92	1		T254	1
auto[2]	auto[StReset]	auto[OpGenId]	25	1			T95	1		T68	1		T92	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	18	1			T43	1		T57	1		T274	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	39	1			T210	1		T143	1		T275	2
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T139	1		T276	1		T268	1
auto[2]	auto[StInit]	auto[OpGenId]	7	1			T20	1		T277	1		T45	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	6	1			T95	1		T71	1		T223	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	20	1			T278	1		T53	1		T279	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T147	1		T280	1		T281	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T48	1		T95	1		T68	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T75	1		T282	1		T223	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T48	1		T205	1		T204	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T283	1		T284	1		T285	2
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T139	1		T198	1		T6	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T94	1		T147	1		T286	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	52	1			T84	1		T205	1		T251	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T140	1		T58	1		T287	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	13	1			T155	1		T135	1		T136	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T139	1		T202	1		T45	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T4	1		T203	1		T213	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	23	1			T40	1		T6	1		T20	1
auto[2]	auto[StDisabled]	auto[OpGenId]	54	1			T5	1		T15	2		T144	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T5	1		T144	1		T288	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T4	1		T12	1		T205	1
auto[2]	auto[StDisabled]	auto[OpDisable]	14	1			T13	1		T57	1		T7	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T42	1		T289	1		T290	1
auto[2]	auto[StInvalid]	auto[OpGenId]	16	1			T43	1		T111	1		T91	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T89	1		T256	1		T291	2
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	18	1			T91	1		T255	1		T97	2
auto[3]	auto[StReset]	auto[OpGenId]	21	1			T6	1		T244	1		T89	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	13	1			T292	1		T7	1		T293	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	33	1			T215	1		T147	1		T80	1
auto[3]	auto[StInit]	auto[OpAdvance]	9	1			T58	2		T68	1		T294	1
auto[3]	auto[StInit]	auto[OpGenId]	8	1			T295	1		T296	1		T237	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	11	1			T40	1		T20	1		T297	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	32	1			T210	1		T213	1		T206	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T140	1		T155	2		T68	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T13	1		T6	1		T296	2
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T208	1		T147	1		T7	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	29	1			T203	1		T214	1		T108	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T53	1		T68	1		T298	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T64	1		T66	1		T299	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T155	1		T53	1		T266	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T4	1		T48	1		T203	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T53	1		T300	1		T75	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	12	1			T12	1		T248	1		T149	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	22	1			T108	1		T6	1		T244	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T212	1		T206	1		T204	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	19	1			T6	1		T155	1		T147	1
auto[3]	auto[StDisabled]	auto[OpGenId]	57	1			T140	2		T40	1		T197	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	68	1			T12	1		T48	1		T139	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	161	1			T4	1		T84	1		T86	1
auto[3]	auto[StDisabled]	auto[OpDisable]	10	1			T58	1		T301	1		T302	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	11	1			T42	1		T256	1		T92	1
auto[3]	auto[StInvalid]	auto[OpGenId]	12	1			T43	1		T111	1		T303	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	17	1			T89	1		T256	1		T253	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T109	1		T255	1		T252	1
auto[4]	auto[StReset]	auto[OpGenId]	3	1			T58	1		T221	1		T304	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	8	1			T49	1		T30	1		T301	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	16	1			T275	1		T305	1		T306	1
auto[4]	auto[StInit]	auto[OpAdvance]	4	1			T155	2		T66	1		T37	1
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T256	1		T307	1		T227	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	11	1			T149	1		T7	1		T250	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T108	1		T79	1		T308	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T250	1		T309	2		T310	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T66	1		T75	1		T311	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T155	1		T312	1		T313	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T251	1		T314	1		T286	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T68	1		T309	1		T315	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T194	1		T25	1		T270	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T65	1		T6	1		T66	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T275	1		T316	1		T66	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T202	1		T276	1		T317	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	8	1			T196	1		T297	1		T309	2
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T197	1		T45	1		T317	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	13	1			T143	1		T6	1		T318	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	25	1			T6	1		T155	2		T146	1
auto[4]	auto[StDisabled]	auto[OpGenId]	31	1			T198	1		T155	1		T211	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	33	1			T6	1		T244	1		T53	2
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	79	1			T4	1		T84	1		T212	1
auto[4]	auto[StDisabled]	auto[OpDisable]	7	1			T319	1		T74	1		T223	1
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T320	1		T321	1		T322	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T256	1		T93	1		T120	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T271	1		T289	1		T323	1
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T258	1		T58	1		T324	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T6	2		T58	1		T221	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	17	1			T278	2		T80	1		T202	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T325	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	9	1			T198	1		T326	1		T327	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T328	1		T329	1		T330	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	12	1			T215	1		T331	1		T332	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T5	1		T333	1		T315	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T79	1		T66	1		T202	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T301	1		T334	1		T335	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	12	1			T4	1		T316	1		T53	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T336	1		T337	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T7	1		T202	1		T258	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T293	1		T338	1		T223	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T16	1		T53	1		T308	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T15	1		T57	1		T66	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	4	1			T339	1		T22	1		T340	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T293	1		T135	1		T68	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T86	1		T210	1		T257	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	17	1			T15	1		T341	1		T184	1
auto[5]	auto[StDisabled]	auto[OpGenId]	33	1			T5	1		T6	1		T53	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T3	1		T6	1		T53	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	87	1			T84	1		T204	1		T251	2
auto[5]	auto[StDisabled]	auto[OpDisable]	7	1			T114	1		T75	1		T342	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T90	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T42	1		T44	1		T111	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T252	1		T290	1		T343	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T115	1		T90	1		T344	1
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T57	1		T345	1		T68	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	10	1			T25	1		T117	1		T346	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	18	1			T5	1		T143	1		T20	1
auto[6]	auto[StInit]	auto[OpAdvance]	4	1			T148	2		T135	1		T324	1
auto[6]	auto[StInit]	auto[OpGenId]	3	1			T347	1		T223	1		T218	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T75	1		T223	1		T348	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	12	1			T1	1		T305	1		T349	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T15	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T193	1		T137	1		T217	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T58	1		T268	1		T62	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T212	1		T137	1		T350	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T146	1		T191	1		T351	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T15	1		T108	1		T352	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T148	2		T246	1		T217	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T212	1		T193	1		T149	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T353	1		T354	1		T351	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	3	1			T355	1		T356	1		T357	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T350	1		T358	1		T223	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T80	1		T308	1		T359	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T146	1		T45	1		T339	1
auto[6]	auto[StDisabled]	auto[OpGenId]	22	1			T3	1		T139	1		T196	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T139	2		T7	1		T45	2
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T4	1		T203	1		T212	1
auto[6]	auto[StDisabled]	auto[OpDisable]	6	1			T68	1		T75	1		T231	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T42	1		T289	1		T360	1
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T271	1		T361	1		T362	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T43	1		T82	1		T290	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T273	1		T363	1		T364	1
auto[7]	auto[StReset]	auto[OpGenId]	11	1			T6	1		T66	1		T137	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	14	1			T25	1		T37	1		T276	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	28	1			T213	2		T207	1		T143	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T365	1		T366	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T58	1		T266	1		T311	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T147	1		T231	1		T367	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	9	1			T108	1		T75	1		T368	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T369	1		T357	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T76	1		T228	1		T266	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T108	1		T7	1		T47	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T84	1		T86	1		T206	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T370	1		T371	1		T372	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T45	2		T370	2		T373	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T5	1		T53	1		T326	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T86	1		T141	1		T214	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T374	1		T313	1		T227	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T53	1		T345	1		T326	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T198	1		T6	1		T375	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T376	1		T377	1		T378	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	12	1			T23	1		T317	1		T370	1
auto[7]	auto[StDisabled]	auto[OpGenId]	26	1			T288	1		T379	1		T83	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T57	1		T53	2		T68	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	68	1			T86	1		T205	1		T207	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T53	1		T380	1		T381	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T43	1		T82	1		T273	1
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T382	1		T383	1		T384	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T291	1		T385	1		T383	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T109	1		T93	1		T120	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1444

1

T1

1

T3

2

T4

3

clear_one[1]

auto[0]

auto[0]

auto[0]

422

1

T2

1

T4

2

T5

3

clear_one[1]

auto[0]

auto[0]

auto[1]

130

1

T206

1

T207

2

T261

2

clear_one[1]

auto[0]

auto[1]

auto[0]

110

1

T48

1

T212

1

T213

1

clear_one[1]

auto[0]

auto[1]

auto[1]

41

1

T48

1

T94

1

T297

1

clear_one[2]

auto[0]

auto[0]

auto[0]

408

1

T4

2

T5

1

T13

1

clear_one[2]

auto[0]

auto[0]

auto[1]

120

1

T5

1

T205

3

T207

1

clear_one[2]

auto[1]

auto[0]

auto[0]

168

1

T12

1

T15

1

T84

1

clear_one[2]

auto[1]

auto[0]

auto[1]

35

1

T94

1

T53

1

T286

1

clear_one[3]

auto[0]

auto[0]

auto[0]

428

1

T13

1

T205

1

T210

1

clear_one[3]

auto[0]

auto[1]

auto[0]

135

1

T4

2

T86

1

T48

2

clear_one[3]

auto[1]

auto[0]

auto[0]

123

1

T12

2

T84

1

T24

1

clear_one[3]

auto[1]

auto[1]

auto[0]

30

1

T140

2

T155

1

T264

1

clear_none

auto[0]

auto[0]

auto[0]

1332

1

T1

1

T2

1

T4

1

clear_none

auto[0]

auto[0]

auto[1]

153

1

T3

1

T87

1

T205

2

clear_none

auto[0]

auto[1]

auto[0]

130

1

T86

2

T48

2

T194

1

clear_none

auto[0]

auto[1]

auto[1]

34

1

T57

1

T148

1

T292

2

clear_none

auto[1]

auto[0]

auto[0]

146

1

T84

1

T24

1

T210

3

clear_none

auto[1]

auto[0]

auto[1]

31

1

T6

1

T53

1

T286

1

clear_none

auto[1]

auto[1]

auto[0]

16

1

T386

1

T246

1

T228

2

clear_none

auto[1]

auto[1]

auto[1]

33

1

T48

1

T40

1

T53

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1347	1			T1	1		T3	2		T4	3
clear_all	auto[1]	97	1			T15	2		T139	5		T155	4
clear_one[1]	auto[0]	672	1			T2	1		T4	2		T5	3
clear_one[1]	auto[1]	31	1			T294	1		T247	1		T387	1
clear_one[2]	auto[0]	699	1			T4	2		T5	2		T12	1
clear_one[2]	auto[1]	32	1			T15	2		T139	1		T140	1
clear_one[3]	auto[0]	667	1			T4	2		T12	2		T13	1
clear_one[3]	auto[1]	49	1			T139	1		T140	1		T155	5
clear_none	auto[0]	1823	1			T1	1		T2	1		T3	1
clear_none	auto[1]	52	1			T144	7		T155	1		T148	1