Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11135

1

T1

4

T2

6

T3

4

auto[Attestation]

7806

1

T1

1

T2

4

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2740	1			T5	16		T12	2		T15	1
auto[Aes]	3389	1			T1	2		T3	2		T5	19
auto[Kmac]	3389	1			T2	2		T3	1		T4	13
auto[Otbn]	3423	1			T2	3		T3	1		T5	16

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7776	1			T1	1		T2	1		T3	8
auto[OpGenId]	6000	1			T1	3		T2	5		T3	4
auto[OpGenSwOut]	5990	1			T2	4		T3	2		T5	46
auto[OpGenHwOut]	6951	1			T1	2		T2	1		T3	2
auto[OpDisable]	144	1			T2	1		T5	2		T13	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10931

1

T1

1

T2

2

T3

8

auto[OpDoneFail]

15930

1

T1

5

T2

10

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6341	1			T1	5		T2	5		T3	1
auto[StInit]	3742	1			T1	1		T2	5		T3	2
auto[StCreatorRootKey]	3267	1			T3	2		T4	2		T5	18
auto[StOwnerIntKey]	2893	1			T3	2		T4	2		T5	14
auto[StOwnerKey]	2497	1			T3	2		T4	2		T5	7
auto[StDisabled]	8121	1			T2	2		T3	7		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	323	1			T5	3		T85	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	113	1			T5	2		T48	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	90	1			T39	1		T48	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T94	1		T40	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T48	1		T40	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	217	1			T16	1		T48	2		T139	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	315	1			T5	1		T48	1		T23	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	91	1			T5	1		T24	1		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	83	1			T5	1		T48	2		T109	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	73	1			T5	1		T12	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	66	1			T87	1		T24	1		T94	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	225	1			T5	1		T140	1		T40	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	310	1			T2	2		T5	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	121	1			T5	2		T24	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T87	1		T35	1		T94	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	78	1			T15	1		T24	1		T140	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	51	1			T12	1		T23	1		T140	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	230	1			T3	1		T5	2		T85	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	344	1			T85	2		T87	2		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	88	1			T36	1		T195	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	84	1			T39	1		T110	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	69	1			T16	1		T48	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	76	1			T5	1		T139	2		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	239	1			T2	1		T5	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	82	1			T5	4		T108	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	101	1			T24	1		T34	1		T155	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	89	1			T40	1		T198	1		T155	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	62	1			T85	1		T65	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	63	1			T40	1		T108	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	222	1			T5	2		T48	2		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	68	1			T5	2		T108	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	92	1			T5	2		T6	3		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	82	1			T15	1		T36	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	85	1			T5	1		T23	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	71	1			T3	1		T12	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	196	1			T5	2		T12	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	80	1			T5	3		T108	1		T53	6
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	96	1			T5	1		T40	1		T109	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T5	1		T194	1		T40	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T199	1		T144	1		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	68	1			T40	1		T200	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	224	1			T5	4		T13	1		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	70	1			T5	3		T53	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	105	1			T2	1		T5	2		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T5	1		T12	1		T24	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	80	1			T94	1		T40	2		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	58	1			T24	1		T139	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	243	1			T5	1		T87	1		T24	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	252	1			T5	2		T48	2		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	90	1			T194	1		T40	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	68	1			T5	1		T194	2		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	52	1			T94	1		T40	1		T202	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	45	1			T94	1		T108	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	196	1			T5	1		T12	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	514	1			T1	1		T5	2		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	119	1			T5	1		T84	1		T194	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	102	1			T12	1		T84	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	94	1			T16	1		T203	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	98	1			T5	1		T48	1		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	281	1			T3	1		T12	1		T84	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	411	1			T4	5		T5	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	110	1			T4	1		T13	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T5	1		T86	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	101	1			T4	1		T5	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	92	1			T4	1		T86	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	277	1			T4	2		T5	1		T86	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	386	1			T2	1		T5	2		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	127	1			T5	2		T29	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	121	1			T3	1		T24	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	110	1			T39	1		T194	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	105	1			T205	1		T206	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	280	1			T5	2		T13	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T108	1		T57	2		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	110	1			T6	2		T208	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	69	1			T5	1		T12	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	56	1			T36	1		T196	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	49	1			T48	2		T6	1		T209	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	206	1			T15	1		T24	1		T139	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	53	1			T5	2		T108	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	103	1			T1	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	118	1			T204	1		T142	1		T40	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	97	1			T5	1		T12	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	98	1			T84	1		T210	1		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	265	1			T12	2		T15	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	64	1			T5	3		T53	1		T66	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T86	1		T212	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	113	1			T4	1		T212	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	116	1			T86	1		T48	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	91	1			T48	1		T213	1		T143	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	282	1			T4	2		T212	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	54	1			T108	1		T57	2		T53	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	118	1			T205	1		T206	1		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T5	1		T15	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	103	1			T39	2		T48	1		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	78	1			T214	1		T215	1		T147	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	287	1			T48	1		T24	1		T205	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	198	1			T39	1		T48	2		T94	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	668	1			T5	5		T16	1		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	206	1			T5	1		T12	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	647	1			T5	4		T48	1		T23	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	202	1			T12	1		T15	1		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	679	1			T2	2		T3	1		T5	5
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	216	1			T5	1		T16	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	684	1			T2	1		T5	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	194	1			T85	1		T40	2		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	425	1			T5	6		T48	2		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	215	1			T3	1		T5	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	379	1			T5	6		T12	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	224	1			T5	1		T194	1		T40	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	412	1			T5	8		T13	1		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	208	1			T5	1		T12	1		T24	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	433	1			T2	1		T5	6		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	152	1			T5	1		T194	2		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	551	1			T5	3		T12	1		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	278	1			T5	1		T12	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	930	1			T1	1		T3	1		T5	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	276	1			T4	2		T5	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	815	1			T4	8		T5	3		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	321	1			T3	1		T39	1		T194	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	808	1			T2	1		T5	6		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	161	1			T5	1		T12	1		T48	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	391	1			T15	1		T24	1		T139	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	299	1			T5	1		T12	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	435	1			T1	1		T5	2		T12	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	305	1			T4	1		T86	1		T48	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	476	1			T4	2		T5	3		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	280	1			T5	1		T15	1		T39	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	473	1			T48	1		T24	1		T205	3